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Ron tells me that this is the first mention that he is aware of for plans to create
compound semiconductor memory ICs and chiplets.
A relatively new challenger, the triple barrier resonant tunnelling (TBRT) non-
volatile memory, has joined the ranks of emerging memory technologies. It has
been named by its developers at Lancaster University as ULTRARAM.
As you will find from my correspondence with a member of the development team,
in the future ULTRARAM might even take peripheral memory technology in a
radical new direction away from silicon towards new compound material based
integrated circuits, with memory chiplets as possible initial ULTRARAM memory
products.
A Simple Overview
ULTRARAM has a similar configuration to a flash memory cell, with a control gate
above a floating gate above the transistor channel. In Flash each of these is isolated
from the layer below with layer of SiO2. As shown in the simple illustration below,
the oxide barrier which separates the floating gate from the channel of a Flash
memory is replaced in ULTRARAM by three thin tunnelling barriers.
For the ULTRARAM the three barriers are part of an epitaxial stack consisting of
floating gate, barriers and quantum wells. This cross-section is configured to show
the compound semiconductor materials and thicknesses involved.
The spacing between the tunnelling barriers has been carefully tuned to create two
quantum wells of unequal thickness, which separate the floating gate from the
channel.
Quantum wells provide discrete new energy levels at the semiconductor band
edge. Those levels relate directly to the physical width of the thin film which forms
the well. The energy levels are represented by different colours (red, blue and
green lines) in the band-gap illustration below:
This illustration contrasts the ULTRARAM to standard flash, which is shown in the
box in the lower left side. Flash programs and erases by applying a high forward or
reverse voltage to cause an electron to tunnel through the barrier oxide (shown as a
yellow vertical bar).
The need for the new gate complexity, vis-a-vis Flash, is outweighed by the
advantages which come with it:
Lower read and write voltages, almost an order of magnitude lower than
Flash
Lower write/erase power and lower write/erase times making it a non-
volatile contender to replace DRAM/SRAM
Retention times greater than are ever likely to be needed.
ULTRARAM does not have source and drain diffusions like some types of Flash
memory, the metal for the contacts is applied directly to the transistor channel.
Readers will find a more formal and detailed explanation of the operation of
ULTRARAM in the following references:
The Lancaster University team have reported success with integrating ULTRARAM
with silicon. One possible next step if they follow that path will be a need to
convince one of the leading silicon memory fabrication companies to adopt the
technology.
My starting point in our correspondence was the three bullet points that are linked
to the near-term probability of success for emerging memory entrepreneurs, which
I introduced in a recent Memory Guy blog post of mine. They are:
The number of new materials and tools required, which are not already
available in existing solid state fabrication facilities.
The number of additional fabrication steps required
The number of device characteristics where the explanation of the
underlying mechanism is debatable and lacks a clear agreed science-based
understanding.
The ULTRARAM memory, like any other memory array, requires peripheral
interface circuits to access a memory array for read, write and erase, utilising
conventional silicon technology, and fabrication as a BEOL to silicon processing.
In the context of the need to integrate with silicon, my first question for Manus
Hayne was how he positioned ULTRARAM with respect to my first two bullet
points. I also requested in his answer for him to include discussion of some aspects
the BEOL process, which I see as potential problem areas, as sub-questions.
I asked for his responses to only the first two bullet points because, of all the
emerging memory contenders, this one has the fewest problems with my third
bullet point.
That would appear to mean that for your epitaxial process you will require on the
pre-processed silicon wafers areas of clean single-crystal silicon surfaces, to be left
untouched by processing, on which to deposit your GaSb-to-Silicon interface-
matching buffer layer and memory array.
If those areas on the pre-processed silicon wafers that are reserved for the
ULTRARAM array are oxidised, either deliberately or from atmospheric oxidation,
some pre-epitaxial silicon surface cleaning process will be needed, with the
potential to damage the existing silicon devices already on the wafers.
The Second Sub-Question
Your memory transistor does not have separate source and drain diffusions. The
contact metallization makes direct contact with the InAs channel of the transistor,
which your published work indicates is Ti/Au. I understand Cr and Ni can also be
used to make Ohmic contacts, while in the early days triple metals were used.
It also means your epitaxial stack will have to include the metallization link to the
pre-processed peripheral, driver, decoder sense amplifiers. Will it be possible for
you be able to utilise the metal systems already in use for source and drain contact
metal?
Third Sub-Question
What temperatures are required for your epitaxial processing or for any annealing-
like fabrication steps or other environment conditions required for the stack and
contact metal deposition?
All three of these are important questions because as a BEOL process there needs
to be some assurance that the silicon devices already on the 12-inch wafers being
processed will not be compromised.
“We have spent some time thinking about different options for the
peripheral circuitry, i.e. the addressing logic: wafer bonding the
array onto a Si chip that has the logic, co-integrating with Si
CMOS (BEOL you suggest) and implementing the logic in the III-
Vs. All of these options are challenging.”
I replied that this raises the question of the exciting possibility that the team might
be heading in the direction of a new dedicated compound semiconductor
integrated circuit fabrication line and compound semiconductor Chiplets.
Another important process related question relates to film thickness and allowable
tolerance in film thicknesses for each layer of the triple epitaxial memory stack.
The thickness of the films appears to be an important variable in order to fix the
levels in the quantum wells.
“Our channels are InAs, which has very high mobility, so we are
not expecting a problem with undetectably-low readout
currents.”
An important question is memory array and interface design and I raised with Prof
Manus the question of what the ideal target bit density for a first ULTRARAM
based product chiplet or otherwise.
Similarities to Flash
I asked if there are some preliminary ULTRARAM memory array designs especially
in relation to the interface with silicon, and if the array design is similar to Flash
memory?
“Yes, we have already published our array design, and also some
preliminary results on 4-bit arrays that validated the array
concepts and potential performance, such as very low disturb.
The interface with Si has been discussed above.”
There is close similarity between the ULTRARAM cell and Flash. I asked if it is
possible that this new memory could be a drop-in replacement for existing Flash
array designs as far as the peripheral circuits are concerned, or because of the
single value of write/erase voltages would orthogonal half-voltage write arrays be a
practical use of ULTRARAM, giving access to individual devices in the array?
“However, due to the very low cost per bit of NAND flash, we
decided to go in the RAM direction, more like NOR flash (bits in
parallel), but with DRAM performance.”
Other emerging memory competitors have had to deal with forming. An obvious
question: Does the ULTRARAM require forming in its as fabricated state and what
is the logic sate of the as-fabricated memory?
The University’s claims for calculated retention are impressive and represent a
unique selling point. In your team’s published works, the term “room-temperature
operation of non-volatile, charge-based memory cells” is used, suggesting that
elevated temperature operation has not been evaluated. This raises the question:
“What is the operating temperature of the memory and what has been established
from real device experience?”
“You are right that the calculated retention times are extremely
long, which is due to the size of the potential barrier trapping the
charge in the floating gate. This large barrier also implies
excellent high temperature operation. However, we do not know
what any unintended charge loss mechanisms are, i.e. at what
temperature they kick-in, so there is no substitute for experiment
here. To date all our tests have been at room temperature, but we
will start testing at higher temperatures very soon.”
I would like to thank Prof Manus Hayne for his time, forbearance and his
willingness to answer all and any of my questions regarding ULTRARAM and
providing pointers to the future.
Perhaps rather than “Silicon Valleys”, success in the future might rest with
“Compound Semiconductor Valleys” or the like, producing Chiplets and ICs.
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