International Islamic University,

Islamabad
Digital System Design LAB

EXPERIMENT # 07: Core Generator & Design Implementation

(Sequential Logic)

Name of Student:

Roll No.:

Date of Experiment:

Report submitted on:

Marks obtained:

Remarks:

Instructor’s Signature:

Digital System Design Lab (EE-319L) Page 54

 Core Generator & Design Implementation
(Sequential Logic)
1. Objective
This lab exercise is designed to understand the concepts related to generating cores for
projects and implementing designs on Spartan 3E board.

2. Resources Required
• A Computer
• Xilinx ISE
• Spartan 3E board

3. Introduction
Xilinx is the largest vendor in the programmable logic market. Its FPGAs are the most widely used
in the world. Currently, its FPGAs are divided mainly in 3 families: Virtex-7(most powerful),
Kintex-7(mid-range) & Artix-7(least powerful) where 7 represents the current generation. Initially
there were only two, High Power (Virtex series) and High Volume (Spartan Series). Spartan 3E
has been one of the most widely used FPGA ever made and currently many educational institutions
use it to teach Digital Logic Design to its students.

3.1 Xilinx CORE Generator System

Xilinx CORE Generator™ System accelerates design time by providing access to highly
parameterized Intellectual Properties (IP) for Xilinx FPGAs and is included in the ISE® Design
Suite. Using these IP blocks can save days to months of design time. The highly optimized IP allows
FPGA designers to focus efforts on building designs quicker while helping bring products to market
faster. You can also generate tailored HDL to quickly configure FPGA architectural elements such
as MGTs and Ethernet and PCI Express hard blocks using the integrated LogiCORE™ GUI-based
customizers and Core Generator Architecture Wizards. Through its seamless integration with the
ISE development environment, the CORE Generator system streamlines your design process,
improves design quality and helps you finish faster.

The CORE Generator IP catalog provides IP which include:

Targeted Design Types of IP IP Cores
Platform
Base Platform Building Blocks • Memories and FIFOs
• Arithmetic Operators (Adder,
Accumulator, Multiplier, Complex
Multiplier, etc.)
• Floating Point Operators
Debug and Verification • ChipScope™ Pro Integrated
Controller
• Integrated Logic Analyzer
• Virtual Input/Output
FPGA Architecture • Clocking Wizard
features • Memory Interface Generator (MIG)
• RocketIO™ Multi-Gigabit
Transceivers (MGTs)
• System Monitor Wizard

Digital System Design Lab (EE-319L) Page 55

Domain Specific Connectivity • Standard bus interfaces such as PCI™
and PCI-X™
• Networking Interfaces such as
Ethernet, SPI-4.2, RapidIO, CAN and
PCI EXPRESS®
DSP Functions • FIR Compiler, FFT, etc.
• Forward Error Correction IP such as
Reed-Solomon Decoder and Encoder,
Viterbi Decoder, etc.
Video and Image • Color-Space Converters
Processing Embedded IP • Color Conversion Matrix, Color Filter
Array Interpolation, Image Processing
Pipeline, etc.
Market Specific Automotive and Industrial • CAN, Ethernet AVB, etc.
Wired • Ten Gigabit Ethernet MAC, Tri-mode
Telecommunications Ethernet MAC, etc.
Wireless • LTE Channel Encoder/Decoder,
Telecommunications 3GPP Searcher, etc.
• CPRI, OBSAI and Serial Rapid IO,
etc.

4. Verilog Codes + Files (to be utilized in this lab)

This is the main diagram for the Lab task. The board has a 50MHz CLK, we have to divide the
clock to make it 1Hz using another counter.
Our design will be divided in the following modules:
1. ClkDivider
2. 4-bit Counter
3. Display4Leds

For 50 MHz, our clock cycle is 0.02µ sec. So our clock divider counter will have to run for up to
the value of 25M before inverting its output so as to give us a 1 Hz clock (0.5/0.02µ=25M). The
counter size would be 25-bits (1 0111 1101 0111 1000 0100 0000 = 25’h17D7840 = 25,000,000).

Also we will be using a special buffer named Global Buffer (BUFG). Using the BUFG ensures
that the clock signal reaches all the flip-flops in the design with minimal skew so they all change
state at the same time.

Digital System Design Lab (EE-319L) Page 56

4.1 TopModule always @(posedge clk, negedge rst)
begin
module TopModule(out, clk, rst); if(!rst)
output [3:0] out; out <= 0;
// 4-bit output on LEDs
else
input clk, rst; out <= out + 1;
wire dividedCLK, bufferedCLK; end
wire [3:0] counterOut; endmodule
BUFG bg(bufferedCLK, dividedCLK);
//Global Buffer, used here to prevent
//any skew
ClkDivider CD(dividedCLK, clk, rst); 4.4 Display4Leds (For Spartan3E)
Counter C1(counterOut, bufferedCLK,
rst); module display4leds(out, in);
Display4leds D1(out, counterOut); output [3:0]out;
Endmodule input [3:0]in;
reg [3:0]out;
4.2 ClkDivider always @ (in)
module ClkDivider(out, clk, rst); begin
output out; case(in)
input clk, rst; 4'h0: out <= 4'b0000;
reg out;
reg [24:0] counter; 4'h1: out <= 4'b0001;
always @(posedge clk, negedge rst) 4'h2: out <= 4'b0010;
begin 4'h3: out <= 4'b0011;
if(!rst) 4'h4: out <= 4'b0100;
begin out <= 0;counter <= 0; 4'h5: out <= 4'b0101;
end 4'h6: out <= 4'b0110;
else if (counter == 25'h17D783F) 4'h7: out <= 4'b0111;
//25M – 1, as the counter starts from 0(zero) 4'h8: out <= 4'b1000;
begin out <= !out; counter <= 0; 4'h9: out <= 4'b1001;
end 4'hA: out <= 4'b1010;
else 4'hB: out <= 4'b1011;
counter <= counter + 1; 4'hC: out <= 4'b1100;
end 4'hD: out <= 4'b1101;
endmodule 4'hE: out <= 4'b1110;
4'hF: out <= 4'b1111;
4.3 Counter default:out <= 4'bxxxx;
module Counter(out, clk, rst); endcase
output [3:0] out; end
input clk, rst; endmodule
reg [3:0] out;

Digital System Design Lab (EE-319L) Page 57

4.5 UCF (pin locations file – created using PACE- PinOut Area Constraints Editor)
NET "clk" LOC = "C9" ;
NET "rst" LOC = "L13" ;
NET "out<0>" LOC = "F12" ;
NET "out<1>" LOC = "E12" ;
NET "out<2>" LOC = "E11" ;
NET "out<3>" LOC = "F11" ;

5. Xilinx Core Generator

1. Open Xilinx ISE. Go to File/New Project. Create a new project named Coregen. Choose
HDL as top-level source type.

2. Choose the respective values for Spartan 3E board in the next Dialog box.

3. Add a new file to the project named Coregen with type as IP(Coregen & Architecture
Wizard).

4. Choose Binary Counter (From Basic Elements/Counters).

5. After clicking next, a new window will open titled Binary Counter. Set the values as you
like. Use View Data Sheet to understand this IP Core’s features in detail.

Digital System Design Lab (EE-319L) Page 58

6. After setting the values, click finish to end the process. Xilinx ISE will automatically create
all the files necessary for the process.

7. The TestBench WaveForm Editor can’t be used with Coregen files so create a Verilog
module file and instantiate your Coregen file in it. To view RTL code for the Coregen file,
select the Coregen file and click View HDL Functional Model.

8. Binary Counter is one of the IP Cores that doesn’t support Verilog Behavioral Modeling.
So instead you can perform Timing (Post-Route) Simulation to verify the functionality.

9. Try Timing Simulations for Spartan 3. This IP Core’s results will show you why it is
necessary to perform timing simulations.

Digital System Design Lab (EE-319L) Page 59

6. Addendum (Few problems that may occur even if the procedures are followed exactly
100%)

File doesn’t appear in Implementation mode:

1. All the procedures mentioned above are in Implementation mode. (Chosen from Sources
for (in the upper-left corner). It is also the default option for new projects.

2. If after saving your Verilog module file, it doesn’t appear in the Implementation mode, check
other modes to find it. It is usually placed in Behavioral Simulation mode.

3. When found, right-click the file, choose its properties and change Association from
Simulation Only to Synthesis/Imp + Simulation.

4. If not found in any mode then it might not be added to the project, right click your project
and choose Add Source to add the file to your project manually. Make sure to choose the right
Association in the dialog box that appears after adding the file.

4. Go back to the Implementation mode and follow the remaining procedure for your issued
board.

7. Home Work

Implement the 4-bit counter + LED decoder as done in the lab. But instead of using Four
LEDs use 8 LEDs now. Four for ten’s digit while the other four for unit’s digit.

Submit the code, synthesis report and UCF files in the next lab. Bring the complete
project folder in your pen drives. Implementation will be checked in the next lab.

Digital System Design Lab (EE-319L) Page 60

 International Islamic University, Islamabad
Digital System Design Lab

LAB WORKSHEET (Lab # 7)

Q.1 What is the advantage of using Xilinx IP Core Generator System?

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Q.2 Why can’t we use Behavioral Simulation for the Binary Counter (Coregen)?
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Q.3 Write the names of (any) four IPs that are available in Coregen.
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Digital System Design Lab (EE-319L)