Session 1B: Emerging Memory-Enabled Computing for Future Electronics GLSVLSI ’20, September 7–9, 2020, Virtual Event,
’20, September 7–9, 2020, Virtual Event, China
IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid
Memory Cube
Zheyu Li
The Pennsylvania State University
State College, PA, USA
zil5126@psu.edu
Akshay Krishna Ramanathan
The Pennsylvania State University
State College, PA, USA
axr499@psu.edu
ABSTRACT
Processing-in-memory (PIM) architectures have gained significant
importance as an alternative paradigm to the von-Neumann archi-
tectures to alleviate the memory wall and technology scaling prob-
lems. PIM architectures have achieved significant latency and en-
ergy consumption improvements for various emerging and widely
used workloads such as deep neural networks, graph analytics,
databases and computational genomics. In this work, we propose
IMC-Sort, an in-memory parallel sorting architecture using the
hybrid memory cube (HMC) for accelerating the sort workloads.
Sort is one of the fundamental and widely used algorithm in vari-
ous applications such as databases, networking, and data analytics.
IMC-Sort architecture augments the hybrid memory cube memory
system by incorporating custom sorting network at each of the
HMC vault’s logic layer. IMC-Sort uses optimized folded Bitonic
sort and merge network to sort input sequences of arbitrary length
at each vault and optimized address mapping mechanism to distrib-
ute the input data across HMC vaults. Merging of the sorted results
across individual vaults is also performed using the vault’s sorting
network by communicating with other vaults through the HMC’s
crossbar network. Overall, IMC-Sort achieves 16.8×, 1.1× speedup
and 375.5×, 13.6× savings in energy consumption compared to the
widely used CPU implementation and state-of-the-art near memory
custom sort accelerator respectively.
KEYWORDS
processing-in-memory, sort, merge, vault, hybrid memory cube
ACM Reference Format:
Zheyu Li, Nagadastagiri Challapalle, Akshay Krishna Ramanathan, and Vi-
jaykrishnan Narayanan. 2020. IMC-Sort: In-Memory Parallel Sorting Archi-
tecture using Hybrid Memory Cube . In Proceedings of the Great Lakes Sym-
posium on VLSI 2020 (GLSVLSI ’20), September 7–9, 2020, Virtual Event, China.
ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3386263.3407581
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GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
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ACM ISBN 978-1-4503-7944-1/20/09. . . $15.00
https://doi.org/10.1145/3386263.3407581
45
Nagadastagiri Challapalle
The Pennsylvania State University
State College, PA, USA
nrc53@psu.edu
Vijaykrishnan Narayanan
The Pennsylvania State University
State College, PA, USA
vxn9@psu.edu
1 INTRODUCTION
In recent times, processing in memory (PIM) architectures tailored
for specific workloads have gained significant attention owing to
their computational efficiency. Moving compute closer to memory
bridges the ever increasing latency gap between memory systems
and compute systems and overcomes the memory-wall in conven-
tional von-Neumann architectures. PIM architectures can be catego-
rized into two variants, first variant leverages the in-situ compute
capabilities of crosspoint memory architectures augmented with
peripheral circuitry such as digital-to-analog converters, analog-
to-digital converters, and shift-and-add units [1, 2]. Second vari-
ant incorporates the compute elements such as arithmetic-logic
units, mutiply-and-accumulate units near to the memory at various
granularity such as SRAM sub-array level [3], DRAM rank level
and DRAM bank level [4, 5]. These PIM architectures have shown
significant speedups and energy savings for various application do-
mains such as deep neural networks, computational genomics, and
databases. To complement the advancements in application PIM
accelerator architectures, enterprise companies such as VMWare
introduced platforms like vSPhere BitFusion to simplify the run
time management and scheduling of various emerging workloads
elastically across pool of hardware accelerators and conventional
CPUs.
Sort is one of the fundamental algorithms in computational sci-
ence and important building block for various data management and
warehousing applications such as database management systems,
and data analytics systems. For instance, sort is used in several func-
tions in relation data management such as merge, aggregation, and
selection. Several big data analytics applications and frameworks
such as MapReduce [6], Hive [7] also uses sort in their comput-
ing pipeline. Several prior works have established that sort is one
of the primary bottleneck in these applications. In addition, this
bottleneck is further aggravated by the big data explosion where
there is lot of variation in the width of the data records etc. Tech-
niques such as unrolling, assigning multiple hardware mergers, are
discussed to scale the Bonsai design for various sort workloads
etc. Several custom hardware and FPGA-based accelerators are pro-
posed to alleviate the sort bottleneck in these applications. Amin et.
al. [8] proposed an ASIC-based accelerator architecture for sorting,
they construct large sorting networks by grouping and reusing
Session 1B: Emerging Memory-Enabled Computing for Future Electronics GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

smaller sorting units. Pugsey et. al. [9] accelerated the sort oper- they can communicate with other units using the HMC crossbar
ation in map phase of MapReduce application by incorporating network. In the subsequent sections, we elaborate on the intra-
low power cores near each of the Hybrid Memory Cube (HMC) vault sorting unit and its operation, merging of the sorted values
vaults. Bonsai [10] proposed adpative merge tree based sorting near (of different input sequences) within a vault (intra-vault merging),
the memory with custom hardware compute elements to leverage and merging of the sorted values across different vaults using the
the massive bandwidth of the emerging main memory systems HMC crossbar network (inter-vault sorting).
such as High Bandwidth Memory (HBM). Several FPGA architec-
tures [11, 12] implement the parallel merge sort, parallel bitonic DRAM bank DRAM bank DRAM bank
or hybrid merge-bitonic sort algorithms using custom dataflow DRAM bank DRAM bank DRAM bank
and pipe line mechanisms to achieve superior compute and energy ...... ...... ......

efficiency. ...... ...... ......

3D Stacked

3D Stacked
3D Stacked
...... ...... ......
In this work, we propose IMC-Sort architecture which augments
...... ...... ......
the logic layer in vaults of hybrid memory cube (HMC) to incor-
...... ...... ......
porate a custom parallel sorting unit (intra-vault sorting unit) to
...... ...... ......
realize a customized Bitonic sorting network. IMC-Sort proposes
two variants of intra-vault sorting unit, first variant leverages the
existing compute capabilities (using the HMC’s native instruction
set) of logic layer in each of the HMC vault for doing the sort oper- Vault Vault Vault
Controller Controller Controller
ation. We use the compare and swap (CAS) operation available in
the current generation HMC systems to build a custom sort acceler-
ator. Next variant incorporates custom compute elements near each
Crossbar Network
HMC vault to perform intra-vault sort operation and a efficient
merge hardware to aggregate and sort the results from intra-vault
sorting phase. We leverage the massive vault level bandwidth to
perform parallel sorting across all the vaults and merge the results Host

across the vaults using the HMC’s crossbar network and intra-vault
sorting units. Figure 1: Overall architecture overview of the IMC-Sort
The key contributions of the paper include:
• Two variations of intra-vault sorting unit utilizing HMC’s
native instruction set and custom compute logic to sort input
2.1 Intra-vault sorting
sequences of arbitrary length in each vault with fixed hard-
ware units. Custom optimizations to the input permutation
unit to reduce the number of compare and swap units.
• Merging of the sorted results across vaults using the intra-
vault sorting units by leveraging the HMC’s crossbar commu-
nication network to move the data elements across different
vaults. Custom address mapping strategy to distribute the
input data across HMC vaults to aid the intra-vault and inter-
vault sort and merge operations.
• Detailed performance evaluation of IMC-Sort architecture
and comparison against widely CPU implementations and
state of the art custom near memory accelerator architec-
ture [10]. Overall, IMC-Sort achieved 16.8×, 1.1× speedup
and 375.5×, 13.6× savings in energy consumption compared
to the widely used CPU implementations and state-of-the-art
near memory custom sort accelerator.

2 ARCHITECTURE
In this section, we discuss overall architecture of the proposed in-
memory sort accelerator IMC-Sort. We augment the conventional
HMC architecture with custom compute elements to perform highly
efficient parallel sort operation. Figure 1 illustrates the overall IMC-
Sort architecture. IMC-Sort consists of custom intra-vault sorting
units at logic layer of each HMC vault. The control unit of the HMC
vault is also augmented with the necessary logic to perform the
sort operation. These sorting units can be accessed in parallel and
Figure 2: IMC-Sort intra-vault sorter architecture
A HMC vault, in the form of a single stack consists multiple
DRAM banks connected to the logic layer through TSV (Through-
Silicon-vias). A significant advantage of such architecture is al-
lowing high bandwidth and low energy access within local vault
provided by TSV. A highly parallel, flexible and low overhead intra
vault sorting unit is implemented at the logic layer to leverage

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Session 1B: Emerging Memory-Enabled Computing for Future Electronics GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

the high bandwidth at each HMC vault. Figure 2 illustrates the

architecture of the intra vault sorter. It consists of a data loading
unit, input permutation logic, compare-and-swap (CAS) units, and
control unit. The data loading unit is responsible for loading inputs
from local DRAM banks into the sorting units internal registers
and writing result in-place to the DRAM banks. The n-input per-
mutation unit grouped with n compare-and-swap (CAS) units sort
inputs in parallel. The sorting mechanism is based on Batcher’s
Bitonic network described in [13]. Figure 3 illustrates a simple 8
input Bitonic sorting network. A naive implementation of n-input
Bitonic sorting network takes significant amount of space due to
the 𝑂 ( log2 𝑛 ) space complexity. In our architecture, we fold the
network into a single stage of n parallel compare-and-swap units
along with a inter-stage input permutation unit. The permutation
unit, shuffles the intermediate results as per the current Bitonic
sorting stage and feeds them to appropriate CAS units. In addition,
to further minimize the performance and space overhead, input
permutation unit is implemented as a semi-crossbar permutation
network by exploiting the regularity of data-movement in Bitonic
Figure 4: IMC-Sort intra-vault N-input semi-crossbar permu-
network. Bitonic sorting network works by recursively applying a
tation unit

BH2 BH4 BH2 BH8 BH4 BH2 2.2 Intra-vault merging

6 6 3 2 2 1 0 In order to support various lengths of input sequences with fixed
number of CAS units, and fixed input permutation unit, we sort the
7 7 2 3 3 0 1
sequence in chunks (chunk size is determined by number of CAS
3 3 6 6 1 2 2 units etc.) and merge the sorted values into single sorted sequence.
Given two sorted list a,b with each size of 𝑛/2, a concatenation
2 2 7 7 0 3 3
of a and inversion of b is a Bitonic sequence. Thus, applying a
4 1 5 5 5 5 4 single stage of Bitonic half cleaner 𝐵𝐻𝑛 can separate the lower
half and higher half in one stage. The result is then another four
1 4 4 4 4 4 5
sorted list separated in lower and higher halves. By scheduling
5 5 1 1 6 6 6 half cleaner operation recursively (𝐵𝐻𝑛− > 𝐵𝐻 (𝑛/2)− > 𝐵𝐻 (𝑛/4)
etc.) a globally sorted list can be obtained in 𝑂 ( log 𝑛 ) stages. An
0 0 0 0 7 7 7 example of merging two list of size 4 is illustrated in Figure 5. With
the merging capability, the intra-vault sorter can easily sort data
larger than its input size. In larger context, when merging two lists
Figure 3: Over view of steps in the bitonic sorting network with arbitrary size, assuming sorter input size (number of CAS
units etc.) 𝑛, a single intra-vault sorting unit can emit 𝑛/2 numbers
every 𝑂 ( log 𝑛 ) stages which is significantly higher than ordinary
software based 1 number per cycle merging.
Bitnoic half cleaner. A Bitonic sorting network for n-input sequence
𝑙𝑜𝑔 (𝑛) (𝑙𝑜𝑔 (𝑛)+1)
consists of 2 Bitonic half cleaners. Each bitonic half 2.3 Inter-vault sorting
cleaner 𝐵𝐻𝑥 is a single compare-and-swap stage with every in-
Intra-vault sorting network performs sorting of arbitrary length
put i compared with input i+x/2. For example, an 8 input Bitnoic
sequences within a vault. Inter-vault sorting mechanism merges
sorter consists of 6 Bitonic half cleaners connected in a sequence
the sorted values/sequences from all the vaults to obtain a global
as 𝐵𝐻 2− > 𝐵𝐻 4− > 𝐵𝐻 2− > 𝐵𝐻 8− > 𝐵𝐻 4− > 𝐵𝐻 2 illustrated in
sorted sequence. In subsequent sections, we discuss the address
Figure 3. In this example, the data permutation unit needs to support
mapping strategy to distribute the input sequence across different
3 permutations which are 𝐵𝐻 2, 𝐵𝐻 4,and 𝐵𝐻 8 Thus, for a sorting
vaults and strategies for merging the results across vaults.
network with size 𝑛 , we only need 𝑂 ( log 𝑛 ) of data permuta-
tions instead of a fully connected 𝑂 (𝑛 2 ) crossbar network. Figure 4 2.3.1 Address Mapping: In the stacked HMC memory organiza-
shows the logical view of a 8 input semi-crossbar permutation net- tion, direct high bandwidth access is guaranteed only within local
work. The sequence of required input pattern is implemented as vaults. Also, the intra-vault sorter operates by accessing a block of
lookup table. During execution, control unit activates the required data within consecutive addresses, which indicates consecutive ad-
permutation accordingly as per the network stage. Similarly, the dresses of data is desired to mapped in the same vault. On the other
ascending/descending sequence of each CAS unit is predetermined hand, in order to enable inter-vault parallelism, blocks of data need
and implemented as a simple lookup table. to be distributed evenly across all vaults. The default HMC address

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 Session 1B: Emerging Memory-Enabled Computing for Future Electronics
BH8 BH4 BH2
2 2 1 0
3
sorted
3 0 1 obtained.
6 1 2 2
7
sorted
0 3 3 methodology used for evaluation of IMC-Sort architecture. We
5 5 5 4
4 4 4 5
sorted
1 6 6 6
0 width per cycle. In this particular configuration, intra-vault sorting
7 7 7
Figure 5: Overview of the steps in Bitonic sorting network
based merge operation
mapping which interleaves addresses across all vaults is then not
suitable. We adopt a simple optimization to map every 4KB page in
the same vault to facilitate both intra-vault and inter-vault sorting
mechanisms. We leverage the user-defined address mapping mode
of the HMC to perform the above mentioned custom mapping.
2.3.2 Sorting Strategy: As each vault can sort and merge blocks
of data independently in parallel, two types of strategies can be
adopted to distribute the global sorting task. The first strategy will
be sampling and bucketing the task into non-overlapping chunks
of data, and then re-distribute across vaults. Thus, after each vault
finishes its sub-task (sorting) independently, a global sorted list is
obtained. Such mechanism relies on the host-CPU sampling strat-
egy, the performance can vary greatly depending on the data dis-
tribution and sampling which does not represent a general case.
However, in ideal cases where the value distribution of sort task
is known before, sampling and bucketing can be highly efficient.
The second strategy will be progressively merging across vaults
after each independent vault finishes its local task. This represents
a more general case where data already resides across vaults, and
a global sorting is requested. In HMC memory organization, each
vault acts as an independent memory controller which can also
send read request into device crossbar like a host to read the data
from other vaults. This allows the intra-vault sorting unit to bring-
in non-local data from other vaults and merge across two different
vaults, the result is then sent to a pre-allocated memory space. We
adapt the second strategy in IMC-Sort architecture to have flexi-
bility to support sorting in a more generalized manner. Consider a
HMC organization with 32 vaults, first each of the vaults perform
sort and merge operations to sort their input sequences of arbi-
trary length (data to be sorted within each vault) independently in
parallel resulting in 32 sorted sequences. Next, in parallel, every
pair of 2 vaults merges data into a single list resulting in 16 sorted
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GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
sequences using the HMC crossbar network. Due to the address
mapping optimization, every vault should have similar size of data,
either vault can be activated to operate the merging, the merge step
across the vaults will be repeated until a single global sorted list is
3 EVALUATION
In this section, we discuss the implementation and evaluation
also compare performance and energy efficiency of IMC-Sort archi-
tecture with GNU implementation of parallel sort on CPU and state-
of-the-art FPGA based near memory accelerator architecture [10].
3.1 Area and Power Model
For the performance and energy evaluation we have configured
the IMC-Sort architecture to accept 64 inputs, each with 64 bit
unit can sort and output 64 inputs every 21 cycles which trans-
lates to approximately 18 GB/s throughput per vault. Considering
the HMC vault’s bandwidth of 16GB/s, the chosen configuration
can sufficiently saturate the intra-vault bandwidth. A larger design
will have minimal benefit due to bandwidth saturation and also
introduce significant routing overhead. For the area and power
estimation of custom intra-vault sorting logic, we have synthesized
the design at 800 MHz using Synopsis Design Compiler at 32nm
technology node. Each intra-vault sorting unit has an area foot-
print of 0.19𝑚𝑚 2 and an average power consumption of 21𝑚𝑤.
Considering the total number of 32 vaults in HMC memory system,
the overall area and average power consumption of intra-vault
sorting units are 6.08𝑚𝑚 2 and 0.67𝑊 respectively. Each vault in
HMC memory system has a headroom of 3.5𝑚𝑚 2 [14], IMC-Sort
architecture’s intra-vault sorting unit is well within this area head-
room. The IMC-Sort architecture is functionally verified using a
custom cycle accurate model which models the the parallel vault
accesses and crossbar interconnection in HMC memory system.
For performance and power evaluation purposes, we fed the area
and power numbers from synthesis for the intra-vault sorting unit
to the model. For the energy consumption for HMC accesses, we
have assumed 4pj/bit for low level DRAM accesses, 2pJ/bit for vault
access, 0.05pJ/bit for TSV, and 4pJ/bit off-chip SerDes link as re-
ported in [15]. The custom cycle accurate model is built using the
PyMTL3 [16] framework.
3.2 Performance and Energy Evaluation
We have compared the performance and energy consumption of
IMC-Sort architecture with GNU parallel sort implementation [17]
executed on a 8-threaded CPU in Amazon cloud instance. Figure 6
shows the speedup in execution time and energy savings of the IMC-
Sort architecture normalized to CPU implementation. We have used
datasets ranging from 32 MB to 4GB with 64 bit keys for the evalu-
ation. As shown in the Figure 6, IMC-Sort architecture achieves an
average speedup of 16.8× and average energy savings of 375.5× w.r.t
to the CPU implementation. The performance and energy gains
over CPU implementation can be attributed to efficient utilization
of available high bandwidth across each HMC vault with custom
sorting unit in the logic layer. Figure 7 shows the comparison of
Session 1B: Emerging Memory-Enabled Computing for Future Electronics GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

Performance/Energy Comparison
near-memory FPGA based sorting accelerator architecture Bon-
18 450
sai [10]. We have used datasets ranging from 32 MB to 4GB with
16 400
14 350
64 bit keys for the evaluation. Bonsai proposed an unrolled merge
tree sorting architecture for a similar multi channel stacked mem-

Energy Savings
12 300
Speedup

10 250 ory system-HBM. We apply this same mechanism for performance

8 200
6 150
4 100
2 50
0 0
32 64 128 256 512 1024 2048 4096
Dataset Size (MB)
Normalized Speedup Normalized Energy Savings
Figure 6: Speedup in execution time and energy savings of
IMC-Sort architecture normalized to GNU implementation
on CPU
IMC-Sort architecture with custom intra-vault sorting unit with re-
spect to IMC-Sort architecture which uses native HMC instruction
set (atomic compare-and-swap (CAS) instruction) to perform intra-
vault sorting operation for various input sequence lengths. The
atomic CAS instruction only supports a single 8 or 16 byte swap of
a memory operand with an immediate operand. We generated the
sequences of atomic CAS requests and interfaced with HMC_sim
comparison, where an unrolled merge tree is attached to every
vault. In order to saturate the available bandwidth of 16GB/s per
vault, a 2 way 16 throughput merge tree is used. As shown in Fig-
ure 8, IMC-Sort architecture achieves an average speedup of 1.1×
and average energy savings of 13.6× w.r.t to the Bonsai architec-
ture. By analyzing the custom cycle accurate model traces, we infer
that performance gain mainly comes from the initial sorting phase
where small sorted lists are created. In our design, a sorted list
of size 64 can be quickly obtained within one invocation of the
intra-vault sorting unit, while Bonsai merge tree requires multiple
runs to obtain a sorted list of size 16 and then progressively merge
into a sorted list of size 64. The energy gains can be attributed to
the custom optimized implementation of Bitonic sorting network-
based intra-vault sorting unit with lesser hardware requirements
in comparison to Bonsai architecture.
Performance/Energy Comparison
1.11 14.2
1.108 14
1.106 13.8

Energy Savings
2.0 [18] to analyze the performance. Resultant execution cycles are 1.104 13.6
Speedup

normalized and compared with the IMC-Sort custom intra-vault 1.102 13.4
sorting unit implementation. As shown in Figure 7, custom intra- 1.1 13.2
vault sorting unit design achieves an average speedup of 17.1× and 1.098 13
average energy savings of 14.5×. The performance and energy gains 1.096 12.8
can be attributed to sufficiently utilizing the available intra-vault 1.094 12.6
32 64 128 256 512 1024 2048 4096
bandwidth with parallel CAS units. Instead of executing sequence
Dataset Size (MB)
of CAS instructions ( 8 or 16 byte granularity) per vault, custom
sorting unit accesses data at a 256 byte granularity and performs Normalized Speedup Normalized Energy Savings
several CAS operations in parallel resulting in the performance and
energy gains. Figure 8: Speedup in execution time and energy savings
of IMC-Sort architecture normalized to Bonsai architec-
Performance/Energy Comparison
ture [10]
25 18
16
20 14
4 CONCLUSION
Energy Savings

12
Speedup

15
10 In this paper, we present a processing-in-memory architecture
8
10 called IMC-Sort which incorporates custom intra-vault sorting unit
6
5 4 at HMC vault’s logic layer to perform parallel sort operation. The
2 intra-vault sorting unit along with the vault controller is further
0 0 used to merge the sorted results from the individual sorts by moving
4 8 16 32 64 the data elements across the vaults using HMC’s crossbar network.
Number of Data Elements (x1024)
IMC-Sort also uses custom address mapping for distributing input
Nornalized Speedup Normalized Energy Savings data elements across vaults and custom Bitonic sorting network
input permutation units and folded compare and swap units for
Figure 7: Speedup in execution time and energy savings of reducing the hardware requirements. IMC-Sort achieved 16.8×,
IMC-Sort architecture with custom intra-vault logic normal- 1.1× speedup and 375.5×, 13.6× savings in energy consumption
ized to IMC-Sort architecture using native HMC instruction compared to the widely used CPU implementations and state-of-
set the-art near memory custom sort accelerator. The performance and
energy gains of IMC-Sort architecture are due to efficient utilization
Figure 8 shows the speedup in execution time and energy savings of high intra-vault bandwidth at each of the HMC vaults with
of the IMC-Sort architecture normalized to the recently proposed custom efficient parallel sorting hardware.

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Session 1B: Emerging Memory-Enabled Computing for Future Electronics GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

ACKNOWLEDGMENTS [8] A. Farmahini-Farahani, H. J. Duwe III, M. J. Schulte, and K. Compton, “Modu-

lar design of high-throughput, low-latency sorting units,” IEEE Trans. Comput.,
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poration (SRC) Center for Research in Intelligent Storage and Pro- [9] S. H. Pugsley, A. Deb, R. Balasubramonian, and F. Li, “Fixed-function hardware
sorting accelerators for near data mapreduce execution,” in 2015 33rd IEEE Inter-
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[10] N. Samardzic, W. Qiao, V. Aggarwal, M. F. Chang, and J. Cong, “Bonsai: High-
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