EXPERIMENT VII

COMBINATIONAL LOGIC CIRCUITS

I. OBJECTIVES

1. To develop the truth table for a combinational logic circuit problem.

2. To read the sum-of-products expressions from the table, and plot it on a Karnaugh map.

3. To use the Karnaugh map to simplify the sum-of-products expressions.

4. To build and test a circuit that implements the simplified expression.

II. DISCUSSION

In combinational logic circuits, the outputs are determined solely by inputs. For instance,
a 2-bit comparator may be programmed to output HIGH if one 2-bit value is greater than another
2-bit value. A truth table makes it simpler to assess this information. There is a clear
identification of each conceivable input combination, and the desired result is displayed. Finding
the most efficient method to build the particular circuit by making it simpler is the next stage in
realizing the circuit. In contrast to Sequential Logic Circuits, whose outputs are dependent on
both their current inputs and their previous output state, providing them with some form of
Memory. Combinational Logic Circuits' outputs are only determined by the logical function of
their current input state, logic "0" or logic "1," at any point in time.

The function's truth table is used to generate the results, which are later plotted on a
Karnaugh map. With 4 or less inputs, Karnaugh mapping is typically the best choice, but logic
designers should keep other options in mind. After drawing the Karnaugh map, the smallest sum-
of-products can be defined using a variety of ways.

III. MATERIALS & EQUIPMENT

● 7400 NAND gate

● LED
● 330 Ω resistor
● 7243 OR gate
IV. CIRCUIT DIAGRAM

Figure 7.1 Circuit Diagram with 1 OR Gate and 1 NAND Gate

Figure 7.2 Circuit Diagram with 4 NAND Gates

 Figure 7.3 Circuit Diagram with 3 NAND Gates and 1 OR Gate

V. PROCEDURE

1. Complete the truth table shown in Table 5.1 containing all possible inputs and desired output. Assume
that the desired output for a valid code is a 1 and for invalid code a 0. D is the most significant bit and

letter A is the least significant bit.

2. Plot the result of Table 5.1 in a Karnaugh map. Group the 1s according to the rules. Read the minimum

sum-of-products expression from the map and write the Boolean expression below :

X = DB+DC
 3. Apply de Morgan’s theorem to your expression above and write the resulting expression

X = (D’+B’)(D’+C’)
Solution: X = (DB+DC)’= (DB)’(DC)’

4. Using the result of Table 5.1, group all zeros on the Karnaugh map. Write the expression for X’

X’ = D(C+B)

5. Construct the circuit shown in Figure 5.2 and Figure 5.3. Test all possible inputs shown in Table 5.2

and Table 5.3 for any possible output. Complete the table.

VI. DATA

Table 7.1 Circuit with 1 OR Gate and 1 NAND Gate

INPUTS
OUTPUT (X)
D C B

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1
 Figure 7.4 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=0, C=0, B=0)

Figure 7.5 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=0, C=0, B=1)

Figure 7.6 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=0, C=1, B=0)
 Figure 7.7 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=0, C=1, B=1)

Figure 7.8 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=1, C=0, B=0)

Figure 7.9 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=1, C=0, B=1)
 Figure 7.10 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=1, C=1, B=0)

Figure 7.11 Circuit Diagram with 1 OR Gate and 1 NAND Gate (D=1, C=1, B=1)

Table 7.2 Circuit with 4 NAND Gates

INPUTS
OUTPUT (X)
C B A

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1
1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Figure 7.12 Circuit Diagram with 4 NAND Gates (C=0, B=0, A=0)

Figure 7.13 Circuit Diagram with 4 NAND Gates (C=0, B=0, A=1)
Figure 7.14 Circuit Diagram with 4 NAND Gates (C=0, B=1, A=0)

Figure 7.15 Circuit Diagram with 4 NAND Gates (C=0, B=1, A=1)

Figure 7.16 Circuit Diagram with 4 NAND Gates (C=1, B=0, A=0)
Figure 7.17 Circuit Diagram with 4 NAND Gates (C=1, B=0, A=1)

Figure 7.18 Circuit Diagram with 4 NAND Gates (C=1, B=1, A=0)

Figure 7.19 Circuit Diagram with 4 NAND Gates (C=1, B=1, A=1)
Table 7.3 Circuit with 3 NAND Gates and 1 OR Gate
INPUTS
OUTPUT (X)
D C B

0 0 0 1

0 0 1 1
0 1 0 1

0 1 1 1
1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Figure 7.20 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=0, C=0, B=0)

Figure 7.21 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=0, C=0, B=1)
Figure 7.22 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=0, C=1, B=0)

Figure 7.23 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=0, C=1, B=1)

Figure 7.24 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=1, C=0, B=0)
Figure 7.25 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=1, C=0, B=1)

Figure 7.26 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=1, C=1, B=0)

Figure 7.27 Circuit Diagram with 3 NAND Gates and 1 OR Gate (D=1, C=1, B=1)
VII. ANALYSIS OF DATA

The first table which the data is derived from figure 7.1 utilizes one NAND and OR gate.
The possible outputs were determined through careful analysis of the circuit in which it is written
and presented in a tabular form. The table tells us that the output was only high in three scenarios
wherein the input is 101, 110, and 111. This tells us that the output is high if the input from D is
high and the other two inputs are also high. It signifies that the input in D will determine whether
the circuit is in a high or low state.
The second table which is derived from figure 7.2 utilizes four NAND gates. The possible
outputs were also determined through careful analysis of the circuit to which it was also written
and presented in a tabular form. The table tells us that the output was high in three scenarios
wherein the input is 011, 101, and 111. According to the acquired data, input is responsible for
determining whether the output is high or low.
The third table which is derived from figure 7.3 utilizes three NAND gates and one OR
gate. The outputs were also determined by carefully analyzing the circuit. Based on the acquired
data, the output was low in only one scenario which is the input 111. According to the table, the
output is low if the inputs in B, C, and D are high. It also tells us that even if inputs in B, C, and
D are a combination of high and low, which can also be represented as 1 and 0, the output would
always be high. The output will only be low if all the inputs are high.

VIII. CONCLUSION

We learned about boolean expressions, how to simplify logic circuits and expressions using
Boolean Algebra, and DeMorgan's theorems in this lab experiment. We discovered that a
boolean expression and a simplified expression have the same truth table values. Finally, this
experiment was completed successfully and all objectives were met. We can also recommend
this experiment for future reference if necessary.
IX. QUESTIONS/PROBLEMS

1. Assume that the circuit in Figure 5.3 indicates an invalid codes for binary 1000 and 1001 in addition to
the other invalid codes. What fault could cause this indication?

- The circuit can only accept three inputs that's why the 4-bit code is not applicable

2. BCD is a 4-bit code, yet the least significant bit was not in the circuits above. Why not?

- Because all the circuits above can only accept 3 input code that's why a 4-bit code is not

applicable

X. APPLICATIONS

1. A man, goat wolf and cabbage wish to cross a river in a boat. The man, who must row, can either take
the goat, wolf or cabbage with him during a single trip across the river. If, however, the wolf and goat

are together without the man, the wolf will eat the goat. If the goat and cabbage are together without

the man, the goat will eat the cabbage. The objective is to get the man, goat, wolf and cabbage across

the river in the boat without a disaster occurring, without someone being eaten.

a. Derive a truth table, which could be used to design a combinational circuit.

Man (M) Cabbage (C) Goat (G) Wolf (W) Output (X)

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 1

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0
1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

b. Draw the Karnaugh map to simplify the solution, and derive the minimum expression for a

disaster.

GOAT and WOLF

00 01 11 10

00 1

MAN and
CABBAGE 01 1 1

11 1 1

10 1

c. Draw the simplified logic diagram.