AI Applications in DC-DC Converter Design

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Applications of artificial intelligence in the circuit
and modulation design of DC‑DC converters
Li, Xinze
2023
Li, X. (2023). Applications of artificial intelligence in the circuit and modulation design of
DC‑DC converters. Doctoral thesis, Nanyang Technological University, Singapore.
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Applications of Artificial Intelligence in the Circuit and
Modulation Design of DC-DC Converters
LI XINZE
School of Electrical and Electronic Engineering
2023
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Applications of Artificial Intelligence in the Circuit and
LI XINZE
School of Electrical and Electronic Engineering
A thesis submitted to the Nanyang Technological University in partial

fulfillment of the requirement for the degree of
Doctor of Philosophy
2023
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Statement of Originality
I hereby certify that the work embodied in this thesis is the result of original
research, is free of plagiarised materials, and has not been submitted for a higher
degree to any other University or Institution.
25-01-23
................. ...........................
Date Li Xinze
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Supervisor Declaration Statement
I have reviewed the content and presentation style of this thesis and declare it is free
of plagiarism and of sufficient grammatical clarity to be examined. To the best of
my knowledge, the research and writing are those of the candidate except as
acknowledged in the Author Attribution Statement. I confirm that the investigations
were conducted in accord with the ethics policies and integrity standards of
Nanyang Technological University and that the research data are presented honestly
and without prejudice.
25-01-23
................. ...........................
Date Mao Kezhi
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Authorship Attribution Statement
This thesis contains materials from 5 papers published or under review in the following
peer-reviewed journals where I was the first author.
Chapter 3 is published as X. Li, X. Zhang, and F. Lin, ‘Multi-Objective Design of Output

LC Filter for Buck Converter via the Coevolving-AMOSA Algorithm’, IEEE Access, vol.
9, pp. 11884–11894, 2021, doi: 10.1109/ACCESS.2020.3034361.
The contributions of the co-authors are as follows:

• I programed the design approach, conducted the hardware experiments and prepared
the manuscript drafts.
• Prof. Zhang Xin provided the initial research direction and edited the manuscript drafts.
• Lin Fanfan were responsible for editing, polishing, and proofreading.
Chapter 4 is published as X. Li, X. Zhang, F. Lin, and F. Blaabjerg, “Artificial-Intelligence-

Based Design (AI-D) for Circuit Parameters of Power Converters,” IEEE Trans. Ind.
Electron., pp. 1–1, 2021, doi: 10.1109/TIE.2021.3088377.

• I proposed the initial research ideas, programed the automated design algorithms,
conducted hardware experiments, and prepared the manuscript drafts.
• Lin Fanfan assisted with regards to the hardware experiments, idea reconstruction,
paper revision, language polishing, and proofreading.
• Prof. Zhang Xin and Prof. Frede Blaabjerg were responsible for revising, polishing,
and proofreading.
Chapter 5 is published as X. Li, X. Zhang, F. Lin, C. Sun, and K. Mao, ‘Artificial-

Intelligence-Based Triple Phase Shift Modulation for Dual Active Bridge Converter with
Minimized Current Stress’, IEEE J. Emerg. Sel. Top. Power Electron., pp. 1–1, 2021, doi:
10.1109/JESTPE.2021.3105522.
ix
• I proposed the initial research ideas, programed the automated modulation design
algorithms, constructed the FPGA modules, conducted hardware experiments, and
prepared the manuscript drafts.
• Lin Fanfan assisted with regards to the hardware testing, paper editing, language
polishing, and proofreading. Dr. Sun Changjiang helped in modulation scheme.
• Prof. Zhang Xin and Prof. Mao Kezhi were responsible for polishing and proofreading.
Chapter 6 includes two journal papers. One is published as X. Li, K. Mao, F. Lin, and X.
Zhang, “Particle swarm optimization with state-based adaptive velocity limit strategy,”
Neurocomputing, vol. 447, pp. 64–79, Aug. 2021, doi: 10.1016/j.neucom.2021.03.077.

• I proposed the initial ideas, performed the experiments, and prepared the manuscripts.
• Prof. Mao Kezhi and Lin Fanfan assisted with regards to the idea reconstruction, paper
revision, paper editing, language polishing, and proofreading.
• Prof. Zhang Xin helped with paper editing, language polishing, and proofreading.
Another paper of Chapter 6 is published as X. Li, X. Zhang, F. Lin, C. Sun and K. Mao,
"Artificial-Intelligence-Based Hybrid Extended Phase Shift Modulation for the Dual
Active Bridge Converter with Full ZVS Range and Optimal Efficiency," in IEEE J. Emerg.
Sel. Top. Power Electron., doi: 10.1109/JESTPE.2022.3185090.
• I proposed the initial research ideas, programed the automated hybrid modulation
design algorithms, constructed the FPGA modules, conducted hardware experiments,
and prepared the manuscript drafts.
• Lin Fanfan assisted with regards to the hardware testing, paper editing, language
polishing, and proofreading. Dr. Sun Changjiang helped in ZVS analysis.
• Prof. Zhang Xin and Prof. Mao Kezhi were responsible for polishing and proofreading.
11-01-23
................. ...........................
Date Li Xinze
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Acknowledgements
Ph.D. journey is hard. The road is rugged, and the mist blurs the path. Thankfully, I have
the support of mentors, family, and companions. I am extremely grateful for all the people
along the road. Thank you all for lighting the way for me.
Foremost, let me express my sincere appreciation to my supervisors, Prof. Mao Kezhi
and Prof. Zhang Xin. It was your patient guidance, illuminating advice, and constant
supervision that encouraged me to move ahead. You made this thesis possible.
I am also genuinely thankful for my technical advisory committee members, my
qualifying examination members, and my oral defense members: Prof. Tang Yi, Prof. Josep
Pou, Prof. Wang Huai, Prof. Wang Youyi, Prof. Wang Danwei, and Prof. Chan Chok You,
John. It was your technical support and emotional encouragement that ensured the right
progress of my research.
I also want to thank for the professional supports from the postdocs in my group: Prof.
Zeng Zheng, Prof. Huang Jingjing, Dr. Sun Changjiang, Prof. Cheng Fanyong, Dr. Peng
Yelun, Dr. Li Zhan, Prof. Zhao Bin, Prof. Ma Zhixun, Prof. Cai Hui.
My appreciation also goes to the professors who gave lectures in Nanyang Technological
University. The knowledge learned in class has accompanied me throughout the whole
journey. The support from my friends was also precious to me. We are comrades struggling
towards the victory. My heartfelt thankfulness also goes to Nanyang Technological
University for offering this invaluable opportunity, giving financial support, and providing
lab facilities for me. I am always a part of Nanyang Technological University.
Last but not least, I would like to express my appreciations to my parents, grandparents,
and relatives for their continuous support and care in the past 26 years. Specially, I would
like to thank my girlfriend Ms. Lin for being there for me all the time. When I was in the
valley, inclining to drop, it was you who dragged me up to the ground. It was you who gave
me the courage and motivation to keep going when I had nothing and hopeless. It was you
who encouraged me to try out new things, and because of that, I am much clearer about my
future path now. Thank god for arranging the day I kissed you. Because without you, I
wouldn’t be me.
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Table of Contents
Acknowledgements ............................................................................................................ i
Table of Contents .......................................................................................................... iii
List of Tables .................................................................................................................... ix
List of Figures................................................................................................................... xi
List of Abbreviations .................................................................................................... xvii
Nomenclature ...................................................................................................................xx
Abstract ....................................................................................................................... xxvii
Chapter 1 Introduction ..................................................................................................1

1.1 Research Background ...............................................................................................2
1.2 Circuit Design and Modulation Design of DC-DC Converters ...............................6
1.3 Motivation and Objectives .......................................................................................8
1.4 Major Contributions of This Thesis .......................................................................11
1.5 Organization of This Thesis ...................................................................................13
Chapter 2 Literature Review ......................................................................................15

2.1 Topology and Applications of DC-DC Converters ................................................16
2.2 Circuit Parameter Design Approaches for DC-DC Converters .............................19
2.2.1 Various Design Parameters of DC-DC Converters ....................................20
2.2.2 Various Design Objectives of DC-DC Converters .....................................21
2.2.3 Existing Circuit Parameter Design Approaches for DC-DC Converters ........... 22
2.3 Modulation Approaches for DC-DC Converters ...................................................25
2.3.1 Major Modulation Techniques for DC-DC Converters ..............................25
2.3.2 Phase Shift Modulation Approaches for DAB Converters .........................27
2.4 Applications of AI Algorithms in the Design of DC-DC Converters ....................30
2.4.1 Basic Introduction to Artificial Intelligence ...............................................30
2.4.2 Applications of AI Algorithms in the Life Cycle of Power Electronics ....37
2.4.3 Applications of AI Algorithms in the Circuit and Modulation Design of DC-
DC Converters ............................................................................................38
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2.5 Summary ................................................................................................................41
Chapter 3 Multi-Objective Design of Output LC Filter for Buck Converter via the
Coevolving-AMOSA Algorithm ....................................................................................42
3.1 Introduction ............................................................................................................43
3.2 Problem Descriptions for the Multi-Objective Design of the Output LC Filter in
Buck Converters .....................................................................................................45
3.2.1 Preliminaries: Introduction to Pareto Frontier ............................................45
3.2.2 Problem I: Trade-off Relationships among the Three Design Objectives for
the Output LC Filter in Buck Converter .....................................................46
3.2.3 Problem II: The Nonuniform and Incomplete Coverage of Pareto Frontier
.....................................................................................................................47
3.3 Analysis of Three Design Objectives for LC Filters: Power Efficiency, Cutoff
Frequency, and Volume .........................................................................................48
3.3.1 Analysis of Design Objective 1: Optimized Total Power Loss for the Buck
Converter of Optimal Power Efficiency .....................................................48
3.3.2 Analysis of Design Objective 2: Optimized Cutoff Frequency for the Buck
Converter with Optimal Filtering Capability .............................................51
3.3.3 Analysis of Design Objective 3: Optimal Volume for a Compact Buck
Converter ....................................................................................................51
3.4 The Proposed Multi-Objective Design Approach for the Output LC Filter in Buck
Converter with Coevolving AMOSA algorithm ....................................................54
3.4.1 Stage 1: Analysis of Three Design Objectives ...........................................54
3.4.2 Stage 2: Multi-Objective Optimization of the Three Design Objectives with
the Coevolving-AMOSA Algorithm ..........................................................54
3.4.3 Stage 3: Obtain the Optimal Design Solution Based on Application
Requirements ..............................................................................................58
3.5 Design Examples of the Proposed Multi-Objective Design for the Output LC Filter
in Buck Converter with Coevolving-AMOSA Algorithm .....................................58
3.5.1 Design Example with Traditional Design Method .....................................58
3.5.2 Design Examples with the Proposed Multi-Objective Design of Output LC
Filter for Buck Converter with the Coevolving-AMOSA ..........................59
iv
3.6 Experimental Verifications ....................................................................................62
3.6.1 Experimental Waveforms of the Traditional Design Case and Three Optimal
Design Cases ..............................................................................................63
3.6.2 Evaluation of the Experimental Results .....................................................64
3.7 Conclusion...............................................................................................................66
Chapter 4 NN-Based Automated Design for Circuit Parameters of Power

Converters .......................................................................................................................68
4.1 Introduction ............................................................................................................70
4.2 Problem Descriptions for the Parameter Design Approaches for Power Converters
and the Proposed Solutions ....................................................................................72
4.2.1 Problems in the Existing Circuit Parameter Design Approaches for Power
Converters ..................................................................................................72
4.2.2 The Proposed Solutions for the Automated Design for the Circuit Parameters
of Power Converters ...................................................................................73
4.3 AI-D Approach for the Parameter Design of Power Converters ...........................76
4.3.1 Stage 1: Determine Design Specifications ..................................................79
4.3.2 Stage 2: Create Lookup Tables for Inductors and Capacitors ....................79
4.3.3 Stage 3: Build Data-Driven Models for Power Losses, Voltage Ripple and
Current Ripple ............................................................................................82
4.3.4 Stage 4: Search for Optimal Design Parameters fs*, L*, C* via Genetic
Algorithm ...................................................................................................86
4.4 Design Case of the Proposed AI-D Approach to Design an Efficiency-Optimal
Synchronous Buck Converter in EV ......................................................................87
4.4.1 Determine Design Specifications ................................................................87
4.4.2 Create Lookup Tables for Inductors and Capacitors ..................................89
4.4.3 Build Data-Driven Models for Power Losses and Ripples .........................90
4.4.4 Search for Optimal fs*, L*, C* via GA .........................................................91
4.4.5 Average CPU Execution Time for Applying the Proposed AI-D Approach
in the Design Case ......................................................................................92
4.5 Experimental Verification ......................................................................................93
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4.5.1 Steady-State Waveforms of the Designed Optimally Efficient Synchronous
Buck Converter ..........................................................................................94
4.5.2 Experimental Efficiency of the Designed Converter .................................94
4.5.3 Experimental Volume and Ripples of the Designed Converter .................97
4.5.4 Comparison between the Experimental and Theoretical Efficiency, Volume
and Ripples of the Designed Converter ......................................................97
4.6 Conclusion ..............................................................................................................98
Chapter 5 Current-Stress-Minimized Triple Phase Shift Modulation Design for the

Dual Active Bridge Converter Utilizing Neural Networks, Particle Swarm
Optimization, and Fuzzy Inference System ..................................................................99
5.1 Introduction ..........................................................................................................101
5.2 Operating Principle of TPS Modulation and the Existing Challenges .................103
5.2.1 Operating Principle of TPS modulation for DAB Converter ...................103
5.2.2 Challenge Descriptions for Optimization of TPS Modulation with
Minimized Current Stress ........................................................................104
5.3 The Proposed AI-Based TPS Modulation ............................................................107
5.3.1 Stage I: NN-Based Analysis of Current Stress .........................................108
5.3.2 Stage II: Optimization with PSO Algorithm .............................................109
5.3.3 Stage III: Realization of TPS with FIS .....................................................111
5.4 Design Case of Applying the Proposed AI-TPSM ...............................................112
5.4.1 Stage I: NN-Based Analysis of Current Stress .........................................113
5.4.2 Stage II: Optimization with PSO Algorithm .............................................115
5.4.3 Stage III: Realization of TPS with FIS .....................................................116
5.4.4 Computational Resources to Apply the Proposed AI-TPSM Approach in the
Design Case ..............................................................................................118
5.5 Experimental Verification ....................................................................................118
5.5.1 Rated Operating Waveforms .....................................................................119
5.5.2 Operating Waveforms under Different Output Power P and Output Voltage
V2 ..............................................................................................................119
5.5.3 Transient Response under Power and Voltage Step .................................122
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5.5.4 Current Stress and Efficiency Performance of the Optimal TPS Modulation
via the Proposed AI-TPSM ......................................................................126
5.5.5 Comparisons between the Experimental and Theoretical Results of the
Optimal Modulation .................................................................................128
5.6 Conclusion ............................................................................................................129
Chapter 6 XGBoost-Based Hybrid Extended Phase Shift Modulation Design for

the Dual Active Bridge Converter with Full ZVS Range and Optimal Efficiency .130
6.1 Introduction ..........................................................................................................132
6.2 Preliminary: Basics about EPS Modulations .......................................................135
6.2.1 Fundamentals of EPS1 .............................................................................135
6.2.2 Fundamentals of EPS2 .............................................................................136
6.3 Preliminary: Basics about the Proposed PSO-SAVL ...........................................137
6.3.1 Functions of Velocity Limit .....................................................................137
6.3.2 Challenge in the Existing Adaptive Velocity Limit Strategies ................138
6.3.3 Process of the Proposed PSO-SAVL .......................................................139
6.3.4 Experimental Results of the Proposed PSO-SAVL .................................142
6.4 Conventional Modeling Approaches of ZVS and Efficiency ..............................145
6.4.1 Piecewise Approach for Modeling ZVS ...................................................145
6.4.2 Harmonic Approach for Modeling ZVS ...................................................146
6.4.3 Piecewise and Harmonic Approaches for Modeling Efficiency ...............147
6.5 Stage I of The Proposed HEPS Modulation: Build Data-Driven Models of ZVS and
Efficiency ........................................................................................................................148
6.5.1 Stage I: Build Data-Driven Models of ZVS and Efficiency with XGBoost
Algorithm .................................................................................................148
6.5.2 XGBoost Adopted in Stage I of the Proposed HEPS ...............................150
6.6 Stage II of The Proposed HEPS Modulation: Optimize Efficiency with Full ZVS
Operation .........................................................................................................................151
6.6.1 Stage II: Optimize Efficiency with Full ZVS Operation through PSO-SAVL
Algorithm .................................................................................................151
6.6.2 PSO-SAVL Adopted in Stage II of the Proposed HEPS .........................152
6.7 Design Case with the Proposed AI-Based HEPS .................................................154
vii
6.7.1 Stage I: Build Data-Driven Models of ZVS and Efficiency with XGBoost
Algorithm .................................................................................................154
6.7.2 Stage II: Optimize Efficiency with Full ZVS Operation through PSO-SAVL
Algorithm .................................................................................................156
6.8 Experimental Validation ......................................................................................158
6.8.1 Experimental Waveforms .........................................................................158
6.8.2 ZVS Analysis ...........................................................................................161
6.8.3 Transient Response after Voltage and Load Step ....................................161
6.8.4 Efficiency and ZVS Performance of the Proposed AI-based HEPS
Modulation ...............................................................................................167
6.9 Conclusion ............................................................................................................169
Chapter 7 Conclusion and Future Works ...............................................................170

7.1 Conclusion ............................................................................................................171
7.2 Future Works ........................................................................................................172
7.2.1 AI Algorithms Tailored for Power Electronics ........................................172
7.2.2 AI Algorithms in the Life Cycle of Power Electronics: Design, Control, and
Maintenance .............................................................................................174
Author’s Publications ...................................................................................................178

References .......................................................................................................................180
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List of Tables
Table 2.1 Applications of AI in the Design of DC-DC Converters ..................................39

Table 3.1 Pseudo-Code of the Coevolving-AMOSA Algorithm ......................................56
Table 3.2 Design Specifications of Design Examples ......................................................59
Table 3.3 Objective Values of the Three Required Optimal Designs ...............................61
Table 3.4 Inductance and Capacitance of Three Optimal Designs ...................................61
Table 3.5 Hardware Realization of the Three Required Optimal Designs ........................62
Table 4.1 Design Specifications ........................................................................................88
Table 4.2 Mean-Square-Error of the Compared Regression Methods ..............................91
Table 4.3 Designed Converter in the 48 V to 12 V Accessory-Load Power Supply System
of EV via the Proposed AI-D Approach ...........................................................................92
Table 4.4 Theoretical Performance of the Designed Synchronous Buck Converter ........92
Table 4.5 Average CPU Execution Time of the AI-D Approach ......................................92
Table 4.6 Conventionally Designed Synchronous Buck Converter ..................................95
Table 4.7 CAO-Designed Synchronous Buck Converter .................................................96
Table 5.1 Design Specifications ......................................................................................113
Table 5.2 Configuration of NN and Its Optimizer ..........................................................114
Table 5.3 Accuracy of the Trained NN ...........................................................................115
Table 5.4 Configuration of PSO Algorithm ....................................................................115
Table 5.5 Configuration of FIS .......................................................................................117
Table 5.6 Computational Resources to Apply AI-TPSM ................................................118
Table 6.1 Optimization Solutions of PSO Variants on Benchmark Functions with 50-D
..........................................................................................................................................141
Table 6.2 Computation Speed of PSO Variants on Benchmark Functions with 50-D ....142
Table 6.3 Specifications of Design Case .........................................................................155
Table 6.4 Configurations of XGBoost Models of ZVS and Efficiency ..........................155
Table 6.5 Configurations of PSO-SAVL in Stage II .......................................................156
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List of Figures
Fig.1.1. Worldwide renewable energy generation capacity between 1965 and 2020 .........2
Fig.1.2. Typical power converter systems for solar panel, energy storage system, wind
turbines, electric vehicle and hydropower ..........................................................................3
Fig.1.3. Changes of load profile from year 2012 to 2020 ...................................................4
Fig.1.4. ESS with fuel cell, battery units, super capacitor and flywheel ............................4
Fig.1.5. Propulsion, charging and auxiliary power supply systems of EV .........................5
Fig.1.6. Applications of power converters in smart power grid .........................................6
Fig.1.7. A CLLC-type isolated DAB converter and a conventional Buck converter .........7
Fig.1.8. Issues in the traditional methods for the circuit parameter design of DC-DC
converters ............................................................................................................................8
Fig.1.9. Issues in the traditional methods for the modulation design of DC-DC converters
..............................................................................................................................................9
Fig.2.1. Classifications of DC-DC converters ..................................................................16
Fig.2.2. Examples of non-isolated DC-DC converters .....................................................17
Fig.2.3. Examples of isolated DC-DC converters .............................................................18
Fig.2.4. Basic steps of the circuit parameter design of DC-DC converters ......................19
Fig.2.5. Various design parameters in the circuit parameter design of DC-DC converters
............................................................................................................................................20
Fig.2.6. Voltage-mode and current-mode PWM approaches for DC-DC converters .......26
Fig.2.7. Constant on-time and constant off-time VFM approaches for DC-DC converters
............................................................................................................................................26
Fig.2.8. Modulation waveforms of SPS, DPS, EPS and TPS strategies ...........................28
Fig.2.9. Classifications of machine learning algorithms ...................................................32
Fig.2.10. General structure of NN and three widely used networks .................................33
Fig.2.11. Classifications of machine learning algorithms .................................................35
Fig.2.12. Common process of metaheuristic algorithms ..................................................35
Fig.2.13. Mamdani FIS and Sugeno FIS ..........................................................................36
Fig.2.14. General architecture of expert systems ..............................................................37
Fig.2.15. Applications of AI in the life cycle of power electronics ..................................38
Fig.2.16. Flowchart for the design and control of DC-DC converters .............................39
xi
Fig.3.1. Different applications of Buck converters ...........................................................43
Fig.3.2. Example of a Pareto frontier for the minimization of f1 and f2 ............................46
Fig.3.3. Descriptions of the multi-objective design for the LC filter in Buck converter ..46
Fig.3.4. Problem description: nonuniform coverage of the Pareto frontier ......................47
Fig.3.5. Problem description: incomplete coverage of the Pareto frontier .......................48
Fig.3.6. Circuit diagram of the synchronous Buck converter ...........................................48
Fig.3.7. Effects of L and C on total power loss Pl_tot ........................................................50
Fig.3.8. Effects of L and C on cutoff frequency fc ............................................................51
Fig.3.9. Effects of L on volumes of inductors VolL ..........................................................52
Fig.3.10. Effects of C on volumes of capacitors VolC ......................................................52
Fig.3.11. The proposed three-stage multi-objective design of output LC filter for Buck
converter with the coevolving-AMOSA algorithm ..........................................................53
Fig.3.12. Flowcharts of the traditional AMOSA algorithm and the proposed coevolving-
AMOSA algorithm (in which PF represents Pareto frontier) ...........................................55
Fig.3.13. Expected performance of multi-objective algorithms: (a) SPm; (b) MDR .........57
Fig.3.14. Visualized Pareto frontier of power loss, cutoff frequency and volume, where
each blue dot represents an optimal design case ...............................................................60
Fig.3.15. Projected Pareto frontier (blue points): (a) power loss vs. cutoff frequency; (b)
power loss vs. volume; (c) cutoff frequency vs. volume ..................................................61
Fig.3.16. Main circuit of the designed synchronous Buck converter ...............................62
Fig.3.17. Waveforms of the design cases: (a) traditional design; (b) optimal design case 1;
(c) optimal design case 2; (d) optimal design case 3 ........................................................63
Fig.3.18. Experimental and theoretical results of the conventional and optimal design
cases: (a) total power loss; (b) cutoff frequency; (c) volume ...........................................65
Fig.4.1. Realization of design process (human-dependence or automation) in two kinds of
parameter design approaches for power converters: traditional human-dependent design
approach and CAO design approach .................................................................................72
Fig.4.2. Realization of design process in the proposed AI-D approach for the circuit
parameters of power converters ........................................................................................74
Fig.4.3. Automation in the analysis and deduction process in the proposed AI-D ...........74
Fig.4.4. The parameter design of synchronous Buck converter in the 48 V to 12 V
accessory-load power supply system in EV via the proposed AI-D approach .................76
xii
Fig.4.5. Flowchart of the proposed AI-D approach applied in the parameter design of an
efficiency-optimal synchronous Buck converter in EV ....................................................77
Fig.4.6. Toroidal inductor applied in Buck converter .......................................................80
Fig.4.7. Create Lookup Table I for inductors ...................................................................81
Fig.4.8. Create Lookup Table II for capacitors .................................................................82
Fig.4.9. Detailed realization of Stage 3: build data-driven models for power losses and
ripples with simulations and BN-NN ................................................................................83
Fig.4.10. Data-driven modeling of power losses and ripples via BN-NN ........................85
Fig.4.11. Flowchart of GA in searching for the globally optimal fs*, L*, C* ....................86
Fig.4.12. Lookup Table I for inductors: features of the selected cores ............................89
Fig.4.13. Lookup Table I for inductors: discrete values of L ...........................................89
Fig.4.14. Lookup Table II for capacitors: features of selected capacitors ........................90
Fig.4.15. Lookup Table II for capacitors: discrete values of C ........................................90
Fig.4.16. The hardware platform of the designed DC-DC converter ...............................93
Fig.4.17. Steady-state waveforms of the designed efficiency-optimal converter: (a) vin, vo,
io; (b) zoom-in view of vo; (c) vL, iL, iC .............................................................................93
Fig.4.18. Validation of the optimal efficiency of the designed synchronous Buck
converter: (a) fs varies within [0.8fs*, 1.2fs*]; (b) L varies within [230 µH, 350 µH]; (c) C
varies within [81 µF, 168 µF] ............................................................................................94
Fig.4.19. Experimental efficiency comparison of designed converters via the proposed
AI-D approach, the CAO approach and the conventional approach ................................96
Fig.4.20. Loss breakdown of the designed synchronous Buck converter for high (Po =
100 W), medium (Po = 60 W), and low power (Po = 20 W) levels ..................................97
Fig.4.21. Comparison between the experimental and theoretical performance: (a)
efficiency η; (b) volume VolC+VolL; (c) voltage ripple ∆Vo%; (d) current ripple ∆IL% ...98
Fig.5.1. Typical schematic of an isolated DAB converter with single inductor L ..........101
Fig.5.2. Operating principles of TPS modulation ...........................................................104
Fig.5.3. The process to achieve optimal TPS modulation with minimized current stress
and carry out the modulation ..........................................................................................104
Fig.5.4. Challenge descriptions for optimization of TPS modulation ............................105
Fig.5.5. Equivalent circuit of DAB converter with a single L ........................................105
Fig.5.6. Challenge in Stage I: complex segment-by-segment analysis of current stress
xiii
under different operating modes of TPS modulation ......................................................106
Fig.5.7. Challenge II: discrete nature of lookup table for the realization of TPS
modulation ......................................................................................................................106
Fig.5.8. Descriptions for the proposed AI-TPSM ...........................................................107
Fig.5.9. Flowchart of Stage I: analysis of current stress with NN ..................................108
Fig.5.10. Flowchart of Stage II: PSO for optimization ...................................................110
Fig.5.11. Stage III: online realization of TPS with FIS ..................................................111
Fig.5.12. Comparisons between LUT and the adopted FIS ............................................112
Fig.5.13. Structure of the selected NN ............................................................................115
Fig.5.14. Optimal D1 and D2 under different output voltage V2 and different output
power: (a) V2 = 200 V; (b) V2 = 160 V; (c) V2 = 230 V ..................................................116
Fig.5.15. Outputs of FIS with respect to the inputs P and V2: (a) D1; (b) D2 .................117
Fig.5.16. Hardware platform in the experiments ............................................................118
Fig.5.17. Experimental waveforms under rated power of 1000 W and rated output voltage
of 200 V: (a) vp, vs, and iL; (b) V1, V2 and Io ....................................................................119
Fig.5.18. Experimental waveforms under different output power when output voltage is
200 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W ...................................................120
160 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W ...................................................121
230 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W ...................................................122
Fig.5.21. Experimental waveforms given that V2 steps from 200 V to 160 V and V2 steps
from 160 V to 200 V: V1, V2 and Io during voltage step (top); zoom-in view of vp, vs and
iL at Zone 1 and Zone 2 (bottom) ....................................................................................123
Fig.5.22. Experimental waveforms given that V2 steps from 230 V to 200 V and V2 steps
from 200 V to 230 V: V1, V2 and Io during voltage step (top); zoom-in view of vp, vs and
iL at Zone 1 and Zone 2 (bottom) ....................................................................................124
Fig.5.23. Experimental waveforms given that P steps from 1000 W to 500 W and from
500 W to 1000 W under V2 of 200 V: V1, V2 and Io during power step (top); zoom-in view
of vp, vs and iL at Zone 1 and Zone 2 (bottom) ................................................................124
xiv
Fig.5.26. Current stress ipk and efficiency η performance of SPSM, LUT-TPSM and the
optimal TPS modulation via AI-TPSM when output voltage V2 is 200 V: (a) current stress
ipk performance; (b) efficiency η performance ................................................................126
Fig.5.29. Comparisons between the experimental results and the theoretically optimal
results: (a) V2 = 200 V; (b) V2 = 160 V; (c) V2 = 230 V .................................................128
Fig.6.1. Topology of a non-resonant DAB converter with leakage inductance Lr .........135
Fig.6.2. Fundamentals of EPS1 ......................................................................................135
Fig.6.3. Fundamentals of EPS2 .......................................................................................136
Fig.6.4. Problems of the existing adaptive VL strategies: incompatibility between these
strategies and the current searching state of particles .....................................................139
Fig.6.5. Flowchart of the proposed PSO-SAVL .............................................................140
Fig.6.6. The relations between the value of VL and the evolutionary factor f, blue star is
the position of globally best particle, and grey circle is the position of other particles ..141
Fig.6.7. Convergence performance of all the PSO variants on each of the benchmark
functions (a) f1; (b) f2; (c) f3; (d) f4; (e) f5; (f) f6; (g) f7 .....................................................144
Fig.6.8. Equivalent circuits of DAB converter under: (a) EPS1; (b) EPS2 ....................145
Fig.6.9. Example of piecewise approach for modeling ZVS ..........................................146
Fig.6.10. Example of harmonic approach for modeling ZVS .........................................147
Fig.6.11. Modeling efficiency .........................................................................................148
Fig.6.12. Flowchart of Stage I of the proposed AI-based HEPS modulation .................149
Fig.6.13. Boosting training process of XGBoost ............................................................150
Fig.6.14. Flowchart of Stage II of the proposed AI-based HEPS modulation ................152
xv
Fig.6.15. Flowchart of PSO-SAVL applied in Stage II ..................................................153
Fig.6.16. Optimal Din for strategy EPS1 as obtained by Stage II ...................................156
Fig.6.17. Optimal Din for strategy EPS2 as obtained by Stage II ...................................156
Fig.6.18. ZVS ranges of EPS1 and EPS2 with the obtained optimal Din .......................157
Fig.6.19. Optimal efficiency of EPS1 and EPS2 with the obtained optimal Din ............157
Fig.6.20. Efficiency performance of the proposed AI-based HEPS modulation in the
entire voltage and power ranges .....................................................................................157
Fig.6.21. Hardware platform for experimental validation ..............................................158
Fig.6.22. Experimental waveforms under rated conditions when P is 1000 W and V2 is
200 V: (a) V1, V2 and I2; (b) vp, iL and vs .........................................................................159
Fig.6.23. Experimental waveforms under unit gain mode when V2 is 200 V and: (a) P =
500 W; (b) P = 100 W ....................................................................................................160
Fig.6.24. Experimental waveforms under buck mode when V2 is 160 V and: (a) P = 1000
W; (b) P = 500 W; (c) P = 100 W ..................................................................................160
Fig.6.25. Experimental waveforms under boost mode when V2 is 240 V and: (a) P = 1000
W; (b) P = 500 W; (c) P = 100 W ..................................................................................161
Fig.6.26. ZVS waveforms vds1, vgs1, vds3, vgs3, vds5, vgs5, vds7, vgs7, when V2 = 200 V and: (a)
P = 1000 W; (b) P = 500 W; (c) P = 100 W ...................................................................162
P = 1000 W; (b) P = 500 W; (c) P = 100 W ...................................................................162
P = 1000 W; (b) P = 500 W; (c) P = 100 W ...................................................................163
Fig.6.29. Experimental waveforms during voltage steps when load resistance is 57.6 Ω:
(a) vp, iL and vs when V2 steps from 240 V to 160 V and from 160 V to 240 V; (b)
enlarged view of Zone1; (c) enlarged view of Zone2 .....................................................164
Fig.6.30. Experimental waveforms during load steps when V2 = 240 V: (a) vp, iL and vs
when P steps from 1000 W to 500 W and from 500W to 1000 W; (b) enlarged view of
Zone1; (c) enlarged view of Zone2 .................................................................................165
Fig.6.31. Experimental waveforms during load steps when V2 = 160 V: (a) vp, iL and vs
when P steps from 1000 W to 500 W and from 500W to 1000 W; (b) enlarged view of
Zone1; (c) enlarged view of Zone2 .................................................................................166
xvi
Fig.6.32. Experimental efficiency (η) and ZVS performance (nZVS) of SPS, best EPS2,
and the proposed HEPS approach in buck mode when V2 = 160 V ...............................167
Fig.6.33. Experimental efficiency (η) and ZVS performance (nZVS) of SPS, best EPS1,
and the proposed HEPS approach in boost mode when V2 = 240 V ..............................167
Fig.6.34. Experimental efficiency (η) and ZVS performance (nZVS) of the proposed HEPS
approach in unit gain mode when V2 = 200 V ................................................................168
xvii
List of Abbreviations
AI Artificial intelligence
NN Neural network
FIS Fuzzy inference system
MHA Metaheuristic algorithm
AMOSA Archived multi-objective simulated annealing
AI-D Artificial-intelligence-based design
AI-TPSM Artificial-intelligence-based triple phase shift modulation
HEPS Hybrid extended phase shift
XGBoost Extreme gradient boosting algorithm
ESS Energy storage system
EV Electric vehicle
HEV Hybrid electric vehicle
PHEV Plug-in hybrid electric vehicle
FACTs Flexible AC transmission system
HVDC High-voltage DC transmission
APF Active power filter
SVC Static var compensator
STATCOM Static compensator
TCPST Thyristor control phase shifter
UPS Uninterrupted power supply
DAB Dual active bridge
MAB Multiple active bridge
ZVS Zero voltage switching
ZCS Zero current switching
TPS Triple phase shift
ML Machine learning
xviii
GA Genetic algorithm
PSO Particle swarm optimization
PSO-SAVL Particle swarm optimization with state-based adaptive velocity
limit strategy
EMI Electromagnetic interference
CAD Computer-aided design
CAO Computer-aided optimization
E-CAD Enumeration-based computer aided design
DA-CAD Deterministic-algorithm-based computer aided design
MHA-CAD Metaheuristic-algorithm-based computer aided design
NSGA-II Elitist non-dominated sorting genetic algorithm
MOPSO Multi-objective particle swarm optimization
IBEA Indicator-based evolutionary algorithm
PWM Pulse width modulation
PSM Phase shift modulation
VFM Variable frequency modulation
SPS Single phase shift
DPS Dual phase shift
EPS Extended phase shift
ML Machine learning
FNN Feedforward neural network
CNN Convolutional neural network
RNN Recurrent neural network
ACO Ant colony optimization
MISO Multiple input and single output
MIMO Multiple input and multiple output
BN-NN Batch-normalization neural network
LUT Lookup table
xix
SVR Support vector regression
SPSM Single phase shift modulation
LUT-TPSM Lookup-table-based triple phase shift modulation
HM Hybrid modulation
FB1 Primary full bridge
FB2 Secondary full bridge
EPS1 Extended phase shift with inner phase shift in primary full bridge
EPS2 Extended phase shift with inner phase shift in secondary full bridge
VL Velocity limit
PSO-LDIW Particle swarm optimization with linearly decreasing inertia weight
UPSO Unified particle swarm optimization
HPSO-TVAC Hierarchical particle swarm optimization with time varying
acceleration coefficients
FDR-PSO Fitness-distance-ratio based particle swarm optimization
QPSO Quantum particle swarm optimization
APSO Adaptive particle swarm optimization
CLPSO Comprehensive learning particle swarm optimization
PSO-CL-pbest Comprehensive learning particle swarm optimization with pbest
RODD-PSO Randomly occurring distributedly delayed particle swarm
optimization
GNN Graph neural network
xx
Nomenclature
Pl_dr Driving loss of switches

QG Total gate charge of switches
Vgs Gate-source voltage
f Switching frequency
Pl_on Conduction loss of switches
Vin Input voltage
Vo Output voltage
Io Output current
D Duty ratio of Buck converter
Ron Drain-source resistance of switches
Pl_s Switching loss of switches
tr_H Rising time of high-side switch
tf_H Falling time of high-side switch
tr_L Rising time of low-side switch
tf_L Falling time of low-side switch
VSD Drain-source voltage across switches
Pl_Fe Core loss of inductor
k Coefficient of Steinmetz equation
α Coefficient of Steinmetz equation
β Coefficient of Steinmetz equation
Pl_Cu Copper loss of inductor
Rdc Equivalent DC resistance
Rac Equivalent AC resistance considering proximity and skin effects
Pl_C Capacitor loss
ICk The kth harmonic component of capacitor current
tanδ Dissipation factor
xxi
Pl_tot Total power loss of synchronous Buck converter
fc Cutoff frequency
VolL Volume of inductor
VolC Volume of capacitor
Vtot Total volume of inductor and capacitor
ac Coefficient of capacitor volume
al Coefficient of inductor volume
Pl_tot,max Limit of total power loss
fc,max Limit of cutoff frequency
Vtot,max Limit of total volume
SPm Minimal spacing
MDR Maximum distribution range
Iripple Inductor current ripple constraint
Vripple Output voltage ripple constraint
Po Output power
Vollim Limit of total volume
(∆Vo%)lim Limit of output voltage ripple
(∆IL%)lim Limit of inductor current ripple
fs Switching frequency
L Inductance value of inductor
C Capacitance value of capacitor
Ku Fill factor of inductor core
Nmax_core Maximum number of turns of inductor
Lmax_core Maximum inductance of inductor
ID Inner diameter of inductor core with toroidal shape
AL Nominal inductance
AW Area of wire
MP Maximum number of capacitors connected in series and parallel
xxii
N Population size
OD Outer diameter of inductor
H Height of inductor
Ae Equivalent core area
μi Initial permeability
Bsat Saturation magnetic influx density
RL Equivalent resistance of inductor
ESR Equivalent series resistance of capacitor
ESL Equivalent series inductance of capacitor
r Resistance of wire per unit length
kesl Coefficient of the equivalent series inductance of capacitor
Pl_L_Fe Core loss of inductor
Pl_s1 Switching loss and conduction loss of high-side switch
Pl_s2 Switching loss and conduction loss of low-side switch
Pl_L_Cu Copper loss of inductor
Pl_C Capacitor loss
∆Vo% Output voltage ripple
∆IL% Inductor current ripple
Nh Number of neurons of each hidden layer
Fi Fitness value of the ith individual in Chapter 4
Oi Objective value of the ith individual in Chapter 4
Omax Maximum of objective value
Omin Minimum of objective value
Vol Total volume
fmax Maximum of switching frequency
fmin Minimum of switching frequency
Lmax Maximum of inductance
Cmax Maximum of capacitance
xxiii
Lmin Minimum of inductance
Cmin Minimum of capacitance
VDSS Drain-source voltage when gate and source are short-circuited
RDS(on) Drain-source resistance of switches
η Efficiency
vin Waveform of input voltage
vo Waveform of output voltage
io Waveform of output current
vL Waveform of inductor voltage
iL Waveform of inductor current
iC Waveform of capacitor current
vp Waveform of ac voltage of primary full bridge
vs Waveform of ac voltage of secondary full bridge
Ts Switching period
D0 Outer phase shift between two full bridges
D1 Inner phase shift in primary full bridge
D2 Inner phase shift in secondary full bridge
P Output power
V1 Input voltage
V2 Output voltage
ipk Peak-to-peak inductor current
Pmin Minimum output power
Pmax Maximum output power
V2_min Minimum output voltage
V2_max Maximum output voltage
X Position of particle in particle swarm optimization
V Velocity of particle in particle swarm optimization
c1 Acceleration coefficient regarding personal best position in history
xxiv
c2 Acceleration coefficient regarding global best position in history
ω Velocity inertia weight
Pbest Personal best position in history
Gbest Global best position in history
V2,ref Reference value of output voltage
D1_min Minimum inner phase shift D1
D1_max Maximum inner phase shift D1
D2_min Minimum inner phase shift D2
D2_max Maximum inner phase shift D2
Lr Leakage inductance
n Transformer turn ratio
I1 Input current
I2 Output current
Din Inner phase shift of extended phase shift
Do Outer phase shift of extended phase shift
vt Velocity of particle in the tth iteration in reduced dynamic equation
xt Position of particle in the tth iteration in reduced dynamic equation
Xi Position of the ith particle
Xid dth dimension of the position of the ith particle
D Dimension of solution space
di Mean distance of the ith particle
dg di of the globally best particle
dmin Minimum value of di
dmax Maximum value of di
Vid dth dimension of the velocity of the ith particle
Vi Velocity of the ith particle
Xmax Maximum value of particle position
Xmin Minimum value of particle position
xxv
vlmax Maximum velocity limit
vlmin Minimum velocity limit
pbesti Personal best position in history of the ith particle
gbest Global best position in history
max_iters Maximum number of iterations
φo Outer phase shift angle
φi1 Inner phase shift angle in primary full bridge
φi2 Inner phase shift angle in secondary full bridge
IRMS Root mean square value of inductor current
vds Waveform of drain-source voltage of switches
ids Waveform of drain-source current of switches
V2,min Minimum output voltage
V2,max Maximum output voltage
Ploss Total power loss
nZVS Number of switches satisfying ZVS constraints
yk,θk Output of the kth decision tree in XGBoost
θk Adjustable parameters of the kth decision tree
ok* Objective value for the training of the kth decision tree
yi(1) Output of the ith decision tree in XGBoost-1 for total power loss
yi(2) Output of the ith decision tree in XGBoost-2 for ZVS
cZVS Weight factor of ZVS constraints
V1,rated Rated value of input voltage
V2,rated Rated value of output voltage
Prated Rated output power
xxvi
xxvii
Abstract
Threatened by the global warming and the depletion of fossil fuel, renewable energy
such as solar energy and clean transportation solutions like electric vehicles are attracting
more attentions nowadays, which appeal for a future with more power converters. Among
all types of power converters, DC-DC converters are the key enablers for DC voltage and
power regulation. To realize an optimally performed DC-DC converter, the circuit
parameter aspect and modulation aspect of DC-DC converters should be designed with
great care. However, the conventional approaches for the circuit parameter and modulation
design of DC-DC converters suffer from two nontrivial challenges: heavy manpower
burden and low design accuracy. The issue of heavy manpower burden is primarily
attributable to the massive human-dependence in the analysis and deduction process of
design objectives. The issue of low design accuracy is mainly caused by the model
simplification and mathematical approximations. Fortunately, the advanced artificial
intelligence (AI) techniques such as neural network (NN), metaheuristic algorithm (MHA),
and fuzzy inference system (FIS), can be applied to solve those challenges. Consequently,
this thesis focuses on the applications of AI techniques in the circuit and modulation design
of DC-DC converters to realize high-level automation while maintaining high design
accuracy.
To highlight the objectives and motivation of this thesis, Chapter 2 gives a
comprehensive literature review targeting the circuit parameter design and modulation
design of DC-DC converters. In the beginning, Chapter 2 first introduces the DC-DC
converters, followed by a detailed review of circuit parameter design approaches for DC-
DC converters. Subsequently, the modulation approaches for DC-DC converters are
discussed, and this chapter ends with the existing applications of AI techniques in the
circuit parameter and modulation design of DC-DC converters. Chapter 2 indirectly
emphasizes that the proposed AI-based automated design approaches in this thesis are of
great significance to the circuit and modulation design of DC-DC converters.
Chapter 3 and Chapter 4 aim at the circuit parameter design approaches for DC-DC
converters. In Chapter 3, to achieve a good holistic design of a synchronous Buck converter,
efficiency, cutoff frequency, and power density are optimized at the same time. The
xxviii
optimization of the three conflicted design objectives is intrinsically a multi-objective
design problem, which is solved by the novel coevolving archived multi-objective
simulated annealing (coevolving-AMOSA) algorithm. With the proposed coevolving-
AMOSA algorithm, a Pareto frontier with better uniformity and completeness can be
obtained. Based on the obtained Pareto frontier, considering various application scenarios,
three optimal designs are given. 100 W hardware experiments have been done to verify the
three design cases.
Since the approach in Chapter 3 still relies on human efforts for the deduction of design
objectives, Chapter 4 proposes an AI-based design (AI-D) method, which can achieve full
automation in both the deduction process and the optimization process. The proposed AI-
D approach is composed of four stages, briefly discussed as follows. First, design
specifications are given. Second, lookup tables that contain the practical features of
components are built, which make the simulation closer to the reality and thus increase
design accuracy. Third, simulation is built and run to generate training data for NN, and
the trained NNs serve as the surrogate models for design objectives. Fourth, genetic
algorithm interacts with NNs to search for the optimal design. To reflect how the proposed
AI-D approach can be applied, given the application scenario of the accessory load supply
system in electric vehicle, an efficiency-oriented synchronous Buck converter with
constraints on size and ripples is provided. Detailed hardware experiments validate the
effectiveness and high design accuracy of the proposed AI-D methodology.
Chapter 5 and Chapter 6 study the modulation design approaches for DC-DC converters.
To facilitate the automated design idea in Chapter 4 to modulation design, Chapter 5 puts
forward an AI-based triple phase shift modulation (AI-TPSM) for dual active bridge
converters. In the proposed AI-TPSM, NN, MHA, and FIS are adopted in the deduction
stage, optimization stage, and online realization stage, respectively. With the integration of
NN and simulation, the deduction process of current stress is automated. With an MHA,
the optimal modulation variables under various operating conditions are automatically
found. The proposed FIS-based control diagram realizes the online modulation with
continuous values, which solves the problem of discreteness in lookup-table-based online
modulation approaches. With the proposed AI-TPSM, the optimal current stress can be
achieved over the whole load range and voltage range. 1 kW hardware experiments
xxix
comprehensively validate the optimal current stress and high efficiency performance in
steady state, and verify the fast dynamic response under voltage and load steps.
Except for single modulation strategy, hybrid modulation is also studied in-depth in this
thesis. In Chapter 6, hybrid extended phase shift (HEPS) modulation is considered to reach
high modulation performance while keeping simple implementation. The proposed
approach in Chapter 6 is also a fully automated modulation design approach, but has
several adjustments compared with the method in Chapter 5. First, compared with the
current stress considered in Chapter 5, the optimization objectives in Chapter 6 are
efficiency and full-range ZVS operation. Moreover, an advanced ensemble learning
technique, extreme gradient boosting (XGBoost), is adopted to learn the data-driven
surrogate models of efficiency and ZVS performance. In addition, a novel PSO algorithm
is proposed to achieve fast convergence speed during optimization process. The proposed
AI-based HEPS modulation can realize optimal efficiency and all-switch ZVS operation
over entire operating ranges, which have been experimentally validated. Moreover,
hardware experiments also validate the satisfactory dynamic performance.
Finally, the conclusion of this thesis is summarized. Five potential future research
directions are highlighted, including: AI-based automated design considering more design
parameters, more design objectives, and more power converters; Temporal behavior
modeling of power converters; More complicated modulation strategies; Reinforcement
learning for real-time modulation and circuit topology design; Applications of other
advanced AI techniques in power electronics.
xxx
Chapter 1 Introduction
In this chapter, the research background is presented, including the increasing

penetration of renewable energy, necessary actions to global climate change, and
transformations from traditional power grid to smart grid, all of which appeal for a future
of more power converters. Within power electronics systems, DC-DC converters are of
great importance, which are the research focus in this thesis. The significance of DC-DC
converters is stressed, various applications are introduced, and the circuit parameter design
and modulation design of DC-DC converters to achieve desirable performance are
discussed. However, the existing approaches for the circuit and modulation design of DC-
DC converters suffer from nontrivial problems of massive human-dependence and low
design accuracy. Consequently, the motivation and objectives of this thesis aim to tackle
these problems, and the contributions are highlighted afterwards. Finally, the organization
of the whole thesis is summarized.
1
1.1 Research Background
In this era, there is no country that is not unscathed by the negative impacts of global
warming due to excessive CO2 emissions. The global warming effects threaten our living
environment, economy, and society. To proactively act to the climate change, in the 7th
goal of united nation sustainable goals, united nation appeals to reach carbon neutral around
2050 [1].
In fact, energy supply is the major portion responsible for climate change, which
contributes to 60% of greenhouse gas emissions. To meet the goal of carbon neutral and
tackle the problem of depletion of fossil fuels, the energy generated by traditional fossil
fuels should be gradually replaced by affordable, clean, and sustainable energy such as
solar energy, wind power, hydropower, etc. Ever since the beginning of the 21st century,
the proportion of renewable energy steadily increases worldwide, as shown in Fig. 1.1.
Except for the advantage of sustainability, renewable energy is affordable, flexible, and
independent of the basic infrastructure of power grid. As the demand for energy continues
to grow, the clean renewable energy is the top choice to be considered in the future.
7,000 TWh Other

renewables Wind power and solar energy
6,000 TWh Solar Energy increase significantly
5,000 TWh Wind Power

Hydropower
4,000 TWh
Hydropower steadily
3,000 TWh increases
2,000 TWh
1,000 TWh
0 TWh
1965 1980 1990 2000 2010 2020
Fig. 1.1. Worldwide renewable energy generation capacity between 1965 and 2020 [2].
2
However, the increasing penetration of renewable energy brings challenges to power
grid facilities. First, renewable energy is intermittent and widely distributed in nature, so
how to maintain good power quality, grid stability and the capability to reliably support
customer loads are major concerns. To interface with various renewable energy sources in
different geological location and to regulate the power generated, power converters such
as DC-DC converters, DC-AC inverters, AC-DC rectifiers, and AC-AC converters are the
essential infrastructure. Power converters can transform electricity from one form to
another. For instance, DC-DC converters regulate DC electricity from one voltage level to
another; DC-AC inverters adjust the form of DC electricity to AC electricity. Fig. 1.2 gives
typical power converter systems for interfacing solar energy, wind power and hydropower.
Main Grid
DC Bus Grid-
Connected
Inverter
DC = AC ~
= DC = DC
DC = DC = DC =
= DC = DC Solid = DC
State
Transformer
DC = DC =
~ AC ~ AC
Doubly-fed
induction generator
Solar Panel Energy Storage
Electric Vehicle
System
Wind Turbines Hydropower
Fig. 1.2. Typical power converter systems for solar panel, energy storage system, wind
turbines, electric vehicle and hydropower [3].
Moreover, the rapid growth of renewable capacity leads to a sharper load profile, as the
maligned “duck curve” shown in Fig. 1.3. With the increasing of renewable generation, the
load ramp during busy hours becomes steeper, making it more complicated for power
distribution and operation. To shave peaks and fill valleys, energy storage system (ESS)
should be used, as shown in Fig. 1.4. In Fig. 1.4, DC-DC converters and DC-AC inverters
3
are bidirectional structures to control power flow: store energy during off-peak hours and
release energy during busy hours.
3.0 MW
Flattened ramp with energy
storage system
2.5 MW
2012
2013
2.0 MW
2014
2016
1.5 MW 2018
Load profile of a 2020 Flattened load
typical day in 2020 profile with ESS
1.0 MW
4 AM 8 AM 12 PM 4 PM 8 PM
Fig. 1.3. Changes of load profile from year 2012 to 2020 [4].
AC Bus
AC ~ AC ~ AC ~ AC ~
= DC = DC = DC = DC
Main Grid
DC= DC= DC= DC=
=DC =DC =DC =DC
Fuel Cell Battery Units Super Capacitor Flywheel
Fig. 1.4. ESS with fuel cell, battery units, super capacitor and flywheel [5].
Except for the increasing proportion of renewable energy, to help reduce carbon
emission and preserve fossil fuel, automotive vehicle should rely more on electrical energy
rather than conventional fossil fuel. Recently, automotive companies are focusing on
electric vehicle (EV), hybrid electric vehicle (HEV), plug-in hybrid electric vehicle
(PHEV), etc. As shown in Fig. 1.5, EV heavily depends on power converters for propulsion
system, charging system, power conversion between high DC voltage and low DC voltage,
etc. ESS is also necessary in EV to provide sufficient electrical capacity.
4
Fig. 1.5. Propulsion, charging and auxiliary power supply systems of EV [6].
Power converters are also the key facilitators for the global trend of grid transformation
from traditional power grid to smart grid. Compared to traditional power grid, smart grid
can provide more secure, robust, controllable, and dependable electrical services. Smart
grid utilizes power electronics to achieve modern industrial automation, high-efficiency
power conversion, and flexible distribution and operation. For instance, bidirectional
power converters facilitate two-way distribution in smart grid. Controllable power
converters enable self-monitoring, pervasive control, and self-healing restoration when
fault occurs. Power converters are also indispensable for the integration of distributed
renewable generation and for the large-scale deployment of ESS and grid-connected EV.
Besides, power converters also find their places in other grid-connected industrial
applications and residential applications. To name a few, flexible AC transmission system
(FACTs) and high-voltage DC (HVDC) transmission enhance controllability and
flexibility of AC grids, voltage transformation and current transformation. Active power
5
filter (APF), static var compensator (SVC), static compensator (STATCOM) and thyristor
control phase shifter (TCPST) can compensate reactive power, reduce harmonic distortions
and improve power quality. Power converters have been applied to telecommunications,
cyber-physical systems, household appliances, uninterrupted power supplies (UPS), etc.
These applications are summarized in Fig. 1.6.
AC ~ HVDC DC =
=DC ~AC
AC ~ AC ~ AC ~ AC ~ AC ~ AC ~
=DC =DC =DC =DC =DC =DC
DC= DC= DC= DC= DC=

=DC =DC =DC =DC =DC
STATCOM
/ SVC
Tele- UPS
communication
Home
Energy storage
Renewable appliances
system
energy generation
Fig. 1.6. Applications of power converters in smart power grid.
In a nutshell, the threats of climate change, the depletion of fossil fuels and the
transformation of traditional power grid to smart grid all ask for a future with more power
converters. And how to design these power converters to achieve good comprehensive
performances should be carefully studied.
1.2 Circuit Design and Modulation Design of DC-DC Converters
Among all kinds of power converters, DC-DC converters are playing a crucial role in
DC power regulation and DC voltage conversion, and they are omnipresent in any power
electronics systems. Therefore, DC-DC converters are the main research focus. In this
thesis, to achieve satisfactory holistic performances, the circuit parameter design and
6
modulation design of DC-DC converters are discussed in detail, which are briefly
summarized as the following.
(a) Circuit Parameter Design of DC-DC Converters
CLLC-Type Isolated DAB Converter
CLLC Resonant Tank S5 S7

S1 S3 Lr1 Cr1 n:1 Lr2 Cr2
Lm Cf
S2 S4 Transformer
S6 S8
Full Bridge 1 Full Bridge 1
Conventional Buck Converter
L
SH
SL C
Two Switches LC Filter
Fig. 1.7. A CLLC-type isolated DAB converter and a conventional Buck converter.
In the circuit parameter design of DC-DC converters, there are mainly four parts to
consider: semiconductor switching devices, magnetic transformers, inductors, and
capacitors. Other parts that are also considered in the circuit design include hardware such
as heat sink and PCB routing, and topological schemes. For instance, a synchronous Buck
converter is composed of two MOSFET switches and a LC-based output filter, as shown
in Fig. 1.7. A CLLC-type isolated dual active bridge (DAB) converter shown in Fig. 1.7
has two full bridges, a transformer and a CLLC-type resonant tank to be designed [7]. In
circuit parameter design, some objectives are usually optimized to reach high performance,
such as efficiency, power density, stability, reliability, cost, size, voltage conversion ratio,
transient response, electromagnetic interference (EMI), etc.
(b) Modulation Design of DC-DC Converters
Other than the circuit parameter design, the modulation design of DC-DC converters is
another popular research field. A properly optimized modulation strategy can ensure a
7
robust closed-loop power regulation and boost operating performance. In general, pulse
width modulation, phase shift modulation and variable frequency modulation are three
basic modulation strategies of DC-DC converters. This thesis focuses on the phase shift
modulation due to limited scope. To achieve a good real-time modulation for DC-DC
converters, modulation objectives such as power efficiency, rms current, peak-to-peak
current, transient response, reactive power, zero voltage switching (ZVS) are taken into
account. The comprehensive reviews of circuit parameter design and modulation design of
DC-DC converters are presented in Chapter 2.
1.3 Motivation and Objectives
The circuit design of DC-DC converters consists of two steps: the analysis and deduction
of design objectives, and the optimization to achieve best performance. While the
modulation design requires one more step, which is the real-time implementation of the
optimized strategy. Overall, the conventional methods for the circuit and modulation
design of DC-DC converters inevitably suffer from the issues of heavy manpower burden
and low design accuracy, as shown in Fig. 1.8 and Fig. 1.9.
Circuit Parameter Design of DC-DC Converters

Main Steps Step Descriptions Main Issues in Each Step
Heavy Manpower
I: Analysis and To obtain mathematical expressions Burden: complex
Deduction of for optimization objectives with objectives and topology
Design Objectives respect to design parameters Low Design Accuracy:
model simplifications
Low Design Accuracy:
II: Optimization to To obtain the best design
mathematical
Achieve Best parameters which can achieve
approximations; infeasible
Performance optimal performance
computation; suboptimality
Fig. 1.8. Issues in the traditional methods for the circuit parameter design of DC-DC
converters.
(a) Heavy Manpower Burden
The issue of heavy manpower burden is mainly coming from the analysis and deduction
of design objectives. This issue aggravates as the topology of converters and the model of
8
components become more complex and the number of objectives to consider increases.
As an example, to deduce the efficiency of a CLLC-type resonant DAB converter, the
resonant currents in both primary and secondary sides are firstly analyzed, based on which
the rms and peak-to-peak values are deduced for computing conduction loss and magnetic
core loss. The switching events of all switches are analyzed for the analysis of switching
loss. The aforementioned processes add up to the high complexity of the analysis and
deduction process, leading to heavy manpower burden.

Main Steps Step Descriptions Main Issues in Each Step
Heavy Manpower Burden:
complex objectives; many
I: Analysis and To obtain mathematical degree-of-freedom of
Deduction of expressions for optimization modulation; many working
Modulation objectives with respect to modes and operating conditions
Objectives modulation parameters
few orders of harmonics

II: Optimization to To obtain the best modulation
mathematical approximations;
Achieve Best parameters which can achieve
infeasible computation;
Modulation optimal modulation
suboptimality

III: Real-time Realize the designed
discreteness of lookup table;
Implementation of optimal modulation in
mathematical approximations of
Best Modulation real-time operation
expression-based approaches
Fig. 1.9. Issues in the traditional methods for the modulation design of DC-DC
converters.
Another example is the current-stress-oriented design of triple phase shift (TPS)

modulation for DAB converters. The analysis of current stress of DAB converters under
TPS modulation utilizes either piecewise approach or harmonic approach, while both
approaches have been proven to be exhausted and time-consuming [8], since the same
analysis process has to be repeated for all working modes and operating conditions. If more
degrees of freedom are considered in the modulation, such as the five-degree-of-freedom
modulation [9], the burdensome issue in the analysis process will even exacerbate.
9
(b) Low Design Accuracy
Low design accuracy issue can be induced by model simplifications, mathematical

approximations, and modulation discreteness. As shown in Fig. 1.8 and Fig. 1.9, the
analysis process, optimization process and real-time implementation process all can lead
to low accuracy.
In the analysis process of circuit parameter design of DC-DC converters, models of
circuit components are sometimes simplified. For instance, power switches were simplified
as ideal switches and magnetizing current was neglected in the deduction of rms current of
DAB converters [10]. The equivalent resistance of inductor was ignored to simplify
impedance modeling [11]. The real-world magnetic, electrical, and geometrical
characteristics of output LC filter were not considered in the filter design of Buck converter
[12]. These model simplifications undermine the model accuracy.
After the analysis and deduction of design objectives, in the optimization process of
circuit parameter design, the high-order non-linearity of deduced objective functions raises
challenges for solving the optimization problems by hand. Therefore, mathematical
approximations are applied to reduce optimization difficulty. For instance, in the resonant
tank design of an asymmetrical CLLC-type DC transformer, to obtain the optimal margin
of voltage conversion gain, the design criteria were simplified [13]. In addition to solving
the optimization manually, enumeration approach or deterministic algorithms such as
augmented Lagrangian approach can be adopted. However, by trying out all possible
design cases, enumeration-based approaches may require infeasible computational time
especially when the dimension of design parameters is high or when the design parameters
are continuous with infinite possible values. As for the deterministic algorithms, their
optimization results highly depend on the initial iteration points and the predetermined
convergence threshold, so they can easily get trapped into suboptimal designs.
In terms of modulation design of DC-DC converters, the issue of low design accuracy
also exists. For instance, in the analysis process of inductor current under TPS modulation,
if the harmonic approach is utilized and only the first order of harmonic is considered, the
model accuracy will be sacrificed. Similarly, the conventional approaches for the
modulation optimization can lead to inaccurate and suboptimal designs. Furthermore, the
real-time implementation of modulation with lookup tables bears the disadvantages of
10
discreteness, resulting in inaccurate modulation if the queried situations are not stored in
the lookup tables. Apart from that, the storage size of lookup tables exponentially rises with
the increasing of stored variables, and the exploding storage size will nontrivially slow
down the query speed of lookup tables. If expression-based approaches are used for real-
time modulation, unavoidable mathematical approximations may nontrivially impair the
modulation accuracy.
To overcome the above problems in the analysis, optimization and modulation of DC-
DC converters, artificial intelligence (AI) algorithms are taken advantage of. In this thesis,
three branches of AI techniques can be applied: machine learning (ML) and neural network
(NN), metaheuristic algorithm (MHA) and fuzzy inference system (FIS). Being beneficial
from its high non-linearity and easily adjustable structures, NN can learn any complex and
nonlinear relationships between design variables and design objectives with arbitrary
precision. Due to the capability of inferring from data, NNs can be viewed as data-driven
surrogate models to replace traditionally deduced mathematical models. MHAs are
stochastic optimization techniques, which are derived from biological phenomenon or
physical processes. The key characteristics of MHAs are that better individuals have larger
chances of survival and reproduction, while worse individuals can still survive and
reproduce. As derived from fuzzy theory, FIS provides human-like logic that enables
intermediate degrees other than true or false, offering the capability of continuous real-time
modulation. With FIS-based modulation, the problems of discreteness and large time and
space complexity are solved.
In a nutshell, to conquer the challenges of heavy manpower burden and low design
accuracy in the circuit and modulation design of DC-DC converters, AI techniques with
attractive advantages are applied throughout this thesis. From a macro viewpoint, this thesis
aims to accelerate the penetrations of AI techniques in the field of power electronics: I truly
believe that the advances in AI will facilitate the development of power electronics society.
1.4 Main Contributions of This Thesis
In brief, this thesis investigates the applications of AI techniques in the circuit and
modulation design of DC-DC converters to resolve the challenges of heavy manpower
burden and low design accuracy. Considering the appropriateness and for the sake of clear
11
illustrations of AI-based methodologies, the synchronous Buck converter is adopted for the
circuit parameter design, and the DAB converter is used for the modulation optimization.
The main contributions of this thesis are summarized as follows:
 A multi-objective design approach via a novel coevolving-AMOSA algorithm is

proposed for the output LC filter design of synchronous Buck converters. Three
conflicted objectives including efficiency, power density and cutoff frequency are
considered simultaneously, and various design cases aiming at different application
scenarios are given. The proposed coevolving-AMOSA algorithm greatly improves the
uniformity and coverage of the optimal Pareto frontier.
 An AI-based automated design approach with the assistance of simulations, NN and

genetic algorithm (GA) is proposed for the parameter design of synchronous Buck
converters in EV applications. In the proposed method, detailed magnetic and electrical
features of components are considered, achieving more accurate designs. With the
integration of simulation and NN, the analysis process of design objectives is
automated, freeing engineers from heavy manpower burden. GA helps to achieve
optimal design with fast computation speed.
 A current-stress-optimized TPS modulation for DAB converters is automatically

designed through AI techniques. With the performance data from simulation, NN is
trained and serves as a surrogate model for current stress. PSO is utilized to optimize
the modulation parameters. FIS is adopted to achieve continuous real-time modulation.
This approach is conducted in an automated fashion, mitigating the massive human-
dependence and achieving satisfactory design accuracy.
 A hybrid extended phase shift (HEPS) modulation for DAB converters is designed with
the simultaneous considerations of full ZVS range and optimal efficiency. The
proposed HEPS approach exhibits automated features, where an advanced ML
algorithm acts as the data-driven surrogate models for ZVS and efficiency. A cutting-
edge PSO algorithm is used to achieve optimal modulation with fast convergence speed.
The best modulation strategy and the optimal modulation parameters are selected with
minimum manpower required.
12
 Finally, this thesis presents possible research directions of the applications of AI in the
automated design of circuit and modulation for power converters. Besides, the potential
applications of other advanced AI techniques in design, control, modeling, modulation,
health monitoring, fault diagnosis, and component recommendation are put forward.
The future works aim to raise attentions in the power electronics society regarding the
powerful AI algorithms.
1.5 Organization of This Thesis
This thesis includes 7 chapters in total, the organization of which is given as follows.
Chapter 1 discusses the crisis of global warming and the depletion of fossil fuel. As a
solution, renewable energy generations and electric vehicle should gradually substitute the
burning of fossil fuel. The increasing penetration of renewable energy sources and electric
vehicles requires more power converters in power grid. Among all power converters, the
ubiquitous DC-DC converters are the focus of this thesis. To achieve good performance,
the circuit parameter design and modulation design of DC-DC converters are studied.
However, the conventional approaches for the circuit and modulation design of DC-DC
converters suffer from the problems of heavy manpower burden and low design accuracy.
The analysis and solutions with regards to these issues serve as the main contributions.
Chapter 2 presents comprehensive literature reviews with regards to the motivation and
objectives of this thesis. First, basic introduction to the topology and applications of DC-
DC converters is given. Second, circuit parameter design approaches for DC-DC
converters are illustrated in detail. Furthermore, modulation approaches for DC-DC
converters are reviewed. Finally, the classifications of AI techniques and the applications
of different AI algorithms in the design of DC-DC converters are discussed.
Chapter 3 proposes a multi-objective design for the output LC filter of synchronous Buck
converters, taking the power loss, volume and cutoff frequency as the design targets. This
proposed holistic design approach takes the advantage of Pareto frontier to deal with the
conflicting design targets to achieve a compact LC filter with optimized power efficiency
and filtering capability. In this chapter, a novel coevolving-AMOSA algorithm is proposed
to provide a Pareto frontier with uniform and complete coverage. Via this proposed multi-
13
objective design approach, the output LC filter can be flexibly designed to meet various
applications while maintaining outstanding comprehensive performance.
Chapter 4 puts forward an artificial-intelligence-based design (AI-D) approach for the
parameter design of power converters, aiming to mitigate human-dependence for the sake
of high accuracy and easy implementation. In the proposed AI-D approach, to achieve
automation in the analysis and deduction process, simulation tools and batch-normalization
neural networks are adopted to build data-driven models for the optimization objectives
and design constraints. Besides, to achieve automation in the optimization process, genetic
algorithm is used to search for optimal design results. The design case of an efficiency-
optimal synchronous Buck converter with constraints in volume, voltage ripple and current
ripple is provided in a fully automated fashion.
Chapter 5 proposes an AI-based TPS modulation (AI-TPSM) strategy for current-stress-
optimized DAB converter. Simulation and NN are adopted to automate the analysis and
deduction process of current stress objective. Particle swarm optimization (PSO) algorithm
is utilized for optimizing modulation parameters to obtain best current stress performance.
FIS is used to deal with the discreteness of lookup table and to realize real-time
implementation. With the proposed AI-TPSM, the optimization of TPS modulation for
minimized current stress will enjoy high degree of automation which can relieve engineers’
working burden and improve accuracy.
Chapter 6 presents an AI-based hybrid extended phase shift (HEPS) modulation.
Generally, the HEPS modulation is developed in an automated manner, which alleviates
cumbersome model building process while keeping high model accuracy. In HEPS
modulation, two EPS strategies are considered to realize optimal efficiency with full ZVS
operating ranges. Specifically, to build data-driven models of ZVS and efficiency
performance, extreme gradient boosting (XGBoost) is adopted. Afterwards, an advanced
particle swarm optimization with state-based adaptive velocity limit strategy (PSO-SAVL)
is utilized to select the best EPS strategy and optimize modulation parameters. The
principal of PSO-SAVL is comprehensively discussed, and its convergence and global
searching capability are theoretically and empirically validated.
Chapter 7 summarizes the research works of this thesis and indicates potential future
research directions with respect to the applications of AI in power electronics.
14
Chapter 2 Literature Review
This chapter comprehensively reviews relevant research works centered on the

motivation and objectives of this thesis. This chapter starts with the introduction to the
topology and applications of DC-DC converters. The circuit parameter design approaches
for DC-DC converters are then discussed, followed by the reviews of modulation
approaches for DC-DC converters. In the end, the classifications of various AI techniques
and the applications of AI in the circuit parameter design and modulation design of DC-
DC converters are reviewed.
15
2.1 Topology and Applications of DC-DC Converters
DC-DC converters are high-frequency power conversion circuits which regulate DC

power from one voltage magnitude to another or provide galvanic isolation between two
DC buses. They are able to produce a regulated DC voltage from a fluctuating source and
to a load that is inconstant. Generally, DC-DC converters can be classified into non-isolated
type and isolated type according to whether there is galvanic isolation. The detailed
classifications of isolated and non-isolated types are shown in Fig. 2.1.
One-way power transfer

Conventional
Unidirectional
Bidirectional Cascaded
Two-way power transfer
Interleaved
ZVS / ZCS
Soft-Switching
Hard-Switching Multilevel
Bridge-Type
No Galvanic Isolation
Non-Isolated
DC-DC Push-Pull
Converters Isolated
Galvanic Isolation Forward/Flyback
Capacitive
input filter Z-Source
Inductive Voltage-Fed
input filter Current-Fed Multiport
Fig. 2.1. Classifications of DC-DC converters.
In the non-isolated DC-DC converters, the input and output share a common ground, and
there is no electrical isolation. Non-isolated DC-DC converters are further assorted into
conventional type, cascaded type, interleaved type, and multilevel type. Conventional DC-
DC converters include Buck, Boost, Buck-Boost, Ćuk, Sepic, etc., which have been widely
applied in photovoltaic systems, LED drivers, fuel cell vehicles [14], [15], etc. To enhance
the voltage step-up ability and relieve the burden of current stress, two or more converters
can be connected in a cascaded way, which has applications such as smart grids and
16
distributed power systems [3]. Interleaved and multilevel converters, which are also
potential solutions to high-voltage step-up applications, can be utilized in automotive
systems, HVDC grids [16], [17], etc. Examples of non-isolated DC-DC converters are
shown in Fig. 2.2.
Conventional Buck-Boost Converter Cascaded DC-DC Converter
S D S1
Vin L C R
Vin C R
L
S2
Multilevel DC-DC Converter
Interleaved DC-DC Converter

S1 S1
R L1
S2 C1
Vin
Vin L2 C R
S2
Fig. 2.2. Examples of non-isolated DC-DC converters [18].
From the perspective of isolated DC-DC converters, except for the benefit of safety, the
galvanic isolation can achieve high voltage gain ratio and provide the possibility of multi-
input and multi-output topologies. The galvanic isolation can be achieved by a transformer
or a coupled inductor. Isolated DC-DC converters are classified into bridge-type, push-pull,
forward, flyback, Z-source and multiport converters. Flyback, push-pull and forward DC-
DC converters are commonly applied in low and medium power conditions [18]. Z-source
converters require no extra active switches to realize high-voltage step-up [19]. Multiport
DC-DC converters can be used in decoupled power flow management [18]. Bridge-type
converters include dual half bridge, half-full bridge, DAB, etc. The most popular bridge-
type DC-DC converters are DAB converters, whose applicational fields include electric
vehicle charging, battery storage systems, uninterrupted power supply, solid-state
transformer [5], [16], [18], etc. Recently, DAB converters with resonant tanks such as LC,
LLC, CLLC are hot research topics [20]. Examples of isolated DC-DC converters are
shown in Fig. 2.3.
17
Dual Active Bridge Converter Push-Pull Converter
S1 L
S5 D1
Lr C R
Vin Lm C R
S2 D2
Vin S1
S6
S2
Forward Converter Multiport DC-DC Converter
L S1
D1
D2 C R S9
Lr1
Vin Vin Lm1 C R
D3 S1 S2
S10
Flyback Converter
S5
L
D C R Lr2
Vin Vin Lm2

S6
S1
Fig. 2.3. Examples of isolated DC-DC converters [18].
Other than the classifications of non-isolated and isolated types, DC-DC converters can
also be classified into unidirectional and bidirectional types, hard-switching and soft-
switching types, and voltage-fed and current-fed types. Unidirectional DC-DC converters
can only transfer power flow in one direction, while bidirectional converters can support
two-way power transfer. Unidirectional converters are suitable for on-board loads such as
sensors, safety equipment, utilities [21], and bidirectional converters have applications
such as renewable energy systems, vehicle to grid, uninterrupted power supply, energy
storage system, aerospace applications [22], [23], etc. Soft-switching DC-DC converters
use passive components (capacitance, inductance) or active circuits to achieve zero voltage
switching (ZVS) or zero current switching (ZCS). Compared with hard-switching
counterparts, soft-switching converters can reach high switching frequency, high power
density and high efficiency [21]. Depending on the input circuit, DC-DC converters can be
assorted into voltage-fed and current-fed converters. Voltage-fed converters have a
capacitive input filter, while current-fed converters have an inductive input filter. Current-
fed converters are favored in low-voltage renewable energy systems due to their capability
to provide continuous input current with low input current ripple [21].
18
In this thesis, considering the limited research scope, synchronous Buck converters (non-
isolated DC-DC converters) and DAB converters (isolated DC-DC converters) are taken
as examples to respectively illustrate the circuit parameter design and modulation design
of DC-DC converters.
2.2 Circuit Parameter Design Approaches for DC-DC Converters
Circuit parameter design is an important aspect to be considered, which determines the

operating performances of DC-DC converters. A carefully designed DC-DC converter can
reduce power loss, save cost, reduce size, and operate stably and reliably. The circuit
parameter design of DC-DC converters primarily incorporates two steps, as shown in Fig.
2.4. As a preliminary step, designers have to specify which parameters and components to
be designed (namely, design variables), and which performances to be optimized (i.e.,
design objectives). After clarifying the targeted variables and optimization objectives, the
models and functions of design objectives are analyzed and deduced, which are expressed
in mathematical forms or in other formats. In the next step, given the deduced models and
functions of design objectives, optimization is conducted to find the best design variables
that can reach the optimal performance in design objectives.
Preliminary Step
Specify Design Parameters Param
Various Design Parameters Param
Determine Optimization Objectives Obj
• Topologies E.g. DAB topology
Specified • Semiconductor-related E.g. Switch type
Param & Obj • Inductor-related E.g. Inductance value
Analyze and Deduce Models/Functions of • Capacitor-related E.g. Capacitance value
Objectives with Respect to Design Parameters • Transformer-related E.g. Turn ratio
Obj = f (Param) • Hardware-related E.g. PCB routing
Deduced
Obj = f (Param) Various Optimization Objectives Obj
Optimize Design Parameters to Obtain • Efficiency • Reliability • Size
Optimal Design Objectives • Power density • Stability • Cost
Obj * = min Obj Param
Param
( ) • Soft switching • Transient reponse
Param = arg min Obj Param
*
Param
( )
Fig. 2.4. Basic steps of the circuit parameter design of DC-DC converters.
19
Various circuit parameters and components that are normally considered in circuit
parameter design of DC-DC converters are listed in Section 2.2.1. In Section 2.2.2, various
design objectives to be optimized are reviewed. In Section 2.2.3, to reveal the issues of
heavy manpower burden and low design accuracy, conventional human-dependent
approaches and computer-aided design approaches are reviewed in order.
2.2.1 Various Design Parameters of DC-DC Converters
In general, in the circuit parameter design of DC-DC converters, there are six major parts
to be considered: Topologies, semiconductors, transformers, inductors, capacitors and
hardware. Fig. 2.5 summarizes various design parameters.
Design Parameters
• Non-isolated E.g. Buck, Interleaved, Multilevel
• Isolated E.g. Forward, Push-pull, DAB
Design Components • Materials E.g. Si, SiC, GaN

• Types E.g. IGBT , JFET , MOSFET
Ø Topologies
• Series Specific series
Ø Semiconductor • Switching frequency
Ø Transformer
• Core Material E.g. Ferrite, Nanocrystalline
Ø Inductor • Magnetic Cores
• Core Shape E.g. Toroid , EE , EI
Ø Capacitor • Wires Geometrical details
• Core size
Ø Hardware
• Inductance • Type • Series
• Capacitance Capacitance value

• Type E.g. Electrolytic , film , ceramic
• Series Specific series
• PCB • Heat Sink • Packaging
Fig. 2.5. Various design parameters in the circuit parameter design of DC-DC converters.
The first part to be considered is the topology of DC-DC converters [24]. For instance,
in the design of an isolated DC-DC converter [25], the converter topology was selected
among flyback, push-pull, forward, full-bridge and half-bridge types. In addition, to
achieve ZCS with short-circuit current limiting capability, the topological resonant scheme
20
was designed [26]. Moreover, the topology of Boost modules for grid-connected PV
applications was optimized, where the number of cells and the number of Boosts to cascade
were design variables [27].
The materials, types, series and switching frequency of semiconductor switches are
significant aspects. The materials of semiconductors can be Si, SiC, or GaN, and types can
be IGBT, JFET, MOSFET, etc. Switching frequency is closely related to efficiency, power
density and other performances. In [28], Zhao et al. discussed the selection of switch
materials and switch types for DAB converters. [24], [29], [30] compared different series
of semiconductor switches to select the best one. [25], [31] considered switching frequency
as design parameters to achieve good holistic designs.
In terms of transformers, the magnetic cores and wires are major components. For
magnetic cores, the material (e.g., soft iron, ferrite, nanocrystalline), shape (e.g., toroid,
cylinder, EE shape), and size (e.g., cross sectional area, core window size), are possible
design parameters [25], [32]–[34]. As for the wires of transformers, number of turns, turn
ratio, winding area, and winding diameter are normally considered [31], [35], [36].
Passive components such as inductors and capacitors are the keystones for filtering, soft
switching, energy storage, reactive power regulation, etc. Common design variables
relating with inductors and capacitors are: inductance and capacitance values, inductor and
capacitor types, and inductor and capacitor series. For instance, [37], [38] focused on the
design of inductance and capacitance values of EMI filters. [12] designed the output LC
filter for Buck converter. [39] designed the scheme of capacitor bank.
Besides the components discussed above, hardware-related parameters are sometimes
considered in circuit parameter design, such as the length of heat sink, routing of PCB and
thermal resistance of packaging. Zeng et al. studied the effects of power module packaging
and heat sink design for EV applications [40]. [41] considered the PCB routing and thermal
modeling in the design of high-frequency LLC-type DC-DC converters.
2.2.2 Various Design Objectives of DC-DC Converters
There are numerous design objectives in the circuit parameter design of DC-DC
converters. To name some examples, efficiency, power density, stability, robustness
against fluctuations, reliability, soft-switching, cost, size, voltage conversion ratio, ripples,
21
electromagnetic-interference (EMI), and thermal behaviors are popular objectives to be
optimized.
For example, [20], [24], [25], [27], [30], [36], [42] minimized total power loss or major
losses such as switching, conduction, and core losses to achieve good power conversion
efficiency. Sizes of capacitors [39], inductors [12], [43], resonant tanks [32], transformers
[31] or whole converter modules [27] were optimized for an optimal power density. From
the financial point-of-view, cost was a considered design objective in [24], [29] to be
economically efficient. To ensure the stable operation of DC-DC converters in cascaded
systems, the stability is a concern. Lin et al. discussed the stability of a DAB converter
cascaded with a constant power load, while the robustness of circuit parameters against
parameter drift was considered [11], [20], [44].
Reliability is another intriguing target to be optimized, which decides the lifetime of
components and power converters. In [45], Wang et al. comprehensively discussed the
reliability-oriented design of DC capacitors. Frede et al. overviewed the reliability of power
converters for EV applications [6]. Besides, soft-switching features such as ZVS or ZCS
were considered for the benefits of low switching loss and low EMI [26], [46]. In [20], [44],
[47], the stable voltage conversion gain under open-loop control was maintained. EMI and
ripples have been greatly mitigated in the optimization of filters [37], [38]. Thermal
behaviors like junction temperature rise in power switches have been optimized in [31],
[48].
2.2.3 Existing Circuit Parameter Design Approaches for DC-DC

Converters
Generally, existing circuit parameter design approaches for DC-DC converters can be
classified into two main types: conventional human-dependent design, and computer-aided
design (CAD). In this section, to reflect the issues of heavy manpower burden and low
design accuracy in the existing circuit design approaches, conventional human-dependent
design approaches and CAD approaches are reviewed as the following.
Conventionally, to design DC-DC converters satisfying several design objectives,
engineers have to be fully involved in the manual deduction of analytical models (such as
the models of power loss, reliability and power density), and entirely participate in the
22
manual computation to achieve optimal designs [47]. The exhausted manual deduction and
the complicated computation for optimization are troublesome and time-consuming for
engineers. Attributable to the excessive human-dependence, the conventional human-
dependent design approaches require great deal of time and are prone to error. For instance,
in the circuit design of an unidirectional DC-DC modular multilevel converter for offshore
windfarm [49], key voltage and current models were deduced with the equivalent switching
model, based on which the power balance and efficiency were theoretically analyzed. The
design and optimization of this converter were manually completed by experience.
Considering the design of a planer transformer for high-voltage, high-frequency, and
multiple-output DC-DC converters, great efforts were dedicated to analyzing the leakage
inductance and capacitance given the winding configuration and magnetic structure [35].
Huang et al. analyzed the active power transfer of generalized CLLC-type DAB converters
in different conditions, and manually tried out all frequency options to determine the
optimal value [50]. In [51], voltage conversion gain and active power transfer were
analyzed with respect to resonant tank parameters, and the optimization problem was
solved manually with mathematical simplifications.
With the thriving of computer techniques, engineers are equipped with computer-aided
tools in the optimization process of the parameter design of DC-DC converters [52]. CAD
approach for DC-DC converters becomes dominant since its presence, because it can free
engineers from lousy manual computation to realize optimal designs. Compared with
conventional human-dependent design, CAD can achieve optimization automatically.
CAD approaches can be further categorized into enumeration-based CAD (E-CAD)
approaches, deterministic-algorithm-based CAD (DA-CAD) approaches, and recently
popular metaheuristic-algorithm-based CAD (MHA-CAD) approaches.
E-CAD approaches use looping to enumerate all possible designs. In the high-frequency
transformer design for a multiport DC-DC converter, all possible transformer structures
have been exhausted to find the optimal design with high-efficiency, high-power-density
and high-voltage insulation [32]. In the circuit design of an ACLLC-type DAB converter,
all feasible inductance and capacitance values were enumerated to search for optimal
solutions [13]. However, E-CAD approaches cannot be applied in cases when design
parameters are continuous, since the combinations will be infinite.
23
DA-CAD approaches utilize deterministic optimization algorithms to solve the
optimization problem. For example, in the design of a cascaded DC-DC converter for grid-
connected photovoltaic systems, a deterministic algorithm was adopted to search for the
best cascading strategy, switching frequency and inductance value which can minimize
loss or volume [27]. Another example is the optimization of a transformer in [34], where a
mixed integer nonlinear programming algorithm was adopted. DA-CAD approaches suffer
from suboptimal issues, leading to low design accuracy.
As further improvements, recently popular MHA-CAD approaches utilize one branch of
AI techniques, metaheuristic algorithms, to find the optimal solutions. Metaheuristic
algorithms utilize some non-deterministic and heuristic searching strategies to guide the
optimization process, which can improve global optimization capability and convergence
speed. For example, [12] realized the multi-objective design of output LC filter for Buck
converter considering reliability, volume, and cutoff frequency through elitist non-
dominated sorting genetic algorithm (NSGA-II). [25] adopted NSGA-II for the design of a
general-purpose isolated DC-DC converter considering the objectives of weight, power
loss, and cost. [36] combined genetic algorithm and particle swarm optimization (PSO) in
designing a high-efficiency and high-power-density resonant DAB converter. To meet the
design requirements of stable voltage transfer ratio and cascaded system stability, [44]
adopted PSO in optimization. In addition, to design the splitting inductance to reduce high-
frequency oscillation and inductor loss of a GaN-based DAB converter, genetic algorithm
was adopted in [53].
Although CAD approaches have many benefits over conventional design approaches,
they still suffer from nontrivial drawbacks attributable to the human-dependent deduction
of analytical models: burdensome analysis process, and low design accuracy.
To free engineers from heavy manpower burden, some researchers recommend taking
the advantage of simulation software. For instance, in [54], simulation was used to evaluate
the thermal performance under certain load profiles, based on which the lifetime of circuit
components was evaluated. In [55], linear generator was designed through the interaction
with simulation, which provided automatic generator evaluation. Although these
approaches indeed automate performance evaluation to some extent, there are still some
problems left unsolved: first, the performance of designs with unseen parameters (not given
24
by simulation) is unknown, limiting the number of design cases to be considered; second,
low design accuracy still exists.
2.3 Modulation Approaches for DC-DC Converters
Except for the circuit parameters of DC-DC converters, the modulation strategy is
another significant aspect, which requires careful design. Modulation provides voltage,
current or power regulation, and it determines the static and dynamic performances of DC-
DC converters, such as the efficiency, stability, steady-state deviation, settling time, peak
overshoot, etc. Some commonly used modulation techniques for DC-DC converters are
briefly discussed in Section 2.3.1, including fixed-frequency pulse width modulation
(PWM), fixed-frequency phase shift modulation (PSM), and variable frequency
modulation (VFM). In this thesis, considering that DAB converters are one of the most
popular isolated DC-DC converters and due to limited scope, the most attractive
modulation approaches for DAB converters, PSM approaches, are the main focus and are
reviewed in detail in Section 2.3.2.
2.3.1 Major Modulation Approaches for DC-DC Converters
Generally, the modulation techniques for DC-DC converters mainly include three kinds:
PWM, PSM, and VFM.
With PWM approaches, the pulse duty ratio is adjustable, which is achieved with a
sawtooth carrier at fixed frequency, a comparator, and a latch. Depending on the feedback
signal, PWM approaches can be further assorted into voltage-mode and current-mode, the
diagrams of which are shown in Fig. 2.6. The fixed-frequency PWM approaches can be
digitalized using analog-to-digital converters and digital controllers. Voltage-mode PWM
is a single control loop strategy, the applications of which are mostly voltage regulators
[56]. Current-mode PWM approaches take current as the feedback signal, which sometimes
have a voltage control loop and a current control loop, such as peak current-mode control
and average current-mode control. Current-mode PWM approaches have been widely
applied in low-voltage, high-current applications, such as chargers, LED, etc. To give some
examples, in a multiphase Buck converter, the modulation strategy adopted was the peak
25
current-mode control [57]. To improve the robustness and dynamic response of a Buck
converter, an improved average current-mode control was designed in [58].
vo (t) - vo (t) +
Compare reset vgs (t) Compare set vgs (t)
vc (t) + set
Q vc (t) - Q
fsw (t) fsw (t) reset
fsw (t) Tsw fsw (t) Tsw
vc (t) vc (t) vo (t)
vo (t) vo (t)
vo (t)
vc (t) vc (t)
vgs (t) On Off On Off vgs (t) Off On Off On

Voltage-mode PWM with Trailing Edge Voltage-mode PWM with Leading Edge
im (t) - im (t) +
Compare reset vgs (t) Compare set vgs (t)
iL (t) + set
Q iL (t) -
fsw (t) reset
Q
fsw (t)
fsw (t) Tsw fsw (t) Tsw
im (t) iL (t)
im (t) iL (t)
im (t)
iL (t) iL (t) im (t)
vgs (t) On Off On Off vgs (t) Off On Off On

Current-mode PWM with Trailing Edge Current-mode PWM with Leading Edge
Fig. 2.6. Voltage-mode and current-mode PWM approaches for DC-DC converters [59].
im (t) + im (t) -
Compare set vgs (t) Compare reset vgs (t)
iL (t) - reset
Q iL (t) + set
Q
fsw (t) fsw (t)
fsw (t) Varying Tsw fsw (t) Varying Tsw
iL (t) im (t)
iL (t) im (t)
im (t)
im (t) iL (t) iL (t)
vgs (t) Off On Off On Off vgs (t) On Off On Off On

Constant On-time VFM Constant Off-time VFM
Fig. 2.7. Constant on-time and constant off-time VFM for DC-DC converters [59].
As its name suggests, PSM adjusts the phase shift angles between bridge legs and is
widely applied in DAB converters for bidirectional power transfer. Popular PSM
approaches are single phase shift, dual phase shift, extended phase shift and triple phase
26
shift modulations. If modulation parameters like inner phase shift angles and outer phase
shift angles are chosen appropriately, PSM can greatly reduce rms current, reactive power,
and circulating current, and can improve efficiency and soft-switching range. PSM
approaches for DAB converters will be systematically reviewed in Section 2.3.2.
Compared to PWM and PSM which are fixed frequency, VFM adaptively tunes the
switching frequency to reach modulation goal. Flexible switching frequency can extend
power transfer capability and improve power quality [60]. VFM often adopts one of the
two forms: constant on-time VFM and constant off-time VFM, the diagrams of which are
shown in Fig. 2.7. In terms of the constant on-time VFM, the on interval of active switches
is fixed, and the off interval is adjustable. Constant on-time VFM approaches have been
widely adopted in light load conditions because they can improve the light load efficiency.
For instance, in the modulation design of a synchronous Buck converter for battery
applications, fixed-frequency modulation was adopted under high-power conditions, and
the control strategy shifted to constant on-time VFM under low-power conditions [61]. On
the contrary, constant off-time VFM fixes the off period and flexibly adjusts the on period.
Primary applications of constant off-time VFM approaches are wide duty ratio scenarios,
such as the Boost converter in a Boost-based power factor correction converter. To give
some examples, in the hybrid modulation design of a Boost converter with wide output
range, constant off-time VFM was considered as a major strategy [62]. Aiming at the
application of EV charging stations, to ensure high-efficiency performance of DAB
converters over wide output voltage range, VFM was adopted [63].
2.3.2 Phase Shift Modulation Approaches for DAB Converters
All the three types of modulation approaches (PWM, VFM and PSM) can be applied for
DAB converters. In particular, PSM approaches are the most popular techniques for DAB
converters due to their easy implementation, flexibility and high performance. PSM
strategies can also be applied for other DC-DC converters such as the multiple active bridge
(MAB) converter which consists of three or more full bridges [64], the multi-level
converter like the DAB converter with neutral-point-clamped full bridges [65], etc.
Overall, PSM approaches adjust the phase shifts between bridge legs, including the outer
phase shifts and inner phase shifts. There are four main types of PSM approaches for DAB
27
converters: single phase shift (SPS), dual phase shift (DPS), extended phase shift (EPS),
and triple phase shift (TPS). From the perspective of modulation objectives, current stress
[10], [66], [67], efficiency [8], [68], [69], transient response [70], [71], soft switching range
[72], [73] and robustness against parameter fluctuations [74], [75] are commonly
considered. The principles and modulation waveforms of SPS, DPS, EPS and TPS are
discussed as the following.
Ts/2 Ts Ts/2 Ts
S1 S2 S1 S2
S4 S3 S4 S3 S4
Q2 Q1 Q2 Q2 Q1 Q2
Q3 Q4 Q3 Q4 Q3
vp(t) vp(t)
DinTs/2
DoTs/2 vs(t) vs(t) DoTs/2
DinTs/2
Modulation Waveforms of SPS Modulation Waveforms of DPS
Ts/2 Ts Ts/2 Ts
S1 S2 S1 S2
S4 S3 S4 S4 S3 S4
Q2 Q1 Q2 Q2 Q1 Q2
Q3 Q4 Q3 Q4 Q3
vp(t) vp(t)
DinTs/2 Din1Ts/2
DoTs/2 vs(t) vs(t) DoTs/2
Din2Ts/2
Modulation Waveforms of EPS Modulation Waveforms of TPS
Fig. 2.8. Modulation waveforms of SPS, DPS, EPS and TPS strategies [60].
SPS modulation regulates the outer phase shift between the primary full bridge and the
secondary full bridge. Due to its one degree of control freedom, SPS modulation is the
simplest PSM strategy. The modulation waveforms are shown in Fig. 2.8, where Ts is the
switching period, S1 - S4 are the gate drive signals for primary bridge, and Q1 - Q4 are the
signals for secondary bridge. Both vp and vs are two-level voltage waveforms, and the outer
28
phase shift Do is applied between S1 and Q1. SPS modulation is mainly used for regulating
power transfer. In the application of a medium-voltage DC power conversion system, SPS
modulation was adopted to achieve active bidirectional power transfer [76]. Besides, SPS
strategy has been applied for power regulation in a DC transformer [77]. Even though SPS
strategy is easy to implement, it has some disadvantages such as small ZVS range, large
rms current when the voltage gain is not unit gain, low efficiency [77], etc.
DPS modulation has two degrees of control freedom, which are the inner phase shift Din
between the bridge legs of one full bridge and the same outer phase shift Do as SPS. Its
modulation scheme is given in Fig. 2.8. As can be seen, the same inner phase shift Din is
applied to both primary and secondary sides, so vp and vs are three-level voltage waveforms
with the same shape. With the zero-level voltage plateau introduced by Din, DPS
modulation can achieve higher efficiency, wider ZVS range and less circulating current
compared with SPS modulation. Various researchers optimize DPS modulation to achieve
better operating performance. For example, to reduce surge current and realize stable power
control, Liu et al. put forward a novel DPS strategy [78]. Bai and Mi minimized reactive
power and improved efficiency utilizing DPS modulation [68].
EPS modulation is also a two-degree-of-freedom modulation, but compared to DPS
modulation, it applies inner phase shift to either primary bridge or secondary bridge.
Consequently, as the waveforms shown in Fig. 2.8, vp is a three-level waveform while vs is
a two-level waveform, and Din represents the phase shift between S1 and S3. As analyzed
in [66], the three-level voltage waveform can reduce circulating power to improve
efficiency and current stress, because the backflow power is eliminated during the period
of zero voltage. To give some examples, Hou et al. optimized the dynamic and static
performance of DAB converters under EPS modulation [79]. In [80], EPS modulation has
been improved to achieve zero backflow power. In addition, Xu et al. adopted EPS strategy
to realize full ZVS operating range [81].
TPS modulation, which is the general version for SPS, DPS and EPS strategies, has three
degrees of control freedom, including the outer phase shift Do, inner phase shift of primary
bridge Din1, and inner phase shift of secondary bridge Din2. Fig. 2.8 presents the waveforms
of TPS modulation, in which vp and vs are both three-level voltage waveforms. Being
beneficial from its three degrees of freedom, TPS modulation exhibits lower current stress,
29
higher efficiency and wider ZVS range compared to SPS, DPS and EPS [60]. TPS
modulation has gained lots of research attentions in recent years due to its superior
modulation performance. For example, Li et al. optimized the peak-to-peak current of DAB
converters under TPS scheme, achieving high power conversion efficiency at the same time
[67]. Lin et al. properly optimized the phase shift angles of TPS to reach best efficiency
[8]. Considering the transient process during power changes, the transient DC bias current
has been reduced [71]. Full ZVS operation was achieved in [73] together with dead-zone
control. In the design of a current-stress-optimized TPS modulation, the robustness against
parameter variations was considered [75].
However, TPS modulation is hard to implement because of the three degrees of control
freedom. To maintain the modulation performance as close to TPS modulation as possible
while reducing implementation complexity, researchers explore the possibility of hybrid
modulation techniques. For instance, [82] combined EPS and several operating modes of
TPS to realize high efficiency, soft-switching and low rms current. To achieve full ZVS
operation and reduce conduction loss, a hybrid EPS approach was put forward [83].
Moreover, Deng et al. combined PWM and PSM to reach high efficiency over wide voltage
range [84].
2.4 Applications of AI Algorithms in the Design of DC-DC Converters
To solve the potential problems in the existing circuit and modulation design approaches
for DC-DC converters, AI techniques are adopted. In this section, to have some basic
understandings about AI, some popular AI algorithms are introduced in Section 2.4.1, and
their applications in the design of DC-DC converters are reviewed in Section 2.4.2.
2.4.1 Basic Introduction to Artificial Intelligence
With the fast development of AI hardware such as graphical processing unit, AI

techniques have been prosperous in recent years. Different from traditional mathematical
deduction which requires massive human involvements, AI techniques can help machines
to perceive, analyze, think, and make decisions like human beings, but in an automatic
manner. The fascinating AI techniques can be the potential solutions to relieve human-
dependence and improve design accuracy in the circuit parameter and modulation design
30
of DC-DC converters. In general, popular AI techniques in the design of DC-DC converters
can be assorted into four types: machine learning, metaheuristic algorithms, fuzzy
inference system, and expert system.
(a) Machine Learning
Machine learning (ML) provides computer the capability to interpret data, to aggregate
similar patterns and to detect interesting features. In definition, ML is a data-driven method
which automates analytical model building process. Based on the task features, ML can be
further classified into supervised learning, unsupervised learning, and reinforcement
learning, which are graphically presented in Fig. 2.9.
Given the labeled data (X, Y) where X represents the inputs and Y indicates possible
outputs, supervised learning learns a function fSL that maps inputs X to outputs Y, which is
formulated as Y=fSL(X). Classic supervised learning algorithms include support vector
machine, decision tree, linear regression, ensemble learning such as random forest and
gradient boosting, etc. These classic algorithms have some intriguing features such as fast
inference speed, strong mathematical foundations, and human-like reasoning [85]. For
instance, support vector machine is intrinsically a sparse algorithm which only relies on the
support vectors to make predictions, so its inference speed is fast [86]. Linear regression
and ridge regression are fundamentally based on linear algebra, and Bayesian regression is
derived from Bayesian theory [85]. Decision tree utilizes a tree structure to mimic the
human-like decision process, so it exhibits certain levels of interpretability [87].
However, the classic ML algorithms may lack sufficient learning capability for
complicated mapping functions, which are the general situations in real world problems.
Consequently, attributable to its possibly infinite learning capability, neural network (NN)
is the most popular supervised learning techniques.
31
Decision tree
Classical ML Support vector machine
Supervised Algorithms Random forest
Learning Linear regression
Neural Network
Clustering E.g. K-means

Machine Unsupervised
E.g. Principal
Learning Learning Dimension reduction component analysis
Density Estimation E.g. Kernel density

estimation
Reinforcement E.g. Deep Q learning, One-step actor-
Learning critic, Advantageous actor-critic
Ensemble Learning
Neural Network
Supervised Learning
Cluster 1
Cluster 2
Clustering
3-D Dimension 2-D

Space Reduction Space
Unsupervised Learning
State Feedback
Actor Environment
& Reward
Action
Reinforcement Learning
Fig. 2.9. Classifications of machine learning algorithms.
32
Input features
General Structure of NN
Input Layer
Hidden Layers: weights
Fully-Connected, bias ... bias
Convolution, Recurrent
Output Layer
Output features
FNN CNN RNN

Fig. 2.10. General structure of NN and three widely used networks.
NN is a parallel-structured computational graph mimicking the flexible connections of

biological neurons in brain [88]. As shown in Fig. 2.10, the general structure of NN consists
of input layer, hidden layers and output layer, which are responsible for obtaining inputs,
learning underlying behaviors and inferring outputs. Artificial neurons in NN connect with
one another through adjustable weights, biases, and non-linear activation functions. Being
beneficial from its high non-linearity and easily adjustable structure, NN can learn any
complex and nonlinear relationships between design parameters and objectives with
arbitrary precision. In the current literatures, three types of NN are commonly adopted,
namely feedforward NN (FNN), recurrent NN (RNN) and convolutional NN (CNN). FNN
passes the information in only one direction, from inputs to hidden layers and then to
outputs. CNN utilizes convolutional and pooling layers to handle image-like data, so CNN
is widely used in image recognition, object detection, and video detection [89]. Different
from FNN which does not have cycles or loops in the network, RNN utilizes loops to
recurrently feed the historical information to the current output, exhibiting temporal
dynamic behaviors. RNN is proficient in handling time-series data, so is widely used in
time-series prediction, natural language processing, voice detection, and control [90].
In contrast to supervised learning, unsupervised learning extracts possible patterns from
unlabeled data (X,), where only inputs X are given. There are three major types of
unsupervised learning approaches: clustering, dimension reduction and density estimation.
33
Clustering algorithms such as K-means and fuzzy-C-means find the clusters of data by
defining similarity metrics on feature space. Dimension reduction algorithms such as
principal component analysis and linear discriminant analysis reduce the redundant
dimensions to keep the useful features. Density estimation approaches such as kernel
density estimation aim to find the probability distribution that can best describe the data.
Reinforcement learning is another thriving class of machine learning. In reinforcement
learning, an actor (which is commonly represented by a NN) takes an action based on the
current state, and the environment updates the current state and returns a reward to the actor.
By minimizing the loss functions relating to future rewards, a good actor can be trained,
which can be deployed in real-world environments. In this process, no training data is
required. Reinforcement learning is viewed as the future of machine learning because of
the following attracting features. First, no labeled data is required, which saves efforts for
data collection and annotation. Second, reinforcement learning exhibits good temporal
behaviors, and can quickly adapt to new environments. Besides, reinforcement learning is
robust to data bias. Commonly used reinforcement learning algorithms are deep Q learning,
one-step actor-critic, and advantageous actor-critic.
(b) Metaheuristic Algorithms
Metaheuristic algorithms (MHAs) are stochastic optimization techniques, which are

derived from biological phenomena or physical processes. As shown in Fig. 2.11, MHAs
have two main categories, namely trajectory-based algorithms and population-based
algorithms. Trajectory-based MHAs only have one solution to be updated per iteration, and
a typical trajectory-based algorithm is the simulated annealing algorithm, which simulates
the slow cooling of metals. Population-based algorithms update a population of candidate
solutions in one iteration, so they are faster than trajectory-based algorithms. Population-
based algorithms have two main categories: evolutionary algorithm and swarm intelligence.
The most widely used evolutionary algorithm is the genetic algorithm (GA), which is meant
for solving mixed-integer optimization problems. Some examples of swarm intelligence
are particle swarm optimization (PSO) and ant colony optimization (ACO) algorithms.
PSO algorithm is originated from the social behaviors of bird flocks and performs the best
in continuous optimization problems. Imitating the information tracking mechanism of ants,
ACO algorithm specializes in solving discrete optimization.
34
The key characteristics of MHAs are that better individuals have larger chances of
survival and reproduction, while worse individuals can still survive and reproduce, because
of which the candidate solutions can maintain good diversity while can still converge to
optimum. The common steps of MHAs shown in Fig. 2.12 are discussed as follows. First,
the hyperparameters and states of algorithms are initialized, and the objective values of
individuals are then evaluated. Subsequently, individuals will be selected to generate new
solutions according to their fitness values, and better ones stand larger chance of survival.
Afterwards, new solutions are compared to original ones and get updated. This process
repeats until the stopping criterions have been met. MHAs can overcome the limitations of
conventional optimization techniques and obtain better optimization results with faster
convergence speed.
Trajectory-based E.g. Simulated annealing
Metaheuristic Genetic algorithm

Algorithms Evolutionary Immune system
Algorithm
Population-based Differential evolution
Swarm Particle swarm optimization
Intelligence Ant colony optimization
Fig. 2.11. Classifications of metaheuristic algorithms.
PSO
Start
Initialization Continuous
Optimization
Fitness/Objective Function Evaluation
GA
Select & Generate
Mixed-Integer
Compare & Update
Optimization
No
Stop criterion met? ACO
Yes Discrete
End Optimization
Fig. 2.12. Common process of metaheuristic algorithms.
35
(c) Fuzzy Inference System
Taking the advantage of fuzzy set theory, fuzzy inference system (FIS) can properly
interpret the ambiguity and fuzziness of real-world data. FIS transfers the usual crisp value
(0 or 1) to a degree of truth (continuous between 0 and 1), which provides human-like logic
that enables intermediate degrees other than true or false [91]. FIS has the advantages of
good interpretability, the capability of embedding prior knowledge, and low time and space
complexity. In general, FIS is classified into Mamdani and Sugeno types [92], which are
shown in Fig. 2.13.
Fuzzy Inference
Congregation
x* =
∫ xµ ( x)dx
∫ µ ( x)dx
Defuzzification
Input 1 Input 2 …
Fuzzification
Max Mamdani FIS
Fuzzy Inference
Rule 1
ω1 f1 = a1 x + b1 y + c1 Congregation
and Output
Rule 2 f = a x + b y + c
ω2 2 2 2 2 ω1 f1 + ω2 f 2 + ω3 f3
f =
ω1 + ω2 + ω3
Rule 3 f 3 = a3 x + b3 y + c3
ω3
Input 1 Input 2 … Sugeno FIS
Fuzzification
Fig. 2.13. Mamdani FIS and Sugeno FIS.
The output function of Mamdani FIS belongs to fuzzy membership functions, and a
typical Mamdani FIS contains four steps: fuzzification, fuzzy inference, fuzzy rule
congregation and defuzzification. Fuzzification step computes the membership degrees of
input variables belonging to each fuzzy linguistic set. Fuzzy inference step evaluates fuzzy
rules. The results of all fuzzy rules are congregated and defuzzified to calculate the outputs.
Mamdani FIS can be implemented in both multiple input and single output (MISO) system
and multiple input and multiple output (MIMO) system [92]. Compared to Mamdani FIS
whose outputs are fuzzy membership functions, Sugeno FIS has no fuzziness in its output,
36
and it only utilizes crisp functions as the output. After the fuzzy inference step, Sugeno FIS
computes its final output through the mathematical combinations of crisp values and rule
firing strength, which is different from the defuzzification step in Mamdani FIS. Sugeno
FIS possesses more flexibility than Mamdani FIS, but it can only be used in MISO system.
(d) Expert System
Expert system is one of the earliest AI techniques that has been mainly used for the
design of power converters. As shown in Fig. 2.14, it consists of an embedded
knowledgebase and database and an inference engine to perform prediction and action.
Conventionally, the expert knowledge is integrated with Boolean logic catalogs, and the
human-like reasoning can be realized through interacting with the inference engine. For
instance, the input filter, output filter, inverter, and rectifier in uninterrupted power supply
systems can be designed by expert systems [93]. The technique of expert systems is
reviewed in detail in [94].
Prediction
and Forecast
Action and
Operation
Embedded Knowledgebase
Inference Engine
and Database
Fig. 2.14. General architecture of expert systems.
2.4.2 Applications of AI Algorithms in the Life Cycle of Power Electronics
The mentioned four main types of AI techniques have been applied in the life cycle of
power electronics, including the design, control, and maintenance of power converters. Fig.
2.15 lists some applications of AI in the life cycle of power converters, where machine
learning techniques have been widely adopted in modelling, fault diagnosis, advanced
control, performance optimization, condition monitoring, etc. Metaheuristic algorithms are
mostly used for the design and optimization of power converters, while fuzzy inference
systems have been applied for real-time control and fault diagnosis. Besides, expert
37
systems are mainly adopted for computer-aided design. A holistic overview of AI in power
electronics is given in [95].
Condition monitoring
Modelling Remaining useful life prediction
Design automation Predictive maintenance
Performance optimization Abnormality detection
Circuit parameter design Fault diagnosis
PID tuning
Adaptive control
Energy management
Fault-tolerant operation
Modulation optimization
Fig. 2.15. Applications of AI in the life cycle of power electronics.
2.4.3 Applications of AI Algorithms in the Circuit and Modulation Design

of DC-DC Converters
In this section, the applications of AI algorithms in the circuit and modulation design of
DC-DC converters are presented. The flowchart shown in Fig. 2.16 summarizes the design
and control of DC-DC converters. As a preliminary stage, circuit and control models are
built offline with hybrid data-driven and knowledge-based approaches. The first stage
optimizes the circuit parameters of DC-DC converters, and the second stage designs the
controller and deploys the controller in real time. The third stage actively collects operation
data and updates the built circuit and control models if outdated.
As discussed in Section 1.3, traditional circuit and modulation design approaches for
DC-DC converters bear the limitations of heavy manpower burden and low design
accuracy due to the following reasons: overwhelming manual analysis and deduction of
design objectives, mathematical approximations, suboptimal optimization, and suboptimal
modulation. To overcome the limitations, NN, MHA and FIS can be used, the applications
of which in the design of DC-DC converters in Table 2.1 are demonstrated one by one
below.
38
Preliminary: Offline Model Building for Circuit or Controller
Simulation Expert Knowledge
Data Offline Surrogate Models
• Preprocessing
Hybrid Data-driven and
Knowledge-based • Feature Extraction
• Data-driven Modeling
Performance • Fitness / Objective functions
Analysis Circuit Physics
2. Control Design and

1. Circuit Parameter Design
Implementation
Identify Design Parameters and Build Control
Objectives Models
Trained
control
models
Build Circuit Controller Optimization and
Models Design
Trained
circuit
models
Optimize Converter
Online Implementation
Designs
Update Models if Evaluate the Collect Operation

Outdated Existing Models Data
3. Feedback Experimental Data to Update Built Models
To fine-tune or retrain models
Fig. 2.16. Flowchart for the design and control of DC-DC converters.
Table 2.1 Applications of AI in the Design of DC-DC Converters.

AI Algorithms Functions Exemplar Applications
Machine learning Data-driven modelling [8], [54], [96]
Single or multi-objective
Meta-heuristic algorithm [11], [12], [25], [97], [98]
optimization
Real-time modulation [67], [99], [100], [101],
Fuzzy inference system
and control [102], [103], [104]
39
Utilizing NN, the drawbacks of burdensome manual deduction and inaccurate
performance analysis can be significantly relieved. If sufficient performance data such as
efficiency, reliability, ripples and stability is provided, NN can be trained to automatically
learn the underlying mathematical expressions, serving as accurate data-driven models to
substitute time-consuming human-dependent performance analysis. For instance, in [54] ,
a NN was trained on simulation data to predict the junction temperature under given
mission profiles. With the thermal behaviours evaluated by the first NN, another NN was
trained to act as the surrogate model for component lifetime consumption for reliability-
oriented parameter design. In addition, in the efficiency-oriented design of TPS modulation
for DAB converters [8], simulation was run for sufficient number of times to collect the
training data of total power loss. Given the power loss data, a NN was automatically trained,
acting as the equivalent data-driven model for efficiency performance. Therefore, the
deduction of efficiency model was achieved automatically, realizing full design automation.
Another example is the design of an isolated DC-DC converter in the modular multilevel
cascaded back-to-back system, in which a recurrent NN was trained to reproduce the time-
varying temporal behaviors of converters [96]. The surrogate recurrent NN facilitated fast
and accurate circuit design.
MHA aims to tackle the issues of suboptimality and high computational cost in
conventional enumeration-based and deterministic algorithms. Recently, MHAs have been
increasingly adopted in the circuit and modulation design of DC-DC converters because of
the advantages of good optimization capability, fast convergence speed, no mathematical
deduction required, and easy implementation. For instance, in [97], simulated annealing
algorithm has been adopted to optimize the parameter values of a DC-DC converter.
Considering the infinite combinations of varying parameter values, a cutting-edge PSO
algorithm was adopted in [11] to achieve stability, high efficiency and robust voltage
conversion gain of a resonant DAB converter cascaded with a Buck converter. If multiple
optimization objectives are considered simultaneously, multi-objective MHAs can be used.
For example, the efficiency, reliability and cost of a distributed maximum power point
tracking converter were optimized by NSGA-II [98]. With the output LC filter as design
parameters, good holistic performance of a DC-DC converter was realized via NSGA-II
[12]. Furthermore, by tuning the frequency, current density, magnetic influx, transformer
40
topology and material, and type of power switches, the weight, cost and power loss of an
isolated DC-DC converter were minimized altogether through NSGA-II [25].
To conquer the drawbacks of discreteness and high algorithm complexity in
conventional approaches for real-time modulation, FIS can be used. Compared with the
conventional online modulation approaches, the time and space complexity of FIS is
independent of data size, and a carefully designed FIS only requires low storage size and
has fast computation speed [99], [100]. Apart from its superior algorithm complexity, FIS
has other appealing advantages such as easy implementation, good linguistic
interpretability, and satisfactory generalization capability [101]. Being beneficial from all
the merits, FIS has been widely implemented in the real-time modulation of DC-DC
converters. For instance, in the maximum power point tracking of a Boost-converter-
supplied PV system, the fuzzy inference controller, substituting the conventional PID
controllers, has shown strong robustness against the fluctuation of parameters, loads, and
supply voltage [102]. Li et al. have proposed a FIS-based modulation scheme for a current-
stress-minimized TPS modulation for isolated DAB converters under varying operating
power and voltage [67]. In [103], the network-based FIS approach offered extremely fast
dynamic response, effectively controlled the injected power, and maintained the stringent
voltage, current, and frequency conditions. [104] presented an adaptive-network-based FIS
controller for the unbalanced voltage compensation in a low-voltage microgrid with
multiple voltage source converters.
2.5 Summary
In this chapter, relevant research works regarding the objectives and motivation of this
thesis have been comprehensively reviewed. This chapter covers the basic introduction to
DC-DC converters, the reviews of circuit parameter design approaches and modulation
approaches for DC-DC converters, and the applications of AI techniques in the design of
DC-DC converters. The advantageous AI techniques can solidly relieve the issues of heavy
manpower burden and low design accuracy. Consequently, the proposed AI-based
methodologies for the circuit and modulation design of DC-DC converters in this thesis
can truly provide some values to the current academia and industry.
41
Chapter 3 Multi-Objective Design of Output LC Filter for
Buck Converter via the Coevolving-AMOSA Algorithm
In this chapter, to tackle the problems of suboptimality and infeasible computational load
in conventional optimization approaches as illustrated in Section 1.3, an MHA is adopted.
Particularly, a simulated-annealing-based multi-objective design approach considering the
trade-off among efficiency, power density and cutoff frequency is proposed for the design
of output LC filter for Buck converters. The multi-objective MHA has been improved to
generate a Pareto frontier with wider coverage and better uniformity. The proposed
approach here is a computer-aided design approach, which solves the optimization problem
automatically with the MHA.
Output LC filter is one of the most important parts for Buck converters. The existing
optimization methods for LC filter fail to provide fully optimized design with considerations
of only few design targets. The difficulty in a holistic design approach for LC filter lies in
the trade-off relationships among different design targets. For example, higher efficiency
leads to larger volume and smaller volume results in worse filtering capability. To improve
the overall performance of the output LC filter in Buck converter, a multi-objective design
approach is proposed in this chapter, taking the power loss, volume and cutoff frequency as
the design targets. This proposed holistic design approach takes the advantage of Pareto
frontier to deal with the conflicting design targets to achieve a compact LC filter with
optimized power efficiency and filtering capability. However, the Pareto frontier generated
by the previous multi-objective algorithms suffers from the nonuniform and incomplete
coverage, which seriously undermines the design accuracy. Thus, the coevolving-AMOSA
algorithm is proposed specially for this multi-objective design to provide a Pareto frontier
with uniform and complete coverage. Via this proposed multi-objective design approach for
the output LC filter in Buck converter with the coevolving-AMOSA algorithm, the output
LC filter can be flexibly designed to meet requirements in various applications while
maintaining outstanding comprehensive performance. Three optimal design cases for three
specific application scenarios are presented as design examples. Finally, the experimental
results validate the effectiveness of the proposed multi-objective design approach.
42
3.1 Introduction
Buck converters are playing important roles in both industries and our daily life. In
industry, Buck converters are applied in electric vehicles [105], renewable energy systems
[106], and others [107] for power regulation and voltage conversion [108]. In our daily life,
the applications of Buck converters are everywhere, such as portable electronic devices
[109], power audio systems [110], photovoltaic systems [111], etc.
To reduce the ripples of Buck converters, passive output LC filter is commonly accepted,
due to its low cost and easy implementation. Traditional design [112] of output LC filter
mainly relies on the output voltage and current ripple requirements. However, output LC
filter not only has influence on the ripples of output voltage and current, but also affects
other performance [113] of Buck converters. For example, the parameter selection of LC
filter will directly affect the power loss of Buck converter which is expected to be as small
as possible to maintain high power efficiency. Moreover, the values of inductance and
capacitance will influence the volume of LC filter. Additionally, to ensure better filtering
capability, the cutoff frequency is required to be small, which is also determined by the
parameters of output LC filter.
High-efficiency applications
Airplane Satellite Ferry Electric vehicle

Small-size applications
Battery adapter Rooftop PV Digital camera LED

Optimal-filtering-capability applications
Audio amplifier MP3 player Audio system
Fig. 3.1. Different applications of Buck converters.
Apparently, some specific applications have strict requirements on certain design

objectives. As described in Fig. 3.1, airplanes, satellites and electric vehicles demand high-
efficiency products [114]. Battery adapter, rooftop PV, digital camera and LED, which have
43
limited space, prefer more compact electronic devices [115]. And the LC filter with smaller
cutoff frequency in Buck converter displays better filtering capability, which is suitable for
audio amplifier or MP3 player with strict requirements on the ripple reduction [110]. Even
though some specific applications have strict requirements on certain performance
indicators, the overall performance of Buck converter is still expected to be optimal, which
means that other design objectives should also be taken into considerations.
However, the literature survey reveals numerous research publications on the design of
LC filter which only deals with one design objective, such as cost [29], volume [39], voltage
quality [116] and reliability [117]. For instance, the volume of the capacitor is set as the
design objective in [39]. To improve power efficiency, power loss is optimized in [118].
For optimal filtering performance, cutoff frequency is considered in [119].
The difficulty in conducting the multi-objective design for the LC filter in Buck converter
lies in the trade-off relationships among different design objectives. For example, smaller
volume requires smaller values of inductance and capacitance, resulting in larger power loss
and worse filtering capability [118]. It is admitted that there are some researchers working
on the multi-objective optimization for the LC filter in Buck converter such as [113], [116]
and [12]. Whereas power efficiency is neglected in these research works which is of great
significance for energy saving and environmental friendliness. Therefore, to conduct the
multi-objective design considering the power efficiency, filtering capability and volume for
the LC filter in Buck converter is the first challenge of this chapter.
Additionally, to solve the multi-objective design problems, usually multi-objective
optimization algorithms are adopted to locate the Pareto frontier which is composed of all
optimal solutions. Multi-objective algorithms incorporate three main types: indicator-based
algorithms, decomposition-based algorithms, and population-based algorithms. Indicator-
based algorithms adopt indicator functions to obtain the Pareto frontier. Decomposition-
based algorithms decompose the original multi-objective problem into several single
objective problems and solve them. Population-based multi-objective algorithms evaluate
multiple solutions (which form the population) at one time, and thus can quickly generate
the Pareto frontier. The commonly used multi-objective algorithms include NSGA-II [120],
multi-objective particle swarm optimization (MOPSO) [121], AMOSA [122],
decomposition-based multi-objective evolutionary algorithm (MOEA/D) [123], and
44
indicator-based evolutionary algorithm (IBEA) [123]. However, the existing multi-
objective algorithms suffer from the nonuniform or incomplete coverage of the Pareto
frontier, seriously undermining the design accuracy [124]. Thus, the second challenge in
this chapter to conduct the multi-objective design for the LC filter in Buck converter is to
improve the uniformity and completeness of the Pareto frontier for more accurate and fully
optimized designs.
Therefore, in this chapter, a multi-objective design approach for the output LC filter in
Buck converter with coevolving-AMOSA algorithm is proposed to achieve a fully
optimized LC filter. In Stage 1, power efficiency, cutoff frequency and volume as three
design objectives are analyzed. And in Stage 2, the specially proposed coevolving-AMOSA
algorithm is adopted for this multi-objective design approach to locate the Pareto frontier
accurately. Then in Stage 3, the final design solutions can be selected along the obtained
Pareto frontier according to the application requirements. In this chapter, three design cases
which fit three specific application scenarios will be provided as design examples.
The rest of the chapter is organized as follows. In Section 3.2, problem descriptions will
be provided, regarding the trade-off relationships among the three design objectives and the
nonuniform and incomplete Pareto frontier obtained by common multi-objective algorithms.
Detailed analysis of the three design objectives, power efficiency, cutoff frequency and
volume will be offered in Section 3.3. The proposed multi-objective design approach for the
LC filter in Buck converter with the coevolving-AMOSA algorithm is detailly introduced
in Section 3.4. Three design examples are listed in Section 3.5, and the corresponding
experimental verification are given in Section 3.6. Finally, conclusion is summarized.
3.2 Problem Descriptions for the Multi-Objective Design of the Output

LC Filter in Buck Converters
3.2.1 Preliminaries: Introduction to Pareto Frontier
When several conflicting objectives are considered, it is impossible to reach one global
optimal design with the optimization of all the objectives, since the optimization of some
objectives will sacrifice the others. Thus, Pareto optimum is defined for a solution if there
is no change that could lead to improvements of all objectives [125]. And the Pareto frontier
45
is composed of all Pareto optima for this multi-objective optimization problem. There
exists no design that can be better than the designs on the Pareto frontier in all objectives.
An example of a Pareto frontier for the minimization of f1 and f2 is given in Fig. 3.2 where
f1 and f2 are negatively related.
f2 * f1 and f2 are negatively related.

Problem: min (f1, f2)
Pareto-Frontier
Designs on
f1 becomes Pareto-Frontier
better, f2 worse Designs outside
f2 becomes Pareto-Frontier
better, f1 worse
f1
Fig. 3.2. Example of a Pareto frontier for the minimization of f1 and f2.
In a word, when objectives are in trade-off relationships, the Pareto frontier provides
optimal designs, based on which the optimal multi-objective designs for LC filter can be
obtained. With considerations of the various application requirements, one final design
solution along the Pareto frontier can be picked out.
3.2.2 Problem I: Trade-off Relationships among the Three Design

Objectives for the Output LC Filter in Buck Converter
Objective 1: Higher Objective 2: Better

efficiency filtering capability
Fully-Optimized
LC Filter in
ff
Tr
Buck Converter
e-o
ad
ad
e-o
Tr
ff
Objective 3: Smaller volume

Fig. 3.3. Descriptions of the multi-objective design for the LC filter in Buck converter.
To guarantee a holistic performance, more comprehensive design objectives should be

considered for the optimization of the output LC filter in Buck converter. Power efficiency,
volume and cutoff frequency are taken into account in this chapter to realize a compact LC
filter with optimized efficiency and filtering capability for Buck converter.
46
However, as described in Fig. 3.3, there are trade-off relationships between these three
objectives. The minimization of power loss is contradicting with smaller volume and the
minimization of volume contradicts with smaller cutoff frequency, which means smaller
volume will lead to worse efficiency and filtering capability.
Targeted at this problem, the first challenge of this chapter is to deal with the conflicting
relationships among the three design objectives (power loss, cutoff frequency and volume)
to realize a fully optimized output LC filter for Buck converter.
3.2.3 Problem II: The Nonuniform and Incomplete Coverage of Pareto

Frontier
As introduced in Section 3.2.1, Pareto frontier is usually utilized to realize the

optimization of multiple conflicting design objectives. The multi-objective optimization
algorithms can be adopted to obtain the Pareto frontier. However, the Pareto frontiers
generated by the commonly used multi-objective optimization algorithms suffer from the
following two drawbacks.
Nonuniform coverage
Legend:
Fail to reach the Real Pareto-Frontier
desired design !
Flawed Pareto-
Frontier
Designs on the flawed
Pareto-Frontier
Desired design
A vacancy spot of the Obtained design
flawed Pareto-Frontier
Fig. 3.4. Problem description: nonuniform coverage of the Pareto frontier.
The first drawback is the nonuniform coverage of the Pareto frontier, as displayed in Fig.
3.4. The obtained Pareto frontier fails to cover the area uniformly, resulting in one or more
vacant areas. If the desired LC filter design is in the vacant position, the final obtained
design solution will differ from the desired design solution, deteriorating the design
accuracy.
The second drawback is the incomplete coverage of the Pareto frontier, as displayed in
Fig. 3.5. Under this case, the Pareto frontier generated by the existing multi-objective
47
optimization algorithms has too small and incomplete coverage. Thus, the obtained design
solution is probably not a fully optimized one, negatively affecting the performance of the
designed LC filter.
Incomplete coverage
The obtained design solution Legend:
can still be further optimized! Real Pareto-Frontier
Flawed Pareto-
Frontier
Designs on the flawed
Pareto-Frontier
Desired design
Uncovered area of the
flawed Pareto-Frontier Obtained design
Fig. 3.5. Problem description: incomplete coverage of the Pareto frontier.
Both drawbacks of the Pareto frontier discussed above, the nonuniform and incomplete
coverage, are expected to be avoided to ensure an accurate and fully optimized design for
the output LC filter in Buck converter. Thus, the second challenge of this chapter is to
improve the uniformity and completeness of the Pareto frontier.
3.3 Analysis of Three Design Objectives for LC Filters: Power

Efficiency, Cutoff Frequency, and Volume
3.3.1 Analysis of Design Objective 1: Optimized Total Power Loss for the
Buck Converter of Optimal Power Efficiency
Since the designed output LC filter will affect the total power loss of the whole Buck
converter, the total power loss of Buck converter is set as the first design objective.
L
Vin SH
SL C R
Fig. 3.6. Circuit diagram of the synchronous Buck converter.
The circuit diagram of synchronous Buck converter is shown in Fig. 3.6. According to
[126]–[128], total power loss includes the power losses of switches SL and SH (SL and SH
48
are defined in Fig. 3.6) and the power losses of LC filters. In this chapter, the designable
parameters are the values of inductance L and capacitance C, and so the power losses are
expressed in terms of whether they are related to L and C, as the following.
(a) Driving loss of switches SL and SH (Pl_dr)
Driving loss Pl_dr [128] is defined in (3.1):

Pl _ dr  2QGVgs f (3.1)
where QG is the total gate charge of main switches. Vgs is gate-to-source voltage. f is the
switching frequency. Pl_dr is constant, since QG, Vgs and f are fixed design specifications.
(b) Conduction loss of switches SL and SH (Pl_on (L))
With [128], the conduction loss of SL and SH, is expressed as:

1 V V
Pl _ on  L  DRon ( ( in o D) 2  I o 2 ) (3.2)
12 Lf
where Vin, Vo are the input and output voltages. Io is the output current. D is the duty
cycle of high-side switch SH. Ron is the equivalent drain-source on resistance of switches.
Pl_on relates to L, according to (2), in which Vo, Io, D, Ron are constant design specifications.
(c) Switching loss of switches SL and SH (Pl_s)
The switching loss Pl_s of switches SH and SL is in (3.3) [128]:
Pl _ s 0.5Vin I L ( tr _ H + t f _ H ) f + 0.5VSD I L ( tr _ L + t f _ L ) f
= (3.3)
where tr_H and tf_H are the rising and falling time of the high side switch SH. tr_L and tf_L
are the rising and falling time of the low side switch SL. VSD is the conduction voltage across
the diode of SL. As can be seen from (3.3), Pl_s is constant.
(d) Core loss of inductor (Pl_Fe (L))
According to [127], the core loss of inductor in Buck converter is computed by the
Steinmetz equation:
Pl _ Fe  L  k B  f   D   (1 D )1  VolL  L

1
  (3.4)
where k, α, β are the parameters in the Steinmetz equation and are constants when the
inductor core material is selected. ∆B is the magnetic fluctuation, calculated by [127] and
datasheets of inductor cores. From (3.4), Pl_Fe only relates to inductance L.
49
(e) Copper loss of inductor (Pl_Cu (L))
The calculation of copper loss of inductor [126] is in (3.5):

1 V V
Pl _ Cu ( L)  ( Rdc  Rac )( ( in o D) 2  I o 2 ) (3.5)
12 Lf
where Rdc is the dc winding resistance of inductor and is obtained from inductor
datasheets, and Rac is the ac winding resistance considering skin and proximity effects and
is computed with [126]. From (3.5), Pl_Cu is related to L only.
(f) Power loss of capacitor (Pl_C (L, C))
The loss of capacitor is computed by (3.6), where ICk is the root mean square of the kth
harmonic current on the capacitor, and is related to both L and C [12]. tanδ is constant and
can be found from the datasheets of capacitors. According to (3.6), with the increasing
values of L and C, Pl_C decreases.

tan 
Pl _ C ( L, C )   I Ck 2  (3.6)
k 2kfC
(g) Total power loss (Pl_tot (L, C))
The total power loss sums (3.1) to (3.6) together, as shown in (3.7). According to (3.7)
and Fig. 3.7, Pl_tot relates to both inductance L and capacitance C.
Pl _ tot ( L, C )  Pl _ dr  Pl _ s  Pl _ on ( L)  Pl _ Cu ( L)  Pl _ Fe ( L)  Pl _ C ( L, C ) (3.7)
Specifications:
Pl_tot (W) Vin=100V, Vo=50V,
18 Io=2A, f = 10 kHz.
Pl_tot decreases when C
14 increases Pl_tot first decreases then
increases when L increases
10
6
1
0.8
0.6 2 2.5
C (mF) 0.4 0.2 1 1.5
0.5 L (mH)
Fig. 3.7. Effects of L and C on total power loss Pl_tot.
Since the minimization of total power loss is equivalent to the maximization of efficiency,
the total power loss is required to be as small as possible. Thus, the design objective 1 is to
50
minimize total power loss for the design of the Buck converter with optimized power
efficiency.
3.3.2 Analysis of Design Objective 2: Optimized Cutoff Frequency for the

Buck Converter with Optimal Filtering Capability
For the output LC filter in Buck converter, smaller cutoff frequency represents better
filtering performance [12]. The relationships between fc and L, C are shown in Fig. 3.8 and
(3.8). The design objective 2 is to minimize cutoff frequency for the Buck converter with
optimized filtering capability.
1
f c ( L, C )  (3.8)
2 LC
fc (Hz)
1200
800
400
0
0.2
0.4 0.6 1 0.5
C (mF) 0.8 2 1.5
1 2.5 L (mH)
Fig. 3.8. Effects of L and C on cutoff frequency fc.
3.3.3 Analysis of Design Objective 3: Optimal Volume for a Compact

Buck Converter
The size of Buck converter is an important factor to be considered in space-restricted

applications [129]. In this chapter, since the design parameters are L and C, only the volume
of inductor and capacitor is considered, and other volume such as the volume of cooling
system is regarded as constant.
The relationship (3.9) between the inductor volume VolL and its inductance is deduced
according to [12].
VolL ( L)  al L (3.9)
where VolL is the inductor volume. al is computed by linear regression method. For
instance, inductors of MCAP series of Multicomp with TAF-200 cores [130] are selected
51
and shown in Fig. 3.9, in which statistical R2 is close to 1, validating the linear relationship
between VolL and L.
According to [12], the volume of capacitor VolC is linearly proportional to capacitance
C, as (3.10) shows.
VolC (C )  ac C (3.10)
where VolC is the capacitor volume. ac can be computed by linear regression method. As
an example, capacitors of ECA1JM series of Panasonic [131] are selected in Fig. 3.10, in
which statistical R2 is close to 1, validating the linear relationship between VolC and C.
With (3.9) and (3.10), the total volume Vtot to be minimized is shown in (3.11), and is
linearly related to the inductance L and capacitance C. The design objective 3 is to
minimize the volume Vtot in (3.11) for a compact Buck converter.
Voltot  L, C   VolC (C )  VolL ( L)  al L  ac C (3.11)
VolL (cm3)
20
16 Data of inductors
12 Fitting curve of VolL (L)
8
4 R2: 91.6%
0
0 100 300 500 L (μH)
Fig. 3.9. Effects of L on volumes of inductors VolL.
VolC (cm3)
5
4 Data of Capacitors
3 Fitting curve of VolC (C)
2
1 R2: 99.6%
0
0 200 400 600 800 C (μF)
Fig. 3.10. Effects of C on volumes of capacitors VolC.
In summary, according to Fig. 3.7 to Fig. 3.10, as L and C increase, Pl_tot generally
decreases, fc decreases and Vtot increases. Thus, the minimization of volume Vtot is
conflicting with the minimization of total power loss Pl_tot and cutoff frequency fc.
52
Start
Ø Specifications: Vin , Vo , P, f
Ø Objectives: Low Pl_tot, Small fc, Small Vtot
Ø Designable Parameters: L, C
Stage 1: Analysis of three design objectives with respects to

inductance and capacitance (Section 3.4.1)
Ø Low power loss: Pl_tot (L, C) with (3.1) to (3.7)
Trade-off Ø Small cut-off frequency: fc (L, C) with (3.8)
Ø Small volume: Vtot (L, C) with (3.11)
Three objective functions
Stage 2: Multi-objective optimization of three design objectives
with coevolving-AMOSA (Section 3.4.2)
(
Solve min Pl _ tot ( L, C ) , fc ( L, C ) ,Vtot ( L, C )
L ,C
)
by the proposed coevolving-AMOSA
Vtot Pareto-Frontier
of Pl_tot , fc ,Vtot
fc Pl_tot
Pareto-Frontier
Stage 3: Obtain the optimal inductance and capacitance
according to application scenarios (Section 3.4.3)
(1) Visually obtain the optimization result O * along Pareto-
Frontier according to the requirement of the application scenario
Vtot O* = ( Pl _ tot* , fc* , Vtot* )
Example of the desired
optimization result O*
for specific application
fc Pl_tot
(2) Obtain the corresponding optimal L* and C*


 ( Pl _ tot ( L, C ) , fc ( L, C ) ,Vtot ( L, C ) )
( L* , C * ) = ( L, C ) 
 ≈ ( Pl _ tot* , fc* , Vtot* ) =O* 
Fig. 3.11. The proposed three-stage multi-objective design of output LC filter for Buck
converters with the coevolving-AMOSA algorithm.
53
3.4 The Proposed Multi-Objective Design Approach for the Output LC
Filter in Buck Converter with Coevolving AMOSA algorithm
In this chapter, aimed at solving problem I and problem II as discussed in Section 3.2.2
& 3.2.3, a three-stage multi-objective design of output LC filter for Buck converter with
the coevolving-AMOSA algorithm is proposed. The flowchart of the proposed design
approach is described in Fig. 3.11.
3.4.1 Stage 1: Analysis of Three Design Objectives
As described in the first part in Fig. 3.11, in Stage 1 of the proposed multi-objective
design of output LC filter for Buck converter, three conflicting objectives (Pl_tot , fc , Vtot)
are detailly analyzed with respects to L and C.
Based on the design conditions, Pl_tot can be analyzed with (3.1) to (3.7) in Section 3.3.1.
fc can be computed with (3.8) in Section 3.3.2. And Vtot can be evaluated with (3.11) in
Section 3.3.3. At the end of Stage 1, three objective functions regarding Pl_tot , fc and Vtot
have been prepared for the multi-objective optimization in Stage 2.
3.4.2 Stage 2: Multi-Objective Optimization of the Three Design

Objectives with the Coevolving-AMOSA Algorithm
(a) Realization of Stage 2
With the three objective functions analyzed in Stage 1, the multi-objective optimization
on these three design objectives will be conducted in Stage 2 with the coevolving-AMOSA
as described in the second part of Fig. 3.11. The optimization function of this problem is
given in (3.12) where Pl_tot,max , fc,max and Vtot,max are defined as the limits of efficiency,
cutoff frequency and size, respectively.
min( Pl _ tot ( L, C ), f c ( L, C ), Vtot ( L, C ))
L ,C
s.t. Pl _ tot ( L, C )  Pl _ tot ,max

(3.12)
f c ( L, C )  f c ,max
Vtot ( L, C )  Vtot ,max
To solve (3.12), an improved AMOSA algorithm called the coevolving-AMOSA is

utilized, which is introduced in Section 3.4.2-(b). The main reason why the AMOSA
54
algorithm is adopted and modified is due to its faster computation speed compared with
other multi-objective algorithms such as NSGA-II [120], MOPSO [121], IBEA [123], etc.
With the proposed coevolving-AMOSA algorithm, a uniformly and completely covered
Pareto frontier can be achieved. And then the obtained Pareto frontier will be delivered to
Stage 3 for further selection of optimal design cases.
(b) The Proposed Coevolving-AMOSA Algorithm
The flowchart of the proposed coevolving-AMOSA is compared with the traditional

AMOSA [122] and shown in Fig. 3.12. The improvements of the coevolving-AMOSA
have been highlighted in red (steps 2 and 5). The pseudo-code of the proposed coevolving-
AMOSA is given in Table 3.1, where U(0, 1) is the uniform distribution between [0, 1].
Compared with the traditional AMOSA, the coevolving-AMOSA algorithm can obtain
the Pareto frontier which has better uniformity and completeness, so the problems of Fig.
3.4 and Fig. 3.5 can be mitigated.
Start AMOSA Start Coevolving-AMOSA
1. Algorithm initialization 1. Algorithm initialization

Improve completeness
& uniformity of PF
2. •Generate new (L, C) by random
2. Generate new (L, C) by fluctuations, if Rand <= pr0
random fluctuations •Generate new (L, C) towards sparse
areas of PF, if Rand > pr0
3. Compute (Pl_tot , fc , Vtot) of
3. Compute (Pl_tot , fc , Vtot) of new (L, C)
new (L, C)
4. Compare & update PF with 4. Compare & update PF with (Pl_tot ,

(Pl_tot , fc , Vtot) fc , Vtot)
Improve uniformity of PF
5. Clustering, if size of PF 5. Remove (L, C) from crowded areas in
exceeds limit PF, if size of PF exceeds limit
6. Update hyper-parameters 6. Update hyper-parameters
7. Go to step 2, until stop 7. Go to step 2, until stop
8. Output PF 8. Output PF
End AMOSA End Coevolving-AMOSA

* PF: Pareto-Frontier *
Fig. 3.12. Flowcharts of the traditional AMOSA algorithm [122] and the proposed
coevolving-AMOSA algorithm (in which PF represents Pareto frontier).
55
Table 3.1 Pseudo-Code of the Coevolving-AMOSA Algorithm.
Algorithm: the Coevolving-AMOSA
1 Initialize parameters of traditional AMOSA, coevolving
probability pr0, and PF to store optimal designs;
2 Rand ← U(0, 1);
3 IF pr0 >= Rand
4 Generate new (L,C) with random fluctuations;
5 ELSE
6 Generate new (L,C) towards sparse areas in PF;
7 Compute (Pl_tot , fc , Vtot) with (1) - (11);
8 IF size of Pareto-Frontier exceeds limit
9 Randomly remove extra (L,C) from crowded areas in PF;
10 Update parameters of traditional AMOSA, decrease pr0 ;
11 IF stop criterion is not met
12 Go to line 2
13 OUTPUT PF
The first advantage, the better uniformity of the achieved Pareto frontier, benefits from
both of the step 2 and step 5 in the proposed coevolving-AMOSA algorithm. In step 2, a
coevolving probability pr0 is introduced to control the process of new design (L, C)
generation. During the iterations, pr0 is decreasing from 1 to 0. If a random number is larger
than pr0, the generated new (L, C) will be led towards the sparse areas within the Pareto
frontier. In step 5, extra designs (L, C) are randomly removed from crowded areas. With
these two steps, uniformity of the obtained Pareto frontier can be greatly improved.
The second advantage, the better completeness of the generated Pareto frontier, is
attributable to step 2 in the coevolving-AMOSA algorithm. In step 2, if a random number
is smaller than pr0, the new (L,C) will be randomly generated, encouraging the algorithm
to thoroughly search for the solution space to broaden the coverage, which benefits the
completeness of the obtained Pareto frontier.
Therefore, with the uniform and complete Pareto frontier found by the coevolving-
AMOSA algorithm, the multi-objective design for the output LC filter in Buck converter
will be more accurate and fully optimized.
56
(c) Comparisons between the proposed coevolving-AMOSA algorithm and other popular
multi-objective algorithms
In this part, several popular multi-objective evolutionary algorithms such as NSGA-II

[120], MOPSO [121], traditional AMOSA [122] and some state-of-the-art algorithms such
as IBEA [123] are given for comparison. Targeted at the multi-objective design in (3.12)
for the output LC filter in Buck converter, these algorithms are repeated for 30 times. To
indicate the uniformity and completeness of the Pareto frontier, two metrics are usually
adopted: minimal spacing (SPm), and maximum distribution range (MDR) [124]. Lower
SPm means better uniformity, and higher MDR means more complete coverage.
Comparison results are listed in Fig. 3.13.
SPm
0.044
0.0434 Better
0.0403
0.04 uniformity
0.0369 0.0371 0.0367
0.036
0.032
NSGA-II MOPSO AMOSA IBEA Coevolving-AMOSA
(a)
1.2 MDR Larger coverage 1.177

1.143
1.1 1.073 1.057
1 0.973
0.9
NSGA-II MOPSO AMOSA IBEA Coevolving-AMOSA
(b)
Fig. 3.13. Expected performance of multi-objective algorithms: (a) SPm; (b) MDR.
As shown in Fig. 3.13 (a), the traditional AMOSA is the worst in terms of uniformity
due to its clustering step 5 in Fig. 3.12 [122]. With the proposed coevolving-AMOSA, SPm
becomes the smallest, indicating that it produces the most uniform Pareto frontier, even
more uniform than the Pareto frontier generated with state-of-the-art IBEA.
As shown in Fig. 3.13 (b), MDR of NSGA-II is the lowest, meaning its coverage is far
from satisfactory [132]. The coevolving-AMOSA displays its MDR at 1.177, so its Pareto
57
frontier covers more complete area, providing fully optimized design choices for engineers.
From Fig. 3.13 (b), the coverage of the proposed coevolving-AMOSA is even wider and
larger than the cutting-edge algorithm IBEA.
To conclude, the proposed coevolving-AMOSA algorithm is able to generate a Pareto
frontier with better uniformity and completeness, providing more accurate and fully
optimized designs for the output LC filter in Buck converter.
3.4.3 Stage 3: Obtain the Optimal Design Solution Based on Application

Requirements
With the Pareto frontier generated in Stage 2, Stage 3 of the proposed design approach
is aimed to obtain the optimal L and C for specific application scenarios. As shown in Fig.
3.11, Stage 3 includes 2 steps, described as the followings.
In the beginning part of Stage 3, the optimization result O* = (Pl_tot* , fc* , Vtot* ) is obtained
visually along the Pareto frontier of three design objectives (power loss, cutoff frequency
and volume) according to the requirement of application scenarios.
After that, with the picked optimization result O*, the corresponding optimal L* and C*
are obtained by (3.13) to find the combination of L and C which can meet the best O*.
Overall, the final optimization solution of L* and C* can be achieved according to the
specific requirement of application scenarios in Stage 3.

 ( Pl _ tot ( L, C ) , fc ( L, C ) ,Vtot ( L, C ) )
( L* , C * ) = ( L, C )  (3.13)
≈ ( Pl _ tot* , fc* , Vtot* ) =
O*
 
3.5 Design Examples of the Proposed Multi-Objective Design for the

Output LC Filter in Buck Converter with Coevolving-AMOSA Algorithm
3.5.1 Design Example with Traditional Design Method
In comparison with the proposed multi-objective design of the output LC filter for Buck
converter, the traditional design is given here [112]. Iripple and Vripple are set as 40%, 10%
respectively.
With (3.14), the inductance is computed as 3.13 mH [112]. According to (3.15), the
capacitance of the traditional design is computed as 30 µF [112]. Pl_tot, fc and Vtot of the
58
traditional design are evaluated as 6.5 W, 495 Hz and 122 cm3.
L=
(1 − D ) ⋅Vo
(3.14)
f ⋅ I o ⋅ I ripple
(π + 4 ⋅ tan δ ) ⋅ I ripple ⋅ I o
C= (3.15)
8π f ⋅ Vo ⋅ Vripple
3.5.2 Design Examples with the Proposed Multi-Objective Design of

Output LC Filter for Buck Converter with the Coevolving-AMOSA
(a) Stage 1 of the design examples
The design specifications are listed in Table 3.2, where the C2M0080120D
semiconductor switches are chosen out of safety purpose to ensure sufficient margins.
Other more appropriate switches can be selected, and the same design process can be
applied. Three objectives with respects to L and C can be analyzed with (3.1) to (3.11), and
are summarized as the following:
• Objective-1: minimize Pl_tot for the design of a high-efficiency Buck converter based on
(3.1) – (3.7);
• Objective-2: minimize fc for the design of a Buck converter with optimal filtering
capability based on (3.8);
• Objective-3: minimize Vtot for the design of a compact Buck converter based on (3.9) –
(3.11).
Table 3.2 Design Specifications of Design Examples.

Parameters of main circuit
Po 100 W f 10 kHz
Vin 100 V Vo 50 V
Main switches (C2M0080120D)
Qg 62 nC Vgs 20 V
Ron 80 mΩ VSD 4.3 V
Output LC filter
Inductor cores TAF-200 series
Capacitor 100 V ECA1JM series of Panasonic
59
(b) Stage 2 of the design examples
With the three design objective functions analyzed in Stage 1, the multi-objective design
problem can be summarized in (3.12), in which the Pl_tot,max is set as 10 W, fc,max is set as
700 Hz, and Vtot,max is set as 100 cm3.
By following the pseudo-code of the proposed coevolving-AMOSA algorithm in Table
3.1, the Pareto frontier of power loss, cutoff frequency, and volume is generated, as shown
in Fig. 3.14.
Vtot (cm3)
100 Pareto-Frontier
80
60
40
20 5
100 300 6
fc (Hz) 500 7 Pl_tot (W)
700
Fig. 3.14. Visualized Pareto frontier of power loss, cutoff frequency and volume,
where each blue dot represents an optimal design case.
(c) Stage 3 of the design examples
In Stage 3, based on the three specific application scenarios in Fig. 3.1, the following
design cases are taken as examples:
Case 1: Minimize total power loss for the design of high-efficiency Buck converter.
Case 1 is suitable for applications such as airplane, satellite, ferry, etc.
Case 2: Keep the same efficiency as the traditional design, while minimizing
volume for the design of a compact Buck converter. Case 2 is appropriate
for space-constrained portable devices such as battery adapter, rooftop PV,
digital camera, LED, etc.
Case 3: Minimize cutoff frequency for the design of the Buck converter with
optimal filtering capability. Case 3 is applicable to areas like power audio
amplifier, MP3 player, audio systems which have stricter requirements on
the reduction of ripples.
60
Optimization results O* of the three design cases, which consist of Pl_tot*, fc* and Vtot*,
are visually obtained from the Pareto frontier in Fig. 3.14 and listed in Table 3.3.
Table 3.3 Objective Values of the Three Required Optimal Designs.

Pl_tot* (W) fc* (Hz) Vtot* (cm3)
Optimal Case 1 5.18 146 63.4
Optimal Case 2 6.46 323 29.1
Optimal Case 3 5.7 103 100.0
For better visualization, the 3-D Pareto frontier in Fig. 3.14 is projected into three 2-D
plots, as shown in Fig. 3.15, together with the traditional design and three optimal design
cases. As shown in Fig. 3.15, compared to the traditional design, case 1 minimizes power
loss by 1.32 W, case 2 keeps the same efficiency as traditional design, while minimizing
volume by 92.9 cm3, and case 3 minimizes the cutoff frequency by 392 Hz.
fc (Hz) Vtot (cm3) Vtot (cm3)

700 140 140
Traditional Traditional
600 120 design 120 design
Traditional
design
500 100 100 Case 3
Case 3
400 80 80
Case 2
Case 1 Case 1
300 60 60
200 40 Case 2 40
Case 1
Case 3 Case 2
5 5.5 6 6.5 7 7.5 5 5.5 6 6.5 7 7.5 100 300 500 700
Pl_tot (W) Pl_tot (W) fc (Hz)
Fig. 3.15. Projected Pareto frontier (blue points): (a) power loss vs. cutoff frequency;
(b) power loss vs. volume; (c) cutoff frequency vs. volume.
Table 3.4 Inductance and Capacitance of Three Optimal Designs.

Inductance L* (mH) Capacitance C* (µF)
Optimal Design Case 1 1.49 800
61
After that, with (3.13) and the optimization results O* of the three design cases in Table
3.3, the corresponding optimization solutions L*and C* are obtained and listed in Table 3.4.
3.6 Experimental Verifications
Switches
Inductor
Output Capacitor
Fig. 3.16. Main circuit of the designed synchronous Buck converter.
To validate the feasibility and effectiveness of the proposed multi-objective design

approach for the output LC filter in Buck converter with the coevolving-AMOSA algorithm,
the design examples given in Table 3.4 in Section 3.5 are verified with hardware
experiments in this section. The hardware main circuit is shown in Fig. 3.16. The detailed
hardware realization of Table 3.4 is shown in Table 3.5. The design specifications are the
same as those in Table 3.2.
Table 3.5 Hardware Realization of the Three Required Optimal Designs.

Inductors of Optimal Design Cases
Cases L* Core Wire N
Case 1 1.49mH T200B-75-200 UEFN/U 1mm 97
Case 2 688µH T175-75-200 UEFN/U 1mm 81
Case 3 2.41mH T250-75-200 UEFN/U 1mm 100
Capacitors of Optimal Design Cases
Cases C* Realization
Case 1 800µF Parallel: 330µF & 470µF, 100V ECA1JM
Case 2 352µF Parallel: 22µF & 330µF, 100V ECA1JM
Case 3 1000µF Single: 1000µF, 100V ECA1JM
62
3.6.1 Experimental Waveforms of the Traditional Design Case and Three
Optimal Design Cases
Vin Vin: [50V / div]

Vo: [20V / div]
Vo
Time: [50 μs / div]
Io: [2A / div]
Io Po: [100W / div]
Po
(a)

Vo: [20V / div]
Vo
Io: [2A / div]
Io Po: [100W / div]
Po
(b)
Vo: [20V / div]

Vo
Io: [2A / div]
Io Po: [100W / div]
Po
(c)

Vo: [20V / div]
Vo
Io: [2A / div]
Io Po: [100W / div]
Po
(d)
Fig. 3.17. Waveforms of the design cases: (a) traditional design; (b) optimal design
case 1; (c) optimal design case 2; (d) optimal design case 3.
63
The experimental waveforms of the traditional design case illustrated in Section 3.5.1
are given in Fig. 3.17 (a). And the three optimal design cases with the proposed multi-
objective design approach of output LC filter in Buck Converter via the coevolving-
AMOSA algorithm illustrated in Section 3.5.2 are given in Fig. 3.17 (b) to (d) respectively.
3.6.2 Evaluation of the Experimental Results
The performance indicators of the traditional and three optimal design cases are
evaluated in experiments and are listed in Fig. 3.18 with respects to total power loss, cutoff
frequency, and volume. The detailed evaluations are stated as follows.
(a) Traditional design case
With the traditional design approach introduced in Section 3.5.1, the volume of the
designed output LC filter in Buck converter is 123 cm3. The input power and output power
are 97.9 W and 91.1 W respectively, and thus the total power loss is 6.8 W and the
efficiency is 93.05 %. Its cutoff frequency is 490 Hz.
(b) Optimal design case 1: maximizing efficiency
The optimal design case 1 as introduced in Section 3.5.2-(c) is expected to have

minimized power loss. The experimental results show that the optimal design case 1 has a
volume at 59.6 cm3, 51.5% smaller than traditional design. Its input power and output
power are 98.1 W and 92.8 W respectively, and thus the total power loss is 5.3 W and the
efficiency is 94.6%. This optimal design case 1 saves 1.6 W loss compared with the
traditional design case. Besides, its cutoff frequency is 147 Hz. Therefore, the optimal
design case 1 is suitable for high-efficiency applications in Fig. 3.1 like airplanes, electric
vehicles, etc.
(c) Optimal design case 2: minimizing volume while maintaining the same efficiency as the
traditional design
The optimal design case 2 as introduced in Section 3.5.2-(c) is expected to have smaller
volume while not sacrificing its power efficiency. The experimental results show that the
optimal design case 2 has the input power and output power at 96.4 W and 89.7 W
respectively, and thus the total power loss is 6.7 W and the efficiency is 93.0%, almost the
same as the traditional design case. Its volume is 29 cm3, 76.4% smaller than the traditional
64
design. The cutoff frequency is 323 Hz. Therefore, the optimal design case 2 is applicable
to space-constrained portable devices such as battery adapters, rooftop PV, digital cameras,
LED, etc.
Total Loss (W)
6.5 6.8 6.46 6.7
5.7 6
6 5.18 5.3
4 Theoretical
2
Experimental
0 Traditional Case 1 Case 2 Case 3
(a)
Cutoff frequency (Hz)
491 490
500
400
323 323
300 Theoretical
200 146 147
103 102
100
Experimental
0 Traditional Case 1 Case 2 Case 3
(b)
Volume (cm3)
140 122 123
100 94.5
100
63.4 59.6 Theoretical

60
29.1 29
20 Experimental
Traditional Case 1 Case 2 Case 3
(c)
Fig. 3.18. Experimental and theoretical results of the conventional and optimal design
cases: (a) total power loss; (b) cutoff frequency; (c) volume.
65
(d) Optimal design case 3: minimizing cutoff frequency
The optimal design case 3 as introduced in Section 3.5.2-(c) is expected to have

minimized cutoff frequency for optimal filtering capability. The experimental results show
that the optimal design case 3 has cutoff frequency at 102 Hz, 79.2% lower than the
traditional design. And its volume is 94.5 cm3, 23.2% smaller than traditional design. The
input power and output power are 95.4 W and 89.4 W respectively, and thus the total loss
is 6 W and the efficiency is 93.7%, slightly better than traditional design. Therefore, the
optimal design case 3 is suitable for audio systems in Fig. 3.1 such as power audio
amplifiers and MP3 players which have stricter requirements on filtering capability.
Overall, the experimental results in Fig. 3.18 are in accordance with the theoretical
analysis in Table 3.3, validating the feasibility and effectiveness of the proposed multi-
objective design of output LC filter for Buck converter via the coevolving-AMOSA
algorithm. The three optimal design cases perform better than the traditional design
example in power efficiency, filtering capability and volume, validating the fully optimized
performance of the optimal designs with the proposed design method. And with the
proposed multi-objective design approach, the output LC filters can be flexibly designed to
meet different requirements in various application scenarios.
3.7 Conclusion
In this chapter, a multi-objective design approach for the output LC filter in Buck
converters via the coevolving-AMOSA algorithm is proposed to deal with three conflicting
design objectives, low power loss, better filtering capability, and small volume. This
proposed design approach contains three stages. In the first stage, three design objectives
with respects to inductance and capacitance (power loss, cutoff frequency, and volume)
will be analyzed detailly to generate three objective functions. In Stage 2, the obtained three
objective functions will be adopted for the multi-objective optimization by the coevolving-
AMOSA algorithm to generate a Pareto frontier. Subsequently, in Stage 3, with the
obtained Pareto frontier, the optimization result will be picked out along the Pareto frontier
based on the concrete requirements of applications, and the final optimization solutions of
optimal inductance and capacitance will be obtained. Specially, the coevolving-AMOSA
algorithm is proposed for this multi-objective design approach and is utilized in Stage 2.
66
The coevolving-AMOSA algorithm has been proved to have better uniformity and
completeness of the Pareto frontier than other algorithms, and thus the design solutions can
be more accurate and fully optimized.
Three optimal design examples have been provided with the proposed multi-objective
design approach based on different requirements in three application scenarios. The
optimized performance of these three optimal design examples has been verified through
hardware experiments and compared with the design example by traditional method.
Therefore, the feasibility and effectiveness of this proposed multi-objective design
approach for the output LC filter in Buck converters with the coevolving-AMOSA
algorithm have been validated.
67
Chapter 4 NN-Based Automated Design for Circuit
Parameters of Power Converters
Although the MHA-based multi-objective design approach for Buck converters in

Chapter 3 automates the optimization process with the introduced coevolving-AMOSA
algorithm, it is still heavily depending on human experts in the analysis and deduction of
design objectives, as its Stage 1 discussed in Section 3.3. The proposed approach in Chapter
3 is intrinsically a computer-aided approach, which suffers from heavy manpower burden
and low design accuracy according to the justifications in Section 1.3.
To promote the circuit parameter design of power converters to the next level of
automation, this chapter proposes an artificial-intelligence-based design approach, which
achieves thorough automation in both the analysis process of design objectives and the
optimization process. In brief, simulation and NN are integrated to automatically train
surrogate models for design objectives, and an EA is used to interact with the trained NN to
search for optimal designs.
In this chapter, parameter design approaches for power converters are the main research
focus, since parameter design is significant in ensuring a satisfactory holistic performance.
Generally, circuit parameter design for power converters consists of two processes:
analysis and deduction process and optimization process. The existing approaches for
parameter design consist of two types: traditional approach, computer-aided optimization
(CAO) approach. In the traditional approaches, heavy human-dependence is required. Even
though the emerging CAO approaches automate the optimization process, they still require
manual analysis and deduction process. To mitigate human-dependence for the sake of high
accuracy and easy implementation, an artificial-intelligence-based design (AI-D) approach
is proposed in this chapter for the parameter design of power converters. In the proposed
AI-D approach, to achieve automation in the analysis and deduction process, simulation
tools and the batch-normalization neural network (BN-NN) are adopted to build data-
driven models for the optimization objectives and design constraints. Besides, to achieve
automation in the optimization process, genetic algorithm is used to search for optimal
design results. The proposed AI-D approach is validated in the circuit parameter design of
the synchronous Buck converter in the 48 V to 12 V accessory-load power supply system
68
in electric vehicles. The design case of an efficiency-optimal synchronous Buck converter
with constraints in volume, voltage ripple and current ripple is provided. In the end of this
chapter, feasibility and accuracy of the proposed AI-D approach have been validated by
hardware experiments.
69
4.1 Introduction
Power converters have been increasingly applied nowadays in both industries and our
daily life. Power converters can regulate power transmission and alter the form of voltage
and current [133]. In industrial applications, power converters such as DC-DC converters
and inverters are the critical enablers in renewable energy systems [134], wireless power
transfer [135] and DC microgrids [136]. Even in our daily life, the applications of power
converters are omnipresent, such as electric vehicle [137], solar PV [6], etc.
To ensure the satisfactory performance of power converters in all the applications, the
circuit parameters of power converters should be carefully designed. And efficiency, size,
cost, reliability, ripples and transient response are several commonly-adopted design
objectives [6], [139]–[141]. To achieve a comprehensively better performance, usually
multiple design objectives are considered simultaneously, which renders the parameter
design for power converters significant and challenging.
Generally, the parameter design for power converters consists of two processes: analysis
and deduction process, and optimization process. Up to now, there have been two main
approaches in the parameter design of power converters, which are traditional human-
dependent design approach [142], [143] and computer-aided optimization (CAO) design
approach [24], [52], [139]. For traditional human-dependent design approach, the analysis
of optimization objectives and design constraints are conducted by engineers totally to
deduce mathematical expressions [142]. And the optimization process will also be
conducted with repetitious manual trials and errors. The major drawbacks, from which the
traditional human-dependent design approach is suffering, are heavy work burden and the
low accuracy due to approximation during the analysis and deduction process [142]. As for
the CAO approach which has been proposed in the past two decades, the optimization
process has been carried out with some optimization algorithms on computers, such as the
recent popular particle swarm optimization algorithm, genetic algorithm and ant colony
algorithm [52]. However, the analysis and deduction process for optimization objectives
and design constraints are still highly human-dependent, resulting in low accuracy and
large amount of consumed time [24].
To relieve the manpower burden in the analysis and deduction process of parameter
70
design, neural network (NN), which is an artificial-intelligence (AI) technique, is an ideal
technique to be adopted. Emulating the adaptive connections of neurons in brain, NN has
the capability to learn from and interpret external data by tuning its adjustable weights. The
easily scalable structure of NN makes it possible to learn any complicated non-linear
functions with any accuracy. Due to these advantages, NN has been widely adopted in
motor optimization [144], modulation strategies [145], and control [146], [147]. For
instance, [144] adopts extreme learning machine to fit the results of finite element analysis
to optimize motor. [145] utilizes NN to realize optimal selective harmonic elimination. NN
serves as the model predictive controller for modular multilevel converters in [18].
However, NNs utilized in the current literature of power converters are mostly basic
networks, the generalization accuracy of which in unseen data still has room for
improvements. To realize a higher prediction accuracy in unseen data, the structure of NN
should be improved.
As inspired by the strong learning capability of NN, to deal with the above difficulties
which the existing parameter design approaches for power converters are facing, an
artificial-intelligence-based design (AI-D) approach is investigated in this chapter. In the
proposed AI-D approach, automation in the two procedures in parameter designs can be
achieved: automation in the analysis and deduction process and automation in the
optimization process. The analysis and deduction process will be conducted by data-driven
models with the assistance of simulation tools and batch-normalization neural network
(BN-NN). And the evolutionary algorithm (EA) will take the responsibility for the
optimization process. With BN-NN and the automatic fashion in these two procedures, the
parameter design for power converters can achieve accurately optimal design results as
well as a large extent of freedom for engineers.
The rest of this chapter is organized as follows. The problems in the existing parameter
design approaches for power converters and the proposed solutions are described in Section
4.2. The detailed process of the proposed AI-based design approach is elaborated in Section
4.3. A design case is illustrated in Section 4.4 and experimental results are presented in
Section 4.5. And Section 4.6 draws the conclusion for this chapter.
71
4.2 Problem Descriptions for the Parameter Design Approaches for
Power Converters and the Proposed Solutions
4.2.1 Problems in the Existing Circuit Parameter Design Approaches for

Power Converters
In the design of circuit parameters for power converters, after specifying the design
objectives and operating conditions, there are two major important procedures. The first one
is the analysis and deduction process for the optimization objectives and design constraints,
after which the mathematical expressions for optimization objectives and design constraints
will be obtained. And the second one is the optimization process to find out the circuit
parameters which can realize optimal performance in the optimization objective without
breaking the design constraints.
Fig. 4.1. Realization of design process (human-dependence or automation) in two

kinds of parameter design approaches for power converters: traditional human-
dependent design approach and CAO design approach.
In the traditional human-dependent design approach, as described with the left side in
Fig. 4.1, analysis and deduction process and optimization process are both carried out by
engineers. To derive the mathematical expressions for the targeted optimization objective
and design constraints, many approximations will be taken for the sake of analytical
convenience. For example, to derive the operating point of two-switch forward converter
in [142], the switches are assumed to be ideal. Besides, as introduced by Lin et. al., in the
deduction of output impedance of dual active bridge converter, only 0th and 1st order terms
72
in Fourier expansion are considered [148]. Even though sometimes approximations are
removed for the sake of high accuracy, the computational burden and complexity are heavy
for engineers [143], [149]. When it comes to the optimization process, repetitious manual
trials and errors are also time-consuming and have no guarantee for optimization accuracy
[113].
Time has seen great improvements since the development of computer science has
contributed to the CAO parameter design approach in the last two decades, which is
presented in the right side of Fig. 4.1. The CAO design approach has realized automation in
the optimization process with the assistance of optimization algorithms [24], [36], [97], [98],
[139]. For instance, [139] modifies the archived multi-objective simulated annealing
algorithm (AMOSA) to achieve multi-objective design of Buck converter. [97] adopts
Monte-Carlo for the optimal DC-DC converter in automobiles. Liu et. al. deduces the
capacitor lifetime through the analysis of its internal temperature rise, analyzes the volume
of L and C based on the inductance and capacitance definitions and their geometric features,
and adopts NSGA-II algorithm for a good comprehensive parameter design [12].
Even though CAO design approach has freed engineers from repetitious trials and errors
to achieve optimal design results, the human-dependence in the analysis and deduction
process remains unsolved. To obtain the mathematical expressions of the optimization
objective and design constraints, complicated and time-consuming analysis cannot be
avoided, which is, at the same time, suffering from accuracy concern. Besides, the nature
of optimization algorithms adopted in CAO is intrinsically a set of rigid instructions to find
optimal solutions for a given function, so CAO approaches have no capability to learn from
and interpret external data to grow intelligence. Therefore, CAO approaches cannot be
considered directly as AI.
4.2.2 The Proposed Solutions for the Automated Design for the Circuit
Parameters of Power Converters
To deal with the problems including heavy work burden and low accuracy in the
parameter design for power converters, which is attributable to the high level of human-
dependence, an artificial-intelligence-based design (AI-D) approach is specially put forward.
As shown in Fig. 4.2, this design approach can carry out both the analysis and deduction
73
process and the optimization process in an automatic fashion, facilitating an easy-
implemented and accurate design.
Fig. 4.2. Realization of design process in the proposed AI-D approach for the circuit
parameters of power converters.
(a) Automation in Analysis and Deduction Process
To eliminate human-dependence in the analysis and deduction process, simulation and

batch-normalization NN (BN-NN) are adopted to build a data-driven model, as described
with Fig. 4.3.
Fig. 4.3. Automation in the analysis and deduction process in the proposed AI-D.
74
Simulation models will be built to evaluate the performance in the optimization
objectives as well as the performance in design constraints under different selections of
design parameters. With simulation models, a neural network will be provided with data
set for training. After training with limited performance data, NN can serve as an accurate
data-driven model because it can figure out any complicated and nonlinear relationships
between design parameters and performance. Thus, it can be used to predict the
performance of new designs.
For the sake of better generalization accuracy in predicting unseen design performance,
BN-NN is specially adopted for building the data-driven models. It consists of three kinds
of layers: scalarization layer, hidden layers, and output layer. BN-NN is named because of
its special batch-normalization layer in the hidden layer. The batch-normalization layer aims
to avoid the over-fitting problem, which will seriously deteriorate the NN accuracy.
Compared with other techniques in avoiding over-fitting, such as L2 weight-decay
regularization [150] and dropout [151], batch-normalization layer [152] does not introduce
extra hyperparameters, and thus is simpler for the tuning of NN. Basically, the batch-
normalization layer applies normalization to layer inputs, and it can adaptively tune the
degree of normalization, with which the over-fitting problem is largely mitigated [152].
With simulation models and BN-NN, the analysis and deduction process in the design
process can be conducted in an automatic fashion, freeing engineers from heavy work
burden. And more accurate performance evaluation can be guaranteed compared to the
traditional manual analysis process with approximation. The special structure of BN-NN
also guarantees better generalization accuracy in predicting unseen design performance.
(b) Automation in Optimization Process
Apart from automation in analysis and deduction process, optimization process in which
design results are finalized to achieve optimal performance can also be carried out
automatically.
Genetic algorithm (GA), one of the popular evolutionary algorithms, is chosen to take the
responsibility of parameter optimization. This choice is considered from the special
characteristic of parameter design problem for power converters. When a power converter
is designed, the design parameters may lie in continuous space or discrete space. For
example, when switching frequency is designed, usually continuous design space is
75
considered. Whereas when inductors or capacitors are designed, only discontinuous and
unconnected values can be chosen because of practical components, so they lie in discrete
design space. The mix of design parameters in both discrete and continuous space
contributes to a mixed-integer optimization problem. Among popular EA (PSO, GA and
ACO), PSO is suitable for continuous optimization [153], and ACO aims at discrete
optimization [154]. Fortunately, GA performs the best in mixed-integer optimization and it
also enjoys fast convergence speed [36]. Thus, GA is suitable for AI-D approach for the
parameter design of power converters.
With the adopted GA, global optimal design parameters will be located to achieve good
performance in the targeted optimization objective without breaking design constraints.
Also, its fast convergence speed is helpful for a prompt design of power converters.
In a word, as discussed above, the proposed AI-D approach is able to realize a high level
of automation in two procedures: analysis and deduction process and optimization process.
The special BN-NN adopted in AI-D ensures high predicting accuracy in unseen design
parameters. Hence, the proposed AI-D approach allows for high accuracy and easy-
implementation in the parameter design of power converters.
4.3 AI-D Approach for the Parameter Design of Power Converters
Fig. 4.4. The parameter design of synchronous Buck converters in the 48 V to 12 V

accessory-load power supply system in EV via the proposed AI-D approach.
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Stage 1 (Section 4.3.1)
Determine Design Specifications
• Operating Conditions: Vin, Vo, Po, Io
• Optimization Objective: Power Efficiency η
• Design Constraints: Vollim, (∆Vo%)lim, (∆IL%)lim
• Design Parameters: fs, L, C
• Parameter Limits: L ∈ [Lmin, Lmax], fs ∈ [fmin, fmax]
C ∈ [Cmin, Cmax]
Create Lookup Tables
Lookup Table I for Inductors
Lookup Table II for Capacitors

Database
Analysis & Deduction Process
Deduce Data-Driven Models for Power Losses and Ripples
Select Combinations of fs,

L, C for BN-NN Training
Lookup Tables
Build Simulation
Data-Driven Modeling via BN-NN

fs Pl_s1 fs Pl_L_Cu
L L Advantages
…
…
C Pl_s2 C Pl_L_Fe • Accurate performance

Losses of Switch Inductor Losses evaluation
fs • Automate analysis&deduction,
fs ∆Vo%
L Pl_C L free from manual deduction
…
…
C C ∆IL%
Capacitor Loss Ripples

Optimization Process
Search for fs*, L*, C*with Optimal Efficiency Advantages
• Globally optimal design
Genetic Algorithm • Fast convergence speed
Optimal Design Results fs*, L*, C*
Fig. 4.5. Flowchart of the proposed AI-D approach applied in the parameter design of
an efficiency-optimal synchronous Buck converter in EV.
The proposed AI-D methodology can be applied to design circuit parameters for all kinds
of power converters with no limitations on the application backgrounds. In this chapter, for
the sake of easy understanding, the proposed AI-D approach is validated in the circuit
77
parameter design of the synchronous Buck converter in the 48 V to 12 V accessory-load
power supply system in electric vehicle (EV) [155].
In EV, the 48 V to 12 V power supply system is increasingly adopted to realize the power
conversion from the provided 48 V power supply to the required 12 V accessory-load
voltage [156], as shown in Fig. 4.4. To facilitate this power conversion process, usually a
synchronous Buck topology is adopted thanks to its good efficiency and simple structure
[155], [156]. When it is designed, efficiency is one important performance indicator to
ensure high power transfer efficiency. In addition, volume and ripples are considered for the
sake of a compact and reliable design to ensure good holistic performance.
In this chapter, the design process takes efficiency as the optimization objective and takes
volume and ripples as design constraints as an example. It should be noted that if any other
objectives or constraints, like cost or reliability, are preferred in other design backgrounds,
this proposed AI-D approach can still be applicable and only some customizations are
needed. For objectives like cost, size, and weight that can be obtained from datasheets can
be directly inferred from the built lookup tables. Moreover, for reliability-related objectives
such as remaining useful lifetime, thermal behavioral models should be built to facilitate
reliability optimization. Besides, more complex objectives like EMI and temperature field
of magnetic components can be considered in the automated design process with accurate
finite element models. The essential idea is to acquire the data for training data-driven
surrogate models or use lookup tables to directly infer the objectives or constraints.
The design example of the efficiency-oriented synchronous Buck converter is based on
the rated operating conditions. The proposed AI-D approach can easily consider the effects
of varying operating conditions by conducting simulations of different operating points
within the considered ranges, and the resulting data-driven surrogate models will feature
varying operating conditions.
In this section, the AI-D approach to design the circuit parameters for the efficiency-
oriented synchronous Buck converter in EV is elaborated, which considers volume and
ripple as design constraints. This design process contains 4 stages, as shown in Fig. 4.5. The
AI-D approach can be easily scaled to a wide range of applications with few modifications,
and the essential steps are always the same. The fully automated AI-D approach adopts
simulation software for data acquisition, applies machine learning algorithms for data-
78
driven modeling, and uses meta-heuristic algorithms for optimization. For different
applications, major efforts are required in building the simulations. As an example, to
optimize the ZVS and ZCS performances for the multi-level DC-DC converter, the circuit
models of the considered converter should be built in simulation tailored for the specified
operating conditions, and the soft switching performances are captured for further data-
driven modeling and meta-heuristic optimization.
4.3.1 Stage 1: Determine Design Specifications
Before further design process, determining all the design specifications is the first stage.
The design conditions should be firstly figured out, including input voltage Vin, output
voltage Vo, output power Po and output current Io. Power efficiency is the optimization
objective, and the design constraints include volume constraint Vollim, voltage ripple
constraint (∆Vo%)lim and current ripple constraint (∆IL%)lim. The parameters that need to be
designed contain switching frequency fs, inductance L and capacitance C. The limits of
design parameters are also necessary as [fmin, fmax], [Lmin, Lmax] and [Cmin, Cmax].
The volume as a design constraint only takes the size of the inductor and capacitor (VolL,
VolC) into considerations because they will be greatly influenced by the choices of design
parameters [139]. The minor effects of parameter design on the volume of other parts, like
PCB board, are neglected.
4.3.2 Stage 2: Create Lookup Tables for Inductors and Capacitors
In Stage 2, since the values of the inductor and capacitor are both design parameters,
lookup tables have to be created for them. With the considerations of practical components,
lookup tables store all the reachable values of inductors and capacitors and aim to bridge
the gap between theoretical analysis and reality.
For inductors, Lookup Table I maps the value of inductor L to the geometric and magnetic
features of the selected core. For capacitors, Lookup Table II maps the value of capacitor C
to the features of the selected capacitor components.
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Fig. 4.6. Toroidal inductor applied in Buck converter.
The core with toroidal shape, as shown in Fig. 4.6, is chosen as an example. The process
to create Lookup Table I for inductors is described with Fig. 4.7. After the specification of
the fill factor of inductor core [157], Ku, with the geometric and magnetic features of cores
obtained from core database, the maximum number of turns Nmax_core and the maximum
inductance Lmax_core each core can reach are computed with (4.1) and (4.2), respectively. In
(4.1) and (4.2), core inner diameter ID, nominal inductance AL are obtained with database,
and AW is the area of wire. Afterwards, Lmax_core is sorted in an ascending order. Lmax_core
partitions the selection of inductor core. For instance, if L is lower than or equal to Lmax_core1,
for the sake of smaller size of the core, core 1 is selected; If L is greater than Lmax_core1, to
avoid core saturation, core 2 is selected. Subsequently, a lookup table on the choices of
cores for the reachable values of inductors can be created.
π ID 2
N ≤ Ku ⋅ =
N max_core (4.1)
4AW
AL
Lmax_core = N max_core 2 µH (4.2)
1000
When it comes to the creation of a lookup table for capacitors, flowchart in Fig. 4.8 is
followed. To realize more values of capacitors with the limited practical components,
possible parallel and serial connections of single capacitors are considered. After the
specification of maximum number of components for parallel and serial connections MP,
all available values of capacitors can be obtained. And then Lookup Table II on the different
ways of connections for different values of capacitors can be built. If there are different
combinations for the same designed value (e.g., for 660 μF, there can be 220 μF * 3 and 330
μF * 2), the combination with smallest volume is selected.
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Specify fill factor Ku
Compute the maximum number of turns

Nmax_ core of every core with (4.1)
Core Database Compute the maximum inductance

Lmax_core of every core with (4.2)
Sort Lmax_core from low to high: Lmax_core1 < Lmax_core2 < Lmax_core3 …
Create Lookup Table I for Inductors

Lookup Table I for Inductors
Discrete Values of L Selected Core
Lcore1,1
Lcore1,2 L ≤ Lmax_core1 Core 1
...
Lcore2,1 Lmax_core1 <
Lmin ≤ L Core 2
Lcore2,2 L ≤ Lmax_core2
≤ Lmax
...
Lcore3,1 Lmax_core2 < Core 3
Lcore3,2
... ...
L ≤ Lmax_core3
• Lcore1,1, …, Lcore3,1,… are possible discrete values of L.

• After selecting core, the geometric (VolL, Ae, etc.) and
magnetic (B-H curve, etc.) features are known.
Fig. 4.7. Create Lookup Table I for inductors.
In this design case, for the sake of illustration convenience, only toroidal cores and
electrolytic capacitors are taken as design examples. If more types of cores and capacitors
are considered, only minor adjustments are required: one lookup table will be created for
one type of cores or capacitors, so different types of cores and capacitors will have different
lookup tables. With the created different lookup tables which store the information of
different types of cores and capacitors, the types of cores and capacitors can be incorporated
as the design parameters to be optimized in the process of AI-D.
81
Fig. 4.8. Create Lookup Table II for capacitors.
4.3.3 Stage 3: Build Data-Driven Models for Power Losses, Voltage

Ripple and Current Ripple
In Stage 3 of the proposed AI-D approach, data-driven models of power losses, voltage
and current ripples are automatically built with simulations and BN-NN. In this procedure,
simulation, which can provide accurate performance evaluation, evaluates the power loss
and ripple performance of different designs. After the training of BN-NN with these
simulation results, BN-NN will serve as accurate data-driven models for power losses and
ripples. The detailed flowchart of Stage 3 is provided in Fig. 4.9 which contains 3 steps.
(a) Step 1: Select Combinations of fs, L, C for BN-NN Training
In Step 1 of Stage 3, combinations of design parameters fs, L, C should be firstly selected.

fs, L and C are uniformly selected within [fmin, fmax], [Lmin, Lmax] and [Cmin, Cmax] for N1, N2
and N3 number of points, respectively. As a result, the total number of combinations of fs, L,
C generated is N1×N2×N3.
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Step 1 Select Combinations of fs, L,
(Section 4.3.3(a)) C for BN-NN Training
Step 2 (Section 4.3.3(b)) N1×N2×N3 Combinations
of ( fs , L , C )
Lookup Table I
Lookup Table I, II
for Inductors
and (4.3) to (4.5)
Parameters for
Parameters for
Magnetic Simulation:
Electrical Simulation:
N, OD, ID, H, Ae,
RL, ESR, ESL
VolL, μi , Hc, Bsat Build Simulation
Data for BN-NN Training:
Switch, Inductor, Capacitor
Step 3 (Section 4.3.3(c)) Losses & Ripples Performance
Data-Driven Modeling of Power Losses & Ripples via BN-NN
fs Pl_s1 fs Pl_L_Cu fs fs ∆Vo%
L L L Pl_C L
…
…
…
C Pl_s2 C Pl_L_Fe C C ∆IL%
Losses of Switch Inductor Losses Capacitor Loss Ripples
Fig. 4.9. Detailed realization of Stage 3: build data-driven models for power losses
and ripples with simulations and BN-NN.
(b) Step 2: Build Simulation for Power Losses and Ripples of Selected Combinations to
Generate Data for BN-NN Training
Step 2 of Stage 3 aims at building simulations for performance evaluation of the selected
combinations of design parameters in Step 1 to generate data for training BN-NN.
The performance indicators that need evaluations include power losses, voltage ripple,
current ripple, and volume. Among them, power losses will be analyzed by magnetic
simulation and electrical simulation. Voltage ripple and current ripple will be evaluated by
electrical simulation. And volume will be obtained from the created lookup tables.
To build the magnetic simulation, the features of inductor core (number of turns N, core
geometry OD, ID, H, Ae, inductor volume VolL, and magnetic properties μi, Bsat) can be
obtained from Lookup Table I.
In addition, to build the electrical simulation, parasitic parameters RL of inductor, and ESR
and ESL of capacitor are required. With Lookup Table I for inductors, the equivalent
resistance of inductor RL can be computed with (4.3), where r is the resistance of wire per
unit length. With Lookup Table II for capacitors, the equivalent series resistance ESR and
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the equivalent series inductance ESL of capacitor can be computed with (4.4) and (4.5) [112],
respectively, where tanδ and kesl are the dissipation factor and ESL factor, both of which are
obtained with the capacitor database.
RL =N ⋅ (OD − ID + 2H ) ⋅ r (4.3)
tan δ
ESR = (4.4)
2π fsC
ESL = kesl C (4.5)
Magnetic simulation tool, Ansys, is used to evaluate magnetic core loss Pl_L_Fe. With
necessary features of inductor core provided by Lookup Table I, magnetic simulation
models can be built to evaluate Pl_L_Fe of all the selected combinations of fs, L, C.
Electrical simulation tool, LTspice, is utilized to evaluate electrical losses, voltage ripple
and current ripple. With the Spice model of power switches provided by the manufacturer,
LTspice can evaluate the losses of high-side switch Pl_s1 and low-side switch Pl_s2, in which
the switching and conduction losses are included. Besides, with the essential parasitic
parameters obtained, electrical simulation by LTspice can also evaluate the inductor copper
loss Pl_L_Cu, capacitor loss Pl_C. Moreover, voltage and current ripples ∆Vo%, ∆IL% of all
the combinations of fs, L, C are also evaluated with LTspice to generate training data for
BN-NN.
In this process, programming language, such as Python, can be adopted to automatize the
running of simulations through proper interfaces of the simulation tools. Consequently, the
programming language can automatically adjust parameters, conduct running of simulations
and collect performance data.
(c) Step 3: Build Data-Driven Models of Power Losses and Ripples via BN-NN
After implementation of simulations in Step 2 of Stage 3, the losses of switch, inductor

losses, capacitor loss and voltage and current ripples of all the combinations of fs, L, C have
been assessed. With these limited performance data, BN-NN will be trained so that the
performance of any possible designs can be evaluated.
As introduced in Section 4.2.2-(a), BN-NN in Fig. 4.3 which is good at avoiding over-
fitting problem is specially adopted. The adopted BN-NN includes three types of layers:
scalarization layer, hidden layers, and output layer.
84
In the AI-D approach for the parameter design of power converters, the first scalarization
layer aims to rescale the magnitude of design parameters fs, L, C within the range of [0, 1].
For instance, originally, fs is more than tens of kilohertz, while L is smaller than millihenry.
They will be both rescaled into [0, 1] for unbiased BN-NN training.
There is assumed to exist H hidden layers, and each hidden layer includes Nh neurons.
Every hidden layer contains a fully connected layer followed by a batch-normalization layer.
The batch-normalization layer aims to avoid the over-fitting problem, which can seriously
deteriorate the NN accuracy.
The last layer is the output layer, and the outputs include losses Pl_s1, Pl_s2, Pl_L_Cu, Pl_L_Fe,
Pl_C and ripples ∆Vo%, ∆IL%. The complete structure of BN-NN is given in Fig. 4.10.
Fig. 4.10. Data-driven modeling of power losses and ripples via BN-NN.
The performance data of power losses and ripples which are offered by simulations of all
the selected N1×N2×N3 combinations are divided into training (70%), validating (15%) and
testing (15%) sets, which are used to train BN-NN, to select structure of BN-NN (Nh, H),
and to test BN-NN in new unseen designs, respectively. With the training and validating
sets, different options of Nh and H are tried, among them the particular Nh and H that reach
the least error on the validating set are the selected BN-NN structure.
Until here, the automatic analysis and deduction process has been finished.
85
4.3.4 Stage 4: Search for Optimal Design Parameters fs*, L*, C* via
Genetic Algorithm
To achieve optimal parameter design for power converters, GA is utilized in this stage to
find optimal design parameters fs, L, C with design constraints in volume, and current and
voltage ripples. The optimization problem is expressed with (4.6).
min ( Pl _ s1 + Pl _ s 2 + Pl _ L _ Cu + Pl _ L _ Fe + Pl _ C )
f s , L ,C
subject to: VolL + VolC ≤ Vollim ,

(4.6)
∆Vo % ≤ (∆Vo %)lim ,
∆I L % ≤ (∆I L %)lim .
Limits of Design Parameters fs, L, C

fs ∈ [fmin, fmax] Continuous
L ∈ Lookup Table I & [Lmin, Lmax] Discrete
C ∈ Lookup Table II & [Cmin, Cmax] Discrete
Initialize Population
( fs1, L1, C1) , … , ( fsM, LM, CM)
Compute Fitness of Population
fs Pl_s1
L Compute Pl_s1 , Pl_s2 , Pl_L_Cu , Pl_L_Fe ,
…
C Pl_s2 Pl_C , ∆Vo% , ∆IL%

fs Pl_L_Cu Obtain VolL , VolC with Lookup Tables
L
…
C Pl_L_Fe Compute Fitness with (4.7a)

fs Fitness Values:
Pl_C . FM
L F1, … , FM ..
…
C Select Parents f1 F1
fs Parents F2
.
∆Vo% F3
..
L Generate New Population

…
C ∆IL% with Crossover & Mutation

BN-NN-Based Data- New ( fs1, L1, C1) , … ,
Driven Models of ( fsM, LM, CM)
Max Iteration?
Losses and Ripples No
Yes
Best Efficiency η* & Optimal fs*, L*, C*
Fig. 4.11. Flowchart of GA in searching for the globally optimal fs*, L*, C*.
The detailed flowchart of GA in solving (4.6) and searching for the globally optimal fs*,
L*, C* is shown in Fig. 4.11, and briefly illustrated as follows. The fitness value of the ith
individual Fi is computed with (4.7a), where Oi is the ith objective value as expressed in
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(4.7b), Omax and Omin are the maximum and minimum of Oi for all individuals, and ξ is a
small constant. In (4.7b), Pl_tot is the total power loss, which is shown in (4.7c).
Omax − Oi
=Fi +ξ (4.7a)
Omax − Omin
 Vol 
Oi =Pl _ tot + max  0, − 1
 Vollim 
(4.7b)
 ∆Vo %   ∆I L % 
+ max  0, − 1 + max  0, − 1
 (∆Vo %)lim   (∆I L %)lim 
Pl _ tot = Pl _ s1 + Pl _ s 2 + Pl _ L _ Cu + Pl _ L _ Fe + Pl _ C (4.7c)
To restrict the volume and ripples of the designed converters, the objective value Oi in
(4.7b) has introduced penalty terms such as “max(0, Vol/Vollim - 1)”, so that the negative
effects of these constraints being exceeded are considered.
Till now, the optimization process has been finished with the assistance of GA. Thus, all
stages of the proposed AI-based design approach have completed, and the optimal
synchronous Buck converter with satisfactory comprehensive performance has been
designed.
4.4 Design Case of the Proposed AI-D Approach to Design an

Efficiency-Optimal Synchronous Buck Converter in EV
With the proposed AI-D approach elaborated in Section 4.3, an efficiency-optimal

synchronous Buck converter applied in 48 V to 12 V accessory-load power supply system
of EV [155] is designed. The design case is illustrated below stage by stage.
4.4.1 Determine Design Specifications
In Stage 1, design conditions and requirements of the synchronous Buck converter applied
in 48 V to 12 V accessory-load power supply system of EV are specified, as listed in Table
4.1. Rated power Po is selected as 100 W for the accessory loads in the EV power supply
system [156], [158].
When the limits of design parameters are determined, switching frequency fs is selected
within the suitable range [20 kHz, 200 kHz] according to [159], [160]. As determined by the
range of fs, the ranges of L and C are chosen from several tens of μH, μF to mH, mF, where
87
the selection of upper limits Lmax and Cmax is out of cost and power density perspectives [12],
and the selection of lower limits Lmin and Cmin considers filtering performance [139]. If a
specific application requires different ranges of fs, L and C from the given ranges in this
design case, the proposed AI-D approach can still be applied with no changes in any steps.
Table 4.1 Design Specifications.

Operating Specifications
Topology Synchronous Buck Vo 12 V
Vin 48 V Po 100 W
Power Switches
Switches IRFB4310PbF, Infineon Dead time 200 ns
RDS(on) 5.6 mΩ VDSS 100 V
Output LC Filter
Inductor cores Toroidal TAF-200 series
Inductor wire UEFN/U 1mm
Capacitors 25 V Nippon KZE series
Design Parameters
Switching frequency fs Inductance L Capacitance C
Limits of Design Parameters
fs fmin = 20 kHz; fmax = 200 kHz
L Lmin = 30 µH; Lmax = 2 mH
C Cmin = 20 µF; Cmax = 1000 µF
Design Constraints
Volume Vol ≤ Vollim = 7 cm3
Voltage ripple ∆Vo% ≤ (∆Vo%)lim = 1%
Current ripple ∆IL% ≤ (∆IL%)lim = 10%
In terms of power switch selection, Infineon IRFB4310PbF is chosen with the

considerations of smaller drain-source on-resistance and suitable drain-source breakdown
voltage under the given operating specifications. The proposed AI-D approach is still
applicable if other power switches are considered. It should be noticed that the simulations
built in Stage 3 need to adopt the models of the used power switches.
88
The modified AI-D approach with the selection of power devices is discussed as follows.
Stage 3 and Stage 4 will be slightly adjusted to incorporate the effects of various power
devices. In Stage 3, after selecting the combinations of fs, L, C, and various switches,
LTspice simulations with different switches will be conducted to acquire the performances
of losses and ripples. Neural networks will then be trained which takes fs, L, C, and S (a
discrete variable indicating the types and series of switches) as inputs. In Stage 4, GA
searches for the optimal fs, L, C, and S to consider the selection of power switches.
4.4.2 Create Lookup Tables for Inductors and Capacitors
Fig. 4.12. Lookup Table I for inductors: features of the selected cores.
Fig. 4.13. Lookup Table I for inductors: discrete values of L.
In Stage 2, lookup tables for inductors and capacitors are created. In this design case, four
toroidal cores (T80-75-200, T106-75-200, T131-75-200, T150-75-200) are adopted from
TAF-200 series. By following the flowchart in Fig. 4.7, Lookup Table I for inductors is
created, as shown in Fig. 4.12 and Fig. 4.13, in which the fill factor Ku of inductor core is
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kept below 0.35 for easy manufacture [161]. Fig. 4.12 provides the information about the
practical features of the selected cores, and Fig. 4.13 shows the possible discrete values of
L and corresponding core selections.
Afterwards, with the maximum number of capacitors for parallel and serial connections
MP selected as 5, according to the flowchart in Fig. 4.8, Lookup Table II for capacitors is
created as shown in Fig. 4.14 and Fig. 4.15. Fig. 4.14 shows the features of selected
capacitors, and Fig. 4.15 describes the possible discrete values of C considering parallel and
serial connections.
Fig. 4.14. Lookup Table II for capacitors: features of selected capacitors.
Fig. 4.15. Lookup Table II for capacitors: discrete values of C.
4.4.3 Build Data-Driven Models for Power Losses and Ripples
In Stage 3, data-driven models for power losses and ripples with BN-NN are built by
following Fig. 4.9, and the detailed three steps of Stage 3 are illustrated as follows.
• In Step 1, within the range of fs, L and C defined in Table 4.1, N1, N2 and N3 in Fig. 4.9
are set as 20, 20 and 20, respectively, and thus 20×20×20=8000 number of combinations
of design parameters in total are generated.
• In Step 2, magnetic simulation model in Ansys and electrical simulation model in
LTspice are built. Simulations are conducted to evaluate the power losses and ripples of
all 8000 combinations, which serve as training data for BN-NN.
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• In Step 3, four BN-NN are built: BN-NN for losses of switch (Pl_s1, Pl_s2) includes 3
hidden layers and 10 neurons per layer; BN-NN for inductor losses (Pl_L_Cu, Pl_L_Fe) has
3 hidden layers and 20 neurons per layer; BN-NN for capacitor loss Pl_C incorporates 2
hidden layers, each of which has 10 neurons; BN-NN for ripples (∆Vo%, ∆IL%) contains
2 hidden layers, and each layer has 10 neurons.
To reflect the higher generalization accuracy of BN-NN, several AI-based regression

techniques (ridge regression, support vector regression, Bayesian regression, deep NN via
Matlab Toolbox) are compared with, and the learning target is the power loss of the high-
side switch Pl_s1 as an example. As shown in Table 4.2, among all the techniques compared,
the proposed BN-NN in Fig. 4.10 manifests the smallest error on all the datasets, indicating
the highest generalization accuracy.
Table 4.2 Mean-Square-Error of the Compared Regression Methods.

Training Set Validating Set Testing Set
Ridge regression 0.719 0.689 0.712
Support vector regression 0.472 0.441 0.433
Bayesian regression 0.310 0.315 0.294
NN via Matlab toolbox 0.084 0.085 0.076
Proposed BN-NN 0.022 0.018 0.025
4.4.4 Search for Optimal fs*, L*, C* via GA
In Stage 4, globally optimal fs*, L*, C* are found with GA in Fig. 4.11. With the trained
data-driven models with BN-NN for power losses and ripples and Lookup Table I and II for
volume, the optimal fs*, L*, C* are searched. fs* is searched within the continuous space [fmin,
fmax], L is chosen from Lookup Table I which lies within [Lmin, Lmax], and discrete C is chosen
from Lookup Table II which lies within [Cmin, Cmax].
The finalized optimal design results of fs*, L* and C* are 36.6 kHz, 281.3 µH and 112 µF,
respectively. They provide an optimal efficiency η* at 93.85%,
The reason why fs* is optimized to 36.6 kHz is related with the predetermined volume
constraint Vollim. If high power density is expected and Vollim is set at a smaller value
compared with the one set in this case, the optimized fs* may reach a bigger value. But in
this situation, the efficiency will decrease due to the increase of switching and core losses.
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Table 4.3 Designed Converter in the 48 V to 12 V Accessory-Load Power Supply
System of EV via the Proposed AI-D Approach.
Designed Efficiency-Optimal Synchronous Buck Converter in EV
Topology Synchronous Buck
Switch IRFB4310PbF, Infineon
fs 36.6 kHz
L 281.3µH, core T106-75-200, wire UEFN/U 1mm, number of turns 55
C 112 µF, 2 number of 56 µF of 25 V Nippon KZE in parallel
Table 4.4 Theoretical Performance of the Designed Synchronous Buck Converter.

Theoretical Performance of Designed Converter
Efficiency η 93.85%
Volume VolL+VolC 6.746 cm3
Ripples ∆Vo% and ∆IL% ∆Vo% = 0.573%; ∆IL% = 9.7%
The design results for the efficiency-optimal synchronous Buck converter in the 48 V to
12 V accessory-load power supply system of EV via the proposed AI-D approach are
summarized in Table 4.3. The theoretical performance of the designed converter is listed
in Table 4.4.
4.4.5 Average CPU Execution Time for Applying the Proposed AI-D
Approach in the Design Case
Table 4.5 Average CPU Execution Time of the AI-D Approach.

Stages in AI-D Average CPU Execution Time
Stage 2 Total 0.232 seconds
Stage 3: Step 1 Total 0.074 seconds
Total 2 days and 4 hours to run the required
Stage 3: Step 2
simulations using four CPU cores
Stage 3: Step 3 1 minute 13.4 seconds to train all NNs
Stage 4 Total 24.38 seconds
To provide insights of the computational time required to implement the proposed AI-D
approach, under the computer platform with Intel Xeon CPU E5-1630 @ 3.7 GHz, 16 GB
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RAM, and Windows 10 operating system, the average CPU execution time of the proposed
AI-D approach applied in the design case is given in Table 4.5. Based on Table 4.5, most of
the computational time and resources are spent on running simulations to collect power loss
and ripple performance data, while the CPU execution time of other stages is neglectable.
4.5 Experimental Verification
In this section, to further verify the designed synchronous Buck converter in Table 4.3 for
the 48 V to 12 V accessory-load power supply system of EV, a prototype has been built and
hardware experiments have been conducted. The hardware platform is shown in Fig. 4.16.
Fig. 4.16. The hardware platform of the designed DC-DC converter.
(a) (b)
(c)
Fig. 4.17. Steady-state waveforms of the designed efficiency-optimal converter: (a)
vin, vo, io; (b) zoom-in view of vo; (c) vL, iL, iC.
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4.5.1 Steady-State Waveforms of the Designed Optimally Efficient
Synchronous Buck Converter
Under the rated conditions given by Table 4.1, the waveforms of the designed converter
in steady state are shown in Fig. 4.17, where the notation and direction of waveforms are
indicated in Fig. 4.4.
4.5.2 Experimental Efficiency of the Designed Converter
(a) Validation of the Optimal Efficiency of the Designed Synchronous Buck Converter when
fs, L, C are Varying
(a)
(b) (c)
Fig. 4.18. Validation of the optimal efficiency of the designed synchronous Buck
converter: (a) fs varies within [0.8fs*, 1.2fs*]; (b) L varies within [230 µH, 350 µH]; (c) C
varies within [81 µF, 168 µF].
To verify that the designed converter reaches an optimal efficiency, the following
experiments are implemented. The switching frequency fs varies around the optimal
frequency fs*, as shown in Fig. 4.18 (a), where the efficiency reaches the highest at the
designed optimal fs*. In addition, when L varies around the optimal L*, as shown in Fig.
4.18 (b), the values smaller than L* should be avoided because they fail to meet the required
94
10% current ripple constraint in equation (4.6), even though they achieve higher efficiency.
Among the L values no smaller than L*, the selected value L* displays best efficiency, so
the optimal efficiency under given constraints is still achieved at the designed optimal L*.
Besides, as shown in Fig. 4.18 (c), C varies within [81 µF, 168 µF], and the results verify
that the optimal efficiency at the designed C* is achieved. Consequently, based on Fig. 4.18
(a) to (c), the designed synchronous Buck converter applied in EV enjoys the optimal
efficiency.
(b) Efficiency Comparison of Designed Synchronous Buck Converters via the Proposed AI-
D Approach, the CAO Approach and the Conventional Approach
To validate the superiority of the proposed AI-D approach, the conventional approach
[112] and a CAO approach [139] are compared with it. Conventionally, voltage and current
ripple constraints are used to determine the values of L and C [112], which are computed
with (4.8), where Vo, Io, fs, (∆Vo%)lim and (∆IL%)lim are given in Table 4.1. And the computed
L and C are listed in Table 4.6. As detailly discussed in [139], the compared CAO approach
manually analyzes and deduces the expressions of total power loss, and then optimizes the
power loss expressions for optimally efficient synchronous Buck converter. The designed L
and C via the compared CAO are shown in Table 4.7.
L=
(1 − D ) ⋅Vo
(4.8a)
f s ⋅ ( ∆I L % )lim ⋅ I o
(π + 4 tan δ ) ⋅ ( ∆I L % )lim ⋅ I o
C= (4.8b)
8π f s ⋅Vo ⋅ ( ∆Vo % )lim
Table 4.6 Conventionally Designed Synchronous Buck Converter.

Conventionally Designed Synchronous Buck Converter
fs 20 kHz
L 540µH, core T135-75-200, wire UEFN/U 1mm, number of turns 68
C 56 µF, single 56 µF of 25 V Nippon KZE
The comparison of experimental efficiency is shown in Fig. 4.19. Obviously, the designed
converter via the proposed AI-D approach achieves the highest efficiency compared with
the conventionally designed one and the one with CAO approach under different load levels.
95
The peak efficiency of the AI-D designed converter in Table 4.3 reaches 93.68%, while the
peak efficiency of the conventionally designed converter in Table 4.6 is only 90.16%.
Compared with the 92.46% achieved by the design via CAO in Table 4.7, the efficiency of
the design via the proposed AI-D is 1.22% higher.
Table 4.7 CAO-Designed Synchronous Buck Converter.

CAO-Designed Synchronous Buck Converter
fs 36.6 kHz
L 334.8µH, core T106-75-200, wire UEFN/U 1mm, number of turns 60
C 94 µF, 2 number of 47 µF of 25 V Nippon KZE in parallel
Efficiency η
95%
85% Peak efficiency 93.68%

Peak efficiency 92.46%
75%
Peak efficiency 90.59%
Proposed AI-D
CAO
65%
Conventional Po
20W 40W 60W 80W 100W
Fig. 4.19. Experimental efficiency comparison of designed converters via the

proposed AI-D approach, the CAO approach and the conventional approach.
The comparison of experimental efficiency is shown in Fig. 4.19. Obviously, the designed
converter via the proposed AI-D approach achieves the highest efficiency compared with
the conventionally designed one and the one with CAO approach under different load levels.
The peak efficiency of the AI-D designed converter in Table 4.3 reaches 93.68%, while the
peak efficiency of the conventionally designed converter in Table 4.6 is only 90.16%.
Compared with the 92.46% achieved by the design via CAO in Table 4.7, the efficiency of
the design via the proposed AI-D is 1.22% higher.
The loss breakdown charts for high (100 W), medium (60 W), and low (20 W) power
levels are given in Fig. 4.20. Under light load conditions, losses of the low-side switch Pl_s2
dominate 76% of the total losses. With the increasing output power, Pl_s1 and Pl_s2 reduce,
96
while the copper loss of inductor windings Pcu and the core loss of inductor core Pfe increase
significantly. Under high power conditions, the copper loss Pcu takes 40% of the total losses.
Pfe
Pl_s1 (2%) Pl_s1 (5%) Pcu (5%) Pl_s1 (8%)
(10%)
Pfe
Pfe Pl_s2 (18%)
(28%) (29%)
Pl_s2
Pcu (44%) Pl_s2
(34%) (76%)
Pcu
(40%)
Po = 100 W Po = 60 W Po = 20 W
Fig. 4.20. Loss breakdown of the designed synchronous Buck converter for high (Po =
100 W), medium (Po = 60 W), and low power (Po = 20 W) levels.
4.5.3 Experimental Volume and Ripples of the Designed Converter
In terms of the volume of the designed converter via AI-D approach, the volume of
inductor and capacitor is measured as 6.9 cm3, which meets the volume constraint of 7 cm3.
As for the experimental ripples, based on Fig. 4.17, the experimental voltage ripple ∆Vo%
and current ripple ∆IL% are 0.583% and 9.6%, respectively, both of which meet the
corresponding constraints at 1% and 10%.
4.5.4 Comparison between the Experimental and Theoretical Efficiency,

Volume and Ripples of the Designed Converter
In this part, the experimental power losses, volume and ripples are compared with the
theoretical performance in Table 4.4. As shown in Fig. 4.21, the experimental performance
is almost the same as those in theory, and the average error is only 1.31%. This proves the
feasibility and high accuracy of the proposed AI-D approach thanks to the specially adopted
BN-NN in analysis and deduction process and the adopted GA in optimization process.
97
(a) (b)
(c) (d)
Fig. 4.21. Comparison between the experimental and theoretical performance: (a)
efficiency η; (b) volume VolC+VolL; (c) voltage ripple ∆Vo%; (d) current ripple ∆IL%.
4.6 Conclusion
An artificial-intelligence-based design (AI-D) approach is proposed in this chapter for the

parameter design of power converters. This proposed AI-D approach is able to conduct the
analysis and deduction process and the optimization process in an automatic fashion. It
provides two outstanding advantages: Firstly, it greatly relieves the work burden for
engineers and realizes a fast and easy-implemented design process; Secondly, high design
accuracy can also be ensured because of the mitigated human-dependence.
In the proposed AI-D approach, to achieve automation in the analysis and deduction
process, simulation tools and batch-normalization neural network (BN-NN) are adopted to
build data-driven models for the optimization objectives and design constraints. The
specially utilized BN-NN is beneficial for design accuracy because it is good at avoiding
over-fitting problem. Besides, to achieve automation in the optimization process, genetic
algorithm is used to search for optimal design results.
The proposed AI-D approach is validated in the parameter design of an efficiency-
oriented synchronous Buck converter in the 48 V to 12 V accessory-load supply system in
EV. And hardware experiments have validated the feasibility and high accuracy of the
proposed AI-D approach.
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Chapter 5 Current-Stress-Minimized Triple Phase Shift
Modulation Design for the Dual Active Bridge Converter
Utilizing Neural Networks, Particle Swarm Optimization,
and Fuzzy Inference System
Chapter 3 and Chapter 4 have discussed the circuit parameter design approaches for DC-
DC converters, while the design of modulation strategy after the design of circuit is also of
great significance. As highlighted in Section 2.3, the modulation strategy has large impacts
on various performance of DC-DC converters such as efficiency, current stress, soft
switching, and stability. Hence, Chapter 5 here and subsequent Chapter 6 are dedicated to
the modulation design of DC-DC converters.
Similar to the conventional circuit design approaches, the traditional modulation design
approaches for DC-DC converters also bear the challenges of excessive manpower
dependence and low modulation accuracy, as justified in Section 1.3. To facilitate the fully
automated design for modulation optimization, this chapter puts forward an artificial-
intelligence-based triple-phase-shift modulation, which achieves optimal current stress over
entire power and voltage ranges for DAB converters. In the proposed AI-based TPS
modulation, NN, PSO algorithm and FIS are adopted to realize automation in the deduction
and analysis stage, optimization stage and real-time implementation stage, respectively. The
issues of discreteness and low modulation accuracy related with the conventional
approaches for real-time implementation are solved by FIS.
In this chapter, the popular dual active bridge (DAB) converter is the main research target
for its outstanding power density and bidirectional power transfer capacity. Up to now,
triple phase shift (TPS) can be considered as one of the most advanced modulation
techniques for DAB converter. It can widen zero voltage switching range and improve
power efficiency significantly. Currently, current stress of the DAB converter has been an
important performance indicator when TPS modulation is applied for smaller size and
higher efficiency. However, to minimize the current stress when the DAB converter is
under TPS modulation, two difficulties exist in analysis process and realization process,
respectively. Firstly, three degrees of modulation variables in TPS modulation bring
99
challenges to the analysis of current stress in different operating modes. This analysis and
deduction process leads to heavy computational burden and also suffers from low accuracy.
Secondly, to realize TPS modulation, if a lookup table is adopted after the optimization of
modulation variables, modulation performance will be unsatisfactory because of the
discrete nature of lookup table. Therefore, an AI-based TPS modulation (AI-TPSM)
strategy is proposed in this chapter. Neural network (NN) and fuzzy inference system (FIS)
are utilized to deal with the two difficulties mentioned above. With the proposed AI-TPSM,
the optimization of TPS modulation for minimized current stress will enjoy high degree of
automation which can relieve engineers’ working burden and improve accuracy. In the end
of this chapter, the effectiveness of the proposed AI-TPSM has been experimentally
verified with a 1 kW prototype.
100
5.1 Introduction
The dual active bridge (DAB) isolated bidirectional DC-DC converter has been widely
adopted in many applications since it was firstly proposed in 1992 [7], such as wireless
power transfer, electric vehicles, DC microgrid [51] and solid state transformer [162]. This
topology consists of one high-frequency transformer and two full bridges, as shown in Fig.
5.1. It attracts much attention for its galvanic isolation, high power density and bidirectional
power transfer capability [163], [164].
H1 H2
Iin Io
+ S5 S7 +
S1 S3 Lr n:1
V1 + vp iL Lm + vs Cf V2
- -
S2 S4
- S6 S8 -
Fig. 5.1. Typical schematic of an isolated DAB converter with single inductor L.
In terms of the modulation strategies for DAB converter, phase shift modulation is most
commonly used because of its simple implementation and fundamental frequency operation
[165]. The simplest technique in phase shift modulation is single phase shift (SPS)
modulation, which has one degree of control freedom in the phase shift between two full
bridges [166]. By modifying SPS modulation, extended phase shift (EPS) adds one more
degree of control freedom in the duty cycle of one full bridge [66], [167]. Similarly, on the
basis of SPS, dual phase shift (DPS) modulation makes the duty cycle of two full bridges
controllable and share the same value [68], [168]. To further improve modulation
performance, triple phase shift (TPS) modulation has been introduced to include one more
degree of control freedom, which realizes three degrees of control freedom in total [70],
[74], [169], [170]. It can control the duty cycle of two full bridges and the phase shift
between them, and thus SPS, EPS, and DPS can be regarded as special cases of TPS. With
all possible modulation variables, TPS modulation widens zero voltage switching (ZVS)
range and improves power efficiency [69]. Hence, TPS can be viewed as one of the most
advanced techniques in phase shift modulation.
101
Currently, the optimization of current stress is a popular trend in the TPS modulation for
DAB converter. In this chapter, peak inductor current is regarded as the current stress
objective to be optimized, which brings advantages to many aspects. First of all, switching
losses are bounded up by peak current, so the optimization of which can reduce switching
losses [171]. In addition, the optimization of peak current can reduce root-mean-square
current and improve efficiency [10]. Moreover, optimal peak current stress can reduce the
size of magnetic core and protect power devices [172], [173].
However, due to the complexity brought by three degrees of control freedom in TPS
modulation, the analytical formula of current stress is considerably difficult to derive [75],
[174]. In previous research works, researchers have investigated the waveforms in every
operating mode and integrated the current piece by piece, which is time-consuming [75],
[165], [169]. With the derived analytical formula, which is very complex, optimization with
these manually deduced mathematical expressions also face challenges. Besides high
computational complexity, some assumptions are supposed before the derivation process,
such as the assumption of lossless components and negligible magnetizing current [10],
[175]. And these assumptions and approximations undermine the accuracy of the analytical
results, even though they simplify the analysis.
In the aspect of realizing TPS modulation strategy, there are usually two ways. One
method is to store the derived formula of optimal results in the modulator [10], [75], [175].
Modulation results will be calculated according to practical conditions. As discussed above,
the method based on analytical formula is easy to implement, whereas it suffers from
complicated deduction process and time-consuming problem. The other method is to store
the optimal modulation results in a lookup table instead of deriving analytical formula
[176]–[178]. In practice, when current operating conditions have been detected, the
modulation variables in this lookup table will be searched and then applied. However, the
modulation results provided by the lookup table are discrete, which leads to a case when the
practical specifications are not listed in this table.
To overcome the difficulties in the optimization of TPS modulation for DAB converter,
researchers have considered to apply some AI tools. Tang et.al. in [178] have tried to
mitigate human-dependance in the optimization process. They have utilized Q-learning to
find optimal modulation variables, which are stored in a lookup table. However, analytical
102
process to derive formula with approximations remains and the lookup table brings discrete
modulation results. Moreover, Harrye et.al have adopted neural network (NN) as a TPS
controller to minimize reactive power [179]. But the reactive power still needs to be deduced
manually and the modulation performance is not smooth as expected because the NN
controller is applied in an open loop control.
Aimed to optimize current stress of DAB converter under TPS modulation, an AI-based
TPS modulation (AI-TPSM) strategy is proposed in this chapter. Generally, AI-TPSM
contains three stages with three different AI tools. Firstly, NN is trained with simulations to
learn the relationships between current stress and variables, which is to replace traditional
complicated and inaccurate analytical process. Secondly, particle swarm optimization (PSO)
algorithm is adopted to find the optimal modulation results which can minimize current
stress. Lastly, fuzzy inference system (FIS) is utilized to store the optimal modulation results
under different operating conditions, which can provide continuous modulation. The
proposed AI-TPSM enjoys high degree of automation which can relieve engineers’ working
burden and improve accuracy.
This chapter is structured as follows: after the introduction, operation principles of TPS
modulation and the existing challenges will be described in Section 5.2; the detailed process
of AI-TPSM is illustrated in Section 5.3; an application case of AI-TPSM is given in Section
5.4; hardware experimental results are displayed in Section 5.5 and conclusion is
summarized in Section 5.6.
5.2 Operating Principle of TPS Modulation and the Existing Challenges
5.2.1 Operating Principle of TPS modulation for DAB Converter
The circuit configuration of DAB converter is presented in Fig. 5.1. Two full bridges H1
and H2 are connected with a magnetic tank which includes an inductor L and a high
frequency transformer. The ac voltages generated by H1 and H2 are vp and vs, respectively.
Under TPS modulation, gate driving signals and waveforms of vp and vs are depicted in Fig.
5.2.
In Fig. 5.2, 2T is a complete switching period Ts. D0 is the phase shift between two full
bridges (S1 and S5) which belongs to [-1,1]. D1 and D2 are the duty cycle of vp and vs,
103
respectively. The ranges of D1 and D2 are both in [0,1]. All of the three degrees of control
freedom can be adjusted to control the transferred power and the inductor current iL(t).
According to [75], the transferred maximum power can be expressed as (5.1), where fs is the
switching frequency. Based on the maximum power to be transmitted Pmax, the value of
single inductor L follows (5.2).
nVV
Pmax = 1 2
(5.1)
8 fs Lr
nVV
Lr ≤ 1 2
(5.2)
8 fs Pmax
T 2T (Ts)
S1S2
S3S4
(1-D1)T V1
vp(t) D1T -V1
D 0T
S5 S6
S7S8
(1-D2)T nV2
vs(t) D2T -nV2
Fig. 5.2. Operating principles of TPS modulation.
5.2.2 Challenge Descriptions for Optimization of TPS Modulation with

Minimized Current Stress
The process to achieve optimal TPS modulation with minimized current stress and carry
out this modulation in practice can be generally divided into three stages, as shown in Fig.
5.3.
Optimization of TPS Modulation for Minimized Current Stress

I. ANALYSIS II. OPTIMIZATION III. REALIZATION
Analyze the relationships Obtain optimal results of Realize optimal TPS
between modulation modulation variables which lead modulation in real-
variables and current stress to minimized current stress time operation
Fig. 5.3. The process to achieve optimal TPS modulation with minimized current
stress and carry out the modulation.
104
After the specification of operating conditions, the relationships between current stress
and variables are analyzed. Variables include modulation variables (D0, D1 and D2) and
operating conditions (output power P and output voltage V2), and current stress is
represented by the peak ipk of the current through inductor iL. And then the modulation
variables will be optimized for minimal current stress under different operating conditions.
In this last stage, the optimized modulation variables will be implemented in real time
according to different operating conditions.
However, in this process, some challenges exist in Stage I and Stage III which increase
complexity and undermine accuracy, as shown in Fig. 5.4.
Stage I: Stage III:

ANALYSIS REALIZATION
Low Assumptions and Discrete Nature of
Accuracy Approximations Lookup Table
High Many Modulation Variables

Complexity and Switching Modes
Fig. 5.4. Challenge descriptions for optimization of TPS modulation.
(a) Challenge in Stage I: Analysis of Current Stress
iL L
+ vL -
vp / N vs
Fig. 5.5. Equivalent circuit of DAB converters with a single L.
The analysis of current stress in previous research papers follows the process below [10],
[75], [172], [175].The equivalent circuit in Fig. 5.5 is utilized to analyze the inductor
current iL(t) and its peak value ipk (current stress) under all the switching modes of TPS
modulation. For given values of D0, D1 and D2, by applying the principle of inductor volt-
second balance piecewise, iL(t) and ipk can be analyzed segment by segment within a
switching period [75], [175].
This process suffers from two drawbacks. Firstly, the manual derivation of the expressions
of iL(t) and ipk under all the switching modes is tedious and complex. This process is
described with Fig. 5.6. TPS modulation has totally three modulation variables and 12
105
switching modes considering both power transfer directions, and thus the derived expression
current stress ipk has high degree of complexity, which has been presented in [10], [75],
[180]. Secondly, accuracy is undermined during analysis process because of the
assumptions of the lossless component and negligible magnetizing current.
Fig. 5.6. Challenge in Stage I: complex segment-by-segment analysis of current stress

under different operating modes of TPS modulation.
(b) Challenge in Stage III: Realization of TPS Modulation
Lookup Table Discrete

(P,V2)1 (D0, D1, D2)1
... ...
Lookup Output
(P, V2)i (P,V2)i (D0, D1, D2)i (D0, D1, D2)i
Operating (P,V2)i+1 (D0, D1, D2)i+1 Optimal
Condition Modulation
... ... Variable
Fig. 5.7. Challenge II: discrete nature of lookup table for the realization of TPS
modulation.
To realize TPS modulation in practical applications, the optimal values of modulation

variables which are obtained in Stage II will be stored in a lookup table. This lookup table
106
will be saved in the memory of microcontroller. In real-time operation, once the current
operation conditions (P and V2) are detected, corresponding optimal values of modulation
variables (D0, D1 and D2) will be called from the lookup table [175].
Due to the nature of lookup table as shown in Fig. 5.7, the data saved is discrete. As a
result, a situation when (P, V2) lies in between (P, V2)i and (P, V2)i+1 may occur. In this
situation, either (P, V2)i or (P, V2)i+1 will be considered as approximation, whose (D0, D1,
D2) are actually not the optimal one for that specific operating condition [178]. Chances
are that the obtained modulation variables fail to present optimal performance,
deteriorating the accuracy.
In summary, the existing optimization approaches of TPS modulation for minimal current
stress have some challenges in high complexity and low accuracy which need to be
addressed.
5.3 The Proposed AI-Based TPS Modulation
To solve the challenges described above, an AI-based TPS modulation (AI-TPSM)

optimization strategy to minimize current stress is proposed in this chapter. Generally, AI-
TPSM contains three stages with one specific AI tool in every stage. The entire process of
AI-TPMS optimization is described with Fig. 5.8.
Stage I: Analysis of Current Stress AI Tool: NN

Simulation and NN with be utilized to build data-
driven model of current stress under TPS modulation
Stage II: Optimization AI Tool: PSO

Based on the model obtained in Stage I, PSO will be
adopted to optimize modulation variables D1 and D2 for the
sake of minimal current stress
Stage III: Realization of TPS AI Tool: FIS

FIS will be applied online to realize optimal modulation
variables under continuous operating conditions
Fig. 5.8. Descriptions for the proposed AI-TPSM.
107
5.3.1 Stage I: NN-Based Analysis of Current Stress
Aimed at the challenge of complicated manual analysis, data-driven model of current

stress is achieved via NN in this section, realizing high-level automation in analysis. The
detailed process of Stage I is given in Fig. 5.9 and illustrated as the following.
Before the start of Stage I, all the operating specifications should be firstly decided,
including the input voltage V1, output voltage V2, output power P and switching frequency
f s.
Stage I. NN-Based Analysis of Current Stress

Select Combinations of P,
V2, D1, D2 for NN Training
N1×N2×M1×M2 Combinations
of ( P, V2 , D1 , D2 )
Result of Stage I
NN-Based Data-Driven
Modeling of Current Stress
Build and Run Simulation P
V2
ipk
…
D1
NN Training
D2
Use the Performance Data Obtained Current Stress ipk
from Simulation to Train NN
Fig. 5.9. Flowchart of Stage I: analysis of current stress with NN.
Firstly, combinations of operating conditions (P, V2) and modulation variables (D1, D2)
are specified. For operating conditions P and V2, N1 number of values of P and N2 number
of values of V2 are evenly selected within [Pmin, Pmax] and [V2_min, V2_max], respectively. As
introduced in Section 5.2, modulation variables D1 and D2 are both in [0, 1]. M1 number of
values of D1 and M2 number of values of D2 are evenly selected within [0, 1]. As a result,
the total number of combinations of operating conditions and modulation variables is N1
× N2 × M1 × M2.
After that, simulation model of the DAB converter under TPS modulation is built in
PLECS software. This simulation will be implemented for the total N1 × N2 × M1 × M2
combinations of operating conditions (P, V2) and modulation variables (D1, D2) to collect
performance data for current stress. In the simulation, to regulate power transfer flow and
to maintain stable output voltage of DAB converter under TPS modulation, D0 is
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automatically determined by the PI regulator for the given combination of P, V2, D1 and D2
[10].
Afterwards, based on the current stress performance data collected with simulation model,
NN can be trained. The total N1 × N2 × M1 × M2 number of simulation data is divided
into training set (70%), validating set (15%) and testing set (15%), which are used for
training NN, selecting NN structure and testing the trained NN on new and unseen data
points. After the training of NN, it can serve as a data-driven model of current stress which
can evaluate current stress performance for any possible combination of operating
conditions and modulation variables. It should be noted that current stress is evaluated by
the peak current through inductor L (ipk).
5.3.2 Stage II: Optimization with PSO Algorithm
In Stage II, based on the data-driven model built in Stage I, optimal modulation variables
D1, D2 under different operating conditions P, V2 will be found.
The mathematical formulation of the optimization problem can be expressed as follows:
For the given operating conditions P and V2, the goal is:
*
ipk = min ipk (P,V2 , D1, D2 ) (5.3)
D1 ,D2
Subject to:
0 ≤ D1 ≤ 1 (5.4)
0 ≤ D2 ≤ 1 (5.5)
To satisfy the power transfer and voltage regulation requirements of TPS modulation, D0,
as one of the modulation variables, will be determined by the output of PI regulator once
D1 and D2 are specified. Hence, D0 is not an independent optimization variable to be
considered.
To solve this optimization problem, particle swarm optimization (PSO) algorithm is
chosen to get the optimal modulation variables D1 and D2. PSO algorithm is an evolutionary
algorithm which mimics the behavior of bird flocks to search for optimal results in the
solution space [136], [153]. To solve the optimization problem in (5.3), dimension of the
particle position is set as 2, consisting of two modulation variables (D1, D2). The position
X of the particle represents the values of D1 and D2. The velocity V of the particle is the
109
change of position in every iteration. The velocity of each particle in the 2-dimension space
is updated with (5.6) and the position is updated with (5.7):
Vim +1 = ωVim + c1r1(Pbestim − Xim ) + c2r2 (Gbest m − Xim ) (5.6)
+1
Xim= Xim + Vi m (5.7)
where m is the iteration number, c1 and c2 are the learning coefficients, ω is the inertia
weight, Pbest is the personal best information and Gbest is the global best information.
For given P, V2
Initialize basic PSO parameters. m = 1.

Data-Driven Model of ipk
P Obtain objective value (ipk) for each particle.
V2 Update personal best Pbest and global best
ipk
…
D1 Gbest and save as historical information.

D2
Update velocity V and position
X(D1,D2) according to (5.6) and (5.7).
m=m+1
YES
Is m ≤maximum iteration ?
PSO Optimization Process
Legend:
NO
Area for optimization. Save ipk and X (D1 ,D2*) under this P, V2
* * *
Particle: Objective value .
Global best result.
NO
Are all P and V2 completed ?
YES
Collect optimal D1, D2 under
different P, V2
Fig. 5.10. Flowchart of Stage II: PSO for optimization.
The entire process of Stage II to find optimal modulation variables D1 and D2 under
different operating conditions is described with Fig. 5.10. Firstly, operating conditions P
and V2 are given. After the initialization, objective value ipk is evaluated for all particles
individually in every iteration. And the position and velocity of every particle will be
updated according to (5.6) and (5.7). Then, the found optimal ipk* and the corresponding
modulation variables D1* and D2* under the given P, V2 are saved when the stopping
criterion has been met. This process repeats until the optimal D1 and D2 under all
combinations of P and V2 have been found.
110
With the PSO algorithm in Stage II, optimal D1 and D2 can be obtained for the given
combinations of P and V2 to realize minimized current stress performance.
5.3.3 Stage III: Realization of TPS with FIS
To avoid the inaccurate optimal modulation variables caused by discrete lookup tables,
fuzzy inference system (FIS) is adopted, achieving continuous and accurate TPS modulation
in real-time applications. FIS is chosen rather than standard interpolation techniques such
as cubic interpolation because of its good interpretability and superior generalization
capability [99]. The FIS-based control diagram for DAB under TPS modulation as proposed
in this chapter is given in Fig. 5.11.
D0 S1
V2 -+ PI S2
Pulse Generator
S3
V2,ref FIS S4
D1 S5 DAB
Modulator S6
S7
D2 S8
P
Switching signal
Rule 1: IF V2,ref is Low & P is O1

V2,ref Low High Weighted
Medium Low; THEN Output O1 D1
O2 Average
P Rule 2: IF V2,ref is Low & P is D2
Median; THEN Output O2
∑w O
i i
... ∑w i
Fig. 5.11. Stage III: online realization of TPS with FIS.
To meet the requirements of power transfer and voltage regulation under TPS modulation,
one of the three modulation variables (D0, D1, D2) should be tuned by PI regulator. In the
proposed FIS-based closed-loop control diagram for DAB under TPS modulation, the phase
shift D0 between two full bridges is chosen as the output of PI module, the input of which is
the error between the reference voltage V2,ref and V2.
As for the duty cycles D1 and D2 inside two full bridges, FIS modulator decides those
values. The principle of FIS to realize online TPS modulation is shown in Fig. 5.11. In FIS
modulator, input membership functions will compute the degree of membership that V2,ref
and P belong to each of the linguistic set (e.g., P is high, V2,ref is low). Afterwards, all fuzzy
rules will be applied to compute their outputs O1, … ON, where N is the total number of
rules. Finally, D1 and D2 will be computed by the weighted average of all the outputs, in
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which the weights are decided by the firing strength of each rule [95].
With the FIS-based modulation in Stage III, modulation variables D1 and D2 can be
adaptively tuned in online applications to realize minimal current stress under varying
operating conditions P and V2. As shown in Fig. 5.12, compared with the discrete lookup
tables (LUT), FIS-based TPS modulation can realize optimal modulation variables D1 and
D2 under the practical situations of varying operating conditions P and V2 with continuous
values. In terms of time complexity, both LUT and FIS have fast computation speed. As for
space complexity, LUT requires large storage space, while FIS has low space complexity.
Moreover, the complexity of FIS is independent of data size, while the complexity of LUT
rises with the increasing of data size [181].
Fig. 5.12. Comparisons between LUT and the adopted FIS.
In the proposed AI-TPSM, Stage I trains NN-based data-driven model of current stress,
mitigating the dependence of tedious manual current stress deduction. PSO is utilized in
Stage II to minimize the current stress for given combinations of operating conditions. FIS-
based control diagram of TPS modulation is proposed in Stage III to obtain optimal
modulation variables under continuous operating conditions in real-time applications.
5.4 Design Case of Applying the Proposed AI-TPSM
With the proposed AI-TPSM approach elaborated in Section 5.3, a current-stress-optimal

TPS modulation strategy for DAB converter is designed. The design case is illustrated as
the following stage by stage.
In this design case, operating conditions and requirements of the DAB converter under
TPS modulation are listed in Table 5.1, where the output power P can vary from 100 W to
1000 W, and output voltage V2 can vary from 160 V to 230 V. Out of safety reasons,
C2M0080120D is chosen. Even if other power switches are considered, the proposed AI-
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TPSM is still applicable. The dead time is chosen to be around 1% of the switching period
to ensure proper and sufficient gap period considering the complexity of TPS modulation.
In this chapter, for the sake of illustration convenience and computation feasibility, only
P and V2 are considered as varying operating conditions. If input voltage V1 is also
considered, AI-TPSM can still be applied by incorporating the varying of V1 into simulation
and NN training (Stage I), optimization with PSO (Stage II) and FIS-based online
realization (Stage III).
Table 5.1 Design Specifications.

Rated Operating Specifications
P 1000 W V2 200 V
V1 200 V fs 20 kHz
Power Switches
Switches C2M0080120D, Cree Dead time 500 ns
RDS(on) 80 mΩ VDSS 1200 V
High-Frequency Transformer
Inductor L 140 μH
Core material Iron based nanocrystalline alloy
Modulation Variables
Duty cycle of full bridge 1 D1 Duty cycle of full bridge 2 D2
Operating Conditions
Output power P Output voltage V2
Ranges of Modulation Variables
D1 D1_min = 0; D1_max = 1
D2 D2_min = 0; D2_max = 1
Ranges of Operating Conditions
P Pmin = 100 W; Pmax = 1000 W
V2 V2_min = 160 V; V2_max = 230 V
5.4.1 Stage I: NN-Based Analysis of Current Stress
In Stage I of the proposed AI-TPSM approach, by following the flowchart in Fig. 5.9,
NN-based data-driven model of current stress is automatically deduced. The steps are
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summarized as follows.
• Firstly, 20×20×20×20 (160000 in total) combinations of P, V2, D1 and D2 are evenly
selected to properly cover their ranges for the benefits of NN training.
• Subsequently, the simulation of DAB converter under TPS modulation is built using
PLECS software and is repeated for all the given combinations of P, V2, D1 and D2.
Current stress performance is obtained in each simulation.
• All the simulation-generated performance data is partitioned into training set (70%),
validating set (15%) and testing set (15%). NN-based data-driven model of current stress
can be trained on training set, where the inputs are P, V2, D1 and D2, and output is the
current stress indicator ipk. The structure of neural network is chosen according to the
lowest error on validating set, as given in Table 5.2 and Fig. 5.13. Compared with other
regression techniques [182] such as response surface, Bayesian regression and support
vector regression (SVR), the trained NN manifests superior accuracy on all the datasets.
As shown in Table 5.3, the average percentage deviations of the trained NN are much
smaller than other techniques. Even in the worst-case scenarios, NN still gives
satisfactory accuracy in all the considered datasets.
Table 5.2 Configuration of NN and Its Optimizer.

Selected NN
Inputs P, V2, D1, D2
Output Current stress ipk
Two layers, each of which have 128 and 32
Hidden Layers
neurons with ReLU activations
NN Optimizer
Data for NN Training 70%, 112,000
Data for Structure Selection 15%, 24,000
Data for Testing New Data 15%, 24,000
Optimizer Adaptive subgradient method [183]
Learning Rate 0.001
Regularization Coefficient 1e-5
Maximal Epochs 10,000
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Table 5.3 Accuracy of the Trained NN.
Percentage Training Set Validating Set Testing Set
Deviations Average Largest Average Largest Average Largest
Response Surface 26.2% 42.0% 26.5% 42.6% 26.5% 39.3%
Bayesian Regression 25.6% 38.6% 25.8% 40.2% 25.7% 41.4%
SVR 9.14% 13.1% 9.07% 12.3% 9.1% 12.9%
NN 0.47% 1.39% 0.46% 1.33% 0.45% 1.29%
P V2 D1 D2 Layer Description
Scalarization Layer:
1 2 3 4 x j − x j ,min
z (0) = , where j=1, …, 4
w3,128(1)
j
x j ,max − x j ,min
w2,1(1)
w1,1(1) ... w4,128(1) Learnable Features: None
Hidden Layers (Fully-Connected

1 b1(1) 128 Neurons b128(1) 128
with ReLU Activation):
w1,32(2) w128,1(2)
w1,1 (2) =
w128,32(2) z (jl ) ReLU ( ∑w ij
(l )
∗ zi(l −1) + bj (l ) )
... i
where j = 1, …, 128, when l = 1;
(2)
1 b1(2) 32 Neurons b32 32 where j = 1, …, 32, when l = 2;
Learnable Features: wij(l), bj(l)
w1,1(3) w32,1(3) Output Layers:
b1(3) =
ipk ∑wi
i1
(3)
∗ zi(2) + b1(3)
Current Stress ipk Learnable Features: wi1(3), b1(3)
Fig. 5.13. Structure of the selected NN.
5.4.2 Stage II: Optimization with PSO Algorithm
Table 5.4 Configuration of PSO Algorithm.

Hyperparameter Name Hyperparameter Value
Number of particles 20
Maximal number of iterations 100
Inertia weight ω Linearly decrease from 0.9 to 0.4
Learning coefficients c1, c2 c1 = c2 = 2.05
In Stage II, by applying the PSO algorithm in Fig. 5.10, the optimal modulation variables
D1 and D2 to achieve minimal current stress under chosen operating conditions P and V2
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have been found. The configuration of PSO algorithm is given in Table 5.4. Fig. 5.14 (a),
(b) and (c) graphically show the optimal D1 and D2 under the output voltage V2 of 200 V,
160 V and 230 V.
D1 or D2 V2 = 200V
1
0.96
Optimal D1
0.92 Optimal D2
0.88
0.84 P (W)
200 400 600 800 1000
(a)
D1 or D2 V2 = 160V
1
0.8
Optimal D1
0.6
Optimal D2
0.4 P (W)
200 400 600 800 1000
(b)
D1 or D2 V2 = 230V
1
0.8
Optimal D1
0.6
Optimal D2
0.4 P (W)
200 400 600 800 1000
(c)
Fig. 5.14. Optimal D1 and D2 under different output voltage V2 and different output
power: (a) V2 = 200 V; (b) V2 = 160 V; (c) V2 = 230 V.
5.4.3 Stage III: Realization of TPS with FIS
In Stage III, the proposed FIS-based control diagram in Fig. 5.11 can realize optimal
modulation variables D1 and D2 with minimal current stress under all possible continuous
operating conditions P and V2. In this design example, type-1 Takagi-Sugeno FIS [99] is
116
implemented, in which the input membership functions of P and V2 are gaussian and have
three linguistic sets (low, medium and high). The configuration of FIS is summarized in
Table 5.5. The plots on the left side of Fig. 5.15 (a) and (b) show the outputs of FIS (D1,
D2) with respect to the inputs P and V2 of continuous values, while those on the right are
the exemplar discrete values saved in lookup table. As can be seen from Fig. 5.15, the
proposed FIS-based TPS is superior to lookup table, achieving real-time modulation under
all possibilities of P and V2.
Table 5.5 Configuration of FIS.

Inputs P, V2 of continuous values
Output Optimal D1, D2
Type of FIS Type-1 Takagi-Sugeno [99]
Type of input membership functions Gaussian
Number of input membership functions 3
Number of rules 9
D1 FIS Output D1 Lookup Table
0.8
0.6
Continuous Discrete
0.4
230 216 1000
202 640 V2,ref (V)
188 174 280 P (W) P (W)
V2,ref (V) 160
(a)
D2 D2
FIS Output Lookup Table
1
0.8
0.6
0.4 Continuous Discrete

1000 160
640 188 174
P (W) 280 202 P (W) V2,ref (V)
230 216 V2,ref (V)
(b)
Fig. 5.15. Outputs of FIS with respect to the inputs P and V2: (a) D1; (b) D2.
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5.4.4 Computational Resources to Apply the Proposed AI-TPSM
Approach in the Design Case
To provide insights of the computational resources required to apply AI-TPSM in the

design case, the average CPU time of Stage I and II and the average turnaround time and
storage size of Stage III are evaluated and shown in Table 5.6.
Compared to Stage II, running simulation and training NN in Stage I require more CPU
time and resources. In Stage III, the turnaround time of deploying FIS online in the control
platform Dspace 1202 is only 4.64 μs, indicating fast computation speed of FIS, and the
storage size of FIS is only 3.4 kB, validating the low space complexity of FIS. As a
comparison, if lookup table is applied online, the storage size can be large as several MB,
which leads to unacceptable turnaround time [181].
Table 5.6 Computational Resources to Apply AI-TPSM.

Platform Performance
Average CPU Time: 3 days and 21
Stage I Intel Xeon CPU E5-1630 @ 3.7
hours with four CPU cores
GHz, 16 GB RAM, Windows 10
Stage II Average CPU Time: 1.57 hours
Average Turnaround Time: 4.64 μs
Stage III Dspace 1202
Storage Size: 3.4 kB
5.5 Experimental Verification
Fig. 5.16. Hardware platform in the experiments.
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In this section, experiments have been conducted to validate the proposed AI-TPSM
approach in the realization of optimal TPS modulation with minimal current stress in the
design case. In the hardware experiments, design specifications are given in Table 5.1, and
the hardware platform is shown in Fig. 5.16.
The experiments in this section include the following parts: rated operation, operation
under different P and V2, load and voltage step response, comparisons among SPS
modulation, lookup-table-based TPS modulation and AI-TPSM, and comparisons between
the experimental and theoretical results of the optimal modulation.
5.5.1 Rated Operating Waveforms

vp: [200V / div] V1: [100V / div]
vp V2: [100V / div]
V1
iL iL: [10A / div]
V2 Io: [2A / div]
vs vs: [200V / div]
Io
Time: [20 μs / div] Time: [20 μs / div]
(a) (b)
Fig. 5.17. Experimental waveforms under rated power of 1000 W and rated output
voltage of 200 V: (a) vp, vs, and iL; (b) V1, V2 and Io.
Fig. 5.17 presents the rated operating waveforms of the DAB converter under the optimal
TPS modulation with minimal current stress, which is designed by the proposed AI-TPSM
approach. The notations and directions of the measured waveforms are given in Fig. 5.1.
Under rated conditions, optimal D1 and D2 are both 1, so the waveforms vp and vs are purely
square waves.
5.5.2 Operating Waveforms under Different Output Power P and Output

Voltage V2
In this part, experiments under output power P of 100 W, 400 W and 900 W and output
voltage V2 of 200 V, 160 V and 230 V have been conducted.
119
vp: [200V / div]
vp
iL iL: [10A / div]
vs vs: [200V / div]
(a)
vp: [200V / div]
vp
iL iL: [5A / div]
vs vs: [200V / div]
(b)
vp: [200V / div]
vp
iL iL: [1A / div]
vs vs: [200V / div]
(c)
Fig. 5.18. Experimental waveforms under different output power when output voltage
is 200 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W.
Under V2 of 200 V, the waveforms vp, vs, and iL under 900 W, 400 W and 100 W are given
in Fig. 5.18, the working modes of which are mode 1, mode 1 and mode 5, respectively.
120
vp: [200V / div]
vp
iL: [10A / div]
iL
vs vs: [200V / div]

(a)
vp: [200V / div]
vp
iL: [10A / div]
iL
vs vs: [200V / div]

(b)
vp: [200V / div]
vp
iL iL: [2A / div]
vs: [200V / div]

vs
(c)
is 160 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W.
When V2 is 160 V, the waveforms vp, vs, and iL under 900 W, 400 W and 100 W are shown
121
vp: [200V / div]
vp
iL iL: [10A / div]
vs: [200V / div]

vs
(a)
vp: [200V / div]
vp
iL iL: [5A / div]
vs vs: [200V / div]
(b)
vp: [200V / div]
vp
iL iL: [2A / div]
vs vs: [200V / div]
(c)
is 230 V: (a) P = 900 W; (b) P = 400 W; (c) P = 100 W.
Given V2 of 230 V, the waveforms vp, vs, and iL under 900 W, 400 W and 100 W are given
5.5.3 Transient Response under Power and Voltage Step
The experiments below aim at validating the real-time operation of the proposed FIS-
based TPS modulation given the output power or voltage steps.
Firstly, when the load resistance is fixed at 40 Ω, the output voltage V2 steps from 200 V
(1000 W) to 160 V (640 W) and from 160 V (640 W) to 200 V (1000 W). Fig. 5.21 shows
the corresponding waveforms, where the top figures present the waveforms V1, V2 and Io,
and the bottom figures present the modulation waveforms vp, vs and iL.
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Fig. 5.21. Experimental waveforms given that V2 steps from 200 V to 160 V and V2
steps from 160 V to 200 V: V1, V2 and Io during voltage step (top); zoom-in view of vp, vs
and iL at Zone 1 and Zone 2 (bottom).
Secondly, when the load resistance is at 52.9 Ω, the output voltage V2 steps from 230 V
(1000 W) to 200 V (756 W) and from 200 V (756 W) to 230 V (1000 W). Fig. 5.22 plots
the waveforms.
123
Fig. 5.22. Experimental waveforms given that V2 steps from 230 V to 200 V and V2
steps from 200 V to 230 V: V1, V2 and Io during voltage step (top); zoom-in view of vp, vs
and iL at Zone 1 and Zone 2 (bottom).
Fig. 5.23. Experimental waveforms given that P steps from 1000 W to 500 W and
from 500 W to 1000 W under V2 of 200 V: V1, V2 and Io during power step (top); zoom-
in view of vp, vs and iL at Zone 1 and Zone 2 (bottom).
124
125
Additionally, Fig. 5.23, Fig. 5.24, and Fig. 5.25 present the transient responses of load
steps under the output voltage of 200 V, 160 V and 230 V, respectively.
From the waveforms shown in Fig. 5.21 and Fig. 5.22, when the operating conditions V2
and P vary, the proposed FIS-based TPS modulator can realize the real-time adjustments of
D1 and D2 to achieve minimal current stress. Besides, when the output power P varies, as
shown in Fig. 5.23 to Fig. 5.25, the output voltage V2 is capable of tracking the required
reference value, and D0, D1, D2 have been adjusted to their optimal values.
In a word, with the conducted experiments, the proposed FIS-based TPS modulation is
validated to work online under varying operating conditions.
5.5.4 Current Stress and Efficiency Performance of the Optimal TPS

Modulation via the Proposed AI-TPSM
Peak Current ipk (A) Efficiency η
7
SPSM 97%
LUT-TPSM
5 AI-TPSM
95%
3 SPSM
93%
LUT-TPSM
1 AI-TPSM
91%
200 400 600 800 P (W) 200 400 600 800 P (W)
(a) (b)
Fig. 5.26. Current stress ipk and efficiency η performance of SPSM, LUT-TPSM and
the optimal TPS modulation via AI-TPSM when output voltage V2 is 200 V: (a) current
stress ipk performance; (b) efficiency η performance.
To validate the satisfactory current stress and efficiency performance of the optimal TPS
modulation via AI-TPSM, the conventional SPS modulation (SPSM) and the lookup-table-
based TPS modulation (LUT-TPSM) are compared with. Fig. 5.26, Fig. 5.27, and Fig. 5.28
present the current stress ipk and efficiency η from 100 W to 1000 W given that V2 is 200 V,
160 V and 230 V, respectively. In the experiments, efficiency is evaluated by the ratio of
output power Po to input power Pin utilizing the Teledyne LeCroy HDO8058A oscilloscope.
In the comparisons between SPSM and AI-TPSM, the optimal TPS modulation via the
proposed AI-TPSM approach presents significantly lower ipk and higher η at low power
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level. Apart from that, at medium power level, AI-TPSM also performs better in both ipk
and η. At high power level, the conventional SPSM achieves almost the same performance
as AI-TPSM. This relatively small advantage of AI-TPSM at high power level is because
that the optimal D1 and D2 in these situations are close to 1, which renders the difference
between the control signals of AI-TPSM and SPSM to be trivial.
12
SPSM
98%
LUT-TPSM
9 AI-TPSM
96%
6 94% SPSM
LUT-TPSM
3 92% AI-TPSM
200 400 600 800 P (W) 200 400 600 800 P (W)
(a) (b)
98%
SPSM
8
LUT-TPSM
AI-TPSM 94%
6
90% SPSM
4 LUT-TPSM
AI-TPSM
2 86%
200 400 600 800 P (W) 200 400 600 800 P (W)
(a) (b)
In the comparisons between LUT-TPSM and AI-TPSM, the proposed AI-TPSM still
achieves lower ipk and higher η at low power levels. This superiority is benefited from the
continuous modulation feature of AI-TPSM. Even though the lookup table in LUT-TPSM
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stores the optimal modulation variables, its results are still suboptimal due to its discrete
modulation nature.
In this part, in the comparisons among SPSM, LUT-TPSM and AI-TPSM, the superior
current stress and efficiency performance of the proposed AI-TPSM approach is
experimentally validated.
Peak Current ipk (A)

7 Average Deviation Error: 2.96%
Largest Deviation Error: 5.21%
5
Theoretical
3 Experimental
1 P (W)
100 200 300 400 500 600 700 800 900 1000
(a)
Average Deviation Error: 3.51%
10 Largest Deviation Error: 5.16%
8 Theoretical
6 Experimental
4
2
P (W)
100 200 300 400 500 600 700 800 900 1000
(b)
Average Deviation Error: 3.37%
8
Largest Deviation Error: 4.74%
6 Theoretical
Experimental
4
2
P (W)
100 200 300 400 500 600 700 800 900 1000
(c)
Fig. 5.29. Comparisons between the experimental results and the theoretically optimal
results: (a) V2 = 200 V; (b) V2 = 160 V; (c) V2 = 230 V.
5.5.5 Comparisons between the Experimental and Theoretical Results of

the Optimal Modulation
To validate the high accuracy and optimality of the proposed AI-TPSM approach, the
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experimental results and the theoretically optimal results are compared.
As shown in Fig. 5.29, the average deviations between the experimental and theoretical
results are 2.96%, 3.51% and 3.37% when the output voltage is 200 V, 160 V and 230 V,
respectively. In the worst case, the largest deviation error is only 5.21%. Hence, the
neglectable deviations from the experimental results to the theoretically optimal results
validate the high accuracy of the proposed AI-TPSM, and they also prove that the
experimental peak current results are indeed optimal.
In a word, with all the hardware experimental results discussed above, the design case is
comprehensively verified, and the proposed AI-TPSM approach for optimal TPS
modulation with minimized current stress is validated.
5.6 Conclusion
This chapter proposes an artificial-intelligence-based triple phase shift modulation

optimization strategy (AI-TPSM) for the dual active bridge converter, which can realize
minimized current stress in an automatic fashion. Generally, AI-TPSM can be divided into
three stages with one AI tool in every stage: analysis process with neural network,
optimization process with evolutionary algorithm and realization process with fuzzy
inference system. Firstly, in analysis process, neural network is trained with simulations to
learn the relationships between current stress and variables (operating conditions and
modulation variables), which is to replace traditional complicated and inaccurate analytical
process. Secondly, particle swarm optimization, which is an evolutionary algorithm, is
adopted find the optimal modulation results which can minimize current stress. Lastly,
fuzzy inference system is utilized to store the optimal modulation results under different
operating conditions, which can provide continuous modulation. The proposed AI-TPSM
enjoys high degree of automation which can relieve engineers’ working burden and
improve accuracy. Finally, the effectiveness of the AI-TPSM has been verified with a 1kW
prototype of the DAB converter.
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Chapter 6 XGBoost-Based Hybrid Extended Phase Shift
Modulation Design for the Dual Active Bridge Converter
with Full ZVS Range and Optimal Efficiency
In Chapter 5, considering current stress as its modulation objective, an AI-based TPS

modulation strategy for DAB converters is proposed, where the feedforward NN is chosen
as the surrogate model for current stress, and conventional PSO algorithm is used for
optimization. It has to be admitted that the AI-based TPS approach proposed in Chapter 5
indeed realizes a high-level automation, but this approach can still be improved in the
following aspects. To begin with, TPS modulation has three degrees of control freedom,
which is complicated in implementation. Second, current stress is the only modulation
objective considered, while other objectives such as efficiency and zero voltage switching
(ZVS) are highly valuable. Moreover, NN and the conventional PSO algorithm may not be
the perfect algorithms for this task.
Consequently, aiming at the challenges above, Chapter 6 proposes a hybrid extended
phase shift (HEPS) modulation to optimize efficiency while keeping full ZVS over entire
operating ranges. The approach proposed in this chapter has three distinctive features. First,
two two-degree-of-freedom EPS strategies are considered, which maintains the most
performance while is still easy to implement. Besides, efficiency and ZVS are the objectives,
ensuring the holistic modulation performance. In addition, an advanced machine learning
algorithm is chosen instead of NN, and a cutting-edge PSO algorithm is proposed and
utilized, which has been theoretically and statistically validated.
In this chapter, two significant performance indicators, ZVS range and efficiency, are
considered for DAB converters. To obtain the desired ZVS and efficiency performance,
modulation should be carefully designed. Hybrid modulation considers several single
modulation strategies to achieve good comprehensive performance. Conventionally, to
design a hybrid modulation, harmonic approach or piecewise approach is used, but they
suffer from time-consuming model building process and inaccuracy. Therefore, an
artificial-intelligence-based hybrid extended phase shift (HEPS) modulation is proposed.
Generally, the HEPS modulation is developed in an automated fashion, which alleviates
cumbersome model building process while keeping high model accuracy. In HEPS
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modulation, two EPS strategies are considered to realize optimal efficiency with full ZVS
operation over entire operating ranges. Specifically, to build data-driven models of ZVS
and efficiency performance, extreme gradient boosting (XGBoost), which is a state-of-the-
art ensemble learning algorithm, is adopted. Afterwards, the cutting-edge particle swarm
optimization with state-based adaptive velocity limit (PSO-SAVL) is utilized to select the
best EPS strategy and optimize modulation parameters. With 1 kW hardware experiments,
the feasibility of HEPS has been verified, achieving optimal efficiency with maximum of
97.1% and full-range ZVS operation.
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6.1 Introduction
The dual active bridge (DAB) isolated dc-dc converter, since its first appearance in 1990s,
has incrementally gained research attentions and popularity in industry as being benefited
from its high power density, the capability of bidirectional power transfer and its wide zero
voltage switching (ZVS) range [184]. DAB converter consists of two full bridges and one
high-frequency transformer in between, which enjoys more compact size and lighter weight
than bulky line-frequency transformer. This topology has omnipresent applications
nowadays such as, electric vehicle [185], wireless charging [186], solar panel [187], solid
state transformer [11], etc.
To actively control power flow and improve operating performance, modulations of DAB
converters have been widely studied, among which the phase shift modulation is commonly
adopted for its easy implementation. Single phase shift (SPS) modulation has one degree of
control freedom, which is the outer phase shift between two bridges [5]. Although SPS
modulation is a simple strategy, it suffers from narrow ZVS range and low efficiency in
light load conditions. To achieve wider ZVS range and better efficiency, extended phase
shift (EPS) modulation and dual phase shift (DPS) modulation consider one more degree of
control freedom, which is the inner phase shift of full bridges. DPS modulation applies the
same inner phase shift to both bridges [189]. EPS modulation applies the inner phase shift
to only one bridge, so there are two EPS strategies depending on which bridge applies the
inner phase shift [83]. However, EPS or DPS alone still cannot achieve full ZVS range and
optimal efficiency [73]. With the two inner phase shifts and the outer phase shift to be
independently tunable, triple phase shift (TPS) modulation has three degrees of control
freedom [67]. TPS is the generalized and improved version of SPS, EPS and DPS, but it is
complicated to implement. Besides single modulation strategies, some research works focus
on hybrid modulation (HM) to obtain good holistic performance over wide operating ranges.
For instance, Amit et al. analyzed different modulation modes of TPS to realize optimal
efficiency over wide operating conditions [190]. Shen et al. combined EPS and several
modulation modes of TPS for full soft switching range with minimized conduction loss [82].
Deng et al. adjusted phase shift and pulse duty cycle simultaneously to achieve good
efficiency over wide voltage range and extend ZVS range [84].
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With regards to the optimization objective of modulations for DAB converters, ZVS range
is a desirable target to be optimized. Wide ZVS range is of great significance. First,
realization of ZVS can reduce the switching losses, which are dominant when the switching
frequency is high. Second, full ZVS operation can alleviate many undesired phenomena like
voltage polarity reversal, voltage sag and phase drift [191]. Moreover, soft switching
operation can reduce electromagnetic interference, protecting the control circuit [192].
Consequently, in this chapter, an HM consisting of two EPS strategies is optimized to realize
full ZVS range under all operating conditions. Besides, power transfer efficiency is also
considered as an optimization target for a good comprehensive performance.
Nonetheless, the conventional modeling approaches of ZVS and efficiency are truly
cumbersome, and the deduced model may suffer from inaccuracy. For example,
traditionally, ZVS model is built with the piecewise method [60], [72], [73] or the harmonic
method [193], [194]. The piecewise method requires segment-by-segment analysis of
current and voltage for all operating modes in each single modulation. The harmonic model
may fail to reach high accuracy if limited harmonic components are considered for the sake
of simplicity. In HM, the time-consuming and inaccurate problems will even aggravate as
more modulation strategies have to be analyzed. Therefore, how to conquer the challenges
of burdensome model building process of ZVS and efficiency and low model accuracy is
a major concern of this chapter.
As artificial intelligence (AI) thrives, more researchers in power electronics start to
leverage the advanced AI tools to relieve the burden of engineers and improve design
accuracy. For instance, Dragičević et al. modeled the reliability of converters using two
neural networks (NN) to design converters with predetermined lifetime [195]. Li et al.
adopted batch-normalization NN to compute power losses for optimizing synchronous buck
converter in EV [196]. NN was also utilized to model current stress [67] and efficiency [8]
of DAB converter under TPS modulation. Reinforcement learning was applied to optimize
reactive power [197].
Nevertheless, these AI techniques can be problematic. If the learnable parameters of AI
models are insufficient, such as support vector machine, decision tree and shallow NN, low
accuracy problem may occur [196]. Besides, if deep learning model is used to provide
stronger learning capability, it may potentially suffer from overfitting and heavy
133
computation problems. An AI technique that achieves a balance between high accuracy and
fast computational speed is required. Luckily, an AI technique in ensemble learning,
extreme gradient boosting (XGBoost), serves as a good solution. XGBoost utilizes boosting
framework to learn a bag of weak models in sequence: the next model adapts to the error of
previous models [198]. With the weak models ensembled altogether, XGBoost can give
highly accurate predictions. Meanwhile, cache optimization and parallelization features of
XGBoost make it a fast-speed algorithm [198]. In many international AI competitions like
Kaggle, XGBoost earns its reputation for its superb performance.
In Chapter 6, utilizing the state-of-the-art AI techniques, a hybrid EPS (HEPS) modulation
with full ZVS range and optimal efficiency for the entire voltage and power ranges is
proposed. This hybrid modulation is composed of two EPS strategies from the simultaneous
considerations of good operating performance and ease of implementation. Generally,
HEPS consists of two stages. In Stage I, data-driven models of ZVS and efficiency are built.
With the data generated by simulations, XGBoost algorithm is adopted to automatically
build surrogate models for ZVS and efficiency. In Stage II, the best modulation strategy is
selected, and modulation parameters are optimized to achieve full ZVS range with optimal
efficiency. Stage II utilizes the cutting-edge particle swarm optimization with state-based
adaptive velocity limit (PSO-SAVL) to optimize efficiency with the constraint of all-switch
full ZVS range. The proposed HEPS contributes two main points to the existing research
works: first, optimal efficiency under full ZVS range is realized in the proposed HEPS
modulation; second, it significantly reduces the amount of manpower involved and achieves
high modeling accuracy.
The structure of this chapter is discussed as follows. In Section 6.2, the operating
principles of the two considered EPS strategies are introduced. In Section 6.3, the state-of-
the-art PSO-SAVL algorithm is elaborated, the performance of which is theoretically and
empirically validated. Section 6.4 illustrates the potential problems in conventional
modeling approaches of ZVS and efficiency. Stage I and Stage II of the proposed HEPS are
illustrated in detail in Section 6.5 and 6.6, respectively. An easy-to-follow step-by-step case
study is given in Section 6.7. In Section 6.8, hardware experimental results are shown and
analyzed. Section 6.9 summarizes the conclusion of this chapter.
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6.2 Preliminary: Basics about EPS Modulations
The non-resonant DAB converter with single leakage inductance Lr in between is shown
in Fig. 6.1. It consists of two bridges FB1 and FB2, and a galvanically isolated transformer.
The turn ratio of transformer is n:1. V1, I1 and V2, I2 are the dc-side voltage and current of
primary bridge and secondary bridge, respectively. vp and vs are the ac-side voltages of
primary and secondary bridges. iL is the power transfer current through Lr.
I1 FB1 Transformer with FB2 I2

+ leakage inductance Lr
S1 S3 Q1 Q3 +
Lr n:1
V1 + iL + V2
vp vs
- - Cf
S2 S4 Q2 Q4 -
-
Fig. 6.1. Topology of a non-resonant DAB converter with leakage inductance Lr.
6.2.1 Fundamentals of EPS1
Generally, there are two adjustable control parameters in EPS modulations: outer phase
shift Do which controls power transfer, and inner phase shift Din which adjusts the shape of
inductor current iL to improve operating performance. With adjustable Din, a zero-level
voltage plateau is introduced in either primary bridge (FB1) or secondary bridge (FB2).
Attributable to the zero-level voltage plateaus, backflow power and circulating current can
be largely reduced if Din is properly adjusted [84].
EPS1 Ts/2 Ts
Din in S1 S2
FB1 S4 S3 S4
Q2 Q1 Q2
Q3 Q4 Q3
V1
vp(t) DinTs/2
-V1
DoTs/2 V2
vs(t)
-V2
Fig. 6.2. Fundamentals of EPS1.
135
As the fundamentals shown in Fig. 6.2, since the inner phase shift Din is applied to FB1,
this EPS strategy is named as EPS1. With EPS1, the driving signal for S3 has DinTs/2 time
delay than that for S1, while the driving signals for Q1 and Q3 are complementary with 50%
duty ratio. The value of Din lies within [0, 1]. When Din = 1, no zero-level voltage is
introduced, and thus vp will still be a two-level wave. The outer phase shift Do regulates the
time delay (DoTs/2) between Q1 and S1. Do has the range of [-1, 1], where the maximum
forward power is achieved at Do = 0.5, and no power is transferred when Do = 0 [72]. In
EPS1, vp is a three-level ac voltage wave, while vs is still a two-level ac square wave.
6.2.2 Fundamentals of EPS2
Ts/2 Ts
EPS2 S1 S2
S4 S3
Din in Q2 Q1 Q2
FB2
Q4 Q3
V1
vp(t) DoTs/2
-V1
V2
vs(t)
DinTs/2 -V2
Fig. 6.3. Fundamentals of EPS2.
The difference between EPS2 and EPS1 is that EPS2 adjusts the inner phase shift Din of
FB2 rather than that of FB1, as shown in Fig. 6.3. With EPS2, the driving signals for S1
and S3 are complementary square waves with 50% duty ratio. Whereas, because Din is
applied to FB2, there exists a time delay between the driving signals of Q1 and Q3. The
definition of Do is the same as EPS1. The adjustable ranges of Do and Din in EPS2 are [-1,
1] and [0, 1], respectively. Conversely, with EPS2, vp is a two-level waveform, while vs is
a three-level waveform.
In comparison to SPS, benefiting from the extra zero-level voltage plateau, EPS strategy
has higher efficiency, lower current stress, and broader ZVS range [60]. With the two EPS
strategies considered at the same time, Din can be applied to both full bridges, making it
possible for all-switch ZVS over full operating ranges. In this chapter, through properly
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shifting between EPS1 and EPS2 and adjusting Din, optimal efficiency with full ZVS
operation can be realized.
6.3 Preliminary: Basics about the Proposed PSO-SAVL
Velocity limit (VL) has been widely adopted in many variants of particle swarm
optimization (PSO) to prevent particles from searching outside the solution space.
Originally, VL is fixed during the iterations of PSO. Recently, since the performance of
PSO can be improved when VL is properly adjusted during the iterations, several adaptive
VL strategies have been introduced. However, the existing adaptive VL strategies simply
adjust their VL based on the current number of iterations, the strategies of which can be
incompatible with the current searching state of particles, leading to unsatisfactory
optimization results. It has been found that a high value of VL is beneficial for global
searching, and a low value of VL is helpful for local searching. Thus, it will be beneficial
for the performance of PSO if VL is adaptively tuned based on the particles’ current
searching state. In this section, in order to adaptively tune VL considering the current
searching state of particles, a novel PSO variant with state-based adaptive velocity limit
strategy (PSO-SAVL) is proposed.
6.3.1 Functions of Velocity Limit
The functions of VL can be summarized as: to prevent PSO from searching outside the
solution space, to accelerate the convergence speed, and to adjust the tradeoff between local
searching and global searching. An approximated theoretical analysis is given as follows.
As analyzed by Maurice and James [199], the velocity in the reduced dynamic equation
of PSO without VL is shown in (6.1):
vt ϕ ( p − xt ) ,
vt +1 =+ (6.1)
where the problem space is one-dimensional, the population includes one particle, p and
φ are constant, and vt and xt are the velocity and the position of the particles in the tth iteration.
Since VL restricts vt whenever vt exceeds its limit, the effects of VL can be represented
by an equivalent discount factor a, the range of which lies within [0, 1]. Thus, the velocity
in the reduced dynamic equation of PSO with VL can be described in (6.2), where the
discount factor a is regarded as constant for analysis convenience.
137
vt +1 = a ( vt + ϕ ( p − xt ) ) , a ∈ [0,1] . (6.2)
Due to the accumulated discount effects of a in each iteration, the magnitude of vt+1 of the
variants with VL is much smaller than the magnitude of vt+1 of the variants without VL, and
thus the change of position in the variants with VL will be smaller, leading to faster
convergence speed.
Furthermore, when compared with a high value of VL, a lower value of VL is equivalent
to a smaller a, resulting in the smaller magnitude of vt+1 and the smaller change of position,
which encourages PSO to search for the local space thoroughly. In a word, a lower value of
VL can benefit local searching. Similarly, when compared with a low value of VL, a higher
value of VL can be represented by a larger a, because of which the magnitude of vt+1 is larger,
and the change of position is larger, leading to the wider exploration of solution space. The
wider exploration of solution space encourages PSO to globally search for the best solution.
Hence, a high VL is beneficial for global searching.
In a word, if VL is adaptively tuned based on the current state of particles to match global
searching and local searching during the iterations, the performance of PSO can be improved.
6.3.2 Challenge in the Existing Adaptive Velocity Limit Strategies
The major challenge is the incompatibility between the current state of particles and the
existing adaptive VL strategies, since the current state of particles is non-deterministic. The
incompatibility causes the PSO variants with the existing adaptive VL strategies to be
worse than the variants with an adaptive VL strategy that is based on the current state of
particles. To elaborate the incompatibility, PSO with linearly decreasing inertia weight
(PSO-LDIW) [200] is implemented under the Rosenbrock’s function to evaluate
evolutionary factor f with (6.3) to (6.4), where the position of the ith particle is represented
by a vector Xi = [Xi1, Xi2, …, XiD], D stands for the dimension of the solution space, N is
population size, di is the mean distance of the ith particle, dg is the di of the globally best
particle, and dmin and dmax are the minimum and maximum values among all di. As shown
in Fig. 6.4, the incompatibility problem between the existing adaptive VL strategies and
the current state of particles can always occur, leading to unsatisfactory performance of
PSO.
138
1 N D
∑( X − X dj )
2
=di ∑
N − 1 j =≠
1, j i 1
d=
i
d
(6.3)
d g − dmin
f = (6.4)
dmax − dmin
Fig. 6.4. Problems of the existing adaptive VL strategies: incompatibility between

these strategies and the current searching state of particles.
6.3.3 Process of the Proposed PSO-SAVL
The flowchart of PSO-SAVL is shown in Fig. 6.5, in which the velocity of the dth
dimension of the ith particle Vid is updated with (6.5), where r1,id and r2,id are two uniformly
distributed random numbers within [0, 1] of the dth dimension of the ith particle. The
position and velocity of the ith particle are represented by vectors Xi = [Xi1, Xi2, …, XiD] and
Vi = [Vi1, Vi2, …, ViD]. D is the dimension of the solution space. The limits of position and
velocity are represented by vectors Xmax = [Xmax1, Xmax2, …, XmaxD], Xmin = [Xmin1, Xmin2, …,
XminD] and VL = [VL1, VL2, …, VLD]. vlmax and vlmin are the newly introduced hyper-
parameters, representing the maximum and minimum values of VL respectively. pbesti and
gbest are the historical best position of the ith particle and the global best position,
139
respectively. ω is the inertia weight. c1 and c2 are the acceleration coefficients. max_iters
is the maximum number of iterations. N is the population size.
Vid = ω ⋅Vid + c1 ⋅ r1,id ⋅ ( pbestid − X id ) + c2 ⋅ r2,id ⋅ ( gbest d − X id ) (6.5)
Start
vlmax=0.7, vlmin=0.4, ωs = 0.9,
ωe = 0.4, c1 = c2 = 2.05
Initialize velocity limit VL = vlmax•Xmax,
position Xi, velocity Vi
Set pbesti = Xi; Calculate gbest
k=1
Calculate f based on ESE with (6.3) to (6.4)
k
ω =ωs + (ωe − ωs ) ⋅
max _ iters
Adaptively tune VL based on f to match current

state of particles:
1 1
VL
= ⋅ X max ∈ [ vlmin , vlmax ] Sigmoidal = α −1
1+ αe −β f vlmin
 1  
i=1 β= − ln   − 1 α 
Update each dimension of the velocity   vlmax  
th
Vi of the i particle with (6.5)
F Execute Velocity Limit
-VL <= Vi <= VL ?
Handling
T
Xi = Xi + Vi
F Execute Position Limit
Xmin <= Xi <= Xmax ?
Handling
T
th
Evaluate the position Xi of the i particle;
Update pbesti , gbest
i=i+1 T i<N?
F
k=k+1 T k <= max_iters ?
F
End
Fig. 6.5. Flowchart of the proposed PSO-SAVL.
With the flowchart in Fig. 6.5, the current searching state of particles can be adjusted to
match evolutionary factor f, as the illustrative graph shown in Fig. 6.6.
140
Fig. 6.6. The relations between the value of VL and the evolutionary factor f, blue star
is the position of globally best particle, and grey circle is the position of other particles.
Table 6.1 Optimization Solutions of PSO Variants on Benchmark Functions with 50-D.
Solutions f1 f2 f3 f4 f5 f6 f7
mean 1.470 2.69E+05 258.3 66.3 8502.7 55.6 174.6
PSO-LDIW
std 2.484 4.48E+05 34.4 81.9 1087.5 19.8 46.9
mean 4.97E-46 1082.3 117.9 0.3523 9015.7 0.9950 45.6
UPSO
std 2.72E-45 2564.6 22.2 0.6610 1163.0 0.4366 19.0
HPSO- mean 1.52E-13 1723.4 112.0 0.0256 4641.8 2.13 111.8
TVAC std 3.05E-13 3551.7 35.4 0.0311 880.4 0.9889 23.9
mean 1.19E-08 874.6 192.6 21.0 4926.9 21.1 130.8
FDR-PSO
std 3.33E-08 1828.5 44.5 38.7 886.2 17.1 25.9
mean 1.74E-53 147.2 102.6 0.0313 4416.8 3.19 83.2
QPSO
std 6.43E-53 174.4 33.0 0.0383 710.6 4.54 19.7
mean 0.285 829.7 1.6 0.2000 245.9 1.49 80.0
APSO
std 0.766 1885.9 1.2 0.2400 164.8 0.7811 24.2
mean 4.10E-32 97.5 139.7 1.57E-09 6257.3 2.53 126.9
CLPSO
std 4.87E-32 55.8 15.6 6.81E-09 436.4 0.765 16.9
PSO-CL- mean 3.77E-39 91.8 75.4 1.15E-05 6827.0 1.31 100.2
pbest std 8.39E-39 42.4 11.1 6.31E-05 465.9 0.204 16.4
mean 2.85E-43 155.0 139.2 0.0316 4302.9 1.87 88.3
RODD-PSO
std 1.56E-42 181.2 47.9 0.0353 862.5 0.6499 20.2
mean 1.08E-39 76.6 55.8 0.0107 4172.7 0.9902 30.8
PSO-SAVL
std 1.54E-39 39.3 13.5 0.0185 901.1 0.0970 8.2
Rankings of PSO-
4 1 2 3 2 1 1
SAVL
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6.3.4 Experimental Results of the Proposed PSO-SAVL
To validate the good performance of the proposed PSO-SAVL, other popular PSO
variants are compared with it on the benchmark functions with 50 dimensions.
Table 6.2 Computation Speed of PSO Variants on Benchmark Functions with 50-D.
Expected PSO- HPSO- FDR- PSO- RODD PSO-
UPSO QPSO APSO CLPSO
Time LDIW TVAC PSO CL-pbest -PSO SAVL
f1 3.10 4.48 3.75 10.52 4.06 5.68 4.94 4.65 23.47 5.09
f2 3.37 4.43 4.04 10.73 4.58 6.06 4.95 4.97 23.87 5.41
f3 3.88 4.79 4.22 10.68 4.88 6.76 5.55 5.46 25.05 5.63
f4 4.23 4.69 3.98 10.44 4.41 6.44 5.28 5.28 25.51 5.43
f5 4.08 4.48 3.85 10.78 4.44 6.29 5.21 5.24 25.46 5.60
f6 6.65 6.91 6.11 16.66 6.94 10.06 8.14 8.14 36.61 5.26
f7 6.17 6.67 5.92 16.12 6.80 9.30 7.44 7.88 37.66 5.97
Mean
4.50 5.21 4.55 12.28 5.16 7.23 5.93 5.94 28.23 5.48
expected time
(a)
(b)
142
(c)
(d)
(e)
143
(f)
(g)
Fig. 6.7. Convergence performance of all the PSO variants on each of the benchmark
functions (a) f1; (b) f2; (c) f3; (d) f4; (e) f5; (f) f6; (g) f7.
The results of all the PSO variants in terms of the mean (expected solutions) and the std
(standard deviations) are shown in Table 6.1. The last row of Table 6.1 shows the rankings
of the proposed PSO-SAVL among all the PSO variants by the performance of expected
solutions. Fig. 6.7 graphically presents the convergence characteristics of all the PSO
variants on all the benchmark functions. In short, in terms of the expected solutions, the
proposed PSO-SAVL performs the best on complex rotated multimodal functions, and it
reaches satisfactory expected optimization solutions on unrotated multimodal and
unimodal functions.
In PSO-SAVL, although the state-based adaptive VL strategy and the limit handling
strategies require extra operations, Table 6.2 shows that the computation speed of PSO-
SAVL does not slow down and is still satisfactory. Specifically, when compared with FDR-
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PSO, APSO, CLPSO, PSO-CL-pbest and RODD-PSO, PSO-SAVL has faster computation
speed. When compared with PSO-LDIW, UPSO, HPSO-TVAC and QPSO, the proposed
PSO-SAVL shows the comparable expected computation time.
Other statistical tests regarding the experimental performance such as t-Tests and success-
ratio have been done to prove the superiority of the proposed PSO-SAVL. The effectiveness
of the proposed strategies is also verified. Except for that, how to select the hyper-
parameters of the PSO-SAVL is shed light on. All the details are included in [201].
6.4 Conventional Modeling Approaches of ZVS and Efficiency
This section discusses the two main modeling approaches of ZVS and efficiency for DAB
converters under phase shift modulations in the existing literatures: the piecewise approach
and the harmonic approach. Section 6.4.1 and Section 6.4.2 illustrate the piecewise approach
and the harmonic approach for modeling ZVS, respectively. Section 6.4.3 discusses the
piecewise and harmonic approaches for modeling efficiency.
6.4.1 Piecewise Approach for Modeling ZVS
iL Lr
V1 nV2
vp(t) EPS1 nvs(t)
-V1 -nV2
(a)
iL Lr
V1 nV2
vp(t) EPS2 nvs(t)
-V1 -nV2
(b)
Fig. 6.8. Equivalent circuits of DAB converter under: (a) EPS1; (b) EPS2.
The equivalent circuits of DAB converter operating under EPS1 and EPS2 are shown in
Fig. 6.8 (a) and (b), respectively. Both piecewise and harmonic approaches are based on the
equivalent circuits in Fig. 6.8.
145
iL(t2) vp iL(t6)
iL(t4) vs
iL
iL(t3)
iL(t1)
iL(t5)
t1 t2 t3 t4 t5 t6 t7
Segment [t1, t2] [t2, t3] [t3, t4] [t4, t5] [t5, t6] [t6, t7]
vp 0 0 V1 0 0 -V1
vs -V2 V2 V2 V2 -V2 -V2
ZVS Constraint iL(t1)<0 iL(t2)>0 iL(t3)<0 iL(t4)>0 iL(t5)<0 iL(t6)>0
ZVS Switch S4 Q 1, Q 4 S1 S3 Q 2, Q 3 S2
Fig. 6.9. Example of piecewise approach for modeling ZVS.
The piecewise approach for analyzing ZVS under EPS1 is given as an example in Fig.
6.9. Piecewise approach analyzes the inductor current iL segment-by-segment through
applying the volt-second balance principle [202]. The time-variant expressions iL(t) of all
operating modes of EPS1 and EPS2 should be deduced. After that, to achieve all-switch
ZVS operation, the values of iL at the time of commutation have to follow the six constraints
in Fig. 6.9. These constraints ensure that the drain-source voltage of switch is clamped to
zero by antiparallel diode when the switch commutates [193]. Furthermore, these steps have
to be repeated multiple times to achieve all-switch ZVS over entire operating ranges.
Considering the high non-linearity of iL and the requirements to meet all ZVS constraints
over full operating ranges, it would be extremely complex, error-prone, and time-consuming
to build the ZVS model with piecewise approach.
6.4.2 Harmonic Approach for Modeling ZVS
Fig. 6.10 gives an example of applying harmonic approach to model ZVS under EPS1.
First, ac-side voltage waves vp and vs will be converted into harmonics in Fourier series as
shown in (6.6) and (6.7) [193], [203], in which φo is the outer phase shift angle, and φi1 and
φi2 are the inner phase shift angles for FB1 and FB2, respectively. Harmonic components of
iL are then deduced by dividing vp-vs by the impedance of Lr, and thus the time-variant
formula of iL is also expressed in the form of Fourier series. To realize all-switch ZVS
operation, the constraints on iL as listed in Fig. 6.10 should be satisfied.
146
4V1  ϕ 
v p (t ) = ∑ kπ  2  (
cos  k i 1  sin k ω0t ) (6.6)
=k 1,3,...,∞  
 ϕ 
=vs (t ) ∑
4V2
kπ  2  ((
cos  k i 2  sin k ω0t − ϕo )) (6.7)
=k 1,3,...,∞  
Fig. 6.10. Example of harmonic approach for modeling ZVS.
The harmonic approach for modeling ZVS suffers from the compromise between high
model accuracy and fast computation. If all harmonic components are considered, it suffers
from slow computation. And if only fundamental component is used, accuracy is largely
sacrificed. If limited components are taken into account, the modeling of iL through
harmonic analysis may be easier than piecewise approach, but the later steps to satisfy all
ZVS constraints over full operating ranges remain tedious.
6.4.3 Piecewise and Harmonic Approaches for Modeling Efficiency
To build models of efficiency for DAB converter under EPS modulations, the expressions
of inductor current iL(t) should be obtained first with either piecewise approach in Section
6.4.1 or harmonic approach in Section 6.4.2. Based on iL(t), IRMS is then computed with the
square root of the integration of iL(t)2 to analyze conduction and copper losses. The core loss
is analyzed through magnetic modeling with iL(t). Switching loss is obtained by analyzing
drain-source voltage vds(t) and drain-source current ids(t) during commutation.
147
Fig. 6.11. Modeling efficiency.
In a nutshell, to build models of ZVS and efficiency for DAB converter under EPS
modulations, there are two main problems: cumbersome and time-consuming analysis
process, and inaccuracy due to mathematical approximations. Moreover, high non-linearity
of ZVS and efficiency models makes it challenging to optimize efficiency with the
constraints of all-switch ZVS over entire operating ranges by hand. To tackle these
challenges, an AI-based HEPS modulation is proposed in this chapter.
6.5 Stage I of The Proposed HEPS Modulation: Build Data-Driven

Models of ZVS and Efficiency
In this section, Stage I of the proposed HEPS modulation which builds the data-driven
models of ZVS and efficiency for DAB converter under EPS1 and EPS2 is discussed.
6.5.1 Stage I: Build Data-Driven Models of ZVS and Efficiency with

XGBoost Algorithm
As a preparation of Stage I, the operating specifications should be predetermined,

including switching frequency fs, dead time, range of output power [Pmin, Pmax], input voltage
V1 and range of output voltage [V2,min, V2,max]. The value of leakage inductance Lr is designed
with (6.8) considering maximum power transfer [67].
nVV
Lr ≤ 1 2 min
(6.8)
8 fs Pmax
The detailed flowchart of Stage I is shown in Fig. 6.12, consisting of three main steps.
First, combinations of operating and modulation parameters (P, V2, S, Din) should be
selected for running simulations. S is the modulation selector: S = 0 and S = 1 represent
148
EPS1 and EPS2, respectively. The numbers of samples of P, V2 and Din are N1, N2 and M1,
which are uniformly selected from the ranges of [Pmin, Pmax], [V2,min, V2,max] and [0, 1],
respectively. Consequently, the total number of combinations for simulation will be 2 × N1
× N2 × M1. The uniform sampling ensures a nicely covered data distribution for the benefit
of XGBoost learning.
Choose Combinations of (P, V2, S, Din)

Step 1 S=0: EPS1, Din applies to primary bridge
S=1: EPS2, Din applies to secondary bridge
2×N1×N2×M1
Combinations of
( P , V2 , S , Din )
Run Simulations: collect total
Step 2 power loss and the number of
switches meeting ZVS constraints
Build Data-Driven Models

Step 3 With simulation data from Step 2, XGBoost
models of ZVS and efficiency are built
P sum P sum
V2 Ploss V2 nZVS
S S
Din Din (Number of switches
Efficiency Indicator ZVS Indicator satisfy ZVS)
Fig. 6.12. Flowchart of Stage I of the proposed AI-based HEPS modulation.
Step 2 conducts the simulations for the selected 2 × N1 × N2 × M1 combinations of

operating and modulation parameters. In this chapter, PLECS simulation is used for its fast
speed and high accuracy. In the simulations, total power loss Ploss and the number of
switches that satisfy ZVS constraints nZVS are collected as the training targets for Step 3.
In Step 3, trained on the data from Step 2, two data-driven models of ZVS and efficiency
are automatically built with XGBoost algorithm. The inputs of both XGBoost models are P,
V2, S and Din. The outputs of the two models are total power loss Ploss and the number of
switches satisfying ZVS constraints nZVS, respectively. The trained XGBoost models serve
as the data-driven surrogate models for efficiency and ZVS. With the XGBoost models, the
efficiency and ZVS performance under any unseen operating and modulation parameters
can be evaluated.
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6.5.2 XGBoost Adopted in Stage I of the Proposed HEPS
In Stage I of the proposed HEPS modulation, XGBoost is adopted for building the data-
driven models for ZVS and efficiency. XGBoost is a gradient-boosting-based ensemble
learning approach, consisting of a bag of weak machine learning models such as decision
trees [198].
o1*=o* XGBoost
Training Efficiency
Decision Tree 1 Performance
Output of
… y1 XGBoost-1
k
∑y
Boosting
Ploss = （1）
…
i
i =1
o2*=o* - y1
Decision Tree 2
Inputs
…
P, V2, y2
S, Din
…
ZVS
o3*=o*-y2-y1 Performance
Boosting
…
k −1
ok=
*
o* − ∑y i
Output of
XGBoost-2
Decision Tree k i =1
k
nZVS = ∑y （2）
…
i
i =1
yk
…
Fig. 6.13. Boosting training process of XGBoost.
The boosting training process of XGBoost models with k decision trees is described with
Fig. 6.13 for illustrative purposes. During the training of XGBoost, the k decision trees are
sequentially trained to fit the residual oi*, which is the difference between the objective value
o* (such as Ploss, nZVS) and the cumulative sum of the outputs of all previous trees.
For instance, the prediction of Decision Tree 1 y1 will try to follow o1*, and the residual
o1*-y1 will be the training objective o2* for Decision Tree 2 to learn. Similarly, given o2*,
Decision Tree 2 will output y2 to get closer to o2*, and the corresponding residual o3* (which
is o2*-y2) will be regarded as the training target for Decision Tree 3. This sequential training
process of residuals is called bossting learning, and it is applied to all following trees. For
150
Decision Tree k, its learnable parameters θk are adjusted to minimize the mean square error
between its prediction yk,θk and the kth residual ok*, as expressed in (6.9).
2
( ) ( )  * k −1 
2
min objk = min ok − yk ,θ *
= min  o − ∑ yi − yk ,θ  (6.9)
θk θk θk
k
 i
k

k
(
Ploss P,V2 , S , Din =) ∑ y (P,V , S, D )
i =1
i
(1)
2 in
(6.10)
( )
nZVS P,V2 , S , Din = ∑ yi (2) P,V2 , S , Din
i =1
( ) (6.11)
The output of XGBoost models is obtained by the summation of the outputs of all decision
trees. In this chapter, the output of model XGBoost-1 is the total power loss Ploss as shown
in (6.10), and XGBoost-2 predicts the number of switches that meet ZVS constraints nZVS
with (6.11). In (6.10) and (6.11), yi(1) and yi(2) are the outputs of the ith decision tree of
XGBoost-1 model and XGBoost-2 model, respectively.
With the simulation data and the application of XGBoost in Stage I, data-driven models
of ZVS and efficiency can be automatically built, and the challenges of time-consuming
process and inaccuracy in conventional modeling approaches as discussed in Section 6.4
have been greatly conquered.
6.6 Stage II of The Proposed HEPS Modulation: Optimize Efficiency

with Full ZVS Operation
Stage II of the proposed AI-based HEPS modulation searches for the best EPS strategy
and modulation parameters to realize optimal efficiency with full ZVS operation. Section
6.6.1 introduces the flowchart of Stage II, and Section 6.6.2 discusses the applied PSO-
SAVL algorithm in Stage II.
6.6.1 Stage II: Optimize Efficiency with Full ZVS Operation through
PSO-SAVL Algorithm
This chapter aims to optimize efficiency while maintaining all-switch ZVS operation over
entire voltage and power ranges, the mathematical form of which is expressed in (6.12) as
the following:
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For the chosen operating parameters S, P and V2, the target is to minimize total power
loss:
Din
( )
Ploss * = min Ploss (P,V2 , S , Din ) , (6.12a)
Subject to:
nZVS (P,V2, S , Din ) = 8 , (6.12b)
0 ≤ Din ≤ 1 . (6.12c)
In Stage II, the optimization problem in (6.12) is solved by the cutting-edge PSO-SAVL
algorithm. Stage II is composed of three steps, the flowchart of which is given in Fig. 6.14.
First, different values of P and V2 are chosen. Second, given the selected P and V2, a cutting-
edge PSO variant, PSO-SAVL algorithm, is adopted to solve (6.12) for both S = EPS1 and
S = EPS2. Afterwards, the optimal total power loss Ploss* of these two EPS strategies is
compared, and the best EPS strategy under the specified P and V2 is selected.
Through the PSO-SAVL in Stage II, the best EPS strategy and the optimal Din can be
obtained which can achieve the best efficiency and all-switch ZVS over the entire range of
P and V2.
Step 1 For given P, V2 S = EPS2
For given P, V2 S = EPS1
Optimize efficiency with all-switch ZVS

Step 2
constraints in (6.12) through PSO-SAVL
Save the optimal Din and Ploss*
for the specified S, P, V2
*
Compare Ploss of EPS1 and EPS2
Step 3
and save optimal S and Din
Fig. 6.14. Flowchart of Stage II of the proposed AI-based HEPS modulation.
6.6.2 PSO-SAVL Adopted in Stage II of the Proposed HEPS
Particle swarm optimization (PSO) is a famous meta-heuristic optimization algorithm,

which exhibits good performance in continuous problems [11]. PSO-SAVL, a state-of-the-
art PSO variant, is chosen because of its robust global searching capability and fast
convergence speed in low dimensional problems [201]. As discussed in Section 6.3,
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different from many PSO variants, PSO-SAVL adaptively adjusts the velocity limit to match
the evolutionary state of particles, the strategy of which boosts its holistic performance.
For specified operating parameters S, P, V2
Initialize parameters of PSO-SAVL vlmax, vlmin, c1, c2
P sum Initialize particle position Din,j, velocity Vj

V2
S Ploss Evaluate funcj with (6.13), update pbest,j, gbest
Din
P sum
Evaluate f with (6.14), and update VL with (6.15)
V2
S nZVS
Din
Update velocity Vj with (6.16)
Models for ZVS and For velocity Vj exceeding [-VL, VL]:

Efficiency from If f>=0.5, clamp Vi to [-VL, VL];
Stage I If f<0.5, randomly reinitialize Vj.
Update position Din,j with Din,j+Vj, and

randomly reinitialize Din,j if exceeds [0, 1]
No
reach maximum epoch?
Yes
*
Save optimal Din and Ploss for the specified S, P, V2
Fig. 6.15. Flowchart of PSO-SAVL applied in Stage II.
The flowchart of PSO-SAVL is given in Fig. 6.15 and is discussed as follows. Under the
specified operating parameters of S, P and V2, PSO-SAVL are initialized first, such as
velocity limit factors vlmin, vlmax, and learning factors c1, c2. Position Din,j and velocity Vj of
all particles are also initialized. Afterwards, based on the surrogate models of ZVS and
efficiency from Stage I, the objective value funcj is evaluated with (6.13), and personal best
position pbest,j and global best position gbest are updated. In (6.13), cZVS is the weight factor
of ZVS constraint. Subsequently, evolutionary factor f is evaluated with (6.14), where dmin
and dmax are the minimum and maximum values of dj, and dg is the dj of the globally best
particle. Based on f, velocity limit VL is updated with (6.15). Velocity Vj of the jth particle
is updated with (6.16), and the new Vj is then constrained to the range [-VL, VL]. With the
new and bounded Vj, position Din,j is updated and constrained within [0, 1]. This procedure
repeats until the maximum epoch has been reached. If PSO-SAVL terminates, the optimal
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Din which has optimal efficiency and all-switch ZVS under the specified S, P and V2 can
be found.
func j =Ploss + max(8 − nZVS , 0) ⋅ cZVS (6.13)
dg − dmin
f = (6.14a)
dmax − dmin
1 N
=dj ∑
N − 1 =k 1,k ≠ j
Din , j − Din ,k (6.14b)
1
VL ⋅ Din ,max
 1    1   1   (6.15)
1+  − 1 exp  ln   − 1  − 1  f 
 vlmin    vlmax   vlmin  
   
V j = ω ⋅V j + c1 ⋅ r1 ⋅ ( pbest j − Din , j ) + c2 ⋅ r2 ⋅ ( gbest − Din , j ) (6.16)
To sum up, under the selected P and V2, the best EPS strategy S and the optimal inner
phase shift Din can be searched by following the steps of Stage II.
6.7 Design Case with the Proposed AI-Based HEPS
In this section, by following the proposed AI-based HEPS approach, an efficiency-

oriented hybrid EPS modulation with full ZVS range for DAB converters is designed.
6.7.1 Stage I: Build Data-Driven Models of ZVS and Efficiency with

XGBoost Algorithm
As a preparation for the proposed HEPS approach, the operating conditions of design case
are specified in Table 6.3, where the rated power Prated is 1000 W, and rated input and output
voltages V1,rated and V2,rated are 200 V. fs is 20 kHz and dead time is 400 ns. Leakage
inductance Lr is 167 μH as calculated by (6.8). In this design case, both buck and boost
working conditions are considered: V2 varies within [160 V, 240 V]. The adjustable range
of P is [100 W, 1000 W].
By following the flowchart of Stage I in Fig. 6.12, two equivalent data-driven models for
ZVS and efficiency performance are built with XGBoost algorithm. In Step 1,
20×20×80=32,000 combinations of V2, P and Din are uniformly sampled for both EPS1 and
EPS2. Since two EPS strategies are considered, the total number of simulations to run is
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2×32,000=64,000. In Step 2, PLECS simulations with the chosen operating parameters are
conducted to collect the total power loss Ploss and the number of switches nZVS that meet
ZVS constraints. Finally, with the collected Ploss and nZVS, two XGBoost models of ZVS and
efficiency are trained, the configurations of which are shown in Table 6.4.
Table 6.3 Specifications of Design Case.

Rated Conditions
Prated 1000 W V1,rated 200 V
V2,rated 200 V fs 20 kHz
Switching Device
Device series C2M0080120D Dead time 400 ns
Transformer
Leakage inductor Lr 167 μH
Turn ratio n 1
Ranges of Operating Parameters
P [100 W, 1000 W] V2 [160 V, 240 V]
Table 6.4 Configurations of XGBoost Models of ZVS and Efficiency.

Inputs P, V2, S, Din
Learning rate 0.08
Structure of XGBoost-1 for Efficiency Performance
Output Total power loss Ploss
Maximum tree depth 9
Regularization coefficient 0.1
Number of base tree models 1930
Structure of XGBoost-2 for ZVS Performance
Output Number of switches satisfying ZVS nZVS
Maximum tree depth 6
Regularization coefficient 1
Number of base tree models 189
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6.7.2 Stage II: Optimize Efficiency with Full ZVS Operation through
PSO-SAVL Algorithm
With the flowchart of Stage II in Fig. 6.14, the best EPS strategy between EPS1 and EPS2
and the optimal Din are obtained for a broad range of P and V2. The parameters of the adopted
PSO-SAVL in Stage II are given in Table 6.5. The resulting optimal inner phase shift Din
for strategies EPS1 and EPS2 are given in Fig. 6.16 and Fig. 6.17, respectively.
Table 6.5 Configurations of PSO-SAVL in Stage II.

P, V2, S, Din, XGBoost-1 Ploss(P, V2, S, Din),
Inputs
XGBoost-2 nZVS(P, V2, S, Din)
Output Optimal Din and optimal Ploss* for given P, V2, S
Number of particles 5
Maximum iterations 50
Weight inertia ω Linearly decrease from 0.9 to 0.4
ZVS weight factor cZVS = 100
Learning factors c1 = c2 = 2.05
Velocity limit factors vlmax = 0.7; vlmin = 0.4
Optimal Din S=EPS1

1.0
0.8
0.6
0.4
1000 160
P (W)500 100 240 200 V (V)
2
Fig. 6.16. Optimal Din for strategy EPS1 as obtained by Stage II.
Optimal Din
1.0
0.8
0.6 S=EPS2
1000 0
P (W) 500 100 240 200 V2(V) 16
Fig. 6.17. Optimal Din for strategy EPS2 as obtained by Stage II.
With the optimal Din, the ZVS ranges of EPS1 and EPS2 with respect to the considered
ranges of P and V2 are shown in Fig. 6.18. For EPS1, it realizes all-switch ZVS operation in
156
buck mode (V2 < 200 V), but some switches lose their soft switching operation in boost
mode (V2 > 200 V) and light load situations. Conversely, EPS2 achieves ZVS for all 8
switches under boost situations, but it can only achieve partial ZVS in buck mode.
P (W) S=EPS1 P (W) S=EPS2

1000 1000
500 8 switches ZVS 500 8 switches ZVS

6
300 switches 300
ZVS 6 switches
4 switches ZVS
100 100 ZVS
160 200 240 160 200 240
V2 (V) V2 (V)
Fig. 6.18. ZVS ranges of EPS1 and EPS2 with the obtained optimal Din.
η 97.4%
96.8% EPS2
96.2% EPS1
EPS1 EPS2
95.6% P = 1000 W
η 97.6%
97.2% EPS2
EPS1
96.6% P = 600 W
η 96%
Buck : Boost : EPS2
88% EPS1 EPS1 better EPS2 better
80% P = 200 W
160 200 240 V2(V)
Fig. 6.19. Optimal efficiency of EPS1 and EPS2 with the obtained optimal Din.
Ploss* (W) HEPS

45
Buck Mode
35 EPS1
25
Boost Mode
15
EPS2
1000 160
800 6 180
P (W) 00 400 200 (V)
200 220 V2
240
Fig. 6.20. Efficiency performance of the proposed AI-based HEPS modulation in the
entire voltage and power ranges.
The optimal efficiency performance for the two EPS strategies is shown in Fig. 6.19. 1000
157
W, 600 W and 200 W are taken as examples, and other power conditions share the same
patterns as the following. As can be concluded from Fig. 6.19, in buck operating mode,
EPS1 realizes higher efficiency than EPS2 for all three power levels, and EPS2 stands out
in boost mode. Under the unit gain operating mode (V2 = 200 V), from Figs. 6.16 and 6.17,
Din of both EPS1 and EPS2 is optimized to 1, which is the same as SPS modulation.
Consequently, in the proposed HEPS modulation, to realize optimal efficiency and all-
switch ZVS operation over the entire operating ranges, EPS1 and EPS2 are applied in buck
mode and boost mode, respectively. The optimal total power loss Ploss* of the proposed AI-
based HEPS approach is given in Fig. 6.20. In HEPS modulation, the three-level voltage
wave is applied to the high voltage side, reducing reactive power and circulating current,
and thus contributing to high efficiency.
6.8 Experimental Validation
To validate the design case in Section 6.7, hardware experiments have been carried out.
Fig. 6.21 shows the designed hardware platform, which consists of an isolated DAB
converter, a DC source, an auxiliary power supply, a variable resistive load, a DSPACE
1202 control platform, and a Lecroy oscilloscope. The specifications of the design case are
listed in Table 6.3.
Fig. 6.21. Hardware platform for experimental validation.
6.8.1 Experimental Waveforms
In this part, the steady-state experimental waveforms under different P and V2 are shown.
The values of P are 1000 W, 500 W and 100 W, which respectively represent high, medium
158
and low power conditions. And V2 can be 200 V, 160 V and 240 V, which respectively
represent unit gain, buck and boost modes. The notations and directions of waveforms are
given in Fig. 6.1.
Under the rated conditions when P is 1000 W and V2 is 200 V, the ac-side voltage
waveforms vp, vs are two-level waves as shown in Fig. 6.22, which is intrinsically the SPS
modulation. The ZVS constraints of all 8 switches are satisfied, as the inductor current iL
shown in Fig. 6.22 (b).
V1: [100 V / div]
V2: [100 V / div]

V1
V2 I2: [5 A / div]
I2
(a)
vp: [200 V / div]
vp All-switch
ZVS iL: [10 A / div]
iL
vs vs: [200 V / div]
(b)
Fig. 6.22. Experimental waveforms under rated conditions when P is 1000 W and V2
is 200 V: (a) V1, V2 and I2; (b) vp, iL and vs.
Under unit gain operation when V2 is 200 V, the ac-side waveforms vp, iL and vs of 500
W and 100 W are shown in Fig. 6.23. Figs. 6.22 and 6.23 together verify the all-switch
ZVS operation under unit gain mode. Fig. 6.24 presents the waveforms of 1000 W, 500 W
and 100 W under buck mode when V2 = 160 V. When V2 = 160 V, the optimal Din in Fig.
6.16 is applied to primary full bridge, which is EPS1 strategy, and all-switch ZVS
requirements have been met. As shown in Fig. 6.25, for boost mode when V2 = 240 V,
EPS2 strategy with the optimal Din in Fig. 6.17 is selected, which achieves full ZVS
operation over entire power range.
159
vp: [200 V / div]
vp
vs: [200 V / div]
vs
iL iL: [5 A / div]
All-switch ZVS Time: [20 μs / div]
(a)
vp: [200 V / div]
vp All-switch
ZVS iL: [1 A / div]
iL
(b)
Fig. 6.23. Experimental waveforms under unit gain mode when V2 is 200 V and: (a) P
= 500 W; (b) P = 100 W.
All-switch All-switch vp: [200 V / div]

vp ZVS vp: [200 V / div] vp ZVS
iL: [10 A / div] iL: [5 A / div]
iL iL
vs vs: [200 V / div] vs vs: [200 V / div]
(a) (b)
All-switch vp: [200 V / div]
ZVS
vp
iL: [2 A / div]
iL
(c)
Fig. 6.24. Experimental waveforms under buck mode when V2 is 160 V and: (a) P =
1000 W; (b) P = 500 W; (c) P = 100 W.
160
vp All-switch vp: [200 V / div] vp All-switch vp: [200 V / div]
ZVS ZVS
iL: [10 A / div] iL: [5 A / div]
iL iL
vs vs: [200 V / div] vs vs: [200 V / div]
(a) (b)
All-switch vp: [200 V / div]
vp ZVS iL: [2 A / div]
iL
(c)
Fig. 6.25. Experimental waveforms under boost mode when V2 is 240 V and: (a) P =
1000 W; (b) P = 500 W; (c) P = 100 W.
6.8.2 ZVS Analysis

vds1: [100 V / div] vds5: [100 V / div]
S1, S2 ZVS Q1, Q2 ZVS

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]

vgs3: [10 V / div] vgs7: [10 V / div]
(a)
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]

vgs3: [10 V / div] vgs7: [10 V / div]
(b)
161
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vds3: [100 V / div] vgs5: [10 V / div]
vds7: [100 V / div]
S3, S4 ZVS
Q3, Q4 ZVS
vgs3: [10 V / div] vgs7: [10 V / div]
(c)
Fig. 6.26. ZVS waveforms vds1, vgs1, vds3, vgs3, vds5, vgs5, vds7, vgs7, when V2 = 200 V
and: (a) P = 1000 W; (b) P = 500 W; (c) P = 100 W.
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]

vgs3: [10 V / div] vgs7: [10 V / div]
(a)
vds1: [100 V / div]
vds5: [200 V / div]
Q1, Q2 ZVS
S1, S2 ZVS
vgs1: [10 V / div] vgs5: [20 V / div]
vds3: [100 V / div]
Q3, Q4 ZVS vds7: [200 V / div]
S3, S4 ZVS
vgs3: [10 V / div] vgs7: [20 V / div]
(b)
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div]
vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]
S3, S4 ZVS
Q3, Q4 ZVS
vgs3: [10 V / div] vgs7: [10 V / div]
(c)
and: (a) P = 1000 W; (b) P = 500 W; (c) P = 100 W.
162
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]

vgs3: [10 V / div] vgs7: [10 V / div]
(a)
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]

vgs3: [10 V / div] vgs7: [10 V / div]
(b)
vds1: [100 V / div] vds5: [100 V / div]

vgs1: [10 V / div] vgs5: [10 V / div]
vds3: [100 V / div] vds7: [100 V / div]
S3, S4 ZVS
Q3, Q4 ZVS
vgs3: [10 V / div] vgs7: [10 V / div]
(c)
and: (a) P = 1000 W; (b) P = 500 W; (c) P = 100 W.
To further validate the full ZVS operation of the proposed HEPS modulation over the
entire operating ranges, drain-source voltage vds and gate-source voltage vgs of switches are
given. Fig. 6.26 shows the ZVS waveforms when DAB converter operates under unit gain
mode, where vds1 and vgs1 are the vds, vgs waveforms of switch S1, and vds5 and vgs5 are the vds,
vgs waveforms of switch Q1. For load conditions of 1000 W, 500 W and 100 W, during the
commutation process of all switches, vds decreases to 0 V first, and then vgs rises to turn on
the switches. Hence, under unit gain mode (V2 = 200 V), all switches S1~S4 and Q1~Q4 have
realized ZVS for the entire power range.
The ZVS waveforms vds1, vgs1, vds3, vgs3, vds5, vgs5, vds7, vgs7 of DAB converter under buck
163
mode when V2 is 160 V are shown in Fig. 6.27. There exists a gap between the falling of vds
and the rising of vgs for all switches, validating the full ZVS operation under buck mode.
Moreover, Fig. 6.28 verifies the full ZVS operation under boost mode when V2 is 240 V.
In summary, based on the steady-state waveforms in Figs. 6.22 to 6.25 and the ZVS
waveforms in Figs. 6.26 to 6.28, for the entire power range and voltage range, the proposed
HEPS modulation can realize full ZVS operation for all 8 switches.
6.8.3 Transient Response after Voltage and Load Step
Time: [200 ms / div] Time: [200 ms / div]

vp: [200 V / div]
vp: [500 V / div]
Zone1 iL: [10 A / div] Zone2 Zone2 iL: [10 A / div] Zone1
vs: [200 V / div]

vs: [500 V / div]
(a)
vp: [200 V / div] Time: [10 μs / div] Zone1
vp S=EPS2
t2 t3 t4
t5 All-Switch
iL iL: [10 A / div]
t1 ZVS
t6
vs
vs: [200 V / div]
(b)
Zone2 Time: [10 μs / div]
vp: [200 V / div]
vp S=EPS1
t4
t2 t3 t5 iL: [5 A / div]
iL All-Switch t6
ZVS t1
vs
vs: [200 V / div]
(c)
Fig. 6.29. Experimental waveforms during voltage steps when load resistance is 57.6
Ω: (a) vp, iL and vs when V2 steps from 240 V to 160 V and from 160 V to 240 V; (b)
enlarged view of Zone1; (c) enlarged view of Zone2.
To verify that the proposed HEPS modulation can adaptively adjust the best EPS strategy
164
and the optimal Din in varying operating conditions, the experiments of voltage and load
step have been conducted in this part.
Under fixed load resistance of 57.6 Ω, the waveforms when V2 steps between 240 V and
160 V are shown in Fig. 6.29. In Zone1 when V2 is 240 V and P is 1000 W, EPS2 strategy
with the optimal Din is adopted, realizing all-switch ZVS as shown in Fig. 6.29 (b). As the
zoom-in waveforms of Zone2 shown, EPS1 is utilized and all-switch ZVS operation is
maintained. In the experiments of voltage step, the successful transition between two EPS
modulations under different operating conditions validates the hybrid operation of the
proposed HEPS modulation.

vp: [200 V / div] vp: [200 V / div]
vs: [200 V / div] vs: [200 V / div]
(a)
vp S=EPS2
t2 t3 t4 All-Switch
iL iL: [10 A / div] t5
t1 ZVS
t6
vs
vs: [200 V / div]
(b)
vp S=EPS2
t3
t1 t t4
iL iL: [5 A / div] 2 t5
t6
vs All-Switch
vs: [200 V / div] ZVS
(c)
Fig. 6.30. Experimental waveforms during load steps when V2 = 240 V: (a) vp, iL and
vs when P steps from 1000 W to 500 W and from 500W to 1000 W; (b) enlarged view of
Zone1; (c) enlarged view of Zone2.
165
vp: [200 V / div] vp: [200 V / div]
vs: [200 V / div] vs: [200 V / div]
(a)
vp S=EPS1
t3 t4 t5
All-Switch
iL iL: [10 A / div]
t2 ZVS
t1 t6
vs
vs: [200 V / div]
(b)
vp S=EPS1
t4
t3
t2 t5 All-Switch
iL iL: [5 A / div]
t6 ZVS
vs t1
vs: [200 V / div]
(c)
Fig. 6.31. Experimental waveforms during load steps when V2 = 160 V: (a) vp, iL and
vs when P steps from 1000 W to 500 W and from 500W to 1000 W; (b) enlarged view of
Zone1; (c) enlarged view of Zone2.
The experiments of load step under buck mode and boost mode are given in Fig. 6.30 and
Fig. 6.31, respectively. When V2 is 240 V and P steps between 500 W and 1000 W, the best
EPS modulation is EPS2 and the optimal Din is adjusted accordingly to achieve optimal
efficiency and ZVS operation for all switches. As shown in Fig. 6.31, when V2 is 160 V and
load steps occur, EPS1 is the best strategy and Din has been tuned to its optimal.
In a nutshell, the experiments of voltage and load step comprehensively validate the real-
time operation of the proposed AI-based HEPS modulation.
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6.8.4 Efficiency and ZVS Performance of the Proposed AI-based HEPS
Modulation
The experimental performance of efficiency and ZVS of the proposed AI-based HEPS
modulation is discussed as follows.
η 98%
94%
90% SPS
Best EPS2
86% S=EPS1, HEPS
V2=160 V
82%
100 200 300 400 500 600 700 800 900 1000 P (W)
Number of switches satisfy ZVS constraints nZVS
SPS 4 4 4 4 8 8 8 8 8 8
Best EPS2 6 6 6 6 8 8 8 8 8 8
HEPS 8 8 8 8 8 8 8 8 8 8
P (W) 100 200 300 400 500 600 700 800 900 1000
Fig. 6.32. Experimental efficiency (η) and ZVS performance (nZVS) of SPS, best EPS2,
and the proposed HEPS approach in buck mode when V2 = 160 V.
η 98%
94%
90% SPS
S=EPS2,
Best EPS1
V2=240 V
86% HEPS
82%
100 200 300 400 500 600 700 800 900 1000 P (W)
SPS 4 4 4 4 4 4 8 8 8 8
Best EPS1 4 6 6 6 6 6 8 8 8 8
HEPS 8 8 8 8 8 8 8 8 8 8
P (W) 100 200 300 400 500 600 700 800 900 1000
Fig. 6.33. Experimental efficiency (η) and ZVS performance (nZVS) of SPS, best EPS1,
and the proposed HEPS approach in boost mode when V2 = 240 V.
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η 98%
96%
94%
92%
V2=200 V HEPS
90%
88% 100 200 300 400 500 600 700 800 900 1000 P (W)
HEPS 8 8 8 8 8 8 8 8 8 8
P (W) 100 200 300 400 500 600 700 800 900 1000
Fig. 6.34. Experimental efficiency (η) and ZVS performance (nZVS) of the proposed
HEPS approach in unit gain mode when V2 = 200 V.
Under buck operating mode when V2 is 160 V, efficiency η and ZVS nZVS of the proposed
HEPS approach compared with other approaches are shown in Fig. 6.32, where the best
EPS2 is the EPS2 strategy with the optimal Din in Fig. 6.17. The proposed HEPS strategy
exhibits the best efficiency in the entire load range, and its peak efficiency is 97.1%. In terms
of nZVS, the best EPS2 strategy can improve the ZVS performance compared with SPS
strategy, and our HEPS approach can realize all-switch ZVS over entire load range.
Fig. 6.33 presents the performance in boost condition when V2 is 240 V, where the best
EPS1 is the EPS1 strategy with the optimal Din in Fig. 6.16. Compared with SPS and best
EPS1 strategy, our HEPS strategy boosts efficiency by 4% when P ≤ 300 W, and it achieves
the optimal efficiency in all load levels. From the perspective of ZVS performance, when P
is within [200 W, 600 W], the best EPS1 approach improves the 4-switch ZVS operation of
SPS to 6-switch ZVS operation. The proposed HEPS approach can achieve 8-switch ZVS
operation in all range.
The efficiency and ZVS performance of HEPS modulation in unit gain mode is given in
Fig. 6.34. In unit gain mode, HEPS modulation is optimized to SPS strategy. Its peak
efficiency reaches 97.08%, and all-switch ZVS operation is satisfied in the entire load range.
In a word, the proposed AI-based HEPS modulation is experimentally validated to
achieve the best efficiency while meeting all-switch ZVS operation over the full voltage
and power ranges. Steady-state waveforms are presented in a comprehensive manner. Its
full ZVS operation and its superior efficiency performance have been studied in detail. The
experiments of voltage and load step verify the real-time operating capability of HEPS
approach.
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6.9 Conclusion
In this chapter, assisted by AI techniques, a hybrid extended phase shift (HEPS)

modulation is proposed, which combines two EPS strategies. The proposed HEPS approach
can optimize efficiency while maintaining all-switch ZVS operation over the full voltage
and power ranges. With the integration of simulation software and XGBoost algorithm, the
ZVS and efficiency models of the HEPS approach are developed in an automatic fashion,
which alleviates the cumbersome and inaccurate model building process in conventional
approaches. Generally, the proposed HEPS approach includes two stages. In Stage I, with
the simulation-generated performance data, XGBoost algorithm is chosen to build data-
driven models of ZVS and efficiency. Stage II utilizes the cutting-edge PSO-SAVL
algorithm to optimize modulation strategy and parameter for the best efficiency and full
ZVS operation. 1 kW hardware experiments on a DAB prototype validate the optimal
efficiency, full ZVS range, real-time operating capability and thus the effectiveness of the
proposed AI-based HEPS approach.
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Chapter 7 Conclusion and Future Works
First, the contributions of the AI-based methodologies proposed in Chapter 3 to Chapter

6 are summarized in Section 7.1. Subsequently, this thesis looks further ahead in the future
of AI techniques tailored for the domains of power electronics, and envisions prosperous
applications of AI algorithms in the life cycle of power electronics from design, control, to
maintenance.
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7.1 Conclusion
Generally, this thesis comprehensively studies the application of AI methodologies in

the circuit and modulation design of DC-DC converters. In summary, Chapter 1 provides
research backgrounds and firmly justifies the issues of heavy manpower burden and low
design accuracy in the conventional approaches for the design of DC-DC converters.
Chapter 2 systematically reviews relevant research works and gives evidence to the
objectives and motivation of this thesis. Chapter 3 to Chapter 6 propose several AI-based
design approaches for the design of DC-DC converters, the conclusions of which are
summarized as the following.
In the multi-objective design of synchronous Buck converters in Chapter 3, three
conflicted design objectives (efficiency, cutoff frequency, and volume) are considered to
obtain holistic design solutions for different application scenarios. The novel coevolving-
AMOSA algorithm for optimization improves the uniformity and completeness of the
Pareto frontier. The efficiency-oriented design has 94.6% efficiency under rated conditions,
which is 1.55% higher than the conventional design. The power-density-oriented design
maintains the same efficiency as the conventional design case, while reducing 76.4%
volume required. The filtering-capability-oriented design reduces the conventional cutoff
frequency by 23.2%.
Aiming at the challenges of heavy human-dependence and low design accuracy, Chapter
4 suggests combining simulation and NN for the automated analysis process of design
objectives, and using GA for the automated optimization. This approach is implemented in
an automated fashion. Moreover, the lookup tables of inductors and capacitors are adopted
to reach high design accuracy. Given the design case of a 100 W synchronous Buck
converter in the 48 V to 12 V accessory-load supply system of EV, the proposed approach
achieves 93.38% efficiency, 0.583% voltage ripple and 9.6% current ripple. The average
deviation between the automated theoretical analysis and experimental performance is only
1.31%.
Targeting at the similar issues in conventional modulation design approaches and to
facilitate automated modulation design, a fully automated TPS modulation is designed with
the assistance of AI techniques, in which simulation and NN are integrated to build data-
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driven models of current stress, PSO is adopted for optimization, and FIS is chosen for
online real-time modulation. A 1 kW design case is given, where the output voltage varies
within [160 V, 230 V], and the output power lies within [100 W, 1000 W]. The steady-state
current stress and efficiency verify the optimal performance of the proposed approach, and
the dynamic response validates the online real-time operation of the designed modulation.
Even though the proposed approach in Chapter 5 realizes automated modulation design,
it still suffers from the following drawbacks: First, it only considers current stress as the
objective; Second, TPS modulation has three degrees of control freedom, which is hard to
implement; In addition, the utilized NN and conventional PSO algorithm are not the most
suitable techniques. To overcome these disadvantages, Chapter 6 considers two two-
degree-of-freedom EPS strategies, with design objectives to be optimal efficiency and full-
range ZVS. The XGBoost algorithm replaces NN for the data-driven modeling of
efficiency and ZVS, and a novel PSO-SAVL algorithm is proposed, the performance of
which is theoretically and empirically validated. 1 kW hardware experiments have
validated the full-range ZVS operation, optimal efficiency, and good dynamic response of
the proposed hybrid modulation. The proposed approach boosts light-load efficiency by
4%, and the maximal efficiency when output voltage is 200 V, 160 V and 240 V is 97.1%,
97.1% and 97.3%, respectively.
7.2 Future Works
This section points out two future directions for the combination of AI and power
electronics. One future direction is to investigate AI algorithms tailored for power
electronics domains by considering the underlying data characteristics such as sparsity and
invariance. In addition, the applications of AI techniques in the design, control, and
maintenance of power converters can be explored.
7.2.1 AI Algorithms Tailored for Power Electronics
• Data-light and computation-light AI
One of the bottlenecks hindering the applications of AI in power electronics is that most
data-driven techniques are data-intensive, which normally require large datasets for feature
extraction. However, many power electronics domains are hard or infeasible to acquire that
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big amount of data, such as various fault cases in the application of fault diagnosis,
component degradation behaviors for the prediction of remaining useful life, etc. To provide
acceptable learning performance in the absence of sufficient data, data-light AI techniques
should be studied. For instance, the multi-task learning can be utilized to train a single neural
network with shared neurons to represent correlated design objectives to reduce data
requirements. In addition, few-shot learning techniques deal with the situations where only
few data points are given. Besides, generative adversarial net, which can synthesize almost
real data points, can be used as data augmentation to supplement the insufficient dataset.
A significant difference between power electronics and pure AI domains like computer
vision and natural language processing is that the controller of power converters typically
executes thousands of times per second to reliably attain control purpose. The fast execution
speed requires the AI models implemented in real time to be computation light.
Computation-light AI techniques that can be deployed in edge nodes with limited
computation power is a prospective future. Fortunately, advancements in edge computing
and green learning can be referred. Model compression and operation quantization may be
potential approaches. Neural architecture search, which constructs neural networks from
simple architecture to complex structure, is a good alternative for building computation-
light AI models.
• Physics-informed AI with Explainability
Foremost, an urging need for data-driven models is to improve the transparency and
interpretability, which bolsters the confidence of field experts to implement these AI-based
models in industry applications. Physics-informed AI reveals a promising future of AI in
power electronics. The explainable merit of physics-informed AI is indispensable for safety-
critical applications such as condition monitoring, control, etc. Essentially, physics-
informed AI embeds the circuit formular like the Kirchhoff’s law into the architecture,
which enhances explainability and reduces data requirements. Physics-informed neural
network is an example of physics-informed AI. Graph neural network (GNN) can be used
to encode the circuit behaviors since power converters are natural graphs.
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7.2.2 AI Algorithms in the Life Cycle of Power Electronics: Design,
Control, and Maintenance
• Digital twins for power electronics systems
Different from the existing knowledge-based and data-driven approaches, digital twins
are accurate modelling methods that can reproduce the behaviors of physical power
converters in real time. Digital twins for power electronics systems have wide applications
in design and optimization, control, condition monitoring, and fault detection. To effectuate
digital twins for power electronics systems, three perspectives should be satisfied: First,
data-light modelling with less data; Second, temporal behavioral modelling; Third, real-time
AI-based emulation of power converters.
First, data-light modelling with less data shortens the data collection process, speeds up
the industry application cycle, and increases the penetration of AI-based modelling
approaches. Section 7.2.1 has discussed the future trend of data-light AI, which adopts
multi-task learning, few-shot learning, generative models, and other techniques to reduce
the needs of a large dataset for training.
Second, as a possible future direction, the temporal behaviors of power converters such
as the waveforms of inductors, capacitors, and semiconductors, can be directly modeled to
improve the modeling approaches given in this thesis. In this thesis, the proposed
methodologies only learn the mapping functions between design parameters and design
objectives. However, if the circuit temporal behaviors are modeled via time-dependent
recurrent NN, the converter behaviors are totally reproducible. Hence, modeling temporal
behaviors of power converters is a more generalized approach. Moreover, the transparency
and interpretability of AI-based temporal models can be improved with physics-informed
AI, as elaborated in Section 7.2.1. Apart from that, if the AI-based surrogate models
mismatch the actual behaviors in practical world, experimental data can be leveraged to
mitigate the model discrepancy. With experimental data, the uncertainty of environments,
measuring noise, and errors can be quantized, which facilitates practical design, control, and
maintenance.
There are several advantages of modeling the temporal behaviors of power converters.
First, based on the models of converter temporal behaviors, many design objectives can be
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directly evaluated, such as the ripples, harmonics, peak-to-peak values, efficiency, etc.
Second, the temporal models of power converters can be used for quick control design.
Third, AI-based temporal models are much faster than traditional simulation.
Third, digital twins for the temporal behavior of power converters should be computation-
light for real-time emulation of physical components. With the AI-based digital twins
inferencing in real time, the intelligent operation of power electronics systems enables
interactive communication between the physical systems and the cyber systems. This allows
power electronics systems to collect information and respond to the information received
more actively. To fulfill the increasing connectivity, new Internet-of-Things (IoT)
frameworks for the communication among systems will be proposed. Other domains such
as cyber security, IoT, control, and communication should be investigated in accordance
with the increasing digitalization of power electronics systems.
• AI-based automated design considering more design parameters, more design

objectives, and more power converters
The AI-based design methodologies proposed in this thesis are universal and can be
easily scaled to include more design parameters, more design objectives and for more
power converters. For illustrative purposes, this thesis only considers simple design
scenarios. Possible future extensions of the proposed AI-based design methodologies are
discussed as follows.
First, the proposed AI-based design techniques can consider more design parameters to
have more flexible designs. As illustrated in Section 2.2, design parameters of power
converters include topologies, semiconductors, transformers, inductors, capacitors, and
hardware. For instance, as a major part contributing to total power loss, magnetic
components such as the transformer can be included in circuit design, the parameters of
which include the geometric shape, magnetic material, core size, etc. Besides, since the
reliability of electrical components is closely related with the thermal behavior, thermal
models can be considered in the design to improve the overall lifetime of power converters.
Moreover, the circuit topology of power converters can be improved with advanced AI
algorithms such as reinforcement learning and GNN. Reinforcement learning regards the
circuit topology as a chain of components connecting with one another, and GNN can be a
generative tool to synthesize novel circuit diagrams with predetermined attributes.
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Except for more design parameters, more design objectives can be considered for a good
comprehensive performance. With the integration of simulation and AI techniques such as
NN and XGBoost, the mathematical expressions of design objectives can be automatically
deduced, and the only tricky part is to construct accurate simulations for evaluating
performance. In general, electrical performance can be evaluated with Matlab, LTspice,
Pspice, PSIM, Plecs, etc. Magnetic performance can be evaluated with Ansys, and thermal
performance can be obtained with Ansys and Plecs. For design objectives such as cost and
size, lookup tables built from component datasheets can be used. Recently, how to optimize
the complicated objectives such as zero voltage and zero current switching (ZVZCS)
performance of multi-level DC-DC converters attracts many research attentions, the
complexity of which results in heavy manpower burden for formularizing analytical models.
The proposed AI-based design approaches are suitable to attain low computation complexity
and high modelling accuracy simultaneously with the automated design procedure.
Moreover, the proposed AI-based design approaches are universal enough to be applied
in all kinds of power converters. Possible future directions are the applications of these AI-
based automated approaches in different power converters for various design scenarios.
Furthermore, the existing AI-based design methodologies can be further automated
through the embeddings of domain expertise and field experience. GNN is a prospective
approach for embedding domain knowledge of power electronics, based on which
traditional knowledge-dependent tasks such as topology recommendation and component
selection can be automated. Utilizing GNN for knowledge graph embedding, the future of
power electronics will be more automated than the current stage.
• Advanced control and modulation
AI techniques will be retrofitted to facilitate advanced control and modulation to

consider the uncertainty, noise, and component degradation in the real-world environments.
Machine learning and meta-heuristic algorithms can be applied for model predictive
control, sliding mode observer, backstepping control, ultralocal model control, model-
agnostic control, etc. In the research area of control for power converters, reinforcement
learning is an emerging technique that may play important roles. By continuous trials and
errors in the environments, reinforcement learning can find the best control strategy in
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making a chain of decisions, which can be naturally applied in real-time modulation,
controller design, control strategy optimization, etc.
From the perspective of modulation, the most sophisticated modulation considered in this
thesis has three degrees of control freedom, which is the TPS modulation for DAB
converters. More powerful modulation strategies can achieve better operating performance,
but the issues of heavy manpower burden and low modulation accuracy may exacerbate.
Therefore, the proposed AI-based automated modulation design approaches can be
applied in more complicated modulation strategies to achieve outstanding performance
while mitigating excessive human-dependence. As an example, in terms of the modulation
approaches for DAB converters, TPS strategy and PWM strategy can be integrated to form
a hybrid modulation, which can be automatically designed to improve both ZVS and ZCS
performances using the proposed approaches in this thesis. Moreover, in the future, other
popular modulation techniques such as the space vector modulation and selective harmonic
elimination can be designed with the methodologies proposed.
• Applications of AI in the maintenance of power converters
Except for the design and control of power converters, AI algorithms will be applied in
the maintenance stage of power converters, including condition monitoring, remaining
useful life prediction, fault diagnosis, etc. A significant aspect for the domains of
maintenance is how to confidently provide the right prediction for unseen cases given
insufficient and highly biased training data. Unsupervised learning methods such as one-
class SVM can be possible solutions, and semi-supervised learning approaches can make
reliable decisions if trained properly. For safety-critical tasks such as the fault detection in
electric aircraft, model interpretability is a necessary trait to deploy with confidence.
Physics-informed AI is the promising future for explainable maintenance.
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Author’s Publications
Journal Paper:
[1] X. Li, X. Zhang, F. Lin, and F. Blaabjerg, “Artificial-Intelligence-Based Design (AI-D) for
Circuit Parameters of Power Converters,” IEEE Trans. Ind. Electron., pp. 1–1, 2021.
[2] X. Li, J. Pou, J. Dong, F. Lin, C. Wen, S. Mukherjee, and X. Zhang, ‘Data-Driven Modeling with
Experimental Augmentation for the Modulation Strategy of the DAB Converter’, in IEEE Trans.
Ind. Electron. (Accepted).
[3] X. Li, X. Zhang, F. Lin, C. Sun, and K. Mao, ‘Artificial-Intelligence-Based Triple Phase Shift
Modulation for Dual Active Bridge Converter with Minimized Current Stress’, IEEE J. Emerg.
Sel. Top. Power Electron., pp. 1–1, 2021.
[4] X. Li, K. Mao, F. Lin, and X. Zhang, “Particle swarm optimization with state-based adaptive
velocity limit strategy,” Neurocomputing, vol. 447, pp. 64–79, Aug. 2021.
[5] X. Li, X. Zhang, F. Lin, C. Sun and K. Mao, " Artificial-Intelligence-Based Hybrid Extended
Phase Shift Modulation for the Dual Active Bridge Converter with Full ZVS Range and Optimal
Efficiency," in IEEE J. Emerg. Sel. Top. Power Electron., doi: 10.1109/JESTPE.2022.3185090.
[6] X. Li, X. Zhang, and F. Lin, ‘Multi-Objective Design of Output LC Filter for Buck Converter
via the Coevolving-AMOSA Algorithm’, IEEE Access, vol. 9, pp. 11884–11894, 2021.
[7] X. Zhang, X. Li, H. Ma, B. Zhao, and Z. Zeng, ‘AI Based Design Methodology for Power
Converters’, in Springer, ISBN-13: 9789811914034.
[8] F. Lin, X. Zhang, X. Li, H. Ma, and C. Cai, ‘Design of Symmetrical CLLC Resonant DC
Transformer Considering Voltage Transfer Ratio and Cascaded System Stability’, IEEE Trans.
Ind. Electron., pp. 1–1, 2021.
9] F. Lin, X. Zhang, X. Li, L. Chaohui, and H. Ma, ‘Parameter Design for Symmetrical CLLC-
Type DC Transformer Considering Cascaded System Stability and Power Efficiency’, IEEE J.
Emerg. Sel. Top. Power Electron., vol. 9, no. 5, pp. 6219–6231, Oct. 2021.
[10] F. Lin, X. Zhang, and X. Li, ‘Design Methodology for Symmetric CLLC Resonant DC
Transformer Considering Voltage Conversion Ratio, System Stability, and Efficiency’, IEEE
Trans. Power Electron., vol. 36, no. 9, pp. 10157–10170, Sep. 2021.
178
[11] F. Lin, X. Zhang, X. Li, C. Sun, W. Cai, and Z. Zhang, ‘Automatic Triple Phase Shift Modulation
for DAB Converter with Minimized Power Loss’, IEEE Trans. Ind. Appl., pp. 1–1, 2021.
[12] F. Lin, X. Zhang, X. Li, C. Sun, G. Zsurzsan, W. Cai, and C. Wang, ‘AI-Based Design with Data
Trimming for Hybrid Phase Shift Modulation for Minimum-Current-Stress Dual Active Bridge
Converter’, in IEEE J. Emerg. Sel. Top. Power Electron, doi: 10.1109/JESTPE.2022.3232534.
[13] J. Dong, J. Pou, X. Li, Y. Zeng, S. Mukherjee, and G. Amit, ‘Hybrid Duty Ratio and Phase-Shift
Modulation for Si + SiC Neutral-Point-Clamped Dual-Active-Bridge Converter’, IEEE J. Emerg.
Sel. Top. Power Electron. (Corresponding Author, Under Review).
[14] X. Li, K. Mao, F. Lin, and Z. Feng, ‘Feature-aware Conditional GAN for Category Text
Generation’, Neurocomputing. (First Author, Under Review).
Conference Paper:
[15] X. Li, F. Lin, J. Pou, M. Suvajit and J. Dong, " Data-Driven Modeling of Zero Voltage Switching
of Non-Resonant Dab Converters Under TPS Modulation," 2023 IEEE Applied Power Electronics
Conference and Exposition (APEC). (Outstanding Presentation Award)
[16] X. Li, F. Lin, X. Zhang, M. Huang, and H. Wang, “Multi-objective Design of LC Filter for High-
efficiency, High-power-density and High-performance Buck Converter,” in 2019 IEEE Energy
Conversion Congress and Exposition (ECCE), Baltimore, MD, USA, Sep. 2019, pp. 5132–5136.
[17] X. Li, X. Zhang, and F. Lin, “Pareto-Frontier-Based Multi-Objective Design of Output LC Filter
for High Efficiency, High Reliability, and High Power-Density Buck Converter,” in 2020 IEEE
9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia),
Nanjing, China, Nov. 2020, pp. 1579–1582.
[18] X. Li, X. Zhang, and F. Lin, “Design of LC Filter for Boost Converter with the Considerations
of Efficiency and Power Density,” in IECON 2020 The 46th Annual Conference of the IEEE
Industrial Electronics Society, Singapore, Singapore, Oct. 2020, pp. 2846–2849.
[19] X. Li and X. Zhang, “Design of LC Filter in Synchronous Buck considering Power Loss and Cost
Criterions using Particle Swarm Optimization,” in 2019 IEEE 13th International Conference on
Power Electronics and Drive Systems (PEDS), Toulouse, France, Jul. 2019, pp. 1–4.
179
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AI Applications in DC-DC Converter Design

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School of Electrical and Electronic Engineering

School of Electrical and Electronic Engineering

A thesis submitted to the Nanyang Technological University in partial

degree to any other University or Institution.

of plagiarism and of sufficient grammatical clarity to be examined. To the best of

acknowledged in the Author Attribution Statement. I confirm that the investigations

and without prejudice.

Chapter 3 is published as X. Li, X. Zhang, and F. Lin, ‘Multi-Objective Design of Output

The contributions of the co-authors are as follows:

Chapter 4 is published as X. Li, X. Zhang, F. Lin, and F. Blaabjerg, “Artificial-Intelligence-

The contributions of the co-authors are as follows:

Chapter 5 is published as X. Li, X. Zhang, F. Lin, C. Sun, and K. Mao, ‘Artificial-

The contributions of the co-authors are as follows:

The contributions of the co-authors are as follows:

Chapter 1 Introduction ..................................................................................................1

Chapter 2 Literature Review ......................................................................................15

Chapter 4 NN-Based Automated Design for Circuit Parameters of Power

Chapter 5 Current-Stress-Minimized Triple Phase Shift Modulation Design for the

Chapter 6 XGBoost-Based Hybrid Extended Phase Shift Modulation Design for

Chapter 7 Conclusion and Future Works ...............................................................170

Author’s Publications ...................................................................................................178

Table 2.1 Applications of AI in the Design of DC-DC Converters ..................................39

Pl_dr Driving loss of switches

In this chapter, the research background is presented, including the increasing

7,000 TWh Other

5,000 TWh Wind Power

Wind Turbines Hydropower

Fuel Cell Battery Units Super Capacitor Flywheel

DC= DC= DC= DC= DC=

1.2 Circuit Design and Modulation Design of DC-DC Converters

(a) Circuit Parameter Design of DC-DC Converters

CLLC-Type Isolated DAB Converter

CLLC Resonant Tank S5 S7

Two Switches LC Filter

(b) Modulation Design of DC-DC Converters

1.3 Motivation and Objectives

Circuit Parameter Design of DC-DC Converters

(a) Heavy Manpower Burden

Modulation Design of DC-DC Converters

Low Design Accuracy:

Low Design Accuracy:

Another example is the current-stress-oriented design of triple phase shift (TPS)

Low design accuracy issue can be induced by model simplifications, mathematical

1.4 Main Contributions of This Thesis

 A multi-objective design approach via a novel coevolving-AMOSA algorithm is

 An AI-based automated design approach with the assistance of simulations, NN and

 A current-stress-optimized TPS modulation for DAB converters is automatically

1.5 Organization of This Thesis

This chapter comprehensively reviews relevant research works centered on the

DC-DC converters are high-frequency power conversion circuits which regulate DC

One-way power transfer

Fig. 2.1. Classifications of DC-DC converters.

Conventional Buck-Boost Converter Cascaded DC-DC Converter

Interleaved DC-DC Converter

Fig. 2.2. Examples of non-isolated DC-DC converters [18].

Vin Vin Lm2

Fig. 2.3. Examples of isolated DC-DC converters [18].

2.2 Circuit Parameter Design Approaches for DC-DC Converters

Circuit parameter design is an important aspect to be considered, which determines the

2.2.1 Various Design Parameters of DC-DC Converters

Design Components • Materials E.g. Si, SiC, GaN