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combined_clock(hours,minutes,seconds,daystring,stringap,sel_rt,set_rt,sel,set,h_rt,
m_rt,s_rt,ds_rt,sa_rt,clock,reset);
input clock,reset,sel_rt,set_rt,h_rt,m_rt,s_rt,ds_rt,sa_rt;
output hours,minutes,seconds,daystring,stringap,sel,set;
reg[2*8:1]stringap;
reg[3*8:1]daystring;
reg[5:0]minutes;
reg[5:0]seconds;
reg[4:0]hours;
reg sel;
reg set;
wire [4:0]h_rt;
wire [5:0]m_rt;
wire [5:0]s_rt;
wire[3*8:1]ds_rt;
wire[2*8:1]sa_rt;
wire sel_rt;
wire set_rt;
initial
begin
hours=0;
minutes=0;
seconds=0;
daystring="SUN";
stringap="AM";
end
/
***********************************************************************************
*********************/
else if (sel==0)
begin//12
if(hours==0&&minutes<=59&&seconds<=59)
begin//13
hours=hours+12;
assign stringap="AM";
end//13
if(hours<=11&&hours>=1&&minutes<=59&&seconds<=59)
begin
assign stringap="AM";
//$display("**********IN RTL FIRST ELSE 12HR hours=%0d minutes=%0d seconds=%0d
stringap=%0s",hours,minutes,seconds,stringap);
end
if(hours==12&&minutes<=59&&seconds<=59)
assign stringap="PM";
if(hours>=13&&hours<=23&&minutes<=59&&seconds<=59)
begin//14
stringap="PM";
hours=hours-12;
//$display("**********IN RTL of 12HR hours=%0d minutes=%0d seconds=%0d stringap=
%0s",hours,minutes,seconds,stringap);
end//14
assign seconds=seconds+1;
if(seconds==60)
begin//15
assign seconds=0;
assign minutes=minutes+1;
if(minutes==60)
begin//16
assign minutes=0;
assign hours=hours+1;
if(hours==12)
begin//17
if(stringap=="AM")
assign stringap="PM";
else if(stringap=="PM")
begin//18
assign stringap="AM";
if(daystring=="SUN")
assign daystring="MON";
else if(daystring=="MON")
assign daystring="TUE";
else if(daystring=="TUE")
assign daystring="WED";
else if(daystring=="WED")
assign daystring="THU";
else if(daystring=="THU")
assign daystring="FRI";
else if(daystring=="FRI")
assign daystring="SAT";
else if(daystring=="SAT")
assign daystring="SUN";
end//18
end //17
if(hours==13)
assign hours=1;
end//16
end//15
end//12
end//3
end//1
endmodule
/**********************************test
bench*******************************************************/
module testbench;
wire[4:0]hours;
wire[5:0]minutes;
wire[5:0]seconds;
wire[3*8:1]daystring;
wire[2*8:1]stringap;
wire sel;
wire
set;//hours,minutes,seconds,daystring,stringap,sel_rt,set_rt,sel,set,h_rt,m_rt,s_rt
,ds_rt,sa_rt,clock,reset);
reg clock;
reg reset;
reg [4:0]h_tb;
reg [5:0]m_tb;
reg [5:0]s_tb;
reg[3*8:1]ds_tb;
reg[2*8:1]sa_tb;
reg sel_tb;
reg set_tb;
combined_clock
dut(.set_rt(set_tb),.sel(sel),.set(set),.sel_rt(sel_tb),.clock(clock),.reset(reset)
,.hours(hours),.minutes(minutes),.seconds(seconds),.daystring(daystring),.stringap(
stringap),.h_rt(h_tb),.m_rt(m_tb),.s_rt(s_tb),.ds_rt(ds_tb),.sa_rt(sa_tb));
initial clock=0;
always #2 clock=~clock;
initial
begin
$monitor("Day=%s:Hours=%0d:Minutes=%0d:seconds=%0d
%s",daystring,hours,minutes,seconds,stringap);
end
initial
begin
reset=1;
#50
reset=0;
set_tb=1;
h_tb=13;
m_tb=0;
s_tb=0;
ds_tb="THU";
sa_tb="PM";
#100
reset=0;
sel_tb=0;
#100
reset=0;
sel_tb=1;
#10000
$finish;
end
endmodule