SEMINAR REPORT

ON

DESIGN AND SIMULATION OF SRAM USING MENTOR GRAPHICS

Bachelor of Technology
In
Electronics & Communication Engineering
RANGU SRUJALA- 20675A0411

Department of Electronics and Communication Engineering

J.B. INSTITUTE OF ENGINEERING AND TECHNOLOGY
(UGC Autonomous)
(Accredited by NBA & NAAC, Approved by AICTE & Affiliated to JNTU, Hyderabad)

Yenkapally, Moinabad Mandal, R.R. Dist., Hyderabad-500075 2022-

23

Design and Simulation of SRAM using Mentor Graphics 1

 J.B. INSTITUTE OF ENGINEERING AND TECHNOLOGY
(UGC AUTONOMOUS)
(Accredited by NBA & NAAC, approved by AICTE & Permanently Affiliated to JNTU, Hyderabad)
Yenkapally (Vi), Moinabad (M), P.O. HimayatNagar, R. R. District, Hyderabad -500 075.
Phone No: 08413 -235127 , 235053 , Fax : 08413 -235753

CERTIFICATE

This is to certify that RANGU SRUJLA bearing Roll No. 20675A0411 have submitted Seminar
Report on “DESIGN AND SIMULATION OF SRAM USING MENTOR GRAPHICS”.
This is required for the partial fulfilment of the requirements for the award of degree of
BACHELOR OF TECHNOLOGY in Electronics and Communication Engineering, Jawaharlal
Nehru Technological University, Hyderabad during the academic year 2022- 2023.

Dr. Himanshu Sharma Dr. Towheed Sultana

Associate Prof. & Coordinator Prof. & HOD,
ECE Dept. ECE Dept.

2
 J.B. INSTITUTE OF ENGINEERING AND TECHNOLOGY
(UGC AUTONOMOUS)
(Accredited by NBA & NAAC, approved by AICTE & Permanently Affiliated to JNTU, Hyderabad)
Yenkapally (Vi), Moinabad (M), P.O. HimayatNagar, R. R. District, Hyderabad -500 075.
Phone No: 08413 -235127 , 235053 , Fax: 08413 -235753

DECLARATION
I RANGU SRUJALA bearing Roll No. 20675A0411 hereby declare that the Seminar Report entitled
“DESIGN AND SIMULATION OF SRAM USING MENTOR GRAPHICS”. prepared by me is
submitted in the partial fulfilment partial fulfilment of the requirements for the award of degree of
BACHELOR OF TECHNOLOGY in Electronics and Communication Engineering, Jawaharlal Nehru
Technological University, Hyderabad during the academic year 2022- 2023.

RANGU SRUJALA (Roll No. 20675A0411)

 3

ACKNOWLEDGEMENTS
This is to acknowledgement of the intensive drive and technical competence of many individuals who
have contributed to the success of our dissertation.

We would like to sincerely thank to our internal guide, DR. HIMANSHU SHARMA,
Associate Professor who stimulated many thoughts for this project and Staff-Members of Department of
ECE for their good will gestures towards me.

We are very greatful to Dr. Towheed Sultana, HOD, ECE who has not only shown at most
patience, but fertile in suggestions, vigilant in directions of error and who have been
infinitely helpful.

We wish to express deepest gratitude and thanks to Principal Dr. P. C. Krishnamachary for his
constant support and encouragement in providing all the facilities in the college to do the project
work.

RANGU SRUJALA

Design and Simulation of SRAM using Mentor Graphics 4

 Preface

I have made this report file on the topic DESIGN AND SIMULATION OF
SRAM USING MENTOR GRAPHICS; I have tried my best to elucidate all
the relevant detail to the topic to be included in the report. While in the
beginning I have tried to give a general view about this topic.

My efforts and whole hearted Co-corporation of each and every one has ended
on a successful note. I express my sincere gratitude to who assisting me
throughout the preparation of this topic. I thank him for providing me the
reinforcement, confidence and most importantly the track for the topic
whenever I needed it.

Contents Page no
5
ABSTRACT...................................................................................................................4

CHAPTER-1 OVER VIEW OF THE PROJECT....................................................5

1.1 INTRODUCTION..............................................................................................5

1.2 PROBLEM STATEMENT................................................................................6

1.3 MOTIVATION...................................................................................................6

1.4 OBJECTIVE.......................................................................................................6

1.5 METHODOLOGY ADOPTED.........................................................................6

1.6 TOOLS REQUIRED..........................................................................................6

1.7 ORGANIZATION OF REPORT......................................................................7

CHAPTER-2 REFERENCES LITERATURE SURVEY........................................8

2.1 INTRODUCTION..............................................................................................8

2.2 GENESIS REPORT...........................................................................................8

2.3 CONCLUSION...................................................................................................9

CHAPTER-3 STATIC RANDOM ACCESS MEMORY......................................10

3.1 INTRODUCTION:...............................................................................................10

3.2 COMPLEMENTORY METAL OXIDE SEMICONDUCTOR..................10

3.3 SRAM Cell:...........................................................................................................17

Fig-3.7..................................................................................................................17

CHAPTER-4 LOW POWER SRAM CELL............................................................21

4.2 11 T STATIC RANDOM ACCESS MEMORY.............................................21

A. Read Operation..............................................................................................22

B. Write Operation.............................................................................................22

C. Hold Operation..............................................................................................23

4.3 CONCLUSION.................................................................................................24

RESULTS AND DISCUSSIONS...............................................................................25

5.1 INTRODUCTION............................................................................................25

5.2 SIMULATIONS AND RESULTS..................................................................25

CONCLUSION AND FUTURE SCOPE..................................................................30

REFERENCES...........................................................................................................31

APPENDIX PROCEDURE FOR MENTOR GRAPHICS.....................................31

Introduction.............................................................................................................31

1. Invoking Mentor Graphics............................................................................32

7.Waveform comparison........................................................................................57

7
 LIST OF FIGURES: PAGE NO
Figure 1:schematic diagram of CMOS.....................................................................10
Figure 2:Schematic diagram of combination of AND and OR gates.....................12
Figure 3:Functional diagram of OR logic gate........................................................12
Figure 4:Functional diagram of AND Logic Gate...................................................13
Figure 5:Functional diagram of NAND Logic Gate................................................14
Figure 6:Symbol of NOT gate....................................................................................15
Figure 7:Schematic diagram of 6T............................................................................17
Figure 8:Schematic diagram of 4T SRAM...............................................................18
Figure 9:schematic diagram of proposed design 11T SRAM.................................22
Figure 10:Schematic diagram of proposed design 11T SRAM using hold operation 24
Figure 11:Simulation diagram of proposed design 11T SRAM.............................26
Figure 12:Simulation Results of proposed design 11T SRAM...............................27
Figure 13:Simulation diagram of proposed design 11T SRAM during Hold Operation
......................................................................................................................................28
Figure 14:Simulation results of proposed design 11T SRAM cell during hold operation
......................................................................................................................................29
 ABSTRACT

Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary
logic '1' or '0' bit. Modified read and write circuits were proposed in this paper to address
incorrect read and write operations in conventional 6T SRAM cell design available in open
literature. Design of a new highly reliable 6T SRAM cell design is proposed with reliable read,
write operations and negative bit line voltage (NBLV). Simulations are carried out using

MENTOR GRAPHICS. SRAM cell is the key component in memories. A typical SRAM cell
uses two cross-coupled invertersforming a latch and access transistors for enabling access to
the cell during read and write operations and provide cell isolation during the not-accessed
state.

9
 CHAPTER-1 OVER VIEW OF THE PROJECT

In the chapter introduction, problem statement, motivation, objectives and goal,

methodology adopted, tools required, organization of report and conclusion were discussed.

1.1 INTRODUCTION
The rapid growth in the semiconductor device industry has lead to the development of
high performance portable systems with enhanced reliability. In such portable applications, it is
extremely important to minimize current consumption due to the limited availability of battery
power. Therefore power dissipation becomes an important design issue in VLSI circuits.
With the advent of IOT and system on chip (SOC), the demand of SRAM is increasing at
a very high rate. An SRAM based embedded cache memory typical occupies more than 50%
area of modern SOCs. With Moore’s law still holding true, the functionality of these integrated
circuits is continuously improving with time. However, power consumption continues to be a
critical factor while designing a SOC for IOT applications. A challenge is therefore put in front
of the circuit designers to come up with an ultra low power memory solution which can be used
for these SOCs. The aggressive scaling of technology node arises various issues in basic 6T
SRAM cell like write stability, read stability degradation, static power dissipation (due to
leakage currents) etc. In basic SRAM cell, the aspect ratio of pull down transistor should be
greater than access transistor for stable read operation while the aspect ratio of pull up transistor
should be less than access transistor for stable write operation. Various cell configurations are
being proposed to deal with the problem of read and write stability due to conflicting design
requirements. Separate read and write port has also been extensively explored to overcome the
problem of read and write stability but they too have some issues like bit line leakage, voltage
division etc. which eventually increases power dissipation. At the scaled technology node the
static power dissipation is mainly due to leakage current which consists of sub threshold leakage
current, gate leakage current, junction leakage current etc. Various techniques have been
discussed to decrease the overall static power dissipation, but there is a trade-off (between
stability and power dissipation) associated with these techniques. This paper proposes a multi
threshold 11T SRAM cell with a separate write and a read port to overcome the issue of
conflicting design requirements for increasing the stability of read and write. Furthermore, the
power gating technique using sleep transistors have been used in the proposed work for reducing

11
the static power dissipation. Rest of the paper is organized as follows, Section II presents the
proposed design while simulation results have been discussed in section III. Section IV
summarizes the proposed work.
1.2 PROBLEM STATEMENT
Designing the circuits for each and every operation get complicated. By implementing of
the new design circuit we can reduce problems faced by electronic devices. Now-a-days many
types of SRAM are invented. However, we are still facing problems in term having a large static
power and high dynamic power dissipation, which are in the use of high power consumption.
Hence many ideas are implementing to overcome this process.
1.3 MOTIVATION
The present implementation and motivation is relates to a 11T Static Random Access
Memory Cell. One of the major goals in modern circuit design is reduction of power
consumption. To perform all transistors in 180nm CMOS (Complementary metal oxide
semiconductor) technology by using a low power 11T Static Random Access Memory
(SRAM).We can calculate power dissipation value and propagation delay. One of the major goals
in modern circuit design is reduction of power consumption..
1.4 OBJECTIVE
The main objective is to implement the low power high stable Static Random Access
Memory (11T SRAM). While approaching for SRAM, we have shown new proposed methods
by using Multi Threshold Transistor and Read port.
1.5 METHODOLOGY ADOPTED
Power consumption and delay are the two inputs parameters. So need to design, which
take these two parameters into account. Circuits like 11T Static Random Access Memory using
hold operation in 180nm technology to reduce low power consumption and delay.
1.6 TOOLS REQUIRED
Hardware:
1. Personal computer
Software:
2. Mentor Graphics PYXIS Schematic

1.7 ORGANIZATION OF REPORT

The rest of chapters are organized as follows, chapter 2 explains about Reference
Literature survey. Chapter 3 illustrates Static Random Access Memory (SRAM). Chapter 4
Illustrates low power Static Random Access Memory. Chapter 5 illustrates results and

discussion. Chapter 6 illustrates conclusion and future scope.

 CHAPTER-2 REFERENCES LITERATURE SURVEY

2.1 INTRODUCTION
In the references literature survey the information collected about researches and
implementation carried out on the related technologies has been done. This section will highlight
the recent trends and implementation in the concerned technology.
2.2 GENESIS REPORT
Mollick, E. Established moore’s law. The seemingly unshakeable accuracy of Moore's
law - which states that the speed of computers; as measured by the number of transistors that can
be placed on a single chip, will double every year or two - has been credited with being the
engine of the electronics revolution, and is regarded as the premier example of a self-fulfilling
prophecy and technological trajectory in both the academic and popular press. Although many
factors have kept Moore's law as an industry benchmark, it is the entry of foreign competition
that seems to have played a critical role in maintaining the pace of Moore's law in the early VLSI
transition. Many different kinds of chips used many competing logic families. DRAMs and
microprocessors became critical to the semiconductor industry, yet were unknown during the
original formulation of Moore's law [1].
Pal, S., Islam, A. (2016). “Variation tolerant differential 8T SRAM Cell for low power
applications”. Low power and noise tolerant static random access memory (SRAM) cells are in
high demand today. This paper presents a stable differential SRAM cell that consumes low
power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition
of two buffer transistors, one tail transistor and one complementary word line. Due to stacking
effect, the proposed cell achieves lower power dissipation. In this paper, impact of process
parameters variations on various design metrics of the proposed cell are presented and compared
with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended
8T (SE8T) SRAM cells Impact of process variation, like threshold voltage and length, on
different design metrics of an SRAM cell like, read static noise margin (RSNM), read access
time (T RA ), and write access time (T WA ) are also presented. The proposed cell achieves
1.12×/1.43×/5.62× improvement in T RA compared to TG8T/D6T/SE8T at a penalty of
1.1×/4.88× in T WA compared to D6T/TG8T and 1.19×/1.18× in read/write power consumption
compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to
D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows
2.33x narrower spread in hold power @ V DD = 0.4 V compared to D6T SRAM cell [2].

13
 K. J. Zhang, Kun Chen, W. t. Pan and P. j. Ma, “A research of dual port SRAM cell using
8T”. High speed, low power and compatibility with standard technology Static random access
memory (SRAM) is essential for system on chip (SOC) technology. In this paper, we first present a
6T-SRAM (1WR) and two types of 8TSRAM cell (2WR 1W1R). After that how the (1W1R) cell
work with external unit is explained, and we compare the SNM sensitivity and the write/read
operations time of 1WR 1W1R cell [3].
Sridhara et al. “Microwatt embedded processor platform for medical systemonchip
applications”. Battery life specifications drive the power consumption requirements of integrated
circuits in implantable, wearable, and portable medical devices. In this paper, we present an
embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical
applications requiring microwatt power consumption. Ultra-low-power operation is achieved via
0.5-1.0 V operation, a 28 FW/bit fully differential sub-threshold 6T SRAM, a 90%-efficient DC-
DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor
workload. Using a combination of novel circuit design, system architecture, and SOC
implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure
detection is demonstrated [4].
Patel, Harsh N., Farash B. Yahya and Benton H. Calhoun. ”Optimizing SRAM bit cell
reliability and energy for IOT applications”. They compares six different 8T SRAM bit cells
targeting different design space requirements - such as reliability and low power/energy - for
Internet of Things (IOT) applications. Different bit cells leverage the varying characteristics of
high-threshold (high-VT) and standardthreshold (standard-VT) devices to affect SRAM metrics
like write margin (WM), Data Retention Voltage (DRV), Hold Static Noise Margin (HSNM),
Read Static Noise Margin (RSNM), write and read energy, standby leakage power, and
variability. The reliability for each bit cell over process (intra- and inter-die variation) and
temperature variation is also evaluated. Measured results for a commercial 130nm test chip
compare the most promising two 8T bit cell structures targeting low leakage and low energy [5].
2.3 CONCLUSION
In the chapter, reference links have been referred and the analysis of the literature survey

of the project was discussed.

CHAPTER-3 STATIC RANDOM ACCESS MEMORY

3.1 INTRODUCTION:
Static random-access memory (static RAM or SRAM) is a type of semiconductor
random-access memory (RAM) that uses bi-stable latching circuitry (flip-flop) to store each bit.
SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is
eventually lost when the memory is not powered.
The term static differentiates SRAM from DRAM (dynamic random-access memory)
which must be periodically refreshed. SRAM is faster and more expensive than DRAM; it is
typically used for CPU cache while DRAM is used for a computer's main memory.
3.2 COMPLEMENTORY METAL OXIDE SEMICONDUCTOR

Figure 1:schematic diagram of CMOS

Fig 3.1 shows Complementary metal–oxide–semiconductor (CMOS) is a technology
for constructing integrated circuits, and is a form of MOSFET (metal– oxide-semiconductor
field -effect transistor) semiconductor. CMOS technology is used in microprocessors,
microcontrollers, static RAM, and other digital logic circuits.
CMOS circuits are constructed in such a way that all P-type metal–oxide– semiconductor
(PMOS) transistors must have either an input from the voltage source or from another PMOS
transistor. Similarly, all NMOS transistors must have either an input from ground or from
another NMOS transistor. The composition of a PMOS transistor creates low resistance between
15
its source and drain contacts when a low gate voltage is applied and high resistance when a high
gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high
resistance between source and drain when a low gate voltage is applied and low resistance when
a high gate voltage is applied. CMOS accomplishes current reduction by complementing every
nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage
on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low
voltage on the gates causes the reverse. This arrangement greatly reduces power consumption
and heat generation. However, during the switching time, both MOSFETs conduct briefly as the
gate voltage goes from one state to another. This induces a brief spike in power consumption and
becomes a serious issue at high frequencies.
Static CMOS inverter. Vdd and Vss are standing for drain and source respectively. The
adjacent image shows what happens when an input is connected to both a PMOS transistor (top
of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low,
the NMOS transistor's channel is in a high resistance state. This limits the current that can flow
from Q to ground. The PMOS transistor's channel is in a low resistance state and much more
current can flow from the supply to the output.
Because the resistance between the supply voltage and Q is low, the voltage drop
between the supply voltage and Q due to a current drawn from Q is small. The output, therefore,
registers a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF
(high resistance) state so it would limit the current flowing from the positive supply to the
output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from
drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a
current drawn into Q placing Q above ground is small.
This low drop results in the output registering a low voltage.
In short, the outputs of the PMOS and NMOS transistors are complementary such that
when the input is low, the output is high, and when the input is high, the output is low. Because
of this behavior of input
and output, the CMOS
circuit's output is
the inverse of the
input.
 Fig-3.2

Figure 2:Schematic diagram of combination of AND and OR gates

More complex logic functions such as those involving AND and OR gates require
manipulating the paths between gates to represent the logic. When a path consists of two
transistors in series, both transistors must have low resistance to the corresponding supply
voltage, modeling an AND. When a path consists of two transistors in parallel, either one or both
of the transistors must have low resistance to connect the supply voltage to the output, modeling
an OR.

Figure 3:Functional diagram of OR logic gate

17
 Table 3.1:Functional Truth table for OR logic gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of
its inputs are high. A plus (+) is used to show the OR operation.

Figure 4:Functional diagram of AND Logic Gate

Table 3.2 Functional Truth Table of AND Logic Gate

The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that
this dot is sometimes omitted i.e. AB.
Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of
the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram)
will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive
path will be established between the output and Vss (ground), bringing the output low. If

Design and Simulation of SRAM Using Mentor Graphics 18

both of the A and B inputs are low, then neither of the NMOS transistors will conduct,
while both of the PMOS transistors will conduct, establishing a conductive path between
the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs
is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will,
and a conductive path will be established between the output and Vdd (voltage source),
bringing the output high. As the only configuration of the two inputs that results in a low
output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

Figure 5:Functional diagram of NAND Logic Gate

Table
3.3

Table:Functional Truth Table for NAND Logic Gate

19
 This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is an
AND gate with a small circle on the output. The small circle represents inversion.

Figure 6:Symbol of NOT gate

Table 3.4 Functional Truth Table for NOT Logic Gate
The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A, the inverted
output is known as NOT. This is also shown as A', or A with a bar over the top, as shown
at the outputs. The diagrams below show two ways that the NAND logic gate can be
configured to produce a NOT gate. It can also be done using NOR logic gates in the same
way.
An advantage of CMOS over NMOS logic is that both low-to-high and hightolow
output transitions are fast since the (PMOS) pull-up transistors have low resistance when
switched on, unlike the load resistors in NMOS logic. In addition, the output signal
swings the full voltage between the low and high rails. This strong, more nearly
symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit. The
physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type
diffusion are part of the transistors. The two smaller regions on the left are taps to prevent
latch up.

Simplified process of fabrication of a CMOS inverter on p-type substrate in semi-

conductor micro fabrication. In step 1, silicon dioxide layers are formed initially through
Design and Simulation of SRAM Using Mentor Graphics 20
thermal oxidation Note: Gate, source and drain contacts are not normally in the same
plane in real devices , and the diagram is not to scale.
This example shows a NAND logic device drawn as a physical representation as it
would be manufactured. The physical layout perspective is a "bird's eye view" of a stack
of layers. The circuit is constructed on a P-type substrate. The poly-silicon, diffusion, and
n-well are referred to as "base layers" and are actually inserted into trenches of the P-type
substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an
insulating layer between the base layers and the first layer of metal (metal1) making a
connection.
The inputs to the NAND (illustrated in green color) are in poly-silicon. The
CMOS transistors (devices) are formed by the intersection of the poly-silicon and
diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in
salmon and yellow coloring respectively). The output ("out") is connected together in
metal (illustrated in cyan coloring). Connections between metal and poly-silicon or
diffusion are made through contacts (illustrated as black squares). The physical layout
example matches the NAND logic circuit given in the previous example.
The N device is manufactured on a P-type substrate while the P device is
manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and
an N-type n-well tap is connected to VDD to prevent latch up.

3.3 SRAM Cell:

21
 Fig-3.7

figure shows a typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is
stored on four transistors (M1, M2, M3, M4) that form two cross coupled inverters. This
storage cell has two stable states which are used to denote 0 and 1. Two additional access
transistors serve to control the access to a storage cell during read and write operations. In
addition to such six-transistor (6T) SRAM, other kinds of SRAM chips use 4, 8, 10 (4T,
8T, 10T SRAM), or more transistors per bit. Four-transistor SRAM is quite common in
stand-alone SRAM devices (as opposed to SRAM used for CPU caches), implemented in
special processes with an extra layer of poly-silicon, allowing for very high-resistance
pull-up resistors. The principal drawback of using 4T SRAM is increased static power due
to the constant current flow through one of the pull-down transistors.

Design and Simulation of SRAM Using Mentor Graphics 22

Figure 8:Schematic diagram of 4T SRAM
Four transistor SRAM provides advantages in density at the cost of manufacturing
complexity. The resistors must have small dimensions and large values.
This is sometimes used to implement more than one (read and/or write) port,
which may be useful in certain types of video memory and register files implemented
with multi-ported SRAM circuitry.
Generally, the fewer transistors needed per cell, the smaller each cell can be. Since
the cost of processing a silicon water is relatively fixed, using smaller cells and so
packing more bits on one wafer reduces the cost per bit of memory.
Memory cells that use fewer than four transistors are possible – but, such 3T or 1T
cells are DRAM, not SRAM (even the so-called 1T-SRAM).
Access to the cell is enabled by the word line (WL in figure) which controls the
two access transistors M5 and M6 which, in turn, control whether the cell should be
connected to the bit lines: BL and BL. They are used to transfer data for both read and
write operations. Although it is not strictly necessary to have two bit lines, both the signal
and its inverse are typically provided in order to improve noise margins.
During read accesses, the bit lines are actively driven high and low by the
inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs – in a
DRAM, the bit line is connected to storage capacitors and charge sharing causes the bit
line to swing upwards or downwards. The symmetric structure of SRAMs also allows for
differential signaling, which makes small voltage swings more easily detectable. Another
difference with DRAM that contributes to making SRAM faster is that commercial chips
23
accept all address bits at a time. By comparison, commodity DRAMs have the address
multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package
pins in order to keep their size and cost down.
m m
The size of an SRAM with m address lines and n data lines is 2 words, or 2 × n
bits. The most common word size is 8 bits, meaning that a single byte can be read or
m
written to each of 2 different words within the SRAM chip. Several common
m
SRAM chips have 11 address lines (thus a capacity of 2 = 2,048 = 3d words) and an
8-bit word, so they are referred to as "2k × 8 SRAM".

Operation:
An SRAM cell has three different states: standby (the circuit is idle), reading (the
data has been requested) or writing (updating the contents). SRAM operating in read
mode and write modes should have "readability" and "write stability", respectively. The
three different states work as follows:
Standby:
If the word line is not asserted, the access transistors M 5 and M6 disconnect the
cell from the bit lines. The two cross-coupled inverters formed by M1 – M4 will continue
to reinforce each other as long as they are connected to the supply.
Reading:
In theory, reading only requires asserting the word line WL and reading the
SRAM cell state by a single access transistor and bit line, e.g. M 6, BL. However, bit lines
are relatively long and have large parasitic capacitance. To speed up reading, a more
complex process is used in practice: The read cycle is started by pre-charging both bit
lines BL and BL, to high (logic 1) voltage. Then asserting the word line WL enables both
the access transistors M5 and M6, which causes one bit line BL voltage to slightly drop.
Then the BL and BL lines will have a small voltage difference between them. A sense
amplifier will sense which line has the higher voltage and thus determine whether there
was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read
operation. As the NMOS is more powerful, the pulldown is easier. Therefore, bit lines are
traditionally pre-charged to high voltage. Many researchers are also trying to pre-charge
at a slightly low voltage to reduce the power consumption.
Writing:

The write cycle begins by applying the value to be written to the bit lines. If we
wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0.

Design and Simulation of SRAM Using Mentor Graphics 24

This is similar to applying a reset pulse to an SR-latch, which causes the flip flop to
change state. A 1 is written by inverting the values of the bit lines. WL is then asserted
and the value that is to be stored is latched in. This works because the bit line inputdrivers
are designed to be much stronger than the relatively weak transistors in the cell itself so
they can easily override the previous state of the cross-coupled inverters. In practice,
access NMOS transistors M5 and M6 have to be stronger than either bottom NMOS (M1,
M3) or top PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are
much weaker than NMOS when same sized. Consequently, when one transistor pair (e.g.
M3 and M4) is only slightly overridden by the write process, the opposite transistors pair
(M1 and M2) gate voltage is also changed. This means that the M1 and M2 transistors can
be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing
process.
3.4 CONCLUSION:
In the chapter topics like CMOS, Logic Gates are AND, OR, NAND and NOT, 4T
SRAM and 6T SRAM Cells has been discuss.

25
 CHAPTER-4 LOW POWER SRAM CELL

4.1 INTRODUCTION:
In the chapter, topics like 11T SRAM cell and proposed design 11T SRAM using
hold operation are discussed.
4.2 11 T STATIC RANDOM ACCESS MEMORY

Figure 9:schematic diagram of proposed design 11T SRAM

Figure 4.1 represents the circuit diagram of the proposed 11T multi threshold
SRAM cell. The latch of the proposed design is formed using cross coupled high
threshold Voltage (HVT) transistor consisting of M1, M2, M4 and M5. Low threshold
Voltage (LVT) NMOS transistor M3 and M6 act as an access transistor which is activated
by write word line (WWL). Transistor M10 and M11 act as a sleep transistor which
reduces the static power dissipation of proposed design during hold mode. The proposed
design also consist of separate read port with two HVT PMOS transistor M7 and M9 and
one LVT NMOS transistor M8 which improves the read stability of proposed design
during the read operation. Moreover, HVT PMOS M7 and M9 in the read port reduces the
static power dissipation as the high threshold voltage of PMOS device reduces the
leakage current [14]. Q and Qb is the storing node of the proposed design, write bit line
(WBL) and write bit line bar (WBLB) is the input bit lines for writing the data into the

Design and Simulation of SRAM Using Mentor Graphics 26

cell while read bit line (RBL) is used for reading the data from cell. The cell ratio which
is ratio of the width of pull down transistor to access transistor is 1.6 (128/80) whereas
2018 IEEE International Symposium on Smart Electronic Systems (ISES) (Formerly
INIS) the pull up ratio which is the ratio of the width of pull up transistor to access
transistor is 1 (80/80) for proposed design. The operations of the proposed design in
different modes are as follows.
A. Read Operation
The proposed design consists of separate read port which isolates the read path
from storing node for improving the read stability. During the read operation WWL,
WBL and WBLB are connected to ground, hence the transistors M3 and M6 goes to OFF
state. Read word line (RWL) is at Vdd and RBL is pre charged to Vdd. For read 0
operation (assuming initially the proposed design stores logic 0 at node Q and logic 1 at
node Qb) the PMOS transistor M9 is in ON state and PMOS transistor M7 is in OFF
state, hence the voltage at node A drastically increases to Vdd which turns ON the NMOS
transistor M8. Consequently the RBL start to discharge. Similarly for read 1 operation,
the logic 1 being stored at Q and 0 stored at Qb, forces transistor M9 to turn OFF and M7
to turn ON which forces the voltage at node A to fall to zero and eventually turns OFF the
transistor M8. The RBL thus retains at Vdd.
B. Write Operation
During write operation, WWL is connected to Vdd which turns ON the access
transistor M3 and M6. The access transistor M3 and M6 form a conducting path between
input bit lines (WBL and WBLB) and storing nodes. RWL and RBL are connected to
ground. For write 1 operation (assuming initially logic 0 is stored at node Q and 1 is
stored at node Qb) the WBL and WBLB is connected to Vdd and ground respectively. As
soon as the access transistor turns ON, the logic 1 is stored at node Q which indicates the
write 1 operation. Similarly for writing 0, WBLB is connected to Vdd and WBL is
connected to ground. Moreover the input of sleep transistor sleep line
(SL) is connected to Vdd and sleep line bar (SLB) is connected to ground which turns
ON the transistor M10 and M11. The transistor M11 helps in reducing the voltage at
node B which improves the stability during write mode.

C. Hold Operation

27
Figure 10:Schematic diagram of proposed design 11T SRAM using hold operation
The circuit behavior of proposed design during hold mode operation. In hold
mode the WWL, WBL and WBLB are connected to ground which turns OFF the
transistor M3 and M6 (shown by dotted in fig. 2). The RWL and RBL is also connected to
ground (which deactivates the read port), hence the leakage from read bit line gets
reduced. The data stored at node Q and Qb (assuming logic 0 is stored at Q and logic 1 is
stored at Qb) is retained at node Q and Qb during the hold mode. Furthermore as SL and
SLB are connected to ground and Vdd respectively, it turns OFF the sleep transistor M10
and M11. Hence stack is formed between internal latch and sleep transistors which has
following effects on the circuit. 1. Stack is formed between M4 and M10 which increases
the voltage at node C to some positive voltage. Thus the VDS, VGS and VBS of
transistor M4 reduced which drastically reduces the sub threshold leakage as per Equation
1. Subsequently static power dissipation due to sub threshold leakage gets reduced.
The input conditions of proposed design in different modes of operation are
presented in table 4.1

Various Read Write0 Write1 Hold

signal operation operation operation operation

WWL 0 1 1 0

Design and Simulation of SRAM Using Mentor Graphics 28

 WBL 0 0 1 0

WBLB 0 1 0 0

SL 1 1 1 0

SLB 0 0 0 1

RWL 1 0 0 0

RBL 1 0 0 0

Table 4.1 Truth table for proposed design

4.3 CONCLUSION
In the chapter topics like 11T SRAM using hold operation, complementary metal
oxide semiconductor and logic gates has been discussed.

CHAPTER-5
29
 RESULTS AND DISCUSSIONS
5.1 INTRODUCTION
In the chapter the discussion is about simulation results of the 11T Static Random

Access Memory (SRAM), power dissipation and delay.

5.2 SIMULATIONS AND RESULTS

Figure 11:Simulation diagram of proposed design 11T SRAM

The fig-5.1 shows the Simulation diagram of proposed design 11T SRAM. Where
rwl, wbl, rbl, wwl, slb, wblb, sl are the inputs and 0, 01 are the outputs. When rwl, wbl,
rbl, wwl, slb, wblb and sl are in high then all PMOS transistors are in OFF state and all
NMOS transistors are in ON state. Hence the output is high. If the inputs are in low then
all PMOS transistors are in ON state and all NMOS transistors are in OFF state. Hence
the output is low.

Design and Simulation of SRAM Using Mentor Graphics 30

 Figure 12:Simulation Results of proposed design 11T SRAM
The fig-5.2 shows the Simulation results of proposed design 11T SRAM (Static
Random Access Memory).In which V(rwl),V(wbl),V(rbl),V(wwl),V(slb), V(wblb), V(sl)
are the inputs voltages pulses of 5V given to circuit and V(0) and V(01) are the outputs.
When rbl, sl, wbl and wblb are in high then the 0 and 01 outputs are high according to
their states.

31
 Figure 13:Simulation diagram of proposed design 11T SRAM during Hold Operation
The fig-5.3 shows the Simulation diagram of proposed design 11T SRAM using
hold operation. In this diagram rbl,wbl,sl,wblb,wwl,rwl,slb are the inputs and op, op1 are
the outputs. In hold operation rwl, wbl, wwl, rwl, wblb, sl are connected to ground
directly and slb connected to Vdd then the output is low during hold0 operation. In hold1
operation sl is connected to Vdd and the remaining inputs are connected to ground then
the output is high.

Design and Simulation of SRAM Using Mentor Graphics 32

 Figure 14:Simulation results of proposed design 11T SRAM cell during hold operation
The fig-5.4 shows the simulation results of proposed design 11T SRAM cell
during hold operation. In this diagram rbl,wbl,sl,wblb,wwl,rwl,slb are the inputs and op,
op1 are the outputs. In hold operation rwl, wbl, wwl, rwl, wblb, sl are connected to
ground directly and slb connected to Vdd then the output is low during hold0 operation.
In hold1 operation sl is connected to Vdd and the remaining inputs are connected to
ground then the output is high.
5.3 Power Dissipation and Delay of 11T SRAM Cell:
From the simulation results and output waveforms of the circuit it has been
proved that power dissipation can be reduced by about 60% to 70%.furthermode,
modified 11T SRAM was implemented in Mentor Graphics 180nm technology. The
analysis has been done with respect of power dissipation and the delay parameters. From
the simulation results summarized in Table 5.1. It is clear that as compared to11T
SRAM technique, the modified version has about 70% improvement in the speed performance.
The trade-off parameter is the power consumption which has increased about 10% compared
to 11T SRAM cell.

Circuits Power dissipation Delay

33
 6T SRAM 281.19 u W 5.4 ns

11T SRAM 39.3781 u W 4.9 ns

11T SRAM using hold 1.017 n W 4.2 ns

operation

Table 5.1 Power Dissipation and Delay of 11T SRAM cell.

5.4 Conclusion:
In the chapter simulation results, power dissipation and delay of 11T Static
Random Access Memory cells has been discussed.

Design and Simulation of SRAM Using Mentor Graphics 34

 CHAPTER-6
CONCLUSION AND FUTURE SCOPE
6.1 Conclusion:
The 11T Static Random Access Memory circuits are designed using Mentor
Graphics. The delay and power dissipation of the modified 11T SRAM Cell has been
compared with 11T SRAM using hold operation. The power and dissipation by the
modified 11T SRAM circuits still remain low with the improvement of delay by about
70% reduction. Hence our proposed circuits improves delay at the cost of power savings.
6.2 Future Scope:
The design of Low Power SRAM can be designed using 90nm, 45nm technology
which can further reduce the power consumption.

REFERENCES

35
 [1]. Patel, Harsh N., Farah B. Yahya, and Benton H. Calhoun. “Optimizing
SRAM bit cell reliability and energy for IOT applications”. In Quality Electronic
Design (ISQED), 17th International Symposium on, pp. 12-17. IEEE, 2016.

[2]. Sridhara et al. “Microwatt embedded processor platform for medical systemon-
chip applications”. In VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp.
15-16. IEEE, 2010.

[3]. Mollick, E. Establishing Moore’s law. IEEE Annals of the History of

Computing, 28(3), 62-75, 2006.

[4]. Pal, S., Islam, A. (2016). “Variation tolerant differential 8T SRAM cell for
ultralow power applications”, IEEE transactions on computer-aided design of
integrated circuits and systems, 549-558, April 2016

[5]. K. j. Zhang, Kun Chen, W. t. Pan and P. j. Ma, “A research of dual-port

SRAM cell using 8T”, 2010 10th IEEE International Conference on Solid-State and
Integrated Circuit Technology, Shanghai, pp. 2040-2042, 2010.

APPENDIX PROCEDURE FOR MENTOR GRAPHICS

Introduction
This document gives a rough overview of how to design & simulate things with
Mentor graphics Tools. There are six basic steps:

1. Invoking Mentor Graphics

2. Creating Library & Cell

3. Creating Schematic

4. Generating Symbol

5. Creating Test bench

6. Simulating the Schematic

7. Waveform Comparison
1. Invoking Mentor Graphics

First of all we will open the linex os then the view will be Right click in the linex
window Desktop and click on open in terminal

Design and Simulation of SRAM Using Mentor Graphics 36

 Type csh and press enter.
Type source /home/softwares/cshrc/cshrc130.cshrc and press enter.

Type cd /home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP and press enter then

it will enter to the PYSIS_SPT_HEP folder.
Type. /pyxismgr and press enter then pyxis project manager window will be invoked as
shown below..

Where the project navigator windows is shown then click on the file To create a new
project click on File → new project which invokes the new project window as shown

37
 Browse on the folder and specify the project path and the file name is user
defined and click on OK.

After libraries have to be added to the project. In order to add the technology files
browse on the folder Browse the folder to
home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP/ic_reflibs/tech_libs and
Select the generic13 file click on OK.

Design and Simulation of SRAM Using Mentor Graphics 38

 Again click on OK then manage external/logic libraries window will pop up as
Shown. Click on the Add Standard Libra

Then the libraries will be added up as shown below and click on OK

39
 Then the pyxis project manager window will be shown where the technology libraries
are added to the project and are placed below the project name

2. Creating Library & Cell:

To create a library right click on the project name and select new library Or click on the
icon on the icon bar

Then a new library window will pop up asking for the library name. Then name the
Library and click on OK.

To create a cell right click on the library and select new cell Or click on the icon on the
icon bar .

Design and Simulation of SRAM Using Mentor Graphics 40

Then a new cell window will pop up asking for the cell name. Then name the Cell
and click on OK.

To create a schematic right click on the and select new schematic or click on the icon
on the icon bar

Then a new schematic window will pop up asking for the schematic name. Then name
the schematic and click on OK

Now name the schematic and click on OK which in turn leads to the pyxis schematic
editor window as shown

41
3. Creating Schematic:

In this section you will become familiar with placing primitive analog devices for an
inverter. You’ll learn how to:

• Place primitives on the schematic

• select and manipulate devices

• customizing hotkeys for placing devices

• Route devices

• edit device parameter values

• Name instances

• check and save the schematic

• create upper hierarchical symbols

• create test bench

• simulate using Eldo

• view results.

• From the left icon bar press

Design and Simulation of SRAM Using Mentor Graphics 42

Then a file browser which contains entire libraries will pop up as shown.

Next click on the double click on generic13 in the library list

43
 And then follow the path to select pmos from
$generic13/symbols/pmos as shown

Select the pmos and click on OK to place the pmos on the workspace as shown.

Then change the width and length of the pmos device can change by using object
Editor.

Design and Simulation of SRAM Using Mentor Graphics 44

45
Design and Simulation of SRAM Using Mentor Graphics 46
 To select the Vdd and ground from the generic lib or click on the library in the layer
palatte window then layer palatte will be shown as ic library window. Then select
generic library and place Vdd and ground .

After selecting the

generic lib we use the Vdd and ground to pick and place in the required locations.

47
 Give the connects in between the Vdd to pmos and ground to nmos and both pmos &
nmos gates and, source and drain of p & n mos devices

Place in IN and OUT ports in a similar way as above from the generic library or click
on the add ports icon in the left icon bar and connect the circuit.

Design and Simulation of SRAM Using Mentor Graphics 48

To change the name, enter the name in the field given for the net name and press enter.

Then the schematic will be as shown.

49
 After completing the inverter we have to save and check it.

4. Generating Symbol:

To generate a symbol select Add in the menu bar and then select generate
Symbol from pull down menu bar

Design and Simulation of SRAM Using Mentor Graphics 50

Add→ generate symbol

A generate symbol will pop up as shown

Then activates symbol, replace existing and choose shape and click on the customize
pinlist and click on OK symbol will be generate.

51
Design and Simulation of SRAM Using Mentor Graphics 52
53
 After that click on to chick and save

The chick and save is an impotence to shown the result to an window which shows the
error report where the errors and warnings in the symbol can be seen
5. Creating Test bench:

To create a test bench close the pyxis schematic and symbol windows and go back to
pyxis project manager window. In the project manger window to create new cell right
click on the manual library below the project name and select new cell or select the

library and click on the icon in the icon bar.

Design and Simulation of SRAM Using Mentor Graphics 54
 Then a new cell window will pop up asking for the cell name in which give the cell
name and click OK Here the test bench cell name has been specified as inv_tb.

Right click on the test bench cell and select new schematic which in turn opens pyxis
Schematic editor window.

Now instantiate the new inverter symbol by selecting Add > Instance from the Left
icon Palette or pressing the hot key i. Select the Symbol view of the inverter cell from
the inv cell of the manual library
Place the symbol on the work space as shown

55
 Add the IN and OUT net as before by selecting the hot key i. Name the nets with hot
key “ q”.
Add a DC motor

voltage source dc_v_ source, from the MGC_IC_SOURCES_LIB. Change the value of
the DC property to be 1.2V. Add PULSE voltage source pulse_v_source and change the
value of the pulse_value property to be 1.2V change also the delay to
be 0S.

Add Ground ports in a similar fashion. Finally the circuit looks like the following

in the icon bar

Design and Simulation of SRAM Using Mentor Graphics 56

 This will result to an window which shows the error report where the errors and
warnings in the symbol can be seen.

6. Simulating the Schematic:

After chick and save the schematic test bench then run simulation from this icon
window will be popup in that select New Configuration

57
 Then entering simulation mode

In the New

Design and Simulation of SRAM Using Mentor Graphics 58

Go for selecting AC, DC, TRAN then setup simulation window will be open.

59
 After appearing setup window select To set up analysis select analysis in the simulation
panel and in the analysis set up select the required analysis and set the values of the
analysis in the beside window as shown above

Here I have selected the DC analysis with the start time as 0ns,stop time=5 ns and print
time step=0.1ns as shown . After specifying the values click on apply

Design and Simulation of SRAM Using Mentor Graphics 60

Here I have selected the transient analysis with the stop time=1000ns After specifying
the values click on apply .

Select the Edit Probes in the setup simulation panel

61
 Go back to the inverter schematic test bench and select the IN, OUT and come back to
the setup simulation .

In the setup simulation window, set the analysis to both DC and Tran, and Task to
plot and type to voltage, click Add button then the port will be added to the waveform
as shown.

Design and Simulation of SRAM Using Mentor Graphics 62

After adding the analysis, eldo models and probing waveforms minimize the setup

Simulation window and run the simulator. To run the simulation select from

the left icon palette or select simulate-> run simulation

7.Waveform comparison
View the simulation results by selecting the plot results from latest run icon from the
left icon palatte. This will open EZ Wave for you with the output waveforms. This is
how the waveforms look like after zooming

63
 EZ
wave
12.1

Click on Measurement tool

Design and Simulation of SRAM Using Mentor Graphics 64

production window popup to the view of waveform for IN & OUT in the icon bar
which opens up the

measurement tool window where we can measure the different properties of your

waveforms

Save these waveforms as an idle.

65