Unit 2

Computer Arithmetic
 Computer Arithmetic
Objectives:
• To understand different data/information
representation methods.

• To understand formats of instruction and data types.

• To understand arithmetic algorithms and circuits needed to

process numerical data.
 Information Representation:
• Information is represented in a computer by means of
binary sequences which are organized into words.

• Information handled by computer is instruction and data.

• Word Length:
• A word --is a unit of information of some fixed length n.
– n bit word allows up to 2n different items to be represented .
– e.g. with n=4, we can encode the 10 decimal digits as-
0=0000 1=0001 2=0010 3=0011 4=0010 5=0101 6=0110
7=0111 8=1000 9=1001

• It may be viewed as a sequence of binary coded characters.

– Common CPU word sizes are multiples of 8,16,32,64 bit words.
 Information

Data
Instruction
(operands)

Numbers Non-
numerical
(Numerical) data (string)

Floating
Fixed Point
Point

Binary
Decimal Binary Decimal
(0 or 1)

fig. Information Types

 Data representation –Data Storage Order:
– Bit (1 or 0)
– Nibble (4 bit)
– Byte (8 bit)
– Half word(16bit)
– Word(32 bit)
– Double word(64 bit)
• Data representation is the way in which bits of word are
indexed.
• Bits are in increasing order from right to left.

Byte 3 Byte 2 Byte 1 Byte 0

31 23 15 7 0
Most Least
Significant Significant
bit bit

Fig Indexing Convention for the bits and bytes of a word

 Data Storage Order:
• Big endian byte: It is named because MS Byte of the word is assigned
to lowest address and LS Byte of the word is assigned to highest
address.

W0,W1………Wm= B0,3,B0,2,B0,1,B0,0, B1,3,B1,2,B1,1,B1,0, ………. Bm,3,Bm,2,Bm,1,Bm,0

Word 0 Word 1 Word m

e.g. Mem. address=C050, at C050=0x11223344

Mem. C053 C052 C051 C050 CO50 11(MSB)
Address
Storage order Byte 0= 44 Byte 1=33 Byte 2=22 Byte 3=11 CO51 22

CO52 33

CO53 44(LSB)
Note: Byte 0,3 indicates MS byte of the W0
Byte 0,0 indicates LS byte of the W0
 Data Storage Order:
• Little endian byte:
– It is named because LS Byte of the word is assigned to lowest
address and MS Byte of the word is assigned to higher address.

W0,W1………Wm= B0,0,B0,1,B0,2,B0,3, B1,0,B1,1,B1,2,B1,3, ………. Bm,0,Bm,1,Bm,2,Bm,3

Word 0 Word 1 Word m

e.g. Mem. address=C050, at C050=0x11223344

CO50 44(LSB)
Mem. Address C053 C052 C051 C050
Storage order
CO51 33
Byte 3= 11 Byte 2=22 Byte 1=33 Byte 0=44
CO52 22

word CO53 11(MSB)

• While selecting a number representation ,
following factors should be taken into account:

– Number types to be represented

– The range of values
– Precision of the numbers
– Cost of hardware required to store and process
the numbers
 Representation of numbers
• Fixed point numbers
– binary
– Signed and Unsigned integer
• Signed integer--- 1’s and 2’s complement
representation
– Decimal
– Hexadecimal
• Floating point numbers
Fixed point numbers

• Fixed point
– has a fixed number of digits .
– Allow a limited range of values

• Binary numbers:
 Binary numbers:
• Is a positional weighted system
• Base is 2
• e.g.1011.101

• Decimal equivalent of (1011.101)2

1 0 1 1.1 0 1

1 23  0  2 2  1 21  1 2 0  1 2 1  0  2 2  1 2 3

8+0+2+1+0.5+0+0.125 = (11.625)10
Signed numbers:
Sign Magnitude

Two ways of representing signed numbers:

1. Signed magnitude form
• if sign bit is 0 , the number is positive
• if sign bit is 1 , the number is negative
e.g. +75=01001011 while -75=11001011 (8 bit signed representation)
• +6=0110 while -6 =1110 (4 bit signed representation)

2. Complement form (1’s or 2’s)- 2’s complement method is used only to

represent negative numbers
1. If the number is positive , the magnitude is represented in its true binary form
and 0 is placed in front of the MSB
2. If the number is negative , the magnitude is represented in 2’s complement
and sign bit 1 is placed in front of the MSB
e.g. +75 = 01001011
-75 = 1’s complement form= 10110100
+ 1
-------------------------------
2’s complement form(-75)= 10110101
Advantage:
subtraction can be performed by logical complementation and addition
only.
• Hexadecimal no system
– Positional weighted system
– Base is 16
– 16 independent symbols from 0…………9,A,B,C,D,E,F
– Helpful to represent long binary numbers
 Floating point:
• The floating-point representation covers a wider range of values
compared to a fixed-point representation.

• Why floating point numbers?

– The Range of numbers represented by fixed point numbers is
in-sufficient for some complex(scientific) computations where
very large or very small numbers are encountered.
– Given a fixed number of digits, there may be a loss of
precision.
 Floating point numbers:
• Following information represents a floating point number:
– sign of the number, mantissa(M) , base(B --2 or 10) and
exponent(E) as shown below---

Basic format:
– Structure of floating point (Real ) number is as follows—
–
1.0 x 1018
1.0 x 1018, M x BE
Exponent
M=1.0
Mantissa
E=18
Base B=10

• Only mantissa and exponent are stored. The base is implied(known already)
 Floating point numbers:
• The same floating point no can be represented in
more than one way.
– e.g.
1.0 x 1018 can be represented as---
0.1 x 1019
1000000 x 1012
0.000001 x 1024

• Normalization:
– A number with no leading 0’s is called a Normalized Number.
– i.e. putting decimal(radix) point after first nonzero digit .
1.0 x 1018 ----unique normalized form
• Biasing:
• In floating-point arithmetic, a biased exponent is the result of
adding some constant (called the bias) to the exponent
chosen to make the range of the exponent nonnegative.

• A bias of (2n-1 – 1), where n is no of bits used in exponent, is

added to the exponent (e) to get biased exponent (E). So, the
biased exponent (E) of single precision number can be
obtained as
•
Biased exponent(E)= actual exponent + bias
E = e + 127

• The range of exponent in single precision format is -128 to

+127.
– If n=8 bits then bias value =28-1-1 =127
 IEEE 754 floating point format
• Floating point number formats varies from one computer to another making it
difficult to transport the programs between different computers.

• To deal with this problem, IEEE has sponsored a standard for 32bit and 64 bit
floating point numbers known as IEEE754 standard.

• IEEE floating point numbers have 3 basic components

– Sign
– Exponent
– Mantissa (fraction part of floating point number )

Sign Exponent Mantissa

IEEE 754 floating point format

S Sign bit If S=0 -denotes a positive number

If S=1 -denotes a negative number
E Exponent • It is 8 bit exponent field with bias value =127

M Mantissa It is composed of fraction part of floating point number

The real number N is given by----

N=(-1)S 2E-127(1.M) Provided that 0<E<255
The real number N is given by----
N=(-1)S 2E-1023(1.M) Provided that 0<E<2047
• Conversion- Decimal to IEEE 754 single precision floating
point format.
• Steps:
1. Check sign bit.
2. Represent given no into binary
3. Shift radix point towards the first non zero digit. i.e. normalize
the number
4. Calculate the biased exponent by E=e+127 (for single precision) and
E=e+1023 (for double precision)
5. Convert this exponent to binary.
6. Represent it in sign, exponent and mantissa of IEEE 754 format

Sign Exponent Fraction Bias

Single Precision (32 bit) 1 bit 8 bit 23 bit 127
Double Precision (64 bit 1 bit 11 bit 52 bit 1023
• convert (-2.7)10 to IEEE 754 single precision and double precision
floating point format.
1. Sign is -ve, sign bit =1
2. 2.7= (10.10110011)2
3. Normalize the no by Shifting decimal point towards first nonzero digit.
2.7=1.010110011x21
4. compute Biased exponent by –
biased exponent =actual exponent + bias value
E=e+127
Therefore E=1+127=(128)10= (10000000)2
5. Represent in IEEE 754 single precision format (32 bit format)

S Exponent Mantissa
1 10000000 (8 bit)=0xC02CC
010110011……………….00(23 bit)
For 64 bit format

Biased exponent E=1+1023=(1024)10= (10000000000)2

Represent in IEEE 754 64 bit format

S Exponent Mantissa
1 10000000000 (11 bit) 010110011000……………….00 (52 bit)
• e.g Convert –(105.625) to IEEE 754, single precision and double
precision floating point format
1. Sign= -ve, S=1;
2. (105.625)10= (1101001.101)2
3. Shift decimal point to left by 6 bit (first nonzero digit)
105.625=1.101001101x26
4. Biased exponent E=e+127 =6+127=(133)10= (10000101)2
5. Represent in IEEE 754 ,32 bit format

S Exponent Mantissa
1 10000101 (8 bit) 101001101……………….00(23 bit)

= 0xC2D3400
 IEEE754 to decimal conversion:
convert following IEEE 754 floating point format to
decimal.
S Exponent Mantissa
1 10000000 (8 bit) 010110011……………….00(23 bit)

Sign=-ve =1, Exponent(E) = 10000000=128

N=(-1)S 2E-127(1.M)
=(-1)1 2128-127(1.010110011)
N= -(1.010110011)x21
= -10.10110011x20 ----shift decimal pt towards right by 1 bit position.
N=-2.699= -2.7
• S Exponent Mantissa
1 10000101 (8 bit) 101001101……………….00(23 bit)

Sign (s)= -ve= 1, Exponent (E)= 10000101=133

N=(-1)S 2E-127(1.M)
= (-1)1 2133-127(1.101001101)
N= -(1.101001101) x26
= -(1101001.101)x20 ---shift decimal pt towards right by 6 bit position.
N = -(105.625)10
• Exercise:
Convert –(105.625) in IEEE 754 64 bit floating point
format.

1. convert +85.125 and -176.375 in single precision

(32 bit format)and double precision(64 bit
format) floating point format.
2. convert–0.75 and -1.5 in single precision and
double precision floating point format
 Interpretation of FP number

• NaN: If the result of floating point operation is

not a valid FP number then code NaN is used.
 e.g. sq. root of a negative number.

• Overflow: Overflow occurs when numbers exceed the maximum

value that can be represented in the chosen numeric
representation
• Underflow: Underflow occurs when small nonzero values
(positive or negative) become too small.
• Normalized form :
if 0<E<255 then N=(-1)S 2E-127(1.M)
 Fixed point arithmetic:
Design of circuits to implement arithmetic
operations for fixed point numbers---addition,
subtraction, multiplication and division

1. Serial adder
2. Basic adders:
– Half adders:
– Full Adder
– Subtractor
 .
Serial adder
• Is a circuit used for adding n bit
binary numbers.

• It is a least expensive circuit.

• It adds the number bit by bit so

requires n clock cycles.

• It consists of full adders and flip-flop to

store Ci

• One Sum bit is generated in each clk

cycle and carry is computed and stored
.
for the use during next clk cycle. Fig A Serial binary adder
 Half Adder:
Block Diagram:

Truth Table:
A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Circuit diagram:
 Full Adder:
Block Diagram:

Truth Table:
Carry
A B Cin Sum(S)
(Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S=ABCin
Circuit diagram:
 Parallel adders:
• Circuits that adds all the bits of two n-
bit numbers as well as Cin(carry) in one
clock cycle are called n–bit parallel
adders.

• Each one bit adder stage supplies a

carry bit on its left.

• Initially Cin=0

• The carry signal propagates through

the adder from right to left so the
name “Ripple carry adder.”

• Disadvantages:
– Amount of hardware increases
linearly with n.
4 bit 2’s complement adder-subtractor
 High speed adder:
• Why to design fast adders:
– To reduce time required to form carry signals.

• Carry lookahead adder:

– Compute a carry signal by stage directly from carry like signals obtained
from all the preceding stages rather than waiting for normal carries to
ripple from one stage to next stage. Adders using this principle are
called carry lookahead adders.

– A carry lookahead adder reduces the propagation delay by introducing

more complex hardware.

– n-bit carry lookahead adder is formed from n stages.

 High speed adder:
– In n-bit carry lookahead adder, carry out line is
replaced by two auxiliary signals called gi (generate
)and Pi (Propagate) and defined by-----
gi (generate) = Ai Bi
pi (Propagate) = Ai +Bi

stage i generates a carry 1 ---- if Ai Bi =1

stage i propagate a carry ci to ci+1 ---- if Ai +Bi =1

Equation denoting a carry Ci = Ai Bi + Ai cin + Bi cin

= gi + pi cin ---------(1)
C1=g0+p0Cin
carries in a four stage carry look ahead adder are—

Fig. 4 bit carry lookahead adder

 Multiplication:
• Multiplication is implemented by some form
repeated addition.

e.g. Y=Multiplicand
X= Multiplier
• To compute Y x X is to add the multiplicand Y to
itself X(multiplier) times.

• It is implemented by multiplying Y by X, k bits at a

time and adding the resulting terms.
 Multiplication:
• 2’s complement multiplication
– Negate all negative operands at the beginning
– Perform unsigned multiplication on the resulting (positive)
numbers
– Then negate the result if necessary.

• Algorithms for 2’s complement multiplication

– Robertson multiplication (shift and add method)
– Booths multiplication

– Input for both algorithm:

Multiplier(X)= 10110011 , Multiplicand (Y)= 11010101
Multiplier= 10110011 (x7……………..x0)
01001100
+ 1
01001101---- 2’s complement of multiplier

Multiplicand= 11010101 (y7……………..y0)

00101010
+ 1
00101011 ---2’s complement of multiplicand

(00101011)2 x (01001101)2= (000110011101111)2

 Robertson multiplication algorithm
• Step1: initialize F=0,A=00000000,Q=10110011, M=11010101,
count=0

• Step2: add A=A+M*Q[0] and F=M[7] and Q[0]or F

• Step3: Right shift F.A.Q and count=count+1

• Step4: if count≠7 then go to step2

• Step5: subtract A=A-M*Q[0], set Q[0]=0

Fig. Illustration of
Robertson
multiplication
algorithm
• HDL Code(Hardware Description Language) for Robertson
multiplication algorithm
 Booth’s Algorithm:
• It employs both addition and subtraction, but
treats positive and negative numbers uniformly.
– i.e. no special actions are required for negative
numbers.
• It is extended to speed up the multiplication
process.
 Booth’s multiplication Algorithm steps:

• Step1: initialize A=00000000,Q=10110011, M=11010101,

count=0
• Step 2: set Q[-1]=0 , after appending Q[-1]=0, Q= 101100110
• Step 3: perform addition or subtraction by scanning Q[0]Q[-1] bits
Q[0] Q[-1] Operation
performed
0 0 Skip +/-
0 1 A=A+M
1 0 A=A-M
1 1 Skip +/-

• Step 4: if count=7, then goto step 7

• Step 5: perform right shift by one bit and set A[7]=A[7]
• Step 6: Count =count +1, goto step3
• Step 7: set Q[0]=0, output=A, output=Q
2’s complement multiplier: Booth’s Algorithm
HDL code: Booth’s multiplication Algorithm
• HDL:-
– A Hardware Description Language (HDL) is a
specialized computer language used to describe the
structure and behavior of electronic circuits, and most
commonly, digital logic circuits.

• It enables a precise, formal description of an electronic circuit

that allows for the automated analysis and simulation of an
electronic circuit
• Datapath:
– Is a collection of functional units such as arithmetic
logic unit or multipliers that performs data
processing operation , registers and buses along
with control unit.
– In short it performs all required operations.
2’s complement multiplier: