Title of the Course: COMPUTER ORGANIZATION AND ARCHITECTURE

Course Code:18EC35
Semester: 3rd ,B.E
Department: Electronics and Communication
Name and designation of the faculty:Mangala S Jolad,Asst Prof

1
 MODULE 1
Basic Structure of
Computers
(UNIT-2)
2
Machine Instructions and Programs

3
4
5
6
7
Hexadecimal to Binary Conversion
•Translate every hexadecimal digit into its 4-bit binary
equivalent.
•Examples:
(3A5)16 =(0011 1010 0101)2
(12.3D)16 = (0001 0010 . 0011 1101)2
(1.8)16 = (0001 . 1000)2

8
How are Hexadecimal Numbers Written?
•Using the suffix “H” or using the prefix “0x”.
•Examples:
- ADDI R1,2AH // Add the hex number 2A to register R1
- 0x2AB4 // The 16-bit number 0010 1010 1011 0100
- 0xFFFFFFFF // The 32-bit number for the all-1 string

9
Unsigned Binary Numbers
•An n-bit binary number can have 2n distinct combinations.
– For example, for n=3, the 8 distinct combinations are:
000, 001, 010, 011, 100, 101, 110, 111
(0 to 23-1 = 7 in decimal).
Number of bits (n) Range of Numbers

8 0 to 28-1 (255)

16 0 to 216-1 (65535)

32 13
0 to 232-1 (4294967295)

64 0 to 264-1
10
•An n-bit binary integer:
b
n-1bn-2 … b2b1b0
•Equivalent unsigned decimal value:
D = bn-12n-1 + bn-22n-2 + … + b222 + b121 + b020

•Each digit position has a weight that is some power of 2.

11
Signed Integer Representation:

Many of the numerical data items that are used in a program

are signed (positive or negative).

Question:: How to represent sign?

Three possible approaches:

a) Sign-magnitude representation
b) One’s complement representation
c) Two’s complement representation

12
a) Sign-magnitude Representation
 For an n-bit number representation:
 The most significant bit (MSB) indicates sign (0: positive, 1:
negative).
 The remaining (n-1) bits represent the magnitude of the number.
 Range of numbers: – (2n-1 – 1) to + (2n-1 – 1)

 A problem: Two defferent representations for zero.

 +0: 0 00..000 and -0: 1 00..000

13
b) Ones Complement Representation
 Basic idea:
 Positive numbers are represented exactly as in sign-magnitude
form.
 Negative numbers are represented in 1’s complement form.
 How to compute the 1’s complement of a number?
 Complement every bit of the number (1->0 and 0->1).
 MSB will indicate the sign of the number (0: positive, 1: negative).

14
15
 Range of numbers that can be represented in 1’s complement:
Maximum :: + (2n-1 – 1)
Minimum :: - (2n-1 – 1)
 A problem:
Two different representations of zero.
+0 --> 0 000….0
-0 --> 1 111….1
 Advantage of 1’s complement representation:
 Subtraction can be done using addition.
 Leads to substantial saving in circuitry.

16
 c) Twos Complement Representation
 Basic idea:
 Positive numbers are represented exactly as in sign-magnitude form.
 Negative numbers are represented in 2’s complement form.
 How to compute the 2’s complement of a number?
 Complement every bit of the number (1 -> 0 and 0 -> 1 ), and then
add one to the resulting number.
 MSB will indicate the sign of the number (0: positive, 1: negative).

17
 To find the representation of, say, -4, first note that
+4 = 0100
-4 = 2’s complement of 0100 = 1011 + 1
= 1100

18
 Range of numbers that can be represented in 2’s
complement:
Maximum :: + (2n-1 – 1)
Minimum :: - 2n-1

Advantage of 2’s complement representation:

Unique representation of zero.
Subtraction can be done using addition.
Leads to substantial saving in circuitry.
Almost all computers today use 2’s complement
representation for storing negative numbers.

19
 Some other features of 2’s complement representation
a)Weighted number representation, with the MSB having weight -2n-1.

b) Shift left by k positions with zero padding multiplies the number by 2k.

 11100011 = -29 :: Shift left by 2 :: 10001100 = -116

 00010011 = +19 :: Shift left by 2 :: 01001100 = +76

20
c) Shift right by k positions with sign bit padding divides the number

00010110 = +22 :: Shift right by 2 :: 00000101 =

11100100 = -28 :: Shift right by 2 :: 11111001 =
d) The sign bit can be copied as many times as required in the beginning
to extend the size of the number (called sign extension).

21
Addition of Positive numbers

The sum of 1 and 1 requires the 2-bit vector 10 to represent the value
2.
The sum is 0 and the carry-out is 1.
In order to add multiple-bit numbers, we use a method analogous to that
used for manual computation with decimal numbers.
 We add bit pairs starting from the low-order (right) and of the bit vectors,
propagating carries toward the high-order (left) end.
22
Memory locations and addresses
 Memory consists of many millions of storage cells (flip-flops).
Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).
Each group of n bits is referred to as a word of information, and n is called
the word length.
The word length can vary from 8 to 64 bits.
A unit of 8 bits is called a byte.
Accessing the memory to store or retrieve a single item of information
(word/byte) requires unique addresses for each item location. (It is
customary to use numbers from 0 through 2k-1 as the addresses of successive-
locations in the memory).

23
Memory locations and addresses contd..
 If 2k = no. of addressable locations;
Then 2k addresses constitute the address-space of the computer.
For example, a 24-bit address generates an address-space of 2 24 locations (16
MB).

24
Memory locations and addresses contd..
BYTE-ADDRESSABILITY
In byte-addressable memory, successive addresses refer to successive byte locations
in the memory.
Byte locations have addresses 0, 1, 2. . . . .
If the word-length is 32 bits, successive words are located at addresses 0, 4, 8. . with
each word having 4 bytes.

25
Memory locations and addresses contd..
BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS
There are two ways in which byte-addresses are arranged (Figure 2.3).
Big-Endian: Lower byte-addresses are used for the more significant bytes of the
word.
Little-Endian: Lower byte-addresses are used for the less significant bytes of the
word
 In both cases, byte-addresses 0, 4, 8. . . . . are taken as the addresses of successive
words in the memory.

26
Memory locations and addresses contd..

Consider a 32-bit integer,

Hex: 0x12345678 which consists of 4 bytes: 12, 34, 56, and 78.
Hence this integer will occupy 4 bytes in memory.
Assume, we store it at memory address starting from 1000.
On little-endian and Big-endian, memory will look like

27
Memory locations and addresses contd..

WORD ALIGNMENT

Words are said to be Aligned in memory if they begin at a byte-address that

is a
multiple of the number of bytes in a word.
For example,
 If the word length is 16(2 bytes), aligned words begin at byte-addresses 0,
2, 4 . .
 If the word length is 64(8 bytes), aligned words begin at byte-addresses 0,
8, 16 .
Words are said to have Unaligned Addresses, if they begin at an arbitrary
byte- address.

28
Memory locations and addresses contd..

ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS

A number usually occupies one word.

It can be accessed in the memory by specifying its word address.
Individual characters can be accessed by their byte-address.
There are two ways to indicate the length of the string:
A special control character with the meaning "end of string" can be used as
the last character in the string.
A separate memory word location or register can contain a number indicating
the length of the string in bytes.

29
Memory locations and addresses contd..

MEMORY OPERATIONS

Two memory operations are: Load (Read/Fetch) & Store (Write).

The Load operation transfers a copy of the contents of a specific memory-
location to the processor. The memory contents remain unchanged.
Steps for Load operation:
Processor sends the address of the desired location to the memory.
Processor issues „read‟ signal to memory to fetch the data.
Memory reads the data stored at that address.
Memory sends the read data to the processor.

30
Memory locations and addresses contd..

MEMORY OPERATIONS

The Store operation transfers the information from the register to the
specified memory-location.
This will destroy the original contents of that memory-location.
Steps for Store operation are:
Processor sends the address of the memory-location where it wants to store
data.
Processor issues „write‟ signal to memory to store the data.
Content of register(MDR) is written into the specified memory-location.

31
Memory locations and addresses contd..

INSTRUCTIONS & INSTRUCTION SEQUENCING

A computer must have instructions capable of performing 4 types of operations:

1. Data transfers between the memory and the register

(MOV, PUSH, POP, XCHG).
2. Arithmetic and logic operations on data
(ADD, SUB, MUL, DIV, AND, OR, NOT).
3. Program sequencing and control (CALL.RET,
LOOP, INT).
4. I/0 transfers
32
(IN, OUT).
1. REGISTER TRANSFER NOTATION:-
Transfer of information from one location in the computer to another.
Possible locations involved in such transfers are
• memory locations
• processor registers
• registers in the I/O subsystem.
Example, names for the addresses of memory locations may be LOC, PLACE, A, VAR2
 processor registers names may be R0, R5
 I/O register names may be DATAIN, OUTSTATUS
 The contents of a location are denoted by placing square brackets around the name
of the location. R1 <- [LOC]
 Means that the contents of memory location LOC are transferred into processor
register R1. R3 <- [R1] + [R2]
 Means that the operation that adds the contents of registers R1 and R2, and then
places their sum into register R3.
This type of notation is known as Register Transfer Notation (RTN). 33
2. ASSEMBLY LANGUAGE NOTATION:-
For example, an instruction that transfer data from memory location LOC to
processor register R1, is specified by the statement
Move LOC, R1
The contents of LOC are unchanged by the execution of this instruction, but the old
contents of register R1 are overwritten.

The second example of adding two numbers contained in processor registers R1 and
R2 and placing their sum in R3 can be specified by the assembly language statement
Add R1, R2, R3

3.BASIC INSTRUCTIONS:-
The statement C=A+B
In a high-level language program is a command to the computer to add the current
values of the two variables called A and B, and to assign the sum to a third variable, C.
The contents of these locations represent the values of the three variables. Hence,
the above high-level language statement requires the action. C <- [A] + [B]

34
The three-address instruction can be represented symbolically as
 Add A, B, C
Operands A and B are called the source operands, C is called the destination
operand, and Add is the operation to be performed on the operands.
A general instruction of this type has the format.
 Operation Source1, Source 2, Destination
 above instruction can be replaced by two address instructions as
MOVE B,C
ADD A,C
 Instruction with only one operand
ADD A
Add the content of memory location A to the content of accumulator
Load A
Store A
 The operation C <- [A] + [B] can be performed by executing the sequence of
instructions
Load A
Add B
Store C
35
Let Ri represent a general-purpose register. The instructions
 Load A, Ri
 Store Ri, A
 Add A, Ri

In both of below instructions, the source operands are the contents of
registers Ri and Rj.
In the first instruction, Rj also serves as the destination register, whereas in
the second instruction, a third register, Rk, is used as the destination.
 Add Ri, Rj
 Add Ri, Rj,Rk

36
4. INSTRUCTION EXECUTION AND STRAIGHT-LINE
SEQUENCING:-
Let us consider the task C<-[A] +[B].
A possible program segment for this task as it
appears in the memory of a computer.
 Assume that the computer allows one memory
operand per instruction and has a number of
processor registers.
Assume that the word length is 32 bits and
memory is byte addressable.
The three instructions of the program are in
successive word locations, starting at location i.
Since each instruction is 4 bytes long, these
second and third instructions start at addresses
i+4 and i+8.

37
Execution of instruction has two-phase
procedure
I. Instruction fetch-> fetch the instruction
from memory and store in IR reg
II. Instruction execute-> instruction in IR is
examined to determine which operation is
to be done. It involves
*fetching of operands from memory or
from processor register
*performing the operation
*storing the result

 In the execute phase the PC will hold the

address of next instruction

38
5. BRANCHING:-
Consider the task of adding a list of n
numbers.
Instead of using a long list of add instructions,
it is possible to place a single add instruction in
a program loop, as shown.
The loop is a straight-line sequence of
instructions executed as many times as
needed.
 It starts at location LOOP and ends at the
instruction Branch > 0.
During each pass through this loop, the
address of the next list entry is determined,
and that entry is fetched and added to R0

39
5. BRANCHING:-
Consider the task of adding a list of „n‟ numbers .
Number of entries in the list „n‟ is stored in memory-location
N.
Register R1 is used as a counter to determine the number of
times the loop is executed.
The Loop is a straight line sequence of instructions executed
as many times as needed.
The loop starts at location LOOP and ends at the instruction
Branch>0.
During each pass,
 → address of the next list entry is determined and
 → that entry is fetched and added to R0.
The instruction Decrement R1 reduces the contents of R1 by 1
each time through the loop.
Then Branch Instruction loads a new value into the program
counter. As a result, the processor fetches and executes the
instruction at this new address called the Branch Target.
A Conditional Branch Instruction causes a branch only if a
specified condition is satisfied. If the condition is not satisfied,
the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed 40
6. CONDITION CODES
The processor keeps track of information about the results of various operations. This
is accomplished by recording the required information in individual bits, called
Condition Code Flags.
These flags are grouped together in a special processor-register called the condition
code register (or statue register).
Four commonly used flags are:
N (negative) set to 1 if the result is negative, otherwise cleared to 0.
Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.

The N and Z flags will affect

 On arithmetic and logic operations
 On data transfer

41