A. Explain the ARM register set.

ARM has 37 registers in total, all of which are 32 bits long. 1 dedicated program counter, 1
dedicated current program status register, 5 dedicated saved program status registers and 30
general purpose registers. However, these are arranged into several banks. with the accessible
bank being governed by the processor mode. Each mode can access. A particular set of r0-r12
registers a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter,
cpsr (the current program status register) and privileged modes can also access particular spsr
(saved program status register).

B. Describe the following shifting ARM instructions with example: LSL, LSR, ASR, ROR

LSL – LSL means Logical Shift Left. left shifts effectively multiply the content of a register
by 2s where is the shift amount.
EXMAPLE: MOV R0, R0, LSL 7

R0 BEFORE : 0000 0000 0000 0000 0000 0000 0000

0111 =7

R0 AFTER : 0000 0000 0000 0000 0000 0011 1000

=7* 7 = 896
0000 2

LSR – LSR means logical shift right. Right shifts behave like diving the contents of a register
by 2s where s is the shift amount.
EXAMPLE: MOV R0, R0, LSR 2

R0 BEFORE : 0000 0000 0000 0000 0000 0100 0000

0000 = 1024

R0 AFTER : 0000 0000 0000 0000 0000 0001 0000

0000 = 1024 /
2
2 =

896
ASR – ASR means Arithmetic shift right . Arithmetic shift right behave like diving the
contents of a register by 2s where s is the shift amount.
EXAMPLE : MOV R0, R0, ASR 2

R0 BEFORE : 1111 1111 1111 1111 1111 1100 0000

0000 = - 1024

R0 AFTER : 1111 1111 1111 1111 1111 1111 0000

0000 = - 1024 / 2 =-
2
256

ROR – ROR means rotate right shift. Rotating shifts have no arithmetic analogy. However ,
the don’t lose bits like both logical and arithmetic shifts
EXMAPLE : MOV R0, R0, R0R 2

R0 BEFORE : 0000 0000 0000 0000 0000 0100 0000

0111 =7

R0 AFTER : 1000 0000 0000 0000 0000 0001 0000

0001 = - 1,073,741,823

C. Explain following instruction set in ARM: Arithmetic instructions, Logical Instruction and
Branch Instructions

Arithmetic instructions – Only processor and registers are involved with the purposes. The
Arithmetic instructions define the set of operations performed by the processor Arithmetic
Logic Unit (ALU).

Logical Instruction – ARM logical operations include AND, ORR (OR), EOR (XOR), and
BIC (bit clear). Perform the Boolean operation on the pair or operands and are useful for bit
masking purposes, for an example clear status bit or change interrupt masks in CPSR.

Branch Instructions- Branch is an instruction in a computer that can cause a computer to

begin executing a different instruction sequence and deviate from its default behaviour of
executing instructions in order. It is also used to implement control flow in program loops
and conditionals.
D. Explain Flags in ARM Processor

The Arm Processor contains Z, N ,C and V flags which are updated by execution of data
processing instructions. Condition code for the flags, N= Negative result from ALU flag, Z =
Zero results from ALU flag, C= ALU operation Carried out, V = ALU operation overflowed.
Z (Zero) flag is set when the result of an instruction has a zero value or when a comparison of
two data returns an equal result. Then N (Negative) flag, this flag is set when the result of an
instruction has a negative value. The C (Carry ) flag will be set if the result of an unsigned
operation overflows the 32-bit result register. Lastly The V(Overflow) flag operates in the
same way as the C flag, but for signed operations.

E. Briefly explain the component in CMSIS structure.

CMSIS TARGET PROCESSORS DESCRIPTION
CORE (M) All Cortex – M, secure core Standardized API for the Cortex
– M processor core and
peripherals. includes intrinsic
functions for Cortex
-M4/M7/M33/M35P SIMD
instructions.

CORE (A) Cortex-A5/A7/A9 Standardized API and basic run-

time system for the Cortex-
A5/A7/A9 processor core and
peripherals.
DRIVER All cortex-M DSP library collection with over
60 functions for various data
types: fixed-point (fractional q7,
q15, q31) and single precision
floating-point (32-bit).
Implementations optimized for
the SIMD instruction set are
available for
Cortex-M4/M7/M33/M35P
NN Cortex-M0/M0+/M3/M4/M7 Collection of efficient neural
network kernels developed to
maximize the performance and
minimize the memory footprint
on Cortex-M processor core
RTOS V1 Cortex-M0/M0+/M3/M4/M7 Common API for real-time
operating systems along with a
 reference implementation based
on RTX. It enables software
components that can work
across multiple RTOS systems.
RTOS V2 All Cortex-M, Extends CMSIS-RTOS v1 with
Cortex-A5/A7/A9 Armv8-M support, dynamic
object creation, provisions for
multi-core systems, binary
compatible interface.
BUILD All Cortex-M, SecurCore, A set of tools, software
Cortex-A5/A7/A9 frameworks, and work flows
that improve productivity, for
example with Continuous
Integration (CI)
SVD All Cortex-M, SecurCore Peripheral description of a
device that can be used to create
peripheral awareness in
debuggers or CMSIS-Core
header files.
DAP All Cortex Firmware for a debug unit that
interfaces to the CoreSight
Debug Access Port.
ZONE All Cortex-M Defines methods to describe
system resources and to
partition these resources into
multiple projects and execution
areas.
PACK All Cortex-M, SecurCore, Describes a delivery mechanism
Cortex-A5/A7/A9 for software components, device
parameters, and evaluation
board support. It simplifies
software re-use and product life-
cycle management (PLM).
F. Allocate the call function technique with the suitable diagram and state the simple syntax
for call subroutine.

A call subroutine is a set of instructions that are used repeatedly in a program, which can be
referred to Subroutine . Only one copy of this instruction is stored in the memory. When
subroutine is needed it can be called many times during the execution of a program.

INSTRUCTION

CALL SUBROUTINE SUBROUTINE

INSTRUCTION

NEXT INSTRUCTION

Simple syntax for call subroutine

int addthree(int a, int b, int c)

{
return a + b + c;
}
int main()
{
int d = add(3, 4, 5);
printf(“%d\n”, d);
return

REFERENCES
1) https://padlet.com/norsyira/my-verilog-uprocessor-zicutmysp8m
2) https://youtu.be/ibh4tadjUaw
3) https://youtu.be/Q4qu4ADTy9Q
4) https://youtu.be/xt2Q9n1Udb4
5) http://www.csbio.unc.edu/mcmillan/Comp411F18/Lecture07.pdf
6) https://youtu.be/X560ZGrZ2qc
7) https://www.geeksforgeeks.org/subroutine-subroutine-nesting-and-stack-memory/
8) https://www.keil.com/pack/doc/CMSIS/General/html/index.html
9) https://padlet.com/norsyira/my-verilog-uprocessor-zicutmysp8m/wish/379177555