ANANTHA LAKSHMI

INSTITUTE OF TECHNOLOGY & SCIENCES

(Approved by AICTE,New Delhi &Affiliated to JNTU,Anantapur)
TITLE
DESIGN OF AREA AND POWER POTENT BOOTH
MULTIPLIER USING MULTIPLEXER

PROJECT ASSOCIATES
G.SREENAVYA 162G1A04D5
S.SANDHYARANI 162G1A04G4
K.THARUNKUMAR 162G1A04E7
N.HARITHA 172G5A0410
G.YUGANDHAR 162G1A04D4
UNDER THE GUIDANCE OF
K.GOWTHAMI M.TECH.,(Assistant Professor)
 CONTENTS
 Abstract
 Objective
 Problem Definition
 Existing Approach
 Drawbacks
 New Approach
 Methodology
 Expected Outcomes
 Results
 Applications
 References
Abstract
The demand for the improvement of digital signal
processing is highly increasing in present days.
Multiplier plays a crutial role in signal processing that will
decide overall device speed ,area and power consumption.
Objective

The proposed design reduces the area, power, and delay when
compared to the existing multipliers.
Problem Definition

It is found that conventional booth multiplier is consuming

more power and occupying more space because we are using
adders and subtractor gates.
Existing Approach

In the existing method we have a booth multiplier that is

used to multiply the two signed binary numbers. The
blocks of this multiplier are 9 bit multiplexer,9 bit
adder/subtractor and code.
Conventional booth multiplier
Drawbacks
 The main disadvantage of booth multiplier is that requires
large area.
 This multiplier also consumes more power.
New approach
In order to address the disadvantages of conventional
booth multiplier it is decided to propose a new booth
multiplier. This proposed booth multiplier has blocks
like Multiplexer based adder,1-Bit adder/subtractor
and 9-Bitadder/subtractor.
Proposed booth multiplier using multiplexer
Methodology
Booth’s multiplication algorithm which multiplies two
signed binary numbers in the two’s complement
notation.This is implemented by Andrew Donald Booth.
Booth multiplication algorithm flowchart
Expected Outcomes

 In this proposed method we can expect that it consumes

low power, area efficient.
Results
LUT, power and delay comparison between
proposed and existing methods
Applications
It is used for multiplication purpose most notably in signal
processing.
These are also present in microprocessor applications.
It is certainly present in digital computer for scientific
computation.
References
[1] Ramya Muralidharan , Chip-Hong Chang,Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers, IEEE
Trans on Circuits And System, vol. 60(11), Nov 2013.
[2] Soniya1, Suresh Kumar,― A Review of Different Type of Multipliers and Multiplier-Accumulator Unit,
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Volume 2, Issue 4,
July– August 2013
[3] Fayed, Ayman A,Bayoumi, Magdy A, ―A Merged Multiplier Accumulator for high speed signal processing
applications, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp 3212 -
3215, 2002.
[4] Zuber, M. Patel ―Enhancing speed and reducing power of shift and add multiplier International Journal Of
Electrical, Electronics And Data Communication, ISSN: 2320-2084 Volume-4, Issue-6, Jun.- 2016.
[5] Ashwinik Dhumal , Prof.S.S.Shirgan ―Comparison between Radix-2 and Radix -4 based on Booth Algorithm‖,
Electronic and Telecommunication Department, International Journal of Advanced Research in Computer and
Communication Engineering, Vol. 5, Issue 12, December 2016. doi:10.17148/IJARCCE.2016.512113.
[6] Jiang, H., Han, J.Qiao, F., et al.: ―Approximate radix-8 booth multipliers for low-power and high-performance
operation‖, Trans .Comput., 2016, 65, (8), pp. 2638–2644,doi: 10.1109/ TC.2015.2493547.