Grant Report

grant recipient: Mehdi Safarpour

(doctoral student in University of Oulu)
reception year: 2019

Date: 5/16/2020
 1. General Information

A. Research Idea
Operating digital logic with supply voltages near and below threshold voltage of transistors
significantly improves energy efficiency i.e. 10x and 20x respectively [1,2] . Based on experimental
results [1] significant improvement in efficiency (2x to 20x) was observed [3] with adopting Near-
Threshold and Sub-Threshold voltage regimes.

Figure. 1 Energy efficiency versus supply voltage

In addition, recent research of our collaborators in Barcelona Super Computing Center [1] has
demonstrated supply voltage of off-the-shelf components such as GPUs and FPGAs manifest a large
voltage tolerance between critical voltages of operation with nominal voltage that can be exploited to
minimize power consumption.
The reason that near-threshold/sub-threshold operation is not mainstream is the difficulty in
determining the optimum voltage/frequency (clock frequency) of the devices. Due to process
variation and unknown ambient temperature, the threshold voltage of transistor of a chip cannot be
measured exactly in advance. Lower the voltage without setting clock frequency to the optimum,
results in either loss of performance (under-clocking) or loss of reliability (over-clocking). The stare-
of-art solution is arming the digital logic with a so-called Timing Error Detection circuits [2]. This
requires complete modification in circuit layout, cannot be applied to off-the-shelf component, and
requires its own fabrication process. This adds overwhelmingly to the manufacturing costs and
lengthens the design time. As shown in Fig. 2, the same ARM processor core equipped with TED
circuits occupies 2x more die area.
 Figure. 2 Common Methods for TED has large area overhead [Die Photo adopted from is
Reference [2]
Now, imagine extremely energy efficient computing accelerator device that is operating in near-
threshold or even sub-threshold regions without having to add costly redesign and
manufacturing process that guaranties the results merely with only low cost software inspection of
output data. All benefits of sub/near-threshold computing will be attainable, i.e. proven 10x to 100x
improvement in energy efficiency only through introducing small modification on system level
(PCB level not IC level).

B. Proposed Solution
In contrast to state-of-the-art methods, our method does not require any modification on design. It
can potentially be applied on any single digital processor out there that already been manufactured.
The method is somewhat software base (though small modifications on PCB level is required) and
is blind to processor architecture and blind to input data. Through Algorithm-Based Fault Tolerance
(ABFT) methods any inconsistency in computations can be detected in results. Our solution
leverages ABFT into near-threshold computing, relaxing the need for costly hardware based TEDs.
In case of error, the clock rate can be adjusted In other words, we are proposing to leverage a fault
tolerance technique into low power digital design. The general concept of solution is shown in
Fig. 3. The cost of checking for errors is trivial compared to main computations

Figure. 3. In case of errors voltage and clock of the accelerator are adjusted
 2. Most Important Results
A collaboration formed with a group of researcher in Barcelona Supercomputing Center (one of the
most powerful computing centers of the world). Unfortunately, due to recent pandemic the research
visits were cancelled however, the same equipment are being purchased here in Oulu and the
experimental platforms (such as the one shown in following image) are under development.

Figure. 4. The intended experimental platform based on our collaborator’s design

Primary experiments are extremely promising. The method under investigation successfully reduce
power consumption of Matrix Operation Accelerators used in base-stations by more than 20%
percent increasing energy efficiency multiple folds. The research is continuing and the result of
collaboration will be submitted to Transaction on Circuits and Systems journal in following months.

References
[1] Salami, Behzad, Osman Sabri Unsal, and Adrián Cristal Kestelman. "Experimental study
of aggressive undervolting in FPGAs." In Book of abstracts, pp. 71-72. Barcelona
Supercomputing Center, 2019.
[2] Hiienkari, Markus, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Mäkipää,
Arto Rantala, Matti Sopanen, and Mikko Kaltiokallio. "A robust ultra-low voltage CPU
utilizing timing-error prevention." Journal of Low Power Electronics and Applications 5, no.
2 (2015): 57-68.
[3] Das, Shidhartha, David Roberts, Seokwoo Lee, Sanjay Pant, David Blaauw, Todd Austin,
Krisztián Flautner, and Trevor Mudge. "A self-tuning DVS processor using delay-error
detection and correction." IEEE Journal of Solid-State Circuits 41, no. 4 (2006): 792-804.