Shiv Nadar Institution of Eminence, Deemed to be University

Department of Electrical Engineering Document Number: Version: 1.2

SNU/MAN/EHS/EL/01 Effective Date: 02/01/2023
Title: Communication Engineering Lab Manuals Pages 8

LAB: 08
Time Division Multiplexing & De-multiplexing (TDM)
OBJECTIVES:

1. Study the function of Synchronization and Clock in TDM.

2. Study the working of a TDM-PAM Transmitter and receiver using Two Link Communication
Mode.
3. Study the working of a TDM-PAM Transmitter and receiver using the Single Link
Communication Mode.

MATERIALS / COMPONENTS & EQUIPMENT: DSO, Training Kit, and connecting patch chords.

THEORETICAL BACKGROUND:
Multiplexing is the process of combining signals from different information sources so that they can be transmitted
over a common channel. The channel in this context could be a transmission line, e.g. a twisted pair or co-axial cable,
a radio system or a fiber optic system etc.
Multiplexing is advantageous in cases where it is impracticable and uneconomical to provide separate links for the
different information sources. The price that has to be paid to acquire this advantage is in the form of increased
system complexity and bandwidth.
Time-division multiplexing (TDM): The method of combining several sampled signals in a definite time
sequence is called time-division multiplexing (TDM).
TDM is a technique used for transmitting several message signals over a communication channel by dividing the
time frame into slots, one slot for each message signal. This is a digital technique in which the circuit is highly
modular in nature and provides reliable and efficient operation.

Principle operation of TDM-PAM system:

The time division multiplexing system can be simulated by two rotating switches, one at transmitter and the other
at receiver (See figure). The two wipers rotate and establish electrical contact with one channel at a time.

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Each signal is sampled over one sampling interval and transmitted one after the other along a common channel.
Thus part of message 1 is transmitted first followed by part of message 2, message 3 and then again message 1 so
on.
The switches connect the transmitter and the receiver to each of the channels in turn for a specific interval of time.
In effect each channel is sampled and the sample is transmitted.
When the switches are in the channel 1 position, channel 1 forms a PAM channel with an LPF for reconstruction, and
so on for channels 2 and 3. As a result the amplitude samples from each channel shares the line sequentially,
becoming interleaved to form a complex PAM wave.
A major problem in any TDM system is the synchronization of the transmitter and receiver timing circuits. The
transmitter and receiver switches must operate at same time with same frequency. For example, transmitter switch
SWt must be in the channel 1 position when receiver switch SWr is in the channel 1 position, so that the switches
must be synchronized in position also.

It can be anticipated from above process that the receiver switch has to follow two constraints:
1. It must rotate at the same rate as the transmitter switch.
2. It must start at the same time as the transmitting switch and it must establish electrical contact with the same
channel no. as that of the transmitter. If these two conditions are met, the receiver is said to be in synchronization
with transmitter. If constraint one is not met, the samples of different sources would get mixed at the receiver. If
constraint two is not met, the information from source 1 will be received by some other channel which is not
intending to accept the information from that particular channel.
To establish synchronization, the receiver needs to know:
a. Frequency/ rate of operation at transmitter.
b. Sample identification.

Time Division Multiplexed signal:

Sampling time (Ts) = 1/fs

Time duration utilized by each sample (T) = Ts/n (n is no. of channels)
Spacing between consecutive pulses = T – pulse duration

The period allocated for transmitting one sample is called as a time slot. Four channels are multiplexed. The groups
of four time slots are termed as a frame.
Synchronization: The most vital requirement of a time division multiplexed system is synchronization. The
transmitter and receiver are said to be synchronized when:
1. The rate of operation at transmitter is same as the rate of operation at receiver.
2. Samples can be identified with different channels i.e. time slot 0 samples must go to channel 0 output, time slot 1
samples must go to channel 1 output and so on.

Clock signal: For correct operation of receiver, the switching rate should be same as that for transmitter. To do
this the receiver clock must match with the transmitter clock.

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Frame Synchronization signal: Besides clock signal, the receiver also requires information from the transmitter
to identify one timeslot per frame and so as to pass the time slot to correct output channel. If it is achieved for one-
time slot, then other time slots in the frame are passed to the correct channels. It is ensured by frame
synchronization signal.
These two signals namely the clock signal and Frame synchronization signal should be transmitted by the
transmitter along with the information signal.

Transmission modes:
Two Link communication (Mode 1): In this mode of communication, modulated signal and Synchronizing
(Sync) signal are transmitted, Clock and Synchronizing (Sync) signals recover at the receiver.

Single Link communication (Mode 2): In this mode of communication, only modulated signal is transmitted,
Clock and Synchronizing (Sync) signals are recovered at the receiver.

Timing Logic:
The receiver timing logic operates the receiver switch in a manner similar to the transmitter switch operation. The
Rx. Clock signal ticks a two-bit binary counter. The outputs of the two-bit binary counter are passed to a decoder
which identifies which particular switch is to be closed e.g. If the binary count is 01, the switch corresponding to
CH2 will close. To ensure that the count always starts at 0, the binary counter is reset by the frame synchronization
signal at start of every frame.
The opening and closing of particular switch depends upon the decoder output provided in transmitter timing logic.
The decoder's output can be obtained at TP14, 15, 16, 17. Observe that the output at each of these test points is a
train of pulses at frequency 16 KHz and with pulse duration set by the duty cycle selector switch.
The decoder's output depends upon two quantities:
a. Divider output
b. Decoder Enable pulse train which is provided by the duty cycle control signal.

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The decoder output is decided by the divider output. But the operation takes places only when the decoder is
enabled. The enable signal is active low and it is supplied from the duty cycle control switch, the switch is closed
when a low signal is applied to it. The duration of a particular switch closing is decided by the duty cycle control
switch whose output drives the enable input of the decoder. For different setting of the duty cycle switch, the output
width driving the decoder's enable input varies. Hence the duration for which the switch remains closed also varies.

Sampling frequency selector switch:

On-Board four sampling frequencies (32, 40, 50, 80 KHz), out of which user can select anyone using sampling
frequency selector switch. For the selected signal the corresponding LED will light. For selecting a particular
sampling frequency, a three-bit control signal is applied to the Mux unit. These three bit codes are as follows:

Using Duty Cycle selector switch one can vary the duty cycle of the selected sampling frequency from 0 to 90%. The
displayed digit D on the switch indicates (Dx10) % duty cycle of sampling signal. E.g. When displayed 5 it indicates
(5x10) % = 50% duty cycle of selected sampling signal.

Exercise:
Synchronization and Clock
Initial setup:
Function Generator pot direction: clock wise
Duty cycle Position: 5
Delay control: Anti Clock wise
Comparator Threshold level: Clockwise
Frequency Divider Circuit O/P: Highest frequency

1. Connect Oscilloscope CH1 at Sync signal (TP12) and CH2 at Clock (TP13). Note the frequencies and save the
waveforms.
2. Keeping Oscilloscope CH1 at TP12; observe the waveforms at TP14, 15, 16 & 17 on Oscilloscope CH2
respectively. Examine these waveforms.
3. Vary the Sampling Frequency and note the new frequency of Sync signal (TP12) and Clock (TP13). As we
choose different sampling frequency, frequencies of Clock and Sync Signal will vary.
4. Vary the Duty Cycle and observe the variation in both signals. Observe and note the effect.

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Importance of frame synchronization signal
Initial setup:
Function Generator pot direction: clock wise
Duty cycle Position: 5
Delay control: Anti Clock wise
Comparator Threshold level: Clockwise
Frequency Divider Circuit O/P: Highest frequency

1. Make following connections:

a. DC (7V) to CH1 I/P
b. Tx. O/P to Rx. I/P
c. Tx. Clock to Rx Clock
2. Observe the Tx. O/P (TP27) signal on the Oscilloscope channel 1 and on channel 2; observe the wave form
at the inputs of all Low Pass Filters (TP43, 45, 47 & 49).
3. Remove the Tx. Clock and Rx Clock link momentarily. Replace the link after a moment.
4. Repeat steps 2. Examine the effect of clocks on outputs and note the reason.

Two Link communication (Mode 1)

Initial setup:
Function Generator pot direction: clock wise
Duty cycle Position: 5
Delay control: Anti Clock wise
Comparator Threshold level: Clockwise
Frequency Divider Circuit O/P: Highest frequency

5. Switch ‘On’ the kit & Oscilloscope.

6. Make following connections:
a. 500Hz to CH1 I/P socket.
b. 1 KHz to CH2 I/P socket.
c. 2 KHz to CH3 I/P socket.
d. 4 KHz to CH4 I/P socket.
e. Tx. O/P (TP27) to Rx. I/P (TP41)
f. Tx. Sync (TP12) to Rx CH0
g. Clock (TP33) to Rx. Clock (TP36)
h. Sync (TP34) to Rx. Sync (TP35)

7. Set the level of toggle switch in Clock Recovery (PLL) & Delay Control Logic is in upward position.
8. Using CH1 and CH2 of DSO, observe the following signal.
a) TX Clock signal (TP 13) and Receiver Clock signal (TP 33)
b) TX Sync signal (TP 12) and Receiver Sync signal (TP 34)
c) Comparator O/P (TP 31)
d) TDM O/P (TP 27)

9. Now observe the following signals at receiver. Examine input and output of each LPF.
a) LPF 1 I/P at TP 43 and LPF 1 O/P Reconstructed signal at TP 44
b) LPF 2 I/P at TP 45 and LPF 2 O/P Reconstructed signal at TP 46
c) LPF 3 I/P at TP 47 and LPF 3 O/P Reconstructed signal at TP 48
d) LPF 4 I/P at TP 49 and LPF 4 O/P Reconstructed signal at TP 50

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10. Now vary the Duty Cycle Selector switch. Notice the effect of Duty Cycle on Reconstructed Output. Note down
this effect with reason.
11. Set the ‘Duty cycle Selector’ switch again in ‘5’ position.
12. Vary the Sampling Frequency at Transmitter block and observe the effect on Reconstructed Output. Note
down this effect with reason.

Observation table:

Observed Signal Amplitude (Vp-p) Frequency

Transmitter Clock (TP12)
Transmitter Sync (TP13)
Receiver Clock (TP33)
Receiver Sync (TP34)
CH1 I/P (TP18)
CH1 O/P (TP44)
CH2 I/P (TP20)
CH2 O/P (TP46)
CH3 I/P (TP22)
CH3 O/P (TP48)
CH4 I/P (TP24)
CH4 O/P (TP50)

Single Link Communication (Mode 2)

Initial setup:
Function Generator pot direction: clock wise
Duty cycle Position: 5
Delay control: Anti Clock wise
Comparator Threshold level: Clockwise
Frequency Divider Circuit O/P: Highest frequency

1. Make following connections:

a. DC (7 V) to CH1 I/P socket.
b. Message signal 1 (500 Hz, 4V) to CH2 I/P socket.
c. Message signal 2 (1 KHz, 3V) to CH3 I/P socket.
d. Message signal 3 (2 KHz, 2V) to CH4 I/P socket.
e. Tx. O/P (TP27) to Rx. I/P (TP41)
f. Sync (TP34) to Rx. Sync (TP35)
g. Clock (TP33) to Rx. Clock (TP36)

2. Set the level of toggle switch in Clock Recovery (PLL) & Delay Control Logic is in downward position.
3. Using CH1 and CH2 of DSO, observe the following signals.
a) TX Clock signal (TP 13) and Receiver Clock signal (TP 33)
b) TX Sync signal (TP 12) and PLL Sync at receiver (TP 34)
c) TDM O/P (TP 27)

4. Now observe the following signals at receiver. Examine input and output of each LPF.
e) LPF 1 I/P at TP 43 and LPF 1 O/P Reconstructed signal at TP 44
f) LPF 2 I/P at TP 45 and LPF 2 O/P Reconstructed signal at TP 46
g) LPF 3 I/P at TP 47 and LPF 3 O/P Reconstructed signal at TP 48
h) LPF 4 I/P at TP 49 and LPF 4 O/P Reconstructed signal at TP 50
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5. Now vary the Duty Cycle Selector switch. Notice the effect of Duty Cycle on Reconstructed Output. Note down
this effect with reason.
6. Set the ‘Duty cycle Selector’ switch again in ‘5’ position.
7. Vary the Sampling Frequency at Transmitter block and observe the effect on Reconstructed Output. Note
down this effect with reason.

Observation table:

Observed Signal Amplitude (Vp-p) Frequency

Transmitter Clock (TP12)
Transmitter Sync (TP13)
Receiver Clock (TP33)
Receiver Sync (TP34)
CH1 I/P (TP18)
CH1 O/P (TP44)
CH2 I/P (TP20)
CH2 O/P (TP46)
CH3 I/P (TP22)
CH3 O/P (TP48)
CH4 I/P (TP24)
CH4 O/P (TP50)

Post-Lab Questions:

1)What is the advantage of multiplexing used in TDM?

2)Define the term ‘Frame’ in case of TDM.
3)The PAM-TDM signal is _________ . Analog/Digital
4)The transmitter switch and receiver switch must rotate at the same rate, why?
5)If the information from CH1 message will be received by CH3 at LPF. This is due to
………………………..
6) Why is the clock so important?
7) What is the effect of duty cycle on received signal?
8) Name two signals which are transmitted along with the information signal.
9) Write the function of Frame Synchronization signal.
10) The minimum sampling rate for a voice channel is ____ .
11) When do you prefer TDM to FDM?

Results:

Conclusion:

Undertaking:

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Technical Specifications
Crystal Frequency: 8 MHz
Analog Input Channels: 4
Channels Multiplexing: Time Division Multiplexing
Modulation: Pulse Amplitude Modulation
On Board Analog Signal: 500 Hz, 1 KHz, 2 KHz and 4 KHz
Sampling Rate: 32 KHz / Channel, 40 KHz / Channel, 50 KHz / Channel, 80 KHz / Channel
Sampling Pulse: With duty cycle variable from 0-90% in decade steps
Clock Regeneration at: Using Phase Lock Loop (PLL)
Receiver Low Pass Filter Cut-Off: 4 KHz

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