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MEASUREMENT OF MINORITY-CARRIER LIFETIME AND INTERFACE

RECOMBINATION VELOCITIES IN P-I-N DIODES, FROM HIGH FREQUENCY
RESPONSE OF A BIPOLAR JFET STRUCTURE

Article  in  Le Journal de Physique Colloques · September 1988

DOI: 10.1051/jphyscol:1988474

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 JOURNAL DE PHYSIQUE
Colloque C4, supplbment au n09, Tome 49, septembre 1988

MEASUREMENT OF MINORITY-CARRIER LIFETIME AND INTERFACE RECOMBINATION

VELOCITIES IN P-I-N DIODES, FROM HIGH FREQUENCY RESPONSE OF A'BIPOLAR JFET
STRUCTURE' )

G. VITALE and P. SPIRIT0

Dept. of Electronic Engineering, University of Napoli, Via Claudio 21,

I-80125 Napoli, Italy

Abstract - A new method to measure the minority-carrier recombination lifetime in the

low-doped layer of a p-i-n diode, and its emitter recombination current, is presented.
The method is based on the measurement of the cutoff frequency of a three
terminal device structure, similar to a vertical JFET, that incorporates the diode
under test. The paper displays the basic theory of the measurement and some
experimental results.

1 - INTRODUCTION

This paper presents a new method to measure the minority-carrier recombination lifetime
in the low-doped layer of a p-i-n diode, as well as the recombination current in the p+ layer
of the diode.
The method is based on a three terminal device structure, that incorporates the p-.i-n
diode under test, as reported in Fig.1. The test structure is similar to a vertical Junction
Field Effect Transistor, in which the p-i-n diode under test can be either the Gate - Drain
or the Source -Gate diode. A similar device structure was first proposed in [ I ] as a means to
measure the recombination velocity at the high-low transitions that appear in the device
structure, and subsequently used in [ 2 ] to characterize the BSF of a Solar Cell. The method,
which is being presented here, extends the characterization of p-i-n diode (or a Back Surface
Field Solar Cell), by using the same test structure to measure also the lifetime of the low-
doped layer and the recombination into the p region.
For the purposes of the present analysis, the test structure must be operated with the
gate forward biased, with respect to the source, thus inducing an electron-hole plasma within
the low-doped layer of the device. If a small-signal current is added between the gate and
the source, an amplified current is detected at the drain. A measurement of the cutoff
frequency of the device, as a function of the d.c. bias current, allows the simultaneous
determination of the epilayer lifetime and of the recombination velocity associated with the
p+ layer of the p-i-r,diode.

SOU rce
m

SUBSTRATE

Fig.1 - a
The structure of the test device. T e b xes indicate the subdivision of the test
+ B
structure into the n n n and the p n n structures.

his Work was Supported by ENEA under CNR-PFE2 Contract no. 170/87

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988474

C4-360 JOURNAL DE PHYSIQUE

2 - THEORY OF THE MEASUREMENT

A small-signal analysis of the test structure, has been carried out by solving the
fundamental transport: equations, linearized for small-signal. To that purpose, the device has
been splitted into two, one-dimensional structures, as shown in Pig.2 and 3. These are: (1)
The n+-n-n+, source-clrain structure and (2) the surface p+-n-n+ (gate-source) structure. W h ~ n
the latter is forward biased, an electron-hole plasma is induced into the epilayer, within a
thickness, Xl0 which is controlled by the source-drain bias. From the d.c. analysis 131, it
turns out that Xl0 is: given by:

where: ps is the hole density at the source, ND is the epilayer doping, Ad is the device
area, Id is the train current, the subscript o indicates d.c. quantities.
In the analysis, the source - drain structure is further subdivided into two parts,
namely the conductivity modulated region, close to the source transition, and a drift region.
The gate - source diode has been solved by summing the impedances of both the p+-n and the n-
n+ transitions and by accounting for the recombination within the epilayer, the latter being
a function of the thickness of the conductivity modulated region, X1 The two structures are
bound together by setting a common boundary condition both for the static and the dynamic
equations. Finally the small - signal impedances, Z21 and Z22 have been calculated by
integrating the electric field over the various regions to obtain the voltage Vd and by
recalling that:

The small-signal, common source current amplification, hfs has been obtained as: hfs=-
z21/=22-
If it is further assumed that the transport within the drift region is Ohmic, the
general expression for the small-signal drain voltage is:

where: zl = X210/4Dn is the transit time into the conductivity modulated region, Id is the
drain current, ps is the hole density at the source, W is the epilayer thickness a is the
epilayer conductivity, the tilde indicates small-signal quantities.
It is worth to point out that the transport regime of the drift region does affect the
low-frequency value of hfs but it doesn't change its cutoff frequency.
The current at the input source-gate diode, has been derived by taking into account the
effects of transit time between source and gate, the recombination within the epilayer,
including the effects of the floating bounrdary, XI. The recombination currents at the source
and gate layers have been modeled by means of the recombination factors:

I GATE I

Fig.2 - + + structure and the minority-carrier distribution across the epilayer

The p n n
where: As (A ) are the source areas, Ss (S ) are the source (gate) recombination
velocities, &at g
are functions of the minority-carr~er transport properties of these high-
doped layers. It is assumed that the impedance associated with the transport within these
layers enters into the model at frequencies much higher than those of interest in the present
analysis.
With these assumptions ,the gate current at the source interface is:

where: z is the epilayer minority carrier lifetime, TD is the diode transit time
From Eq.3, Z22 is obtained as the ratio vd/Id with Fs=O. The latter condition is in fact
equivalent to: Ig=O. Similarly, if Id is set to zero, in Eq.3, and the ratio of Eq.1 to Eq.3
is taken, the transfer impedance, Z21 is obtained.
The general expression for hfs can be written as:

2 VT U Ad
where: hfo =

The other zeroes and poles lie far above wo over a wide range of device parameters,thus
allowing to simplify hf, as:

$0

3 t ..-. v.:
- --.
....
i
u
-.i:..-. b
5'.

f
0
z
.q.'.,. .
'..-..
I
2
5:
I I
(I) a? 00 cs ( 1 ~ 1~ a
2 (Y m 08 ID
Distnnce fmm Source Distance from Source

Fig.3 - Field (solid lines) and hole (dashed) distributions for constant drain current
(left) and for constant gate current (right) between source and drain.
 JOURNAL DE PHYSIQUE

From Eq.8, it turns out that a plot of wo vs. Id, is a straight line whose intercept
with the w axis equal to l/z and a slope:

is proportional to the recombination velocities of the Source and Gate layers. Fig.4 displays
the experimental determination of these uantities, by using the method outlined above.'
The Base layer is n-type epitaxial, 2 IOP4 cmm3 doped. The measured lifetime is,2.2 psec.
The separation of the two components of the recombination term, can be carried out by
measuring independently the Source recombination velocity, by using the method reported in
Ref.1. From Fig.4, the recombination velocities are: SS = 3 cm/sec, SG = 2.2 cm/sec.
By a proper design of the test structure, namely by making either the source or the gate
area much larger than the other, one of the recombination terms can be made to dominate over
the other, thus improving the accuracy of the measurement.

REFERENCES
[I] S.Bellone et al. "Measurement of the Effective Recombination Velocity of Semiconductor
High-Low Transitions" IEEE Trans. Electron Devices, Vol.ED-32, pp.1771-1775 (1985)
121 T.Daud and F.A.Lindholm "Direct experimental determination of voltage across high-low
junctions" J.Appl.Phys., ~o1.59(I), pp.285-287 (1986)
[3] S.Bellone et Al.:" A quasi-one-dimensional analysis of vertical FET devices operated in
the bipolar mode" Solid-St. Electron. vo1.26, pp.403-413 (1983)

I.I
f4
I*
'b,
0
7
Li
QO I I I . I I I I I
Q 0 1 Q m 3 a l Q ~ € r l m m 9 0
d.c. Drain C u r r e n t (mA)

Fig.4 - The experimental determination of minority carrier lifetime and of gate recombi-
nation velocitv.

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