Design Rules

N- Well

r101 Minimum width 12λ

r102 Between wells 12 λ
r110 Minimum well Area 144 λ2

r 101 r 102

N - Well
r201 Minimum N+ and P+ diffusion width 4λ

r 201 P+ Diff

N - Well

r 201 N+ Diff
r202 Between two P+ and N+ diffusions 4λ

r 202
P+ Diff

N - Well

r 202
N+ Diff
r203 Extra N-well after P+ diffusion 6λ

r 203
P+ Diff

r 203

N - Well

N+ Diff
r204 Between N+ diffusion and n-well 6λ

P+ Diff

N - Well

r 204

N+ Diff
r210 Minimum diffusion area 16λ2

r 210 P+ Diff

N - Well

r 210 N+ Diff
r301 Polysilicon Width 2λ

Polysilicon
r 301

P+ Diff

N - Well

Polysilicon
r 301

N+ Diff
r302 Polysilicon gate on Diffusion 2λ

Polysilicon

r 302

P+ Diff

N - Well

Polysilicon

r 302

N+ Diff
r307 Extra Polysilicon surrounding Diffusion 3λ

Polysilicon

r 307

P+ Diff
r 307

N - Well

Polysilicon
r 307

N+ Diff

r 307
r304 Between two Polysilicon boxes 3λ

Polysilicon

r 304
P+ Diff

N - Well

Polysilicon

r 304
N+ Diff
r307 Diffusion after Polysilicon 4λ

Polysilicon

r 307 r 307

P+ Diff

N - Well

Polysilicon

r 307 r 307

N+ Diff
r401 Contact width 2λ

Contact
r 401

Polysilicon Contact

Metal/Polysilicon Contact
r404 Extra Poly surrounding contact 1λ

Contact

r 404 r 404
Polysilicon Contact

Metal/Polysilicon Contact
r405 Extra metal surrounding contact 1λ

Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 405 r 405
r403 Extra diffusion surrounding contact 1λ

Polysilicon
r 403

P+ Diff

N - Well

Polysilicon
r 403

N+ Diff
 r501 Between two Metals 4λ

Metal 1 Metal 4

r 501

Metal 2 Metal 5

r 501

Metal 3 Metal 6
r510 Minimum Metal area 16λ2

Metal 1 Metal 4
r 510 r 510

Metal 2 Metal 5
r 510 r 510

Metal 3 Metal 6
r 510 r 510
Step 1: Select Foundary
Step 2: Select Foundary
Step 3: n+ Diffussion
Step 4: Polysilicon
Step 5: n+diff and Metal Contact
• This Completes nMOS design

• Now go for pMOS Design, and the first need is

to construct N Well
Step 6: Create N Well
Step 6: p+ Diffusion
Step 7: Polysilicon
Step 8: Contacts
 Final Connections
• pMOS Completed

• Now Interconnection of pMOS and nMOS to

complete inverter

• Connect Source of pMOS to VDD and Source of

nMOS to VSS.

• Short the Drain of both pMOS and nMOS.

INVERTER: Complete Design
Check DRC
 Assign Source
• Assign Signal (Clock) to Gate Terminal

• Add Visible node at Output

Inverter with Source
Run Simulation
VTC Characteristics