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1987-A Functionally Distributed Vision System For Parallel Image Understanding
1987-A Functionally Distributed Vision System For Parallel Image Understanding
SPIEDigitalLibrary.org/conference-proceedings-of-spie
Guo Qiang
Guo Zhong-Rong
Li Zhong -Rong
Harbin Institute
Science, Harbin
Department of Computer Science, of Technology
Institute of
Harbin, P.R. of
Harbin, P.R. China
of China
Abstract
paper, we describe
this paper,
In this design of
the design
describe the distributed multiple
functionally distributed
of aa functionally proce-
array proce-
multiple array
system for parallel vision processing.
ssor system
ssor new architecture
This new
processing. This the power
blends the
architecture blends asso-
of asso-
power of
ciative processor for
ciative processor fast information
performing fast
for performing with the
retrievals with
information retrievals of cellular
capability of
the capability cellular
to process various tasks
array processor to parallel. The
in parallel.
tasks in -based image
pixel-based
The pixel resides in
image resides in an
an
Iconic Array Processor(lAP),
Iconic Array the symbolized
and the
Processor(IAP), and resides in
image resides
symbolized image Array Processor
Symbolic Array
in aa Symbolic Processor
The transfer from iconic to
(SAP). The
(SAP). symbolic is
to symbolic by aa Mapping
accomplished by
is accomplished Multi-Processor(MM
Mapping Multi -Processor(MM
P). The capabilities
P). The of this
capabilities of system allow
this system for feedback
allow for between high
feedback between and low
high and level processing
low level processing
and also
and also support the for mapping
processing for
the parallel processing pixel-based
the pixel
mapping the representation of
-based representation of an
an
image into
image representation(a semantic
symbolic representation(a
into a symbolic used for
network) used
semantic network) -level vision
high-level
for high vision
processing.
Introduction
Dramatic advances
Dramatic declining cost
VLSI and declining
advances in VLSI processor offer
of processor
cost of environment for
offer a new environment for
design of special
design of architectures and
purpose architectures
special purpose algorithms for
parallel algorithms
and parallel in computer
problems in
for problems computer
vision area. Historically,
vision area. special architectures
many special
Historically, many iconic or
for iconic
architectures for data processing
symbolic data
or symbolic processing
were proposed and
were proposed constructed. However,
even constructed.
and even computer vision
as computer
However, as technique matures
processing technique
vision processing matures
the attention is
the attention shifted from
is shifted simple processing
from simple systems to
processing systems more intelligent
to more that not
systems that
intelligent systems not
only can perform
only can processing, but
iconic processing,
perform iconic also apply
but also significant amount
apply significant symbolic processing
of symbolic
amount of processing
and reasoning to
and reasoning operations of
the operations
to the object and
of object scene recognition.
and scene functionally distribu-
The functionally
recognition. The distribu-
ted multiple array
ted multiple system described
processor system
array processor this paper
in this
described in innovative architecture
is aa innovative
paper is architecture
processing.
vision processing.
specially designed for computer vision
is shown the
Fig.1, it is
In Fig.1, diagram of
block diagram
the block distributed multiple
functionally distributed
of aa functionally pro-
array pro-
multiple array
cessor svstem
cessor for computer vision processing.
system for mainly consists
It mainly
processing. It an iconic
of an
consists of proce-
array proce-
iconic array
ssor(IAP), a mapping
ssor(lAP), multi -processor(MMP), aa symbolic
mapping multi-processor(MMP), array processor(SAP),
symbolic array host computer
processor(SAP), aa host computer
network.
the interconnection network.
and the
92 / SPIE
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Vol.804Advances
804 AdvancesininImage Processing(1987)
ImageProcessing (1987)
| Host Computer )
Fig.1
Fig.1 Block Diagram of Function-
of aa Function-
ally Distributed Vision System
Pig.3
Fig.3 SAP Array Architecture
/
/One-Bit
ALU \ mask
the accumulator bit, which is also used for
communication.
Y - - -- the second accumulator bit, which is also
used as SR output register bit.
C - - -- the carry bit, used for arithmetic operations.
A - - -- the activity bit, used for enabling or disabling
this PC on any
his PC operation.
given operation.
any given
B---- the second activity bit, used as a temporary
SR F-'i Y signal storage for activity flag.
r --r S---- the sum register bit, which is also used as SR
ESWN input register bit.
A +---4 B
PCs 1 1
SR - -- the shift reglster(S bits), used for storing
ISL information concerning one pixel.
PCM - --the
PCM localmeraory(256
thelocal bits), used
memory(256 bits), for PC
used for operatloi
PC operations.
ISL- -- the interconnection selecting logic.
SSWM PCs
RS4N the4 4 neighboring(3a3t,
PCs- --the nelghboring(Rast, South, West, North)
3outh, 'West, North)
processing cellsCPCa).
processing cells(PCS).
Data Bus
P
Pig.2
Fig.2 The Basic Function Diagram of
The Cell
IAP Cell
of Each IAP
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(1987)/
The
The Symbolic Array Processor(SAP)
Processor(SAP) mainly
mainly consists
consists ofof aa 2-
2-dimensional square array,
dimensional square array, 22-MGC
-MCC
(2-dimensional
(2- dimensionalMesh
Mesh Connected
Connected array
array of
of Computer),
Computer),-' of
of identical cells which
identical processing cells which are
are
interconnected
interconnected "both and locally
both globally and locally asas shown
shown in
in Fig.3.
Pig. 3. The
The processing
processing cells
cells are
are micro-
micro-
programmable so they can operate
programmable so operate independently.
independently.
In 2-MCC
2 -MCC array,
array, aa processing
processing cell
cell can
can locally
locally communicate
communicate to
to one
one of
of its
its 44 neighbors
neighbors or
or
broadcast along its row or column.
broadcast column. With row and column broadcasting, single pro-
broadcasting, data in any single pro-
cessing
cessing cell
cell can be
be broadcast toto all
all PCs
PCs in
in 22 steps.
steps. Information
Information in
in aa particular
particular cell
cell can
can be
be
retrieved either
either by its content(as in associative
associative memory) or by that
memory) or that cell's
cell's address.
address. The
The
associative
associative concept
concept alone
alone is
is not
not sufficient
sufficient forfor designing
designing efficient
efficient architectural
architectural structure
structure
for AI.
AI. This
This is
is because
because retrieval operations
operations in AI AI are
are more
more complex simple words;
complex than simple words; most
most
frequently we
frequently we need to
to match subgraphs
subgraphs oror other
other patterns.
patterns. Also,
Also, we
we need
need toto pursue several
pursue several
hypotheses
hypotheses in parallel, this is
parallel, and this is not possible
possible with simple
simple associative
associative processors.
processors.
The SAP's
The SAP's architecture
architecture blends the power
blends the power of
of associative
associative processors
processors for
for performing
performing fast
fast
information retrievals
retrievals with the
the capability of
of cellular
cellular array processors to process
processors to process various
various
tasks in parallel;
tasks parallel; and the
the regularity of
of this
this array
array is
is an
an important
important feature
feature which makes
makes fea-
fea-
sible
sible its
its VLSI implementation.
processing cell
Each processing cell contains
contains a content addressable
addressable memory(CAM), unit(PU) and
memory(CAM), processing unit(PU)
control unit(CU)
control unit(CU) asas shown
shown in
in Fig. 4. The
Fig.4. The cell
cell also
also has
has constant
constant number
number of
of registers
registers and
and flags
flags
Processing
Processing unit
unit has
has simple
simple microinstructions
microinstructions such
such as
as AND,
AND, OR,
OR, NOT,
NOT, RESET(
RESET( a flag ), MASK(a
flag ), MASK(a
field
field of
of aa string),
string), MATCH(a
MATCH(a string).
string). There
There are
are two
two types
types of
of data
data transfer
transfer instructions
instructions that
that
can be
can be executed
executed by
by the
the processing
processing cell:
cell: Route
Route data
data to
to one
one of
of the
the four
four nearest
nearest neighbors;
neighbors; and
and
Broadcast data toto a row of processing cells or a column of cells.cells. At any time
time only
only one
one type
type
of
of data
data routing
routing instruction
instruction can
can be
be executed
executed by
by the
the PC.
PC. Further,
Further, ifif broadcast
broadcast instruction
instruction is
is
executed
executed only
only one
one PC
PC per
per row( or column)
row(or column) can
can send
send aa value
value to
to all
all processing
processing cells
cells in
in its
its row
row
column) .
(or column).
(1 -1,) J)
Processing Cell(i,J)
lI /0 Buffer 1
How Broadcast Bue
Column Broadcast Hua
CU
Buay Val CAM
PC memory
áU
Block keg.
}
Input UP
IAP
Queue Plug Bito """Controller
ontroller
SAP
ontroller
m I Ieeatetera
o Routing
Logic Mem.
from
II /0 Buffer lAP
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Processing (1987)
The Iconic to
The Transformation from Iconic Symbolic
to Symbolic
system, the
this system,
In this process from
the transformation process iconic to
from iconic to symbolic into
symbolic can be divided into
four subprocess. An
four subprocess. example is
An example presented in
is presented this section
in this to show
section to how the
show how representa-
the iconic representa-
of a simple
tion of
tion into aa semantic
transformed into
simple object is transformed semantic network representation stored
network representation on SAP.
stored on SAP.
The simple
The object, aa cube,
simple object, is shown
cube, is in Fig.6.
shown in has three
It has
Fig.6. It surfaces S1,
three surfaces S2, and
S1, S2, S3, and
and S3, and
seven vertices A,B,C,D,E,F
seven vertices and G-.
A,B,C,D,E,F and Assume the
G. Assume raw image
the raw is handled
image is very well
handled very the segmenta-
well by the segmenta-
tion process,
tion process, the be divided
can be
the whole process can divided into four steps
into four as follows:
steps as follows:
1; The
STEP 1: symbols of the
The RSV symbols are extracted from
image are
the image from IAP. attributes
IAP. Their required attributes
depend on the
depend on complexity of
the complexity the scene
of the and the
scene and segmentation algorithms.
the segmentation this particular
In this
algorithms. In particular
case, we only
case, we extract regions
only extract and segments
regions and together with
segments together their attributes.
with their region attri-
The region
attributes. The attri-
butes are area,
butes perimeter, and
area, perimeter, line segments
bounding line
and bounding segment attributes
and segment
segments and length,
are length,
attributes are
slope, and
slope, the bounded
and the regions for
bounded regions segments. Each
for segments. cell contains
Each cell 256 bits
contains 256 of memory
bits of which are
memory which are
assigned as
assigned as follows: 16 bits
follows: 16 for pixel
bits for localtion, 88 bits
pixel localtion, for gray level
bits for value, 22
level value, bits for
22 bits for
flag, 18 bits for region label,
property, 44 bits for region property flag,
region property, local
label, 4 bits for local
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AB, AD,
AB, CD, BC,
AD, CD, BC, AE,
AE, EF,
EF, BF,
BF, FG, CO : Segments;
FG, CG R2 :: Bounded by;
R2 : by;
R3 : Adjacent;
R3 :
R4 :: Has
Has length;
R5 :: Has
R5 Has slope(orientation),
slope(orientation).
Fig.8 Allocation of
of Nodes in
in SAP
SAP
Fig.7
Fig.7 The Semantic Network Represen-
The Represen-
tation of A Cubic Object
Object
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STEP 4: is ready
4: Once data is ready to
to send
send to
to SAP,
SAP, MMP
MMP transmits
transmits blocks
blocks of
of data
data as
as shown
shown in
in Fig.8
Pig.8
into SAP cell.
into corresponing SAP cell.
Conclusions
In this paper,
In paper, we
we have
have introduced
introduced aa functionally
functionally distributed
distributedmultiple
multiple-array architecture
-array architecture
which
which is
is capable
capable of
of performing
performing aa broad
broad range
range of
of parallel
parallel algoruthma
algoruthms inin computer
computer vision
vision
processing. This system
processing. This system consists
consists of
of aa low
low-level iconic array
-level iconic array processor,
processor, a ahigh
high-level sym-
-level sym-
bolic
bolic array
array processor,
processor, aa mapping
mapping multiprocessor
multiprocessor system
system and
and aa host
host computer.
computer. WeWe briefly
briefly
discussed the structure of these
discussed the these processors
processors and
and indicate
indicate the
the major
major steps
steps required
required toto trans-
trans-
image from
fer an image iconic to
from iconic to symbolic
symbolic representation.
representation. Usually,
Usually, because
because of the lack
of the of aa
lack of
symbolic
symbolic processor,
processor, in some computer
computer vision
vision systems
systems many
many symbolic
symbolic processing
processing tasks
tasks are
are done
done
in
in iconic
iconic domain. The architecture of
domain. The of our
our system
system allows
allows the
the extraction
extraction of
of primitive
primitive symbolic
symbolic
information
information from domain, and
from iconic domain, and then
then the
the capability
capability ofof performing
performing complex
complex symbolic
symbolic pro-
pro-
cessing domain.
cessing in symbolic domain.
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(1987) / / 97