Chiptop 90nm

101 Input Output (34in + 67 out)

1.5 volt

IR = 10%

Clock 7ns and 10ns

Chip area: 1490.mm^2

From. itf we extract .tf file

Check after DC Compiler and before floorplan.

QOR – qor quality of result

Timing

Design

Constrain

Itra10 copy folder chip90. Inside that five folders are there. Models, ref,

Create a folder and work inside that only.

Terminal => csh

=> icc_shell -gui

Load db files and tlu files

Create a library.

1. Flywire
2. Fan In Fan Out
3. DFA

Place macro by hierarchy

Place macro near to core area

Avoid notch.