Professional Documents
Culture Documents
Contents
1. ASIC Design
2. What is Verification and its challenges
3. Types of Verifications
4. Phases of Verifications
5. Verification Plan
6. Verification Architecture
7. Testbench
8. Coverage based Verification
9. Assertions based Verification
ASIC Design Flow
Verification
- Paul Wilcox
Verification Challenges
a. Missed bugs
b. Lack of Time
c. Lack of resources
Missed Bugs
a. Partly an art
b. Partly luck
c. And lots of hardwork
Lack of resources
Resources:
Experienced verification engineer – hard to find
Specialists + inexperienced = inefficiency
S/W licenses and verification tools are costly
Tools often will have narrow focus
Verification reuse – write once and use often
Basic V design
a. Black Box
b. White Box
c. Grey Box
Black Box Verification
available interfaces
controllability
Testbenches
White Box Verification
• White box verification has intimate knowledge and control of the
internals of design
1. Verification Plan
2. Building Testbench
3. Writing Tests
Initially in CDV, the test are ran randomly till some 70% of
coverage is reached (or) if there is no improvement.
2. Verification Approach:
Which verification approach fits the design
requirements, for example
• Top-down design and verification
• Bottom-up verification
• Platform-based verification
• System interface-driven verification
Cont'd...
• Linting
– Limitations of linting
• Simulation
– Event and cycle based simulation
– co-simulators
• Verification IP
• Code Coverage
• Functional Coverage
Linting
• Linting technology finds common programmer
mistakes.
• Co-simulators
– Most of the cycle based simulators are integrated with
the event driven simulators
Verification IP
a. Model Source
b. Existing Models
- std lib, model from prev design
c. Derived Models
- Gate level model from RTL model using synthesis
d. Authored Models
- Models to be developed as part of verification.
10. Testbench Requirements :
1. Capacity metrics:
Identifies tool capacity assumptions (run
times, memory size, disk size, and so on) and
verifies that the assumptions made holds true
during the execution of that plan.
2. Quality metrics:
Establishes when a verification task is
complete. Quality metrics include functional
coverage and code coverage.
12. Regression Testing :
a. The strategy for regression testing.
b. The test plan details when the regression tests
are to be run (overnight, continuously, triggered
by change levels, and so on) and
c. Specifies the resources needed for the
regression testing
adder DUT(a,b,c);
initial
begin
a = 16'h45;
b = 16'h12;
#10 $display(" a=%0d,b=%0d,c=%0d",a,b,c);
end
endmodule //TestBench code end
Random TestBench
• module top(); //TestBench code start
reg [15:0] a,b;
wire [16:0] c;
adder DUT(a,b,c);
initial begin
repeat (100) begin
a = $random;
b = $random;
#10 $display(" a=%0d,b=%0d,c=%0d",a,b,c);
end
end
endmodule //TestBench code end
Self Checking TestBench
adder DUT(a,b,c);
initial begin
repeat (100) begin
a = $random;
b = $random;
#10 $display(" a=%0d,b=%0d,c=%0d",a,b,c);
if(a+b !=c) $display(“ERROR”);
end
end
endmodule //TestBench code end
a. Using Reference Model
b. Using Transfer Functions
c. Scoreboarding
Verification Environment
Architecture
• Layers of Architecture:
a. Signal and Command Layer
b. Functional Layer
c. Scenario Layer
d. Test layer and Functional coverage
Signal and Command Layers
Functional Layer
Scenario Layer
Test layer and Functional coverage
COVERAGE-DRIVEN RANDOM-
BASED APPROACH
• EXAMPLE: testcase_2.v
module TEST();
initial
repeat(10)
top.read();
endmodule
Code Coverage
• Code coverage is a technology that can identify
what code has been(and more importantly not
been) executed in the design under verification.
• But are there sections of the RTL code that you did
not exercise and therefore not triggered a
functional error?
Code Coverage
a. Statement Coverage
b. Path Coverage
c. Expression Coverage
d. FSM Coverage
Statement Coverage