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S6B0108 v0.0
S6B0108 v0.0
July. 2001
Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change
the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages
which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to
block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip.
Follow the precautions below when using the products.
1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design
stage.
2. Always test and inspect products under the environment with no penetration of light.
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
2
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
CONTENTS
INTRODUCTION ............................................................................................................................................. 1
BLOCK DIAGRAM .......................................................................................................................................... 2
PIN CONFIGURATION .................................................................................................................................... 3
100 QFP.................................................................................................................................................. 3
PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP).................................................................................... 4
PAD CENTER COORDINATES (100QFP).................................................................................................. 5
100TQFP (S6B2108)................................................................................................................................. 6
PAD DIAGRAM (CHIP LAYOUT FOR THE 100TQFP).................................................................................. 7
PAD CENTER COORDINATES (100TQFP- S6B2108).................................................................................. 8
PIN DESCRIPTION ........................................................................................................................................ 9
MAXIMUM ABSOLUTE LIMIT ......................................................................................................................11
ELECTRICAL CHARACTERISTICS ................................................................................................................12
DC CHARACTERISTICS ..........................................................................................................................12
AC CHARACTERISTICS (V DD = +5V ± 10%, VSS = 0V, Ta =-30 to +85°C) ..................................................13
OPERATING PRINCIPLES AND METHODS ....................................................................................................17
I/O BUFFER ...........................................................................................................................................17
RESET...................................................................................................................................................18
DISPLAY CONTROL INSTRUCTION.............................................................................................................21
DISPLAY ON/OFF...................................................................................................................................22
STATUS READ.......................................................................................................................................23
APPLICATION CIRCUIT................................................................................................................................24
1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT ................................................................24
TIMING DIAGRAM (1/64 DUTY)................................................................................................................25
LCD PANEL INTERFACE APPLICATION CIRCUIT .....................................................................................26
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
INTRODUCTION
The S6B0108 (TQFP type: S6B2108) is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic
display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has
the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot
matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal dis-
play system in combination with the S6B0107 (64 channel common driver -TQFP type: S6B2107).
FEATURES
Drivers Controller
Common Segment
S6B0107 Other S6B0108 MPU
1
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
CLK1
CLK2
DB<0:7>
CS1B
CS2B
Input Output
CS3
I/O Buffer
Register Register
R/W
RS
E
8 RSTB
8
Display
Instruction
On/Off Busy
Decoder
1
6
3
Y-Counter ADC
6
X-Decoder
Y-Counter
6
64 8
Display Start Line Register
CL
Page Selector
Z-Decoder
FRM
64
Data Latch
64
V0L V0R
V2L V2R
V3L LCD Driver
V3R
V5L
M V5R
S2
S1
S63
S64
2
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
PIN CONFIGURATION
100 QFP
RSTB
CS1B
CS2B
CLK1
CLK2
FRM
R/W
CS3
DB7
DB6
DB5
DB4
DB3
DB2
RS
CL
E
100
99
98
97
96
95
94
93
92
91
90
86
85
84
83
82
81
ADC 1 80 DB1
M 2 79 DB0
VDD 3 78 VSS
V3R 4 77 V3L
V2R 5 76 V2L
V5R 6 75 V5L
V0R 7 74 V0L
VEE2 8 73 VEE 1
S64 9 72 S1
S63 10 71 S2
S62 11 70 S3
S61 12 69 S4
S60 13 68 S5
67 S6
S59
S58
14
15
S6B0108 66 S7
S57 16 65 S8
S56 17 (100-QFP) 64 S9
S55 18 63 S10
S54 19 62 S11
S53 20 61 S12
S52 21 60 S13
S51 22 59 S14
S50 23 58 S15
S49 24 57 S16
S48 25 56 S17
S47 26 55 S18
S46 27 54 S19
S45 28 53 S20
S44 29 52 S21
S43 30 51 S22
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
RSTB
CS1B
CS2B
CLK1
CLK2
ADC
FRM
R/W
VDD
CS3
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSS
RS
CL
M
E
100
99
98
97
96
95
94
93
92
91
90
86
85
84
83
82
81
80
79
78
3
2
1
V3R 4 77 V3L
V2R 5 76 V2L
V5R 6 75 V5L
V0R 7 74 V0L
VEE2 8 73 VEE 1
S64 9 72 S1
S63 10 71 S2
S62 11 70 S3
S61 12 Y 69 S4
S60 13 68 S5
S59 14 67 S6
S58 15 66 S7
S57 16 65 S8
S56 17 (0, 0) X 64 S9
S55 18 63 S10
S54 19 Chip size: 4090 × 4020 62 S11
S53 20 PAD size: 100 × 100 61 S12
S52 21 Unit : µm 60 S13
S51 22 59 S14
S50 23 58 S15
S49 24 57 S16
S48 25 S6B0108 56 S17
S47 26 55 S18
S46 27 54 S19
S45 28 53 S20
S44 29 52 S21
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
4
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
5
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
100TQFP (S6B2108)
RSTB
CS1B
CS2B
CLK1
CLK2
ADC
FRM
R/W
CS3
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSS
NC
NC
NC
RS
CL
M
E
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100
VDD 1 75 V3L
V3R 2 74 V2L
V2R 3 73 V5L
V5R 4 72 V0L
V0R 5 71 VEE1
VEE2 6 70 S1
S64 7 69 S2
S63 8 68 S3
S62 9 67 S4
S61 10 66 S5
S60 11 65 S6
S59 12 S6B2108 64 S7
S58 13 63 S8
S57 14 (100-TQFP) 62 S9
S56 15 61 S10
S55 16 60 S11
S54 17 59 S12
S53 18 58 S13
S52 19 57 S14
S51 20 56 S15
S50 21 55 S16
S49 22 54 S17
S48 23 53 S18
S47 24 52 S19
S46 25 51 S20
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
RSTB
CS1B
CS2B
CLK1
CLK2
ADC
FRM
R/W
CS3
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSS
RS
CL
M
E
100
99
98
97
96
95
94
93
92
91
89
87
86
84
83
82
81
80
79
78
77
76
VDD 1 75 V3L
V3R 2 74 V2L
V2R 3 73 V5L
V5R 4 72 V0L
V0R 5 71 VEE 1
VEE2 6 70 S1
S64 7 69 S2
S63 8 68 S3
S62 9 Y 67 S4
S61 10 66 S5
S60 11 65 S6
S59 12 64 S7
S58 13 63 S8
S57 14 (0, 0) X 62 S9
S56 15 61 S10
S55 16 Chip size: 4180 × 4030 60 S11
S54 17 PAD size: 100 × 100 59 S12
S53 18 Unit : µm 58 S13
S52 19 57 S14
S51 20 56 S15
S50 21 S6B0108BTQ 55 S16
S49 22 54 S17
S48 23 53 S18
S47 24 52 S19
S46 25 51 S20
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
8
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
PIN DESCRIPTION
74(72), 7(5) V0L, V0R Bias supply voltage terminals to drive the LCD.
76(74), 5(3) V2L, V2R Power Select Level Non-Select Level
77(75), 4(2) V3L, V3R
75(73), 6(4) V5L, V5R V0L(R), V5L(R) V2L(R), V3L(R)
V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be
connected by the same voltage.
92(89) CS1B Input Chip selection
91(87) CS2B In order to interface data for input or output, the terminals have to
90(86) CS3 be CS1B = L, CS2B = L, and CS3 = H.
2(100) M Input Alternating signal input for LCD driving.
1(99) ADC Input Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = H → Y0: S1 - Y63: S64
ADC = L → Y0: S64 - Y63: S1
100(98) FRM Input Synchronous control signal.
Presets the 6-bit Z counter and synchronizes the common
signal with the frame signal when the frame signal becomes
high.
99(97) E Input Enable signal.
Write mode (R/W = L) → data of DB<0:7> is latched at the
falling edge of E.
Read mode (R/W = H) → DB<0:7> appears the reading data
while E is at high level.
98(96) CLK1 Input 2 phase clock signal for internal operation.
97(95) CLK2 Used to execute operations for input/output of display RAM data
and others.
96(94) CL Input Display synchronous signal.
Display data is latched at rising time of the CL signal and
increments the Z-address counter at the CL falling time.
95(93) RS Input Data or Instruction.
RS = H → DB<0:7>: Display RAM data
RS = L → DB<0:7>: Instruction data
9
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
10
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
NOTES:
1. Based on VSS = 0V.
2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE.
3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7.
4. Applies to V0L(R), V2L(R), V3L(R) and V5L(R).
Voltage level: VDD ≥ V0L = V0R ≥ V2L = V2R ≥ V3L = V3R ≥ V5L = V5R ≥ VEE.
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Input leakage current ILKG VIN = VSS - VDD -1.0 – 1.0 µA (4)
NOTES:
1. CL, FRM, M, RSTB, CLK1, CLK2
2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7
3. DB0 - DB7
4. Except DB0 - DB7
5. DB0 - DB7 at high impedance
6. V0L(R), V2L(R), V3L(R), V5L(R)
7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output: no load
8. VDD - VEE = 15.5V
V0L(R) > V2L(R) = VDD - 2/7 (VDD-VEE) > V3L(R) = VEE + 2/7 (VDD-VEE) > V5L(R)
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
Clock Timing
tC Y
tW H 1
tF tR
CLK1 0.7VD D
0.3VD D tD12 tD21
tWL1
CLK2 0.7VD D
0.3VD D tW H 2
tW L 2
tF tR
tC Y
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tW L
0.7VD D
0.3VD D tW H
tD F tD F
0.7VD D
0.3VD D
tD M
0.7VD D
0.3VD D
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
MPU Interface
E rise time tR – – 25 ns
E fall time tF – – 25 ns
tC
2.0V tW L
E
0.8V tW H
tR tF
t ASU tAH
R/W
t ASU tAH
DB0 - 7
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tC
tW L
E tW H
tR tF
t ASU tAH
CS1B, CS2B,
CS3, RS
tD tD H R
DB0 - 7
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
I/O BUFFER
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode,
Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC
can operate regardless CS1B-CS3.
INPUT REGISTER
Input register is provided to interface with MPU which is different operating frequency. Input register stores the data
temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the
input register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for
falling of the E signal and write automatically into the display data RAM by internal operation.
OUTPUT REGISTER
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode
and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active
mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data RAM,
twice access of read instruction is needed. In first access, data in display data RAM is latched into output register.
In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs
dummy read. But status read is not needed dummy read.
RS R/W Function
L L Instruction
H Status read (busy check)
H L Data write (from input register to display data RAM)
H Data read (from display data RAM to output register)
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
RESET
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from
MPU.
— Display off
— Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after
making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power
supply at initial power up are shown in Table 2.
4.5V
VDD
tR S
tR
RSTB 0.7VD D
0.3VD D
18
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
Busy Flag
Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal
operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the
S6B0108.
RS
R/W
Read data
Busy Write Busy Read data Busy Busy Data read
DB0-DB7 check address N check (dummy) check
at address
check address N + 1
N
Busy Check
Busy Flag
T Busy
1/f C L K < T Busy < 3/f C L K
fC L K is CLK1, CLK2 frequency
Busy Check
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
X Page Register
X page register designates pages of the internal display data RAM. Count function is not available. An address is set
by instruction.
Y Address Counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and is
increased by 1 automatically by read or write operations of display data.
Display data RAM address and segment output can be controlled by ADC signal.
— ADC = H → Y-address 0:S1 - Y address 63:S64
— ADC = L → Y-address 0:S64 - Y address 63:S1
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
The display control instructions control the internal state of the S6B0108. Instruction is received from MPU to
S6B0108 for the display control. The following table shows various instructions.
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function
Display L L L L H H H H H L/H Controls the display on or off.
on/off Internal status and display
RAM data is not affected.
L: OFF, H: ON
Set L L L H Y address (0 - 63) Sets the Y address in the Y
address address counter.
(Y address)
Set page L L H L H H H Page (0 - 7) Sets the X address at the X
(X address) address register.
Display L L H H Display start line (0 - 63) Indicates the display data RAM
start line displayed at the top of the
(Z address) screen.
Status read L H Busy L On/ Rese L L L L Read status.
Off t BUSY L: Ready
H: In operation
ON/OFF L: Display ON
H: Display OFF
RESET L: Normal
H: Reset
Write H L Write data Writes data (DB0:7) into
display display data RAM. After writing
data instruction, Y address is
increased by 1
automatically.
Read H H Read data Reads data (DB0:7) from
display display data RAM to the data
data bus.
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY ON/OFF
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0,
it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1.
Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set by instruction
and increased by 1 automatically by read or write operations of display data.
X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is
executed in this specified page until the next page is set.
Z address (AC0 - AC5) of the display data RAM is set in the display start line register and displayed at the top of the
screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD screen, from
the line specified by display start line instruction, is displayed.
22
64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
STATUS READ
• BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
• ON/OFF
When ON/OFF is 1, the display is off.
When ON/OFF is 0, the display is on.
• RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically.
Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1
automatically.
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S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
APPLICATION CIRCUIT
R1 R2 From MPU
E
R
RS
CR
CS3
DB0
DB7
R/W
RSTB
CS1B
CS2B
-
VD D VD D
ADC
V0 V0R, V 0L DIO1 Open V0R, V 0L V0
V5 V5R, V 5L DIO2 Open V5R, V 5L V5
V1 V1R, V 1L M M V2R, V 2L V2
S6B0108
V4 V4R, V 4L FRM FRM V3R, V 3L V3
VEE VEE CLK1 CLK1 VEE1, V EE2 VEE
CLK2 CLK2 VSS
S6B0107 CL2 CL2 VSS
VD D VD D
S1 S64
SHL
FS
MS
PCLK2 SEG1 SEG64
SD2 C1 COM1
DS1 LCD
VSS C64 COM64
VD D
V0
R1
V1
R1
V2
R2
V3
R1
V4
R1
V5
VEE
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108
CLK1
1 2 3 48 49
CLK2
64 1 2 3 64 1 2 3 64 1
Input CL
FRM
1 Frame 1 Frame
V0
V1
C1 V4 V4
V5 V5
V0
V1 V1 V1
Common C2 V4 V4 V4
V5
V0 V0
V1 V1
C64 V4 V4
V5
V0
V2 V2
S1 V3 V3
V5
Segment V0
S64 V2 V2
V3 V3
V5
25
S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Cf
CR
Rf
R COM64
C64
LCD Panel
(128 × 512dots)
COM65
C1
C2
COM66
C3
COM67
C64
S6B0107 COM128
(slave)
..... ..... .....
S1 ..... S64 S1 ..... S64 S1 ..... S64
No. 9 No. 10 ..... No. 16
S6B0108 S6B0108 S6B0108
26