CLOCK TREE SYNTHESIS Learning Objectives: 1. Gel familiar with the clock tree synthesis 2, Set options and exceptions for CTS 3. Usethe applied design constraints and perform Clock Tree Synthesis 4. Generate and analyze clock tree reports Invoke the Tool (Open the Library and Placement Block Check Design - pre clock tree stage 3 4 Define routing rule 5. Specify Clock Cell List 6. Set Clock Target Skew Latency 7. Specify Routing Rule 8. Sythesize and Optimize Clock Tree 9. Logically conneet PG nets with the pins 10, View the Clock Tree 11. Report Clock Tree Open the project directory CHIPTOP. Invoke the tool shell Open the Library and Powerplan Block Sce2_shell > open lib lib To see the blocks present in the ibrary ice2_shell > list blocks 1 Chipedge Technologies Pvt Ltd., BangaloreChipizdga Now, open the powerplan_done block ereated in the previous lab ice? shell > open block placement done Open the Graphical User interface (GUD ice? shell > start_gut Check Design - pre clock tree stage Bofore performing CTS, execute the following command and analyze the report ico2_shell > check design -checks pre_clock tree_stage ‘Activity List the clocks and period using the commands 1. £ee2_shell > get_clock or all_clocks Name of the Clocks used in the design 2. fee2_shell > report_clock Frequeney of clock Define routing rule Lets define Non Default Rls for metal 4 to metal 7 fee? shell > create routing rile clk rule -widths (M4 0.112 M5 0.112 M6 0.112 M7 0.112 } ~spacings {M4 0.056 HS 0.056 M6 0.056 M7 0.056 } Specify Clock Cell List The Clock tree is built by using Inverters / Buffers depending on the projet requirement. Set the choice of buffers thatthe clock tree must use during CTS, 11_purpose ~exclude ct 3 [get_lib cells} icc2_shell > set_1ib cell_purpose -Include cts [get_lib cells 2 Chipedge Technologies Pvt Ltd., Bangalore"eaedl4rvt_tt0p6v1250/SABORVTI4_BUF_S_2 saedl4rvt_tt0pbvi25c/SARDRVTL4 BUP 5 4 saodl 4rvt_tt0p6v125e/SABDRVT24_BUP_S_6 saedl 4rvt_ttOp6vi25e/SAEDRVTL4_2UES_8") Activity 2 Run icc2_sholl > got_lib cells +/+BuF* Note the different Buffers available inthe library Specify Max Fanout icc?_shell > set_app_options -name cts.conmon-max_fanout value 30 Set Clock Target Skew/Latency Set target skew/lateney constraints for clock trees ice2_shell > set_clock tres options ~clocks {all clocks } ~target_latency 0.250 -target_skew 0.030 Activity 9 1 What Specify Routing Rule Set the lock routing rules in terms ofthe Metal layers tobe used for clock synthesis, the NDR rules, locks to be routed. ice2_shell > set_clock_routing_rules -clocks [all clocks } “net_type (internal) -rules clk rule -min_routing layer M4 -max_routing layer N? 4ce2_shell > set_ciock_routing_rules -clocks [all_clocks } cnet_type (root) -rules elk_rule -min_routing layer M4 wmax_routing_layor N7 3 Chipedge Technologies Pvt Ltd., BangaloreChipizdga Synthesize and Optimize Clock Tree Now, wwe have set the Buffers to be used, Clock routing rules, target latency, target skew run the Clock opt command. It is the main core command to syuthesize clock tree, routing of elock nets, extraction, optimization and hold time violation fixing of the design, ice? shell > clock opt Activity 4 eed shell > man clock opt Note down the steps involved in this command, 3. Logically conneet PG nets with the pins ‘Make the logial connection of PG nets forall the standard cells ice2_shell > connect_pg_net -net DD [get_ping -hler * filter "nano == VDD") sce? shell > conn "nané == VSS") After clock_optis executed you ean inspect the clock tree and query for the various attributes, _pg_net -net VSS [get_pins -hier + -filter 4 Chipedge Technologies Pvt Ltd., BangaloreLook for Max_Tran and Max_Cap violations in the design 5 Chipedge Technologies %Chipedg? 3: Report the Clock Tree jce2_shell > report_clock_tree options 4ce2_eheit > report_clock gor 6 Chipedge Technologies Pvt Ltd., Bangalore4- Report Utilization fee? shell > create utilization_configuration -scope block core utilization ~inelude {ail} 4ce2_shell > report_utilization -config core utilization 5; Report Quality of Results seo2 hell > roport_gor ~sunmary Note the WNS, TNS and Number of violating paths 6. Report Timing ice2_shell > report_timing ~delay_type min ec? shell > report timing -delay type max Analyze the reports generated. Activity 5 Define a. Setup Time 2, Hold Time Saving the block {cc2_shel1 > save block -as cts_done ice2_shell > close blocks -force ice? shell > close lib veetbaneseneeeneettanecees ano deneneceuscenezevensvenseenay 7 Chipedge Technologies Pvt Ltd., Bangalore