PLACEMENT Learning Objectives: 1. Adding 1/0 buffers to the design 2, Creation of Placement Blockages 3. Perform Standard Cell Placement 4. Aualyze Congestion, Cell density and Pin Density Tasks: Invoke the Tool Open the Library and Powerplan Block Ada 1/0 buffers Create Placement Blockages Chock design - Pre Placoment Stage Perform Coarse Placement Set Parasitic Parameters Perform Placement Optimization Cheek Legality 10. Cheek Global Route C 3 4 5 6. 7 8 9. stion, Cell density and Pin Density Open the project directory Linux > ed CHIPTOP Invoke the tool Linux > icc? shell Open the Library and Powerplan Block fce2_shell > open lib 1ib To see the blocks present in the library ice? shell > list blocks Now, open the powerplan_done block ereated in the previous lab 2 shell > open block powerplan_done 1 Chipedge Technologies Pvt Ltd., BangaloreChipledgé Open the Graphical User Interface (GUD Add 1/0 Buffers Now insert buffers forall the 10 por oa magnet placement using, ix these buffers hell > set atus Fig 3: 1/0 Buffer tBlockages Now, we need 10 ereate placement black Placement Blockage inthe toolbar a shown in ig 4. A window will pop up as shown in fi s in the channel regions. Selece Create ifhaed macro and deaw che region as shown in fg 6. Phcement selece whether you need S: blockages need co be created for all che channel regions.Chiplzage Fig4: Crete Plicemene Blockage Fig 3: Selecrmame and rype for Hock Fig6: Placement Blockage inthe channel .ck Design - pre placement stageChipledgé a pre_placenent_st View the report generated, look for errors and warnings, Note: The design is not associated with scan def, st ignore sean def for placement, :c2_shel] > set_epp_opt ame place.coarse.continus_on missing scandef -value tru Activity 2 Bounds are placement constraints given toa particular group of eels to foree them toa certain area ofthe hip To create placement bounds run the below comChipedgé Perform Coarse Places Now, perform coarse places cells nt on the current design, which will place the standard the eore area shell > create gestion Set Para We had rend TLU-plus files during design import stage and ic Parameters ined ther as best_para and \worst_para here we consider them as enrly spec and late spec respectively Perform Placement Optimization Once the coarse placement is completed, need to optimize the placed design for timing, electrical DRC violations, area, power, and routability. Then legalize the design placement. Run the following command to perform placement optimization, jell > place opt -to final_opto Cheek legality (Once placement is done we look at the diferent aspects and statistic ofthe design andl check fst has met our expectations er not Activity 3 = eek the uses of the command legalize_placement| jee shell > man legalize placement the report for errors and We 5 Chipedge Technologies Pvt itd., BangaloreChipEdgé Cheek for Global Route Congestion, Cell density and Pin Density. Fig 8 ‘Sinus o Global rote congetion, check ell density and pin density map ‘Activity 4 4. Ren the command > roport_de Number of Standard ell [Number of macros Number of Buer/ Inverters Area of Core aun 2 shell > report utiliza . tion_configuration ~scops block Utilization Ratio 3.Run report_gor wns‘Number of Violating Paths Slack. oR 4.Run ice? shell > report timing report_constraints -all_violators [Number of Max_capacitance violations ‘Number of Max transition violation Make the logical connection of PG nets for all the standard eels, sce2_shell > conn name == VDD") Sce2_shell > conn name == VSS") Saving the block. pg_net -net VDD [get_pins -hier * -filter _pq_net -net VSS [get_pins -hier * -filter HAAAEOR EAA EEAEEEDEAEAEAED SND aeeoeeseseaeseaeDonEDeROR EER Chipedge Technologies Pvt Ltd., Bangalore