6.

Registers and Counters

Outline:
§ Introduction
§ Registers
§ Shift Registers
§ Counters
§ Summary

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6.1. Introduction
o Registers:
n Group of flip-flops capable of storing one bit of
information.
n An n-bit register stores n bits.
n Many combinational gates that perform data processing
o Flip-flops hold the binary information
o Gates determine how information is transferred to the flip-flops
o Counter:
n A register that goes through predetermined sequence of
binary states.
n Gates are connected to produce the prescribed sequence of
states.

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6.2. Registers
o Computer systems use n-bit numbers
n Too complex to worry about individual bits
n Data is stored in “registers”
o What functions should a register
support?
n Store data (and states)
n Getting data in
o In parallel
o In serial

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Parallel versus Serial Transfer
o Serial communications:
n Provides a binary number as a sequence of binary digits, one after
another, through one data line.

o Parallel communications:
n Provides a binary number through multiple data lines at the same
time.

o Mixed: serial/parallel communications:

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Simple Parallel Load Register
o Parallel load:
n All n bits can be stored at the same time
o Straightforward circuit
n n D flip-flops
n Shared clock
n Shared reset
o What is the problem with this
register?
n How long is data stored?
n In some cases, there is a requirement to
hold/store the current data for some time.
o D flip-flops are set on each clock cycle
n Undesired if we want to store data
n Undesired if input requires time to stabilize
o Suggested improvement?

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Parallel Load Register
o Register should only
load when specified
o Design choices:
n Intercept clock signal
o Not desirable, because of added
clock delay
n Feedback flip-flop value
o Circuit Operation:
n When loading (Load = 1),
input is fed to flip-flop DA (t + 1) = LoadA0 (t ) + LoadI 0
n When not loading (Load DB (t + 1) = LoadA1 (t ) + LoadI1
=0), current state is DC (t + 1) = LoadA2 (t ) + LoadI 2
“recycled”! DD (t + 1) = LoadA3 (t ) + LoadI 3

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Serial Data Transfer
o What are the limitations of a parallel load
register?
n Requires n data lines
n Can be expensive for 32-bit or 64-bit registers
o Serial data transfer common in digital systems
n Transfer of information one bit at a time
o Examples:
n Serial port on PC
n USB (Universal Serial Bus)
n Ethernet (and many other) network devices
n Programmable and reconfigurable devices (FPGA, PLD)
o Tradeoffs between serial vs. parallel?
n Serial requires only single wire
n Serial requires higher data rate to achieve same throughput
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6.3. Shift Registers
o Serial transfer:
n Load bits individually
n How should we specify which bit is being loaded?
o Serial loading by shifting is simplest
n Does not require any control bits
n One bit per clock tick

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Serial Transfer Example
o Serial transfer from register A to register B:
o Example:
n Assume A= 1011 and B = 0010
n What are the register values at T1 to T4.

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Serial Addition
o Addition is a “serial”
process
n Need to determine carry before
next significant bit is added
n We can use shift registers to
add bits one-by-one
n Serial adder
o Initial state:
n Augend and addend in A and B
o Shift control
n Controls (stops) addition
o How can we handle carry?
n Feedback via D flip-flop
n Carry is saved in DFF Q
o Where is the result?
n Register A after n shifts

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Universal Shift Register
o Shift registers are useful
n We want to use it as a basic building block
n Used in binary operations such as multiplications,
divisions in calculators and computers.

o Universal Shift Register

n Control functions
o CLEAR: reset register to 0
o CLOCK: synchronizes operation
o SHIFT-RIGHT: shifts right (incl. serial I/O)
o SHIFT-LEFT: shifts left (incl. serial I/O)
o PARALLEL-LOAD: parallel transfer of register value
o PARALLEL OUTPUT: n data lines
o NO OPERATION: state remains unchanged
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Universal Shift Register…
o Circuit and Control
n When s1s0=00, register
keeps its previous values
and no change in next
clock edge
n When s1s0=01, register
shifts to the right and
serial input bit becomes
MSB and so on…

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6.4 Counters
o A counter is a register that goes through
a predetermined sequence of states
upon application of input pulses
o Example: n-bit binary counter
n Counts from 0 through 2n-1
o Two flavors:
n Ripple counter
n Synchronous counter
n Difference:
o How flip-flops are triggered when propagating updates

o Count-down counter
n Also counter, but in reverse direction
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 Ripple Counter
o Circuit with T flip-flops
n Are flip-flops positive or negative edge
triggered?
n Count signal toggles (changes state) A0
n Low-order flip flop provides trigger for
adjacent flip flop
n Not all flops change value
simultaneously
o Lower-order flops change first

o Example:
n Current state: A3A2A1A0 =1011
n Count toggles A0, falling edge
n Falling Edge A0 toggles A1
n Falling Edge A1 toggles A2
n Rising edge A2 – no change on A3
n New state: A3A2A1A0 =1100
o Similar with D flip-flop
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Ripple Counter another example
o Similar to T flop previous example.

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Asynchronous Ripple Counters
o Ripple counter:
n FFs respond one after another in a rippling effect
n Each FF output drives the CLK input of the next FF.
o FFs do not change states in exact
synchronism with the applied clock pulses
n There is delay between the responses of
successive FFs
n Undesirable because of transition states
n Example:
o Desired: A3A2A1A0 = 0011 g A3A2A1A0 = 0100
o A0 is first triggered by the count pulse to change to 0,
because A0 changes from 1 to 0 then A1 changes from
1 to 0, then because A1 changes from 1 to 0, A2
changes from 0 to 1 and since A2 changes from 0 to 1
no change for A3. So flip flops change in succession.
o Real: 0011 g 0010 g 0000 g 0100

o Remedy: Synchronous counter

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Synchronous Counters
o Synchronous (parallel)
counter
n State switches with common
clock
n All FFs change at same time
n What is necessary to switch
state in one step?
o Need to know which bits to toggle
o Very simple “carry look-ahead”
n Remember
o If J = K = 0, flip-flop maintains old
value
o If J = K = 1, flip-flop toggles

o Circuit:
n AND gates test which bits will
roll over
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Binary Counter (Synchronous)
o The least significant bit is
complemented for every pulse
o A flip flop in any other position is
complemented when all the other
LSBs are complemented.
o Example
n A3A2A1A0=0011 to A3A2A1A0=0100
count
o A0 changes for each clock pulse as
long as count is enabled.
o A1 changes since A0 was
previously 1
o A2 changes since A1 & A0 were
previously 1
o A3 doesn’t changes since A2 wasn’t
previously 1 like A1 and A0.

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Up –Down converter
o Goes in the reverse order
n Example from 1111 g 0000
n Bit in the least significant
position is complemented for
each pulse.
n A bit in any other position is
complemented if all lower
significant bits are equal to zero.
n It is just the opposite of Up
counter. Example for Count Down
o Circuit
A3(t)A2(t)A1(t) A0(t):1111
n Same circuit can be used for
both up and down counter A3(t+1)A2(t+1)A1(t+1)
based on control signal A0(t+1):1110

n Up=1, circuit counts up

n Down=1 and Up=0, circuit
counts down.
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6.5. Summary
o Registers and Counters
n Constructed from flip-flops
n Registers store data
n Counters capable of going through predefined states
o Shift Registers
o Binary Counters
n Up and Down counters
o Synchronous and Asynchronous Counters
n Ripple Counters
n Synchronous up and down counters

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