Cypress Traveo Series

Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content

The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers

Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S6J3350 Series
32-bit Microcontroller
Traveo™ Family
The Traveo™ family expands the company’s automotive applications, scalability and high performance into one line-up and at the
same time adds new features to fulfill the latest requirements of the automotive industry. Based on the powerful Arm® Cortex®- R5F
core in single operations, it offers state-of-the-art real time performance, safety and security features. The family supports the latest
in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated
features to increase data security in the car.
S6J3350 is a microcontroller series for body and gateway.
Features
◼ System
 32bit Arm Cortex-R5F CPU core at up to 240 MHz
Applications
 General purpose I/O port: up to 148 ◼ Body Control Module(BCM)
 12-bit A/D converter: up to 64 channels
 External interrupt: up to 24 channels ◼ Lighting
 Base timer: up to 64 channels ◼ Gateway
 32-bit reload timer: up to 6 channels
 32-bit free-run timer: 8 channels
 Input capture unit: 12 channels
 Output compare unit: 12 channels
 Built-in CR oscillator
 Real-time clock
 DMA controller: 16 channels
 JTAG debug interface
◼ Communication
 CAN-FD: up to 8 channels
 Multi-functionserial interface: up to 12 channels,
selectable protocol: UART, CSIO, LIN and I2C
 Ethernet AVB MAC
◼ Memory
 HyperBus™ Memory interface
 DDR High Speed SPI
 External BUS interface
◼ Security and Safety

 Secure Hardware Extension – SHE
 Safety features, such as MPU, TPU, ECC and others
 CRC generator: 1 channel
 Watchdog timer with window function
 Low voltage detector
 Clock supervisor for all source clocks
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-10634 Rev. *J Revised August 5, 2020
S6J3350 Series
Table of Contents
1. Overview ........................................................................ 3 6.2 Remark ................................................................... 44
1.1 Overview ................................................................... 3 7. Port Configuration ...................................................... 45
1.2 Document Definition .................................................. 3 7.1 Resource Input Configuration Module .................... 45
2. Function List ................................................................. 4 7.2 Port Output Function Configuration ...................... 135
2.1 Function List .............................................................. 4 8. Precautions and Handling Devices ......................... 146
2.2 Optional Function ...................................................... 6 8.1 Handling Precautions ............................................ 146
3. Product Description ...................................................... 9 8.2 Handling Devices .................................................. 149
3.1 Overview ................................................................... 9 9. Electric Characteristics............................................ 151
3.2 Product Description ................................................... 9 9.1 Electrical Characteristics....................................... 151
4. Package and Pin Assignment .................................... 14 10. Acronyms .................................................................. 243
4.1 Pin Assignment ....................................................... 14 11. Ordering Information................................................ 244
4.2 Package Dimensions ............................................... 17 12. Errata ......................................................................... 245
5. IO Circuit Type ............................................................ 21 13. Appendix ................................................................... 247
5.1 I/O Circuit Type ....................................................... 21 13.1 Application 1: JTAG Tool Connection ................... 247
5.2 Note ......................................................................... 25 14. Major Changes .......................................................... 248
6. Port Description .......................................................... 26 Document History .......................................................... 305
6.1 Port Description List ................................................ 26 Sales, Solutions, and Legal Information ...................... 307
Document Number: 002-10634 Rev. *J Page 2 of 307

S6J3350 Series
1. Overview
1.1 Overview
S6J3350 is a microcontroller series which is to be applied to automotive systems representative of body and gateway.
1.2 Document Definition

The related documents of S6J3350 are as follows:
Table 1-1: Document Definition
Document Type Definition Primary User Document Code
This document.
Investigator and Hardware
S6J3350 Datasheet 002-10634
The function and its characteristics are Engineer
specified quantitatively.
S6J3300 Series 32-bit Microcontroller
Traveo™ Family Hardware Manual
S6J3300 Hardware
Software Engineer 002-10185
Manual
The function and its operation of
S6J3300 series are described.
32-Bit Microcontroller Traveo™ Family
S6J33xx, S6J34xx, S6J35xx Series
Traveo™ Platform Hardware Manual Platform Part
Software Engineer 002-07884
Hardware Manual
The function and its operation of CPU
core platform are described.
002-04455
002-04446
The reference software, sample 002-09716
Application Note application, the reference board design, Software and Hardware Engineer 002-04452
and so on are explained. 002-04096
002-12061
002-02495
Notes:
− Refer all documents for the system development.
− "Primary user" is a most likely an engineer for whom the document is the most useful.
− The description of the datasheet and the S6J3300 Hardware Manual should precede the duplicated description of TraveoTM
Platform Hardware Manual.
− TraveoTM Platform Hardware Manual is expected to be used as dictionary of platform specification.

S6J3350 Series
2. Function List
2.1 Function List
This table shows the functions which are implemented in S6J3350 series.
Table 2-1: Function List
Function Description Remarks
CPU core Arm Cortex R5F
FPU Available
PPU Available
MPU Available
TPU Available
Endian Little endian
Core clock frequency 240 MHz
HPM bus frequency 200 MHz
LLPM bus frequency 240 MHz
Resource clock frequency 80 MHz (Max)
Slow clock:100 kHz,
Embedded CR oscillation Fast clock: 4 MHz See 9.1.4.1
(Center frequency)
PLL PLL0, 1, 2, 3
SSCG PLL SSCG0, 1, 2, 3
Clock supervisor Available
DMA 16 ch
Boot-ROM 16 Kbyte
JTAG Available
Data cache 16 Kbyte
Instruction cache 16 Kbyte
Program FLASH Option See 2.2.1
Work FLASH 112 Kbyte
TCRAM 128 Kbyte
System SRAM 384 Kbyte
Backup RAM 32 Kbyte
Security (SHE) Option
Low latency interrupt Available
Power domain 5 domains
5 V(VCC5, VCC53),
External power supply 3 V(VCC3, VCC53),
1.2 V(VCC12)
Embedded LDO power supply
Available
for 5.0V
Low voltage detection of
Available
external power supply
Low voltage detection of
Available
internal LDO output
Hardware watchdog timer Available
Software watchdog timer Available
Package Option See 2.2.1
AUTOSAR AUTOSAR 4.0.3
General Purpose I/O Option See 2.2.3
Up/down counter 2 ch
(FRT 5 ch x ICU 6 ch x OCU 6 ch) + (FRT 3 ch x ICU 6 ch x OCU 6
I/O timer
ch)
32bit Reload timer 6 ch
Real time clock Available Automatic calibration
Base timer 32 units (64 ch)
12bit-A/D converter 2 unit - 64 input ports (Max) See 2.2.3
CRC 4 units
Programmable CRC 1 unit

S6J3350 Series
Function Description Remarks

Source clock timer 4 ch
NMI Available
External interrupt 24 ch
Internal interrupt 512 vectors
DDR HSSPI 1 ch A type of Quad SPI
See the AC
Hyper BUS 1 ch specification on
9.1.4.16
Multi-function serial interface 12 ch
CAN-FD 8 ch
CAN-FD RAM (ECC 16 KB/ch
supported) It equivalents to 128 message buffer per channel of MCAN module
Ethernet AVB 1 unit See 2.2.1
External BUS 1 ch
Notes:
− The options are described in 2.2 Optional Function.

S6J3350 Series
2.2 Optional Function

2.2.1 Basic Option
This figure shows the optional function and the part number relations of the series.
Figure 2-1: Option and Part Number for S6J3350 Series
S 6 J 3 3 x x x x x x x x x x x x
Ordering options 7 digit
Revision:
Digit Description
Fixed Operation frequency of embedded Program Flash and CPU,
C
Fixed Stabilization time for sub oscillator
D Fixed TCFLASH Sector Write Permission and Data Retention after Reset
E Leakage current improvement
Option:
Digit SHE MK_CEER* VCC5 DVCC
S 5V
5V
A ON
3V
B Fixed to 3V
U Enable 5V
5V
C OFF
3V
D 3V
T 5V
5V
E ON
3V
F 3V
Selectable
V 5V
5V
G OFF
3V
H 3V
* Chip Erase Enable Register
Pin count:
Digit Pin Count
H 144pin
J 176pin
K 208pin
Memory Size:
Flash RAM
Digit
Program Work Main Backup
E 4,160KB 112KB 512KB 16+16KB
D 3,136KB 112KB 384KB 16+16KB
Function:
Digit Ethernet
5 Yes
Product series
Identifier: Automotive MCU
Notes:
− This table only shows the relations between the optional function and the part numbers. That is, all products are not
necessarily available for orders. See 11 Ordering Information, and confirm actual availabilities of products.
− The main RAM size is configured as follows according to Digit.
E: TCRAM 128KB + System-RAM 384KB
D: TCRAM 128KB + System-RAM 256KB

S6J3350 Series
2.2.2 ID
ID is specified for each function digit and revision which is defined at Figure 2-1.
Function Digit Revision Chip ID JTAG ID
S,U,T,V C 0x10122100 0x1000B5CF
D, E 0x10122200
A,C,E,G C 0x10128100
D, E 0x10128200
B,D,F,H C 0x10120100
D, E 0x10120200
2.2.3 Restriction
Some functions have restrictions which depend on package pin counts.
Table 2-2: Pin Restriction
Function TEQFP176 TEQFP144
AN0~7, AN10~11,
AN0~3, AN19~20,
AN14~15, AN19~20,
Analog input port (12bit-ADC) AN22~23, AN27, AN33~38,
AN22~23, AN25~30,
AN48
AN33~38, AN48
P4_00 ~ P4_31
General Purpose I/O P4_00 ~ P4_31
P3_00 ~ P3_31
RX0_1, TX0_1
RX0_2, TX0_2
RX1_1, TX1_1
RX0_2, TX0_2 RX2_1, TX2_1
RX3_2, TX3_2 RX3_1, TX3_1
CAN RX4_0, TX4_0 RX3_2, TX3_2
RX7_0, TX7_0 RX4_0, TX4_0
RX7_1, TX7_1 RX5_1, TX5_1
RX6_1, TX6_1
RX7_0, TX7_0
RX7_1, TX7_1
PPG16/17/18/19_TOUT0_0
PPG16/17/18/19_TOUT2_0
PPG20/21/22/23_TOUT0_0
PPG20/21/22/23_TOUT2_0
PPG16/17/18/19_TOUT0_0 PPG24/25/26/27_TOUT0_0
PPG16/17/18/19_TOUT2_0 PPG24/25/26/27_TOUT2_0
PPG20/21/22/23_TOUT0_0 PPG28/29/30/31_TOUT0_0
PPG20/21/22/23_TOUT2_0 PPG28/29/30/31_TOUT2_0
PPG24/25/26/27_TOUT0_0
PPG24/25/26/27_TOUT2_0 PPG16/17/18/19/20/21_TIN1_0
BaseTimer
PPG28/29/30/31_TOUT0_0 PPG22/23/24/25/26/27_TIN1_0
PPG28/29/30/31_TOUT2_0 PPG28/29/30/31_TIN1_0
PPG16/17/18/19/20/21_TIN1_0 PPG4/5/6/7/8/9_TOUT0_1
PPG22/23/24/25/26/27_TIN1_0 PPG4/5/6/7/8/9_TOUT2_1
PPG28/29/30/31_TIN1_0 PPG10/11/12/13/15_TOUT0_1
PPG10/11/12/13/14/15_TOUT2_1
PPG0/1/2/3/4/5_TIN1_1
PPG6/7/8/9/10/11_TIN1_1
PPG12/13/14/15_TIN1_1
MDQM1
ExtBus - MAD15~21
MDATA8~15

S6J3350 Series
Function TEQFP176 TEQFP144
EINT0_4, EINT1_1
EINT1_4, EINT1_5
EINT2_1, EINT2_2
EINT2_4, EINT3_1
EINT3_2, EINT3_4
EINT4_2, EINT4_4
EINT5_4, EINT5_5
EINT6_1, EINT6_4
EINT1_4, EINT1_5 EINT7_1, EINT7_4
External Interrupt
EINT17_5, EINT18_1
EINT18_3, EINT18_5
EINT19_1, EINT19_3
EINT19_4, EINT20_1
EINT20_2, EINT20_3
EINT21_1, EINT21_3
EINT22_1, EINT22_3
EINT23_3, EINT23_4
Notes:
− See multiplexed functions on pin assignment sheet.
− The optional restriction will be added without notification.

S6J3350 Series
3. Product Description
3.1 Overview
This chapter explains the product features of S6J3350 series. The description of this chapter should precede the duplicated
description on Traveo™ Platform Hardware Manual.
3.2 Product Description

The table shows features.
Table 3-1: Product Features
Feature Description
40 nm CMOS technology with embedded FLASH
Technology Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
Developed according to ISO26262, safety target ASIL-B
Functional Safety The product series has some functional safety features suited for ASIL-B application.
Peripherals See function list.
Power Domain (PD) See the Traveo™ Platform Hardware Manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,
PD4_1 and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,
and "0" is always read from the reset factor flags of them.
This series doesn't support partial wakeup for PD6.
See the Traveo™ Platform Hardware Manual in detail.
− Standard 5-pin JTAG interface
Debug and Trace
− 4 kB Embedded Trace Buffer
4-bit trace support for TEQFP package.
Main and sub oscillator is available.
System Control − A wide range of 3.6 – 16 MHz is available for main oscillator
− 32 KHz is available for sub oscillator
Sub clock is enable/disable by register settings
Clock CLK_CLKO (Clock Output Function) is supported.
Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)
Stabilization time is as followings.
Embedded CR oscillation
− 30 us or more for 4 MHz (Fast clock)
− 30 us or more for 100 kHz (Slow clock)
Clock Supervisor See the Traveo™ Platform Hardware Manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and internal
circuit is implemented.)
RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)
− Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD
pin
− Release factor: Inputting “H” level to RSTX pin
Reset See the Traveo™ Platform Hardware Manual in detail.
Following resets are not mounted on this device.
− SRSTX (and nSRST pin)
The product series does not support EX5VRST and writing EX5VRSTCNT bits in
SYSC0_SPECFGR has no effect.

S6J3350 Series
Feature Description

Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the
Hardware watchdog bit
ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).
The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and
internal circuit is implemented.)
Standby mode with 5 V (or 3 V) single external power supply is available.
Standby mode
Turning off the 1.2 V external power supply in standby mode is available.
The long term pulse of the indicator PWM can be outputted during RTC Standby mode.
Use case assumption is following.
PLL
− Peripherals
− Trace clock
SSCG
− CPU core
PLL / SSCG PLL − Hyper BUS
− DDR-HSSPI
Product supports down spread and center spread modes with the conditions defined in 9.1.4.3
"Internal Clock Timing".
Stabilization time is as follows.

− 100 us for PLL
− 200 us for SSCG
External Interrupts See the Traveo™ Platform Hardware Manual in detail.
NMI
1 NMI pin.
MPU16 AHB: See the Traveo™ Platform Hardware Manual in detail.
MPU for AXI: ch.0
MPU for AHB: ch.1
Additional MPU for Ethernet AVB. They are described on the chapter of MPU for AHB and MPU
Memory Protection for AXI
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,

− Lock: 0x112ABB56
− Unlock: 0xACCABB56
Peripheral Protection
Protected peripherals are described in the base address map.
Internal Memories 384 kByte
System SRAM 1 wait cycle is necessary for RAM read at over 120 MHz.
Internal Memories
128 kByte
TCRAM
32 kByte
Internal Memories Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the
Backup RAM memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM
is not supported and cannot be used.

S6J3350 Series
Feature Description
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less.
0-wait-cycle: 80 MHz or less.
2-wait-cycle: more than 160 MHz.
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5 MHz or less.
Embedded 12-wait-cycle: 160 MHz or less.
Program/Work Flash
Memory
The wait-cycle setting see the Traveo™ Platform Hardware Manual in details.
The CLK_FCLK maximum frequency should be referred in 9.1.4.3.
Erase suspend is supported. Reading and writing to the other sector are possible when Flash
Erase is suspended.
Serial Flash programing and Parallel Flash programing are supported.
Margin mode is not supported.
PD1: Always ON
PD2: Cortex R5F platform/ additional peripherals
Internal Power Domain PD4: Backup RAM in Always On domain
PD6: Peripherals in Always On domain
* The chapter of the block diagram explains in detail.
5 V, and 3 V, 1.2 V external power supply is required.
Built in LDO provides internal power supply for Always On region (PD1).
Power Supply 1.2 V external power supply control pin is supported.
3 V external power supply could be controlled by GPIO.
There are constraints of power on/off sequence.
LVD for external voltage is supported.
Low Voltage Detection LVD for internal voltage is supported.
See 9.1.4.11 and 9.1.4.12 .
Low voltage detection for RVD for RAM retention is effective during the standby mode only. That is, it is only for the
RAM retention (RVD) Backup RAM of 32 KB that the function is available.
Resource inter-connect The output signal of some resources can be inputted to the other resource.
5 V general purpose I/O
3 V general purpose I/O
Multi input level and multi output drivability
I/O Ports
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain.
12 bit resolution, 2 unit(Unit0 is possible to select channels 0-31. Unit1 is possible to select
channels 32-63.)
64 channels of analog input for TEQFP208
35 channel of analog input for TEQFP144
External trigger and timer trigger are available.
The description of the A/D converter function should be referred in the S6J3300 Hardware
A/D Converter
Manual. Though the chapter of I/O port in Traveo™ Platform Hardware Manual describes
another A/D converter function, do not refer it.
A/D Channel Control Register (ADC12Bn_CHCTRL0)[bit5:0] ANIN[5:0]: Analog Input Selection
bits.
This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).
AN39 to AN63 are not support for S6J335xxAx, S6J335xxCx, S6J335xxEx, and S6J335xxGx
option.
CRC See the Traveo™ Platform Hardware Manual in detail.
Programmable CRC DMA support

S6J3350 Series
Feature Description
Base Timer
A unit consists of a pair of 16bit base timers. 32 units, that is, 64 channels of base timers are
available.
Reload Timer See the Traveo™ Platform Hardware Manual in detail.
I/O Timer See the Traveo™ Platform Hardware Manual in detail.
Up/Down Counter See the Traveo™ Platform Hardware Manual in detail.
Multi-Functional Serial Only 2 ports of MFS have the dedicated I/O for I2C.
(MFS) See I2C timing in 9.1.4.6 Multi-Function Serial in detail.
The I2C is not designed to be hot swappable.
CTS/RTS is not mounted (hardware flow control is not supported for this series.)
Flexible data rate is supported.
16 KB/ch of message RAM is available.
CAN-FD The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function
of the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion
Control Register (FDFECR) is not writeable.
Real Time Clock (RTC)
See the TraveoTM Platform Hardware Manual in detail.
with auto-calibration
DDR High Speed SPI ch.0: HSSPI as a MCU peripheral
ch.0: Hyper Bus as a MCU peripheral
The following register is not supported and cannot be used.
− Controller Status Register (HYPERBUSIn_CSR)
− Interrupt Enable Register (HYPERBUSIn_IEN)
Hyper BUS I/F − Interrupt Status Register (HYPERBUSIn_ISR)
− Write Protection Register (HYPERBUSIn_WPR)
− Test Register (HYPERBUSIn_TEST)
GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can
select using HyperBus of Traveo™ Platform Hardware Manual.
External Interrupt Capture
See the TraveoTM Platform Hardware Manual in detail.
Unit (EICU)
10/100 Mbps
Ethernet AVB MII-Interface
Supports Audio-Video Bridging (AVB)
SHE See the Traveo™ Platform Hardware Manual in detail.
Source Clock Timer See the Traveo™ Platform Hardware Manual in detail.
TEQFP208: 22 bit address and 16 bit data
External BUS TEQFP176: 22 bit address and 16 bit data
TEQFP144: 15 bit address and 8 bit data
PSC (PSC_1) output is used for external 1.2 V power supply module control and automatically
switched with the following condition.
"High": Request to supply VCC12
- "Power ON Reset" is released
Power Supply Control - CPU wakes up from PSS shutdown mode
(PSC) "Low": Request to stop supplying VCC12
- CPU transfers from RUN mode to PSS shutdown mode.
For timing chart of output signals include PSC in detail, see the "S6J3300 Hardware Manual"
and chapter "State Transition"

S6J3350 Series
3.2.1 Ethernet
The following functions are not supported.

Functions Remarks
External FIFO Interface
Additional Low Latency TX FIFO Interface for DMA configurations
MAC Transmit Block
- half-duplex
- collision
- back pressure
MAC Filtering Block
- external address match
- Wakeup On Lan
Energy Efficient Ethernet support
LPI Operation in Cadence IP
PHY Interface
- GMII
- SGMII
- TBI
10/100/1000 Operation
- 1000 M
SGMII Operation
Jumbo Frames
Physical Control Sub-Layer

S6J3350 Series
4. Package and Pin Assignment

4.1 Pin Assignment
Alphabets with pin numbers are signs specify I/O circuit type.
4.1.1 TEQFP-208 Pin Assignment
Figure 4-1: TEQFP-208 (S6J335xKyz *1)
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SCS43_0
SCS42_0
SCS32_1
SCS31_1
SCS23_1
SCS22_1
SCS21_1
SCS20_1
SOT2_1
SDA11
SDA10
SCL12
SCL11
SCL10
SDA4
SDA9
SCL4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG14_TOUT0_1
PPG13_TOUT2_1
PPG13_TOUT0_1
PPG12_TOUT2_1
PPG12_TOUT0_1
SCS111_0
SCS110_0
SCS100_0
EINT20_5
EINT19_5
SCS41_0
SCS40_0
SCS33_1
SCS30_1
SCK12_0
SOT11_0
SCK11_0
SOT10_0
SCK10_0
SCS91_0
SCS90_0
SIN12_0
SIN11_0
SIN10_0
SOT4_0
SCK4_0
SOT3_1
SCK3_1
SOT9_0
SIN4_0
SIN3_1
SDA12
RX7_1
TX7_1
-
-
-
-
-
-
-
-
-
-
-
-
-
EINT20_4 PPG6/7/8/9/10/11_TIN1_0
EINT18_5 PPG12/13/14/15_TIN1_1
EINT6_5 PPG12/13/14/15_TIN1_0
EINT17_5 PPG15_TOUT2_1
ADTRG1_2
ADTRG0_1
EINT9_5 SCS120_0
EINT23_5
EINT22_5
EINT21_5
EINT15_5
EINT14_5
EINT13_5
EINT12_5
EINT11_5
EINT7_5 SOT12_0
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT0_0
-
-
-
-
-
-
-
-
-
-
-
PPG28/29/30/31_TIN1_0
SCK2_1
SIN2_1
PPG31_TOUT2_0
PPG31_TOUT0_0
PPG30_TOUT2_0
PPG30_TOUT0_0
PPG29_TOUT2_0
PPG29_TOUT0_0
-
-
MDATA7 -
MDATA6 -
MDATA5 -
MDATA4 -
MDATA3 -
MDATA2 -
MDATA1 -
MDATA0 -
-
-
-
-
-
MDATA11 -
MDATA10 -
MDATA9 -
MDATA8 -
-
-
-
-
-
MCSX1
MCSX0
MAD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MDATA15
MDATA14
MDATA13
MDATA12
EINT10_5
EINT23_4
EINT19_4
EINT2_1
EINT8_5
EINT5_5
EINT1_5
AN63
AN62
AN61
AN60
AN59
AN58
AN57
AN56
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN48
AN47
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC53
VCC12
DVCC
DVCC
DVCC
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
P2_13
P2_12
P2_11
P2_10
P3_31
P3_30
P3_29
P3_28
P2_09
P3_27
P3_26
P3_25
P3_24
P4_31
P4_30
P2_08
P4_29
P2_07
P2_06
P2_05
P4_28
P2_04
P2_03
P2_02
P4_27
P2_01
P2_00
P4_26
P1_31
P1_30
P1_29
P4_25
P1_28
P1_27
P1_26
P4_24
P1_25
DVSS
DVSS
VSS
VSS
S2
Q
Q
Q
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
P
P
P
P
P
P
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
-
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
- - - - - - - - - - - - - VCC53 - 1 156 - DVSS - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 ● 155 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 154 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 153 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 152 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - -
- - - - - - - - - RX0_2 PPG16_TOUT0_0 EINT7_1 RXCLK_1 P4_00 T 6 151 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - -
- - - - - - - - - TX0_2 PPG16_TOUT2_0 EINT9_1 RXER_1 P4_01 T 7 150 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - -
- - - - - - - - - - PPG17_TOUT0_0 EINT10_1 RXDV_1 P4_02 T 8 149 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 9 148 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 10 147 - DVCC - - - - - - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 11 146 - DVSS - - - - - - - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 12 145 - AVSS - - - - - - - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 13 144 - AVRL5 - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 14 143 - AVRH5 - - - - - - - - - - - -
- - - - - - - - SCS170_1 RX3_2 PPG17_TOUT2_0 EINT2_2 TXCLK_1 P4_03 T 15 142 - AVCC5 - - - - - - - - - - - -
- - - - - - - - SCK17_1 TX3_2 PPG18_TOUT0_0 EINT3_2 TXEN_1 P4_04 T 16 141 G P4_23 AN38 EINT10_4 PPG28_TOUT0_0 TX7_0 SCS160_1 - - - - - - -
- - - - - - - - - SOT17_1 PPG18_TOUT2_0 EINT4_2 TXD0_1 P4_05 T 17 140 E P4_22 ADTRG1_0 EINT22_1 PPG22/23/24/25/26/27_TIN1_0 RX7_0 SCS161_1 - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 18 139 H P1_16 ADTRG0_0 - EINT9_4 - PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 19 138 G P4_21 AN37 EINT8_4 PPG27_TOUT2_0 SCK16_1 - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 20 137 G P4_20 AN36 EINT7_4 PPG27_TOUT0_0 TX4_0 SOT16_1 - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 21 136 G P4_19 AN35 EINT16_1 PPG26_TOUT2_0 RX4_0 SIN16_1 - - - - - - -
- - - - - - - - - - - - - VCC53 - 22 135 - VCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS - 23 134 - VSS - - - - - - - - - - - -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCK1_1
SOT1_1
-
SIN1_1 PPG4_TOUT0_1
PPG4_TOUT2_1
PPG5_TOUT0_1
- -
EINT1_1
EINT9_2
EINT10_2
MAD15
MAD16
MAD17
- -
TXD1_1
TXD2_1
TXD3_1
VCC12
P3_00
P3_01
P3_02
-
T
T
T
24
25
26
27
TOP VIEW 133
132
131
130
G
G
-
-
VCC12
VCC12
P4_18
P4_17
-
-
AN34
AN33
-
-
EINT6_4
EINT5_4
-
-
PPG26_TOUT0_0
PPG25_TOUT2_0
-
-
SIN12_1
SOT12_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS10_1
SCS11_1
-
-
PPG5_TOUT2_1
PPG0/1/2/3/4/5_TIN1_1
-
-
EINT11_2
EINT12_2
PPG19_TOUT0_0
PPG19_TOUT2_0
MAD18
MAD19
EINT13_2
EINT14_2
TXER_1
RXD0_1
RXD1_1
RXD2_1
P3_03
P3_04
P4_06
P4_07
T
T
T
T
28
29
30
31
TEQFP-208 129
128
127
126
H
G
G
G
P1_15
P1_14
P3_23
P3_22
AN32
AN31
AN30
AN29
EINT16_0
EINT15_0
EINT4_4
EINT19_1
-
-
TX6_1
RX6_1
PPG5_TOUT2_0
PPG5_TOUT0_0
SCS120_1
SCS91_1
OCU10_OTD0_0
OCU9_OTD1_0
-
-
ICU10_IN1_0
ICU10_IN0_0
-
-
TIN49_0
TOT48_0
-
-
SCK17_0
TX3_0
-
-
SCK12_1
SIN17_0
-
-
SCL17
SYSC0_CLK_1
-
-
INDICATOR0_1
-
-
-
-
-
-
-
- - - - - - - - SCS12_1 SIN4_1 EINT15_2 MAD20 RXD3_1 P3_05 T 32 125 G P3_21 AN28 EINT3_4 TOT49_1 SCS90_1 - - - - - - - -
- - - - - - - - SCS13_1 SOT4_1 EINT16_2 MAD21 MDIO_1 P3_06 T 33 124 E P3_20 EINT2_4 PPG6/7/8/9/10/11_TIN1_1 TIN49_1 TX5_1 SOT9_1 - - - - - - -
- - - - - - - - SCK4_1 EINT17_2 - MOEX - P0_14 S 34 123 E P3_19 EINT17_1 PPG11_TOUT2_1 OCU10_OTD1_1 ICU10_IN1_1 RX5_1 SCK9_1 - - - - - -
- - - - - - - - SCS40_1 EINT18_2 - MWEX - P0_15 S 35 122 E P3_18 EINT20_1 PPG11_TOUT0_1 OCU10_OTD0_1 ICU10_IN0_1 SIN9_1 - - - - - - -
- - - - - - - - SCS41_1 EINT19_2 - MCLK - P0_16 S 36 121 - VSS - - - - - - - - - - - -
- - - - - - - - - - SCS42_1 EINT20_2 MDQM1 P3_07 T 37 120 - C - - - - - - - - - - - -
- - - - - - - SCS43_1 EINT21_2 - MDQM0 - RXCLK_0 P0_17 V 38 119 O MODE - - - - - - - - - - - -
- - - - - - - - EINT22_2 - MCSX2 MDC_1 RXER_0 P0_18 V 39 118 D PSC_1 - - - - - - - - - - - -
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 40 117 N RSTX - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 41 116 G P4_16 AN27 EINT1_4 PPG25_TOUT0_0 - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 42 115 G P3_17 AN26 EINT0_4 - PPG10_TOUT2_1 OCU9_OTD1_1 ICU9_IN1_1 TOT48_1 TX3_1 - - - -
- - - - - - - - - - - - - VSS - 43 114 G P3_16 AN25 EINT14_1 - PPG10_TOUT0_1 OCU9_OTD0_1 ICU9_IN0_1 TIN48_1 RX3_1 - - - -
- - - - - - - - - - - - - AVSS - 44 113 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - -
- - - - - - - - - - - - - NC A 45 112 L2 JTAG_TMS - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 46 111 L2 JTAG_TCK - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 47 110 L2 JTAG_TDI - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 48 109 M JTAG_TDO - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 49 108 L JTAG_NTRST - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 50 107 K X0 - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 51 106 K X1 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS - 52 105 - VSS - - - - - - - - - - - -
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
B
B
B
B
B
B
B
B
B
B
C
C
C
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
G
G
H
G
G
R
R
-
-
-
-
-
-
-
-
-
-
I
VCC3
P0_21
P0_22
P0_23
P0_24
P0_25
VSS
P0_26
VSS
VCC3
P0_27
P0_28
P0_29
P0_30
P0_31
VSS
VCC3
P1_00
P1_01
P1_02
VCC12
VCC12
VSS
VCC5
P4_08
P4_09
P4_10
P4_11
P3_08
P3_09
P3_10
P3_11
P1_03
P1_04
P3_12
P3_13
P1_05
P1_06
P3_14
P3_15
P1_07
P1_08
P1_09
P4_12
P4_13
P1_10
P4_14
P4_15
NMIX
X0A
X1A
VCC5
-
M_SDATA0_0
M_SDATA0_2
M_SDATA0_1
M_SSEL0
M_SDATA0_3
-
M_SCLK0
-
-
M_SDATA1_0
M_SDATA1_2
M_SDATA1_1
M_SSEL1
M_SDATA1_3
-
-
-
-
-
-
-
-
-
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
-
P1_11
P1_12
-
-
M_DQ3
M_DQ2
M_DQ1
M_DQ0
M_CS#_1
-
M_CK
-
-
M_RWDS
M_DQ4
M_DQ5
M_DQ6
M_DQ7
-
-
M_CS#_2
COL_0
CRS_0
-
-
-
-
EINT13_3
EINT14_3
EINT15_3
EINT16_3
EINT18_1
EINT6_1
EINT17_3
EINT8_1
EINT4_0
EINT5_0
EINT21_1
EINT18_3
EINT6_0
EINT7_0
EINT12_1
EINT19_3
EINT8_0
ADTRG1_1
EINT10_0
EINT20_3
EINT21_3
EINT11_0
EINT22_3
EINT23_3
-
EINT12_0
EINT13_0
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
TXD3_0
-
TXER_0
-
-
RXD0_0
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
MDC_0
EINT11_3
EINT12_3
-
-
-
-
PPG20_TOUT0_0
PPG20_TOUT2_0
PPG21_TOUT0_0
PPG21_TOUT2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
EINT9_0
-
PPG23_TOUT0_0
PPG23_TOUT2_0
-
PPG24_TOUT0_0
PPG24_TOUT2_0
-
PPG4_TOUT0_0
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
-
-
-
-
PPG16/17/18/19/20/21_TIN1_0
PPG22_TOUT0_0 PPG6_TOUT2_1
PPG22_TOUT2_0 PPG7_TOUT0_1
PPG7_TOUT2_1 OCU1_OTD1_1
-
-
-
-
-
-
-
-
-
-
-
OCU8_OTD0_0
OCU8_OTD1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
-
-
-
-
PPG6_TOUT0_1
PPG1_TOUT0_0
PPG1_TOUT2_0
PPG2_TOUT0_0
-
PPG3_TOUT0_0
-
-
PPG3_TOUT2_0
-
-
-
ICU9_IN0_0
ICU9_IN1_0
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCU0_OTD0_1
OCU0_OTD1_1
OCU1_OTD0_1
ICU1_IN1_1
ICU0_IN0_0
ICU0_IN1_0
ICU2_IN0_1
ICU2_IN1_1
ICU1_IN0_0
ICU1_IN1_0
ICU8_IN0_1
ICU8_IN1_1
OCU1_OTD0_0
PPG2_TOUT2_0
OCU2_OTD0_0
-
-
OCU2_OTD1_0
-
-
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU0_IN0_1
ICU0_IN1_1
ICU1_IN0_1
TOT1_1
AIN8
BIN8
TIN16_1
TOT16_1
ZIN8
AIN9
TIN17_1
TOT17_1
ICU2_IN0_0
OCU1_OTD1_0
ICU8_IN0_0
-
-
ICU8_IN1_0
-
-
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_1
TOT0_1
TIN1_1
RX1_1
TIN0_0
TOT0_0
TX1_1
SCK10_1
TIN1_0
TOT1_0
RX2_1
TX2_1
BIN9
ICU2_IN1_0
SCK16_0
-
-
SOT16_0
-
-
-
SCS160_0
SCS161_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIN8_1
RX0_1
TX0_1
SCS80_1
FRT0/1/2/3_TEXT
FRT4/8/9/10_TEXT
SIN10_1
TRACE3_1
RX0_0
TX0_0
SOT10_1
SCS100_1
TIN16_0
ZIN9
SCL16
-
-
SDA16
-
-
-
INDICATOR0_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCK8_1
SOT8_1
TRACE1_1
SIN0_0
SCK0_0
TRACE2_1
-
SOT0_0
SCS00_0
TRACE_CTL_1
TRACE_CLK_1
RX1_0
TOT16_0
TRACE_CTL_0
-
-
TRACE_CLK_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_1
-
-
SCL0
-
-
SDA0
TRACE1_0
-
-
TRACE2_0
TX1_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_0
-
-
-
-
SIN16_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE3_0
-
-
-
-
-
-
-
-
-
-
*1: x, y, z are selected from the following parameters:

x: E, D (Memory Size)
y: S, A, B, U, C, D, T, E, F, V, G, H (Option)
z: C, D, E (Revision)

S6J3350 Series

Figure 4-2: TEQFP-176 (S6J335xJyz *1)
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS43_0
SCS42_0
SCS32_1
SCS31_1
PPG14_TOUT0_1 SCS23_1
PPG12_TOUT0_1 SOT2_1
SDA11
SDA10
SCL12
SCL11
SCL10
SDA4
SDA9
SCL4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS111_0
SCS110_0
SCS100_0
EINT20_5
EINT19_5
SCS41_0
SCS40_0
SCS33_1
SCS30_1
SCK12_0
SOT11_0
SCK11_0
SOT10_0
EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0
SCS91_0
SCS90_0
SIN12_0
SIN11_0
SIN10_0
SOT4_0
SCK4_0
SOT3_1
SCK3_1
SOT9_0
SIN4_0
SIN3_1
SDA12
-
-
-
-
-
-
-
-
-
-
-
-
EINT18_5 PPG12/13/14/15_TIN1_1
PPG12/13/14/15_TIN1_0
PPG14_TOUT2_1
PPG15_TOUT0_0
PPG14_TOUT2_0
PPG14_TOUT0_0
PPG13_TOUT2_0
ADTRG1_2
ADTRG0_1
SCS120_0
EINT23_5
EINT22_5
EINT21_5
EINT15_5
EINT14_5
EINT13_5
EINT12_5
EINT11_5
SOT12_0
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT0_0
-
-
-
-
-
-
-
-
-
EINT3_1
EINT9_5
EINT7_5
EINT6_5
EINT4_5
EINT3_5
EINT2_5
EINT0_5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MDATA11 -
MDATA10 -
-
-
-
-
-
-
-
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
MDATA9
MDATA8
MCSX1
MCSX0
MAD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MDATA15
MDATA14
MDATA13
MDATA12
AN63
AN62
AN61
AN60
AN59
AN58
AN57
AN56
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN47
-
-
-
-
-
-
-
-
-
-
-
VCC53 -
-
VCC12 -
-
-
-
-
-
-
-
-
-
-
DVCC
DVCC
DVCC
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
P2_13
S2 P2_12
S P2_11
P2_10
P3_31
P3_30
P3_29
P3_28
P2_09
P3_27
P3_26
P3_25
P3_24
P2_08
P2_07
P2_06
P2_05
P2_04
P2_03
P2_02
P2_01
P2_00
P1_31
P1_30
P1_29
P1_28
P1_27
P1_26
P1_25
DVSS
DVSS
VSS
VSS
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
-
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
- - - - - - - - - - - - - VCC53 - 1 132 - DVSS - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 ● 131 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 130 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 129 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 128 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 6 127 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 7 126 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 8 125 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 9 124 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 10 123 - DVCC - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 11 122 - DVSS - - - - - - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 12 121 - AVSS - - - - - - - - - - - -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 13 120 - AVRL5 - - - - - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 14 119 - AVRH5 - - - - - - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 15 118 - AVCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 16 117 H P1_16 ADTRG0_0 - EINT9_4 - PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD1_0 TOT49_0 SOT17_0 SDA17 WOT SYSC0_CLK_0 -
- - - - - - - - - - - - - VSS - 17 116 - VCC5 - - - - - - - - - - - -
- - - - - - - - - - - - - VCC12 - 18 115 - VSS - - - - - - - - - - - -
- - - - - - - - SIN1_1 PPG4_TOUT0_1 EINT1_1 MAD15 TXD1_1 P3_00 T 19 114 - VCC12 - - - - - - - - - - - -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCK1_1
SOT1_1
SCS10_1
SCS11_1
PPG4_TOUT2_1
PPG5_TOUT0_1
PPG5_TOUT2_1
PPG0/1/2/3/4/5_TIN1_1
EINT9_2
EINT10_2
EINT11_2
EINT12_2
MAD16
MAD17
MAD18
MAD19
TXD2_1
TXD3_1
TXER_1
RXD0_1
P3_01
P3_02
P3_03
P3_04
T
T
T
T
20
21
22
23
TOP VIEW 113
112
111
110
H
G
G
- VCC12
P1_15
P1_14
P3_23
-
AN32
AN31
AN30
-
EINT16_0
EINT15_0
EINT4_4
-
-
-
TX6_1
-
PPG5_TOUT2_0
PPG5_TOUT0_0
SCS120_1
-
OCU10_OTD0_0
OCU9_OTD1_0
-
-
ICU10_IN1_0
ICU10_IN0_0
-
-
TIN49_0
TOT48_0
-
-
SCK17_0
TX3_0
-
-
SCK12_1
SIN17_0
-
-
SCL17
SYSC0_CLK_1
-
-
INDICATOR0_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCS12_1
SCS13_1
SCK4_1
SCS40_1
SIN4_1
SOT4_1
EINT17_2
EINT18_2
EINT15_2
EINT16_2
-
-
MAD20
MAD21
MOEX
MWEX
RXD3_1
MDIO_1
-
-
P3_05
P3_06
P0_14
P0_15
T
T
S
S
24
25
26
27
TEQFP-176 109
108
107
106
G
G
E
E
P3_22
P3_21
P3_20
P3_19
AN29
AN28
EINT2_4
EINT17_1
EINT19_1
EINT3_4
PPG6/7/8/9/10/11_TIN1_1
PPG11_TOUT2_1
RX6_1
TOT49_1
TIN49_1
OCU10_OTD1_1
SCS91_1
SCS90_1
TX5_1
ICU10_IN1_1
-
-
SOT9_1
RX5_1
-
-
-
SCK9_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - - - - - - - SCS41_1 EINT19_2 - MCLK - P0_16 S 28 105 E P3_18 EINT20_1 PPG11_TOUT0_1 OCU10_OTD0_1 ICU10_IN0_1 SIN9_1 - - - - - - -
- - - - - - - - - - SCS42_1 EINT20_2 MDQM1 P3_07 T 29 104 - VSS - - - - - - - - - - - -
- - - - - - - SCS43_1 EINT21_2 - MDQM0 - RXCLK_0 P0_17 V 30 103 - C - - - - - - - - - - - -
- - - - - - - - EINT22_2 - MCSX2 MDC_1 RXER_0 P0_18 V 31 102 O MODE - - - - - - - - - - - -
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 32 101 D PSC_1 - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 33 100 N RSTX - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 34 99 G P3_17 AN26 EINT0_4 - PPG10_TOUT2_1 OCU9_OTD1_1 ICU9_IN1_1 TOT48_1 TX3_1 - - - -
- - - - - - - - - - - - - VSS - 35 98 G P3_16 AN25 EINT14_1 - PPG10_TOUT0_1 OCU9_OTD0_1 ICU9_IN0_1 TIN48_1 RX3_1 - - - -
- - - - - - - - - - - - - AVSS - 36 97 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - -
- - - - - - - - - - - - - NC A 37 96 L2 JTAG_TMS - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 38 95 L2 JTAG_TCK - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 39 94 L2 JTAG_TDI - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 40 93 M JTAG_TDO - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 41 92 L JTAG_NTRST - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 42 91 K X0 - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 43 90 K X1 - - - - - - - - - - - -
- - - - - - - - - - - - - VSS - 44 89 - VSS - - - - - - - - - - - -
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
B
B
B
B
B
B
B
B
B
B
C
C
C
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
R
R
-
-
-
-
-
-
-
-
-
-
I
VCC3 -
P0_21 M_SDATA0_0 M_DQ3
P0_24 M_SSEL0
P0_25 M_SDATA0_3 M_CS#_1 TXD3_0
VSS
P0_26 M_SCLK0
VSS
VCC3 -
P0_27 M_SDATA1_0 M_RWDS RXD0_0
P0_30 M_SSEL1
VSS
VCC3 -
P1_00 -
P1_01 -
P1_02 -
VCC12 -
VCC12 -
VSS
VCC5 -
P3_08 AN4
P3_09 AN5
P3_10 AN6
P3_11 AN7
P1_03 AN8
P1_04 AN9
P3_12 AN10
P3_13 AN11
P1_05 AN12
P1_06 AN13
P3_14 AN14
P3_15 AN15
P1_07 AN16
P1_08 AN17
P1_09 AN18
P1_10 AN21
NMIX -
X0A
X1A
VCC5 -
-
P1_11
P1_12
-
M_DQ0
-
M_CK
-
-
M_DQ6
-
-
M_CS#_2 MDC_0
COL_0
CRS_0
-
-
-
-
EINT18_1 -
EINT6_1
EINT17_3 -
EINT8_1
EINT4_0
EINT5_0
EINT21_1 -
EINT18_3 -
EINT6_0
EINT7_0
EINT12_1 -
EINT19_3 -
EINT8_0
ADTRG1_1 EINT9_0
EINT10_0 -
EINT11_0 -
-
EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0
EINT13_0 -
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
-
TXER_0
-
-
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
EINT11_3
EINT12_3
-
-
-
-
-
-
-
-
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
-
-
-
PPG7_TOUT2_1 OCU1_OTD1_1 ICU1_IN1_1
-
-
-
-
-
-
-
OCU8_OTD1_0 ICU9_IN1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
PPG1_TOUT0_0 ICU1_IN0_0

-
-
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TOT1_1
AIN8
BIN8
TIN16_1
TOT16_1
ZIN8
AIN9
TIN17_1
TOT17_1
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_1 SIN8_1
TOT0_1 RX0_1
TIN1_1 TX0_1
RX1_1 SCS80_1
TIN0_0 FRT0/1/2/3_TEXT
TOT0_0 FRT4/8/9/10_TEXT
TX1_1 SIN10_1
SCK10_1TRACE3_1
TIN1_0 RX0_0
TOT1_0 TX0_0
RX2_1 SOT10_1
TX2_1 SCS100_1
BIN9
SCK16_0SCL16
SOT16_0SDA16
-
SCS160_0
SCS161_0
-
-
-
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TIN16_0
ZIN9
-
INDICATOR0_0-
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SCK8_1
SOT8_1
TRACE1_1
SIN0_0
SCK0_0
TRACE2_1
-
SOT0_0
SCS00_0
TRACE_CTL_1
TRACE_CLK_1
RX1_0
TOT16_0
TRACE_CTL_0
TRACE_CLK_0
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-
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-
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-
TRACE0_1
-
-
SCL0
-
-
SDA0
TRACE1_0
-
-
TRACE2_0
TX1_0
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TRACE0_0
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SIN16_0
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-
TRACE3_0
-
-
-
-
-
-


S6J3350 Series

Figure 4-3: TEQFP-144 (S6J335xHyz *1)
- - - - - -
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-
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-
SCS43_0
SCS42_0
SCS32_1
SCS31_1
SDA11
SDA10
SCL12
SCL11
SCL10
SDA4
SDA9
SCL4
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-
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-
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-
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-
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-
SCS111_0
SCS110_0
SCS100_0
EINT20_5
EINT19_5
SCS41_0
SCS40_0
SCS33_1
SCK12_0
SOT11_0
SCK11_0
SOT10_0
EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0
SCS91_0
SCS90_0
SIN12_0
SIN11_0
SIN10_0
SOT4_0
SCK4_0
SOT9_0
SIN4_0
SDA12
-
-
-
-
-
-
-
-
-
-
-
-
PPG12/13/14/15_TIN1_0
PPG15_TOUT0_0
PPG14_TOUT2_0
PPG14_TOUT0_0
PPG13_TOUT2_0
ADTRG1_2
ADTRG0_1
SCS120_0
EINT23_5
EINT22_5
EINT21_5
EINT15_5
SOT12_0
EINT3_6
EINT2_6
EINT1_6
EINT0_6
EINT0_0
-
-
-
-
-
-
-
-
-
EINT9_5
EINT7_5
EINT6_5
EINT4_5
EINT3_5
EINT2_5
EINT0_5
-
-
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-
-
-
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-
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-
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-
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
MCSX1
MCSX0
MAD0
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AN63
AN62
AN61
AN60
AN59
AN58
AN57
AN56
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN47
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-
-
-
-
-
-
-
-
VCC53 -
-
VCC12 -
-
-
-
-
-
-
DVCC
DVCC
DVCC
P2_19
P2_18
P2_17
P2_16
P2_15
P2_14
S P2_13
S2 P2_12
S P2_11
P2_10
P2_09
P2_08
P2_07
P2_06
P2_05
P2_04
P2_03
P2_02
P2_01
P2_00
P1_31
P1_30
P1_29
P1_28
P1_27
P1_26
P1_25
DVSS
DVSS
VSS
VSS
S
S
S
S
S
S
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
-
-
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-
144
143
142
141
140
139
138
137
136
135
134
133
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129
128
127
126
125
124
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122
121
120
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118
117
116
115
114
113
112
111
110
109
- - - - - - - - - - - - - VCC53 - 1 108 - DVSS - - - - - - - - - - - - -
- - - - - - - - - EINT0_1 - MAD1 - P0_00 S 2 ● 107 P P1_24 AN46 - EINT14_4 PPG9_TOUT2_0 SCK9_0 SCL9 - - - - - - -
- - - - - - - - SIN1_0 EINT1_0 - MAD2 - P0_01 S 3 106 P P1_23 AN45 - EINT20_0 PPG9_TOUT0_0 SIN9_0 - - - - - - - -
- - - - - - - SCL1 SCK1_0 EINT4_1 - MAD3 - P0_02 S 4 105 P P1_22 AN44 - EINT13_4 PPG8_TOUT2_0 TX6_0 SCS80_0 - - - - - - -
- - - - - - - SDA1 SOT1_0 EINT5_1 - MAD4 - P0_03 S 5 104 P P1_21 AN43 - EINT19_0 PPG8_TOUT0_0 RX6_0 SOT8_0 SDA8 - - - - - -
- - - - - - - SIN0_1 SCS10_0 EINT11_1 - MAD5 - P0_04 S 6 103 P P1_20 AN42 - EINT12_4 PPG7_TOUT2_0 SCK8_0 SCL8 - - - - - - -
- - - - - - - SOT0_1 SCS11_0 EINT13_1 - MAD6 - P0_05 S 7 102 P P1_19 AN41 - EINT18_0 PPG7_TOUT0_0 SIN8_0 - - - - - - - -
- - - - - SCK0_1 SCS12_0 PPG0_TOUT0_1 EINT15_1 - MAD7 - - P0_06 S 8 101 P P1_18 AN40 - EINT11_4 PPG6_TOUT2_0 TX5_0 SCS171_0 - - - - - - -
- - - - - SCS00_1 SCS13_0 PPG0_TOUT2_1 EINT23_1 - MAD8 - - P0_07 S 9 100 P P1_17 AN39 - EINT17_0 PPG6_TOUT0_0 RX5_0 SCS170_0 - - - - - - -
- - - - - - - PPG1_TOUT0_1 EINT0_2 - MAD9 - - P0_08 S 10 99 - DVCC - - - - - - - - - - - - -
- - - - - - SIN17_1 PPG1_TOUT2_1 EINT1_2 - MAD10 - - P0_09 S 11 98 - DVSS - - - - - - - - - - - - -
- - - - - - SCS171_1 PPG2_TOUT0_1 EINT5_2 - MAD11 - - P0_10 S 12 97 - AVSS - - - - - - - - - - - - -
- - - - - - - PPG2_TOUT2_1 EINT6_2 - MAD12 - - P0_11 S 13 96 - AVRL5 - - - - - - - - - - - - -
- - - - - - - PPG3_TOUT0_1 EINT7_2 - MAD13 - - P0_12 S 14 95 - AVRH5 - - - - - - - - - - - - -
- - - - - - - PPG3_TOUT2_1 EINT8_2 - MAD14 - - P0_13 S 15 94 - AVCC5 - - - - - - - - - - - - -
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- SCK4_1
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EINT17_2
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- MOEX
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-
VCC53
VSS
VCC12
P0_14
-
-
-
S
16
17
18
19
TOP VIEW 93
92
91
90
H
-
-
-
P1_16
VCC5
VSS
VCC12
ADTRG0_0
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-
EINT9_4
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PPG0/1/2/3/4/5_TIN1_0
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OCU10_OTD1_0
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TOT49_0
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SOT17_0
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SDA17
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WOT
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SYSC0_CLK_0
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SCS43_1
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SCS40_1
SCS41_1
EINT21_2
EINT22_2
EINT18_2
EINT19_2
-
-
MDQM0
MCSX2
-
-
MWEX
MCLK
MDC_1
-
-
-
RXCLK_0
RXER_0
P0_15
P0_16
P0_17
P0_18
S
S
V
V
20
21
22
23
TEQFP-144 89
88
87
86
H
G
-
-
VCC12
P1_15
P1_14
VSS
-
AN32
AN31
-
-
EINT16_0
EINT15_0
-
-
-
-
-
-
PPG5_TOUT2_0
PPG5_TOUT0_0
-
-
OCU10_OTD0_0
OCU9_OTD1_0
-
-
ICU10_IN1_0
ICU10_IN0_0
-
-
TIN49_0
TOT48_0
-
-
SCK17_0
TX3_0
-
-
SCK12_1
SIN17_0
-
-
SCL17
SYSC0_CLK_1
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-
INDICATOR0_1
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-
- - - - - - - - EINT23_2 - MCSX3 COL_1 RXDV_0 P0_19 V 24 85 - C - - - - - - - - - - - - -
- - - - - - - - EINT0_3 - MRDY CRS_1 TXCLK_0 P0_20 U 25 84 O MODE - - - - - - - - - - - - -
- - - - - - - - - - - - - VCC53 - 26 83 D PSC_1 - - - - - - - - - - - - -
- - - - - - - - - - - - - VSS - 27 82 N RSTX - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 28 81 G P1_13 AN24 EINT14_0 - OCU9_OTD0_0 TIN48_0 RX3_0 - - - - - - -
- - - - - - - - - - - - - NC A 29 80 L2 JTAG_TMS - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 30 79 L2 JTAG_TCK - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 31 78 L2 JTAG_TDI - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 32 77 M JTAG_TDO - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 33 76 L JTAG_NTRST - - - - - - - - - - - - -
- - - - - - - - - - - - - NC A 34 75 K X0 - - - - - - - - - - - - -
- - - - - - - - - - - - - AVSS - 35 74 K X1 - - - - - - - - - - - - -
- - - - - - - - - - - - - VSS - 36 73 - VSS - - - - - - - - - - - - -
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
B
B
B
B
B
B
B
B
B
B
C
C
C
G
G
G
G
G
G
H
H
R
R
-
-
-
-
-
-
-
-
-
-
I
VCC3 -
P0_24 M_SSEL0
P0_25 M_SDATA0_3 M_CS#_1 TXD3_0
VSS
P0_26 M_SCLK0
VSS
VCC3 -
P0_27 M_SDATA1_0 M_RWDS RXD0_0
P0_30 M_SSEL1
VSS
VCC3 -
P1_00 -
P1_01 -
P1_02 -
VCC12 -
VCC12 -
VSS
VCC5 -
P1_03 AN8
P1_04 AN9
P1_05 AN12
P1_06 AN13
P1_07 AN16
P1_08 AN17
P1_09 AN18
P1_10 AN21
NMIX -
X0A
X1A
VCC5 -
-
P1_11
P1_12
-
M_DQ0
-
M_CK
-
-
M_DQ6
-
-
M_CS#_2 MDC_0
COL_0
CRS_0
-
-
-
-
EINT4_0
EINT5_0
EINT6_0
EINT7_0
EINT8_0
ADTRG1_1 EINT9_0
EINT10_0 -
EINT11_0 -
-
EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0
EINT13_0 -
-
-
TXEN_0
TXD0_0
TXD1_0
TXD2_0
-
TXER_0
-
-
RXD1_0
RXD2_0
RXD3_0
MDIO_0
-
-
EINT11_3
EINT12_3
-
-
-
-
-
-
-
-
-
-
-
EINT2_0
EINT1_3
EINT2_3
EINT3_3
EINT4_3
-
EINT5_3
-
-
EINT6_3
EINT3_0
EINT7_3
EINT8_3
EINT9_3
-
-
EINT10_3
SCS32_0
SCS33_0
-
-
-
-
-
-
-
-
-
-
-
OCU8_OTD1_0 ICU9_IN1_0
-
-
SIN2_0
SCK2_0
SOT2_0
SCS20_0
SCS21_0
-
SCS22_0
-
-
SCS23_0
SIN3_0
SCK3_0
SOT3_0
SCS30_0
-
-
SCS31_0
-
-
-
-
-
-
-
-
-
-
SIN9_2
SOT9_2
SCK9_2
SCS90_2
SCS91_2
-
-
-
-
SIN8_2
SCK8_2
SOT8_2
SCS80_2
-
-
-
-
-
-
-
-
-
-
PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9
-
TIN17_0
TOT17_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AIN8
BIN8
ZIN8
AIN9
-
RX2_0
TX2_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN0_0
TOT0_0
TIN1_0
TOT1_0
BIN9
SCK16_0
SOT16_0
-
SCS160_0 INDICATOR0_0
SCS161_0 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FRT0/1/2/3_TEXT SIN0_0
FRT4/8/9/10_TEXT SCK0_0
RX0_0
TX0_0
TIN16_0
SCL16
SDA16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SOT0_0
SCS00_0
RX1_0
TOT16_0
TRACE_CTL_0 -
TRACE_CLK_0 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCL0
SDA0
TRACE1_0 -
TRACE2_0 -
TX1_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE0_0 -
SIN16_0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE3_0
-
-
-
-
-
-


S6J3350 Series
4.2 Package Dimensions

4.2.1 TEQFP208
Figure 4-4: TEQFP208
Package Type Package Code
TEQFP 208pin LEW208
4
D D2
5 7
D1 D3
E1 E E3 E2
EXPOSED PAD
BOTTOM VIEW
0.20 C A-B D 0.20 C A-B D
TOP VIEW
2
DETAIL A R1
L2
A
SEATING
GAUGE
PLANE 10 c
PLANE
A
A1 e b
A'
θ R2 b
0.08 C L
11
L1 SECTION A-A'
0.08 C A-B D
DETAIL A
SIDE VIEW 8
DIMENSION
SYMBOL
M IN. NOM. MAX.
A 1.70
A1 0.05 0.15
D 30.00 BSC
D1 28.00 BSC
D2 7.05 REF
D3 6.05 REF
E 30.00 BSC
E1 28.00 BSC
E2 7.05 REF
E3 6.05 REF
R1 0.08
R2 0.08 0.20
θ 0° 4° 8°
c 0.09 0.20
b 0.17 0.22 0.27
L 0.45 0.60 0.75
L 1 1.00 REF
L 2 0.25
002-12477 **
e 0.50 BSC
PACKAGE OUTLINE, 208 LEAD TEQFP
28.0X28.0X1.7 M M LEW 208 REV**

S6J3350 Series
4.2.2 TEQFP176
Figure 4-5: TEQFP176
TEQFP 176pin LEV176
4
D D2
5 7
D1 D3
E1 E E3 E2
EXPOSED PAD
0.20 C A-B D 0.20 C A-B D
TOP VIEW BOTTO M VIEW
2
DETAIL A
L2 R1
A A GAUGE
PLA N E 10 c
SEATI N G
PLA N E R2
A'
A1 θ
e b
11 0.08 C L
SECTION A -A'
b L1
0.08 C A-B D
8
DETAIL A
SID E VIEW
DIM ENSION
SYM BOL
M IN. NOM . M AX.
A 1.70
A1 0.05 0.15
D 26.00 BSC
D1 24.00 BSC
D2 6.65 REF
D3 5.45 REF
E 26.00 BSC
E1 24.00 BSC
E2 6.65 REF
E3 5.45 REF
R1 0.08 0.20
R2 0.08
θ 0° 2° 8°
c 0.09 0.20
b 0.17 0.22 0.27
L 0.45 0.60 0.75
L 1 1.00 REF
L 2 0.25
e 0.50 BSC
002-13653 **
24.0X24.0X1.7 M M LEV176 REV**

S6J3350 Series
4.2.3 TEQFP144
Figure 4-6: TEQFP144 (0.5mm Pitch)
TEQFP 144pin LEX144
4
D D2
5 7
D1 D3
E1 E E3 E2
EXPOSED PAD
0.20 C A-B D 0.20 C A-B D BOTTOM VIEW
TOP VIEW
2
DETAIL A
L2 R1
A A θ GAUGE
PLANE 10 c
SEATING
A'
PLANE R2
A1 b
11 e 0.08 C L
SECTION A-A'
b L1
0.08 C A-B D
8 DETAIL A
SIDE VIEW
DIM ENSION
SYM BOL
M IN. NOM . M AX.
A 1.70
A1 0.05 0.15
D 22.00 BSC
D1 20.00 BSC
D2 5.80 REF
D3 4.60 REF
E 22.00 BSC
E1 20.00 BSC
E2 5.80 REF
E3 4.60 REF
R1 0.08
R2 0.08 0.20
θ 0° 4° 8°
c 0.09 0.20
b 0.17 0.22 0.27
L 0.45 0.60 0.75
L 1 1.00 REF
L 2 0.25
e 0.50 BSC
002-13553 **
20.0X20.0X1.7 M M LEX144 REV**

S6J3350 Series
Figure 4-7: TEQFP144 (0.4mm Pitch)

TEQFP 144pin LEK144
4
D D2
5 7
D1 D3
E1 E E3 E2
EXPOSED PAD
0.20 C A-B D 0.20 C A-B D BOTTOM VIEW

TOP VIEW
2 DETAIL A
L2 R1
A GAUGE 10 c
A θ PLANE
SEATING
PLANE R2
A'
A1 L b
11 e 0.08 C
b L1
SECTION A-A'
0.08 C A-B D DETAIL A
8
SIDE VIEW
DIMENSION N OTES :
SYMBOL
M IN. NOM. MAX.
A 1.70
A1 0.05 0.15
D 18.00 BSC
D1 16.00 BSC
D2 5.80 REF
D3 4.60 REF
E 18.00 BSC
E1 16.00 BSC
E2 5.80 REF
E3 4.60 REF
R1 0.08
R2 0.08 0.20
θ 0° 4° 8°
c 0.09 0.20
b 0.13 0.18 0.23
L 0.45 0.60 0.75
L1 1.00 REF
L2 0.25
e 0.40 BSC
002-11502 **
16.0X16.0X1.7 M M LEK144 REV**

S6J3350 Series
5. IO Circuit Type
5.1 I/O Circuit Type
This section explains I/O circuit types.
Type Circuit Remarks
B − General-purpose I/O port
Pull-up control
− Output 2 mA, 5 mA, 6 mA or 15 mA selectable
Digital output − 50 kΩ with pull-up resistor control
− 50 kΩ with pull-down resistor control
Digital output − CMOS hysteresis input
− TTL input
Pull-down control
CMOS-hys input
PSS control
TTL input
PSS control
C − General-purpose I/O port
Pull-up control
− 50 kΩ with pull-up resistor control
Digital output
Pull-down control
CMOS-hys input
PSS control
D − External 1.2 V regulator control

Digital output
− Output 2 mA
Digital output
E − General-purpose I/O port

Pull-up control
− Output 1 mA, 2 mA or 5 mA selectable
− Automotive hysteresis input
Pull-down control
CMOS-hys input
PSS control
Automotive input
PSS control

S6J3350 Series

G − General-purpose I/O port with analog input
Pull-up control
Pull-down control
CMOS-hys input
PSS control
Automotive input
PSS control
Analog input
H − General-purpose I/O port with analog input
Pull-up control
− Output 1 mA, 2 mA, 3 mA(I2C) or 5 mA selectable
Pull-down control − TTL input
CMOS-hys input
PSS control
Automotive input
PSS control
TTL input
PSS control
Analog input
I − 50 kΩ with pull-up
− CMOS hysteresis input
CMOS-hys input
K OSC input − Main oscillation I/O
X1
X0
PSS control
L − JTAG_NTRST
− 50 kΩ with pull-down
− TTL input
TTL input

S6J3350 Series

L2 − JTAG_TDI/TMS/TCK
− 50 kΩ with pull-up
− TTL input
TTL input
M − JTAG_TDO
Digital output
− Output 5 mA
Digital output
N − RSTX input
− 50 kΩ with pull-up
O − CMOS hysteresis input

CMOS-hys input
P − General-purpose I/O port with analog input

Pull-up control
Pull-down control
CMOS-hys input
PSS control
Automotive input
PSS control
Analog input
Q − General-purpose I/O port
Pull-up control
Pull-down control
CMOS-hys input
PSS control
Automotive input
PSS control

S6J3350 Series

R − Sub oscillation I/O shared General-purpose I/O port
Pull-up control
Pull-down control
CMOS-hys input
PSS/OSC control
Automotive input
PSS/OSC control
OSC input
PSS/OSC control
Pull-up control
Digital output
Digital output
Pull-down control
CMOS-hys input
PSS/OSC control
Automotive input
PSS/OSC control
T − General-purpose I/O port
Pull-up control
Pull-down control − TTL input
CMOS-hys input
PSS control
Automotive input
PSS control
TTL input
PSS control

S6J3350 Series

U − General-purpose input port
Pull-up conrol
− 50 kΩ with pull-up resistor control
− TTL input
Pull-down control
CMOS-hys input
PSS control;
Automotive input
PSS contor;
TTL input
PSS control
5.2 Note
Alphabet which shows I/O circuit type is described with corresponding pin number in pin assignment figure.

S6J3350 Series
6. Port Description
6.1 Port Description List
This table shows the port function of description which is supported. The port function which is not described in the table is not
supported for the product.
Package Pin Number Remarks
Port Name Description TEQFP TEQFP TEQFP
144 176 208
18, 18, 24,
57, 65, 73,
58, 66, 74,
VCC12 1.2 V external power supply pin
89, 113, 132,
90, 114, 133,
131 159 191
60, 68, 76,
VCC5 5 V external power supply pin 72, 88, 104,
92 116 135,
37, 45, 53,
VCC3 3 V external power supply pin 46, 54, 62,
53 61 69
1, 1, 1,
16, 16, 22,
VCC53 3 V/5 V external power supply pin
26, 34, 42,
133 161 193
17, 17, 23,
27, 35, 43,
36, 44, 52,
43, 51, 59,
45, 53, 61,
52, 60, 68,
VSS GND
59, 67, 75,
73, 89, 105,
86, 104, 121,
91, 115, 134,
132, 160, 192,
144 176 208
29, 37, 45,
30, 38, 46,
NC No connection
33, 41, 49,
34 42 50
AVCC5 A/D converter analog power supply pin 94 118 142
AVRH5 A/D converter upper limit reference voltage pin 95 119 143
AVRL5 A/D converter lower limit reference voltage pin 96 120 144
28, 36, 44,
31, 39, 47,
AVSS A/D converter GND 32, 40, 48,
35, 43, 51,
97 121 145
99 123 147
109 133 157
DVCC 3 V/5 V external power supply pin
119 143 170
129 153 183
98 122 146
108 132 156
DVSS GND
118 142 169
128 152 182
X1 Main clock oscillator output pin 74 90 106
X0 Main clock oscillator input pin 75 91 107
X1A Sub-clock oscillator output 71 87 103

S6J3350 Series

144 176 208
X0A Sub-clock oscillator input 70 86 102
NMIX Non-maskable interrupt input pin 69 85 101
RSTX External reset input pin 82 100 117
PSC_1 External Power Supply Control pin 83 101 118
MODE Mode Pin 84 102 119
C External capacity connection output pin 85 103 120
JTAG_NTRST JTAG test reset input pin 76 92 108
JTAG_TDO JTAG test data output pin 77 93 109
JTAG_TDI JTAG test data input pin 78 94 110
JTAG_TCK JTAG test clock input pin 79 95 111
JTAG_TMS JTAG test mode state input pin 80 96 112
TRACE0_0 Trace data 0 output pin (0) 63 77 89
TRACE_CLK_0 Trace clock (0) 68 84 98
TRACE_CTL_0 Trace control (0) 67 83 95
TRACE0_1 Trace data 0 output pin (1) - 71 83
TRACE_CLK_1 Trace clock (1) - 80 92
TRACE_CTL_1 Trace control (1) - 79 91
ADTRG0_0 A/D converter external trigger input pin (0) 93 117 139
ADTRG1_0 A/D converter external trigger input pin (0) - - 140
AN0 ADC Unit0 ch.0 input pin - - 77
AN4 ADC Unit0 ch.4 input pin - 69 81
AN8 ADC Unit0 ch.8 input pin 61 73 85

S6J3350 Series

144 176 208
TX0_0 CAN transmission data 0 output pin (0) 64 78 90
TX4_0 CAN transmission data 4 output pin (0) - - 137

S6J3350 Series

144 176 208
TX0_1 CAN transmission data 0 output pin (1) - 71 83
RX0_0 CAN reception data 0 input pin (0) 63 77 89
RX4_0 CAN reception data 4 input pin (0) - - 136
RX0_1 CAN reception data 0 input pin (1) - 70 82
EINT0_0 External interrupt input pin (0) 137 169 201

S6J3350 Series

144 176 208
EINT1_1 External interrupt input pin (1) - 19 25
EINT2_1 External interrupt input pin (1) - - 184

S6J3350 Series

144 176 208

S6J3350 Series

144 176 208
SCS00_0 Multi-function serial ch.0 chip select 0 I/O pin (0) 64 78 90
SCS11_0 Multi-function serial ch.1 chip select 1 output pin (0) 7 7 10

S6J3350 Series

144 176 208
SCS10_1 Multi-function serial ch.1 chip select 0 I/O pin (1) - 22 28
SCS11_1 Multi-function serial ch.1 chip select 1 output pin (1) - 23 29
SCS160_1 Multi-function serial ch.16 chip select 0 I/O pin (1) - - 141
SCS161_1 Multi-function serial ch.16 chip select 1 output pin (1) - - 140
SCS170_1 Multi-function serial ch.17 chip select 0 I/O pin (1) - - 15
SCK0_0 Multi-function serial ch.0 clock I/O pin (0) 62 74 86

S6J3350 Series

144 176 208
SCK1_1 Multi-function serial ch.1 clock I/O pin (1) - 20 26
SCK2_1 Multi-function serial ch.2 clock I/O pin (1) - - 185
SIN0_0 Multi-function serial ch.0 serial data input pin (0) 61 73 85
SIN1_1 Multi-function serial ch.1 serial data input pin (1) - 19 25
SIN2_1 Multi-function serial ch.2 serial data input pin (1) - - 184
SOT0_0 Multi-function serial ch.0 serial data output pin (0) 63 77 89

S6J3350 Series

144 176 208
SOT1_1 Multi-function serial ch.1 serial data output pin (1) - 21 27
SOT12_1 Multi-function serial ch.12 serial data output pin (1) - - 130
SCL0 I2C ch.0 clock I/O pin 62 74 86
2
SDA0 I C ch.0 serial data I/O pin 63 77 89
SDA1 I2C ch.1 serial data I/O pin 5 5 5
PPG0_TOUT0_0 Base timer 0 output pin (0) 61 73 85

S6J3350 Series

144 176 208
PPG16_TOUT0_0 Base timer 32 output pin (0) - - 6

S6J3350 Series

144 176 208
PPG4_TOUT0_1 Base timer 8 output pin (1) - 19 25
PPG0/1/2/3/4/5_TIN1_0 Base timer 0/2/4/6/8/10 input pin (0) 93 117 139
PPG6/7/8/9/10/11_TIN1_0 Base timer 12/14/16/18/20/22 input pin (0) 114 138 164
PPG12/13/14/15_TIN1_0 Base timer 24/26/28/30 input pin (0) 125 149 178
PPG16/17/18/19/20/21_TIN1_0 Base timer 32/34/36/38/40/42 input pin (0) - - 81
PPG22/23/24/25/26/27_TIN1_0 Base timer 44/46/48/50/52/54 input pin (0) - - 140
PPG28/29/30/31_TIN1_0 Base timer 56/58/60/62 input pin (0) - - 185
PPG0/1/2/3/4/5_TIN1_1 Base timer 0/2/4/6/8/10 input pin (1) - 23 29
PPG6/7/8/9/10/11_TIN1_1 Base timer 12/14/16/18/20/22 input pin (1) - 107 124
PPG12/13/14/15_TIN1_1 Base timer 24/26/28/30 input pin (1) - 165 197
WOT RTC overflow output pin 93 117 139
OCU0_OTD0_0 Output compare 0 ch.0 output pin (0) 61 73 85

S6J3350 Series

144 176 208
OCU0_OTD0_1 Output compare 0 ch.0 output pin (1) - 69 81
ICU0_IN0_0 Input Capture 0 ch.0 input pin (0) 61 73 85
ICU0_IN0_1 Input Capture 0 ch.0 input pin (1) - 69 81
FRT0/1/2/3_TEXT Free-run timer ch.0/1/2/3 clock input pin 61 73 85
FRT4/8/9/10_TEXT Free-run timer ch.4/8/9/10 clock input pin 62 74 86
TIN0_0 Reload timer ch.0 event input pin (0) 61 73 85
TIN0_1 Reload timer ch.0 event input pin (1) - 69 81

S6J3350 Series

144 176 208
TOT0_0 Reload timer ch.0 output pin (0) 62 74 86
TOT0_1 Reload timer ch.0 output pin (1) - 70 82
AIN8 Up/Down counter AIN input pin ch.8 61 73 85
AIN9 Up/Down counter AIN input pin ch.9 64 78 90
BIN8 Up/Down counter BIN input pin ch.8 62 74 86
BIN9 Up/Down counter BIN input pin ch.9 65 81 93
ZIN8 Up/Down counter ZIN input pin ch.8 63 77 89
ZIN9 Up/Down counter ZIN input pin ch.9 66 82 94
RXD0_0 Ethernet pin (0) 47 55 63
TXD0_0 Ethernet pin (0) 39 47 55
COL_0 Ethernet pin (0) 55 63 71
CRS_0 Ethernet pin (0) 56 64 72
RXER_0 Ethernet pin (0) 23 31 39
RXDV_0 Ethernet pin (0) 24 32 40
RXCLK_0 Ethernet pin (0) 22 30 38
TXER_0 Ethernet pin (0) 44 52 60
TXEN_0 Ethernet pin (0) 38 46 54
TXCLK_0 Ethernet pin (0) 25 33 41
MDC_0 Ethernet pin (0) 54 62 70
MDIO_0 Ethernet pin (0) 51 59 67
RXD0_1 Ethernet pin (1) - 23 29
RXD1_1 Ethernet pin (1) - - 30
RXD2_1 Ethernet pin (1) - - 31
RXD3_1 Ethernet pin (1) - 24 32
TXD0_1 Ethernet pin (1) - - 17
TXD1_1 Ethernet pin (1) - 19 25

S6J3350 Series

144 176 208
COL_1 Ethernet pin (1) 24 32 40
CRS_1 Ethernet pin (1) 25 33 41
RXER_1 Ethernet pin (1) - - 7
RXDV_1 Ethernet pin (1) - - 8
RXCLK_1 Ethernet pin (1) - - 6
TXER_1 Ethernet pin (1) - 22 28
TXEN_1 Ethernet pin (1) - - 16
TXCLK_1 Ethernet pin (1) - - 15
MDC_1 Ethernet pin (1) 23 31 39
MDIO_1 Ethernet pin (1) - 25 33
M_SCLK0 MCU HS-SPI clock output pin 44 52 60
M_SDATA0_0 MCU HS-SPI0 data 0 I/O pin 38 46 54
M_SSEL0 MCU HS-SPI0 select output pin 41 49 57
M_SSEL1 MCU HS-SPI1 select output pin 50 58 66
M_CK MCU Hyper Bus clock output pin 44 52 60
M_CS#_1 MCU Hyper Bus select 1 output pin 42 50 58
M_CS#_2 MCU Hyper Bus select 2 output pin 54 62 70
M_DQ0 MCU Hyper Bus Data 0 pin 41 49 57
M_RWDS MCU Hyper Bus RWDS 47 55 63
Indicator PWM output pin 0
INDICATOR0_0 70 86 102
(It can also obtained from INDICATOR0_1)
Indicator PWM output pin 1
INDICATOR0_1 88 112 129
(It can also obtained from INDICATOR0_0)
SYSC0_CLK_0 System clock output pin (0) 93 117 139
SYSC0_CLK_1 System clock output pin (1) 87 111 128
MAD0 External Bus pin 143 175 207

S6J3350 Series

144 176 208
MAD15 External Bus pin - 19 25
MDATA0 External Bus pin 135 167 199
MDATA8 External Bus pin - 154 186
MCLK External Bus pin 21 28 36
MOEX External Bus pin 19 26 34
MWEX External Bus pin 20 27 35
MDQM0 External Bus pin 22 30 38
MDQM1 External Bus pin - 29 37
MCSX0 External Bus pin 130 158 190
MRDY External Bus pin 25 33 41
P0_00 General-Purpose I/O port 2 2 2

S6J3350 Series

144 176 208
P0_20 General-Purpose input port 25 33 41

S6J3350 Series

144 176 208
P3_00 General-Purpose I/O port - 19 25

S6J3350 Series

144 176 208
P4_00 General-Purpose I/O port - - 6
6.2 Remark
Notes:
− The port description list shows the port function of description which is mounted and supported on the product. The function
which is not described in this table is not supported and assured.
− See the function list of the product as well.

S6J3350 Series
7. Port Configuration
7.1 Resource Input Configuration Module
The resource input configuration module (RIC) is a function to select input from an external or output from another internal
resource as resource input. A resource which supports either a port input relocation or a resource inputs from the other resource
has its RIC_RESIN register to configure resource input configuration. The Resource which are available through only one port
does not have the multiplexer implemented i.e. No RIC_RESIN register.
7.1.1 RIC
RESSEL Source for Resource Input
Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN000 SIN16
PORTSEL
(0x0000) P1_08 P4_19 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN001 SCK16
PORTSEL
(0x0002) P1_09 P4_21 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN002 SCL16 - - - - - - - -
(8-15)
(0x0004)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN003 SDA16 - - - - - - - -
(8-15)
(0x0006)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
TOT48 TOT49 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS16_T (8-15)
SIN004
RIGGER PORTSEL
(0x0008) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN005 SCS16
PORTSEL
(0x000A) P1_11 P4_23 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN007 SIN17
PORTSEL
(0x000E) P1_14 P0_09 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN008 SCK17
PORTSEL
(0x0010) P1_15 P4_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN009 SCL17 - - - - - - - -
(8-15)
(0x0012)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN010 SDA17 - - - - - - - -
(8-15)
(0x0014)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT48 TOT49 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS17_T (8-15)
SIN011
RIGGER PORTSEL
(0x0016) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN012 SCS17
PORTSEL
(0x0018) P1_17 P4_03 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN021 SIN0
PORTSEL
(0x002A) P1_03 P0_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN022 SCK0
PORTSEL
(0x002C) P1_04 P0_06 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN023 SCL0 - - - - - - - -
(8-15)
(0x002E)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN024 SDA0 - - - - - - - -
(8-15)
(0x0030)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT0 TOT1 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS0_TR (8-15)
SIN025
IGGER PORTSEL
(0x0032) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN026 SCS0
PORTSEL
(0x0034) P1_06 P0_07 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN028 SIN1
PORTSEL
(0x0038) P0_01 P3_00 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN029 SCK1
PORTSEL
(0x003A) P0_02 P3_01 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN030 SCL1 - - - - - - - -
(8-15)
(0x003C)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN031 SDA1 - - - - - - - -
(8-15)
(0x003E)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT0 TOT1 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS1_TR (8-15)
SIN032
IGGER PORTSEL
(0x0040) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN033 SCS1
PORTSEL
(0x0042) P0_04 P3_03 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN035 SIN2
PORTSEL
(0x0046) P0_21 P4_30 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN036 SCK2
PORTSEL
(0x0048) P0_22 P4_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT0 TOT1 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS2_TR (8-15)
SIN039
IGGER PORTSEL
(0x004E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN040 SCS2
PORTSEL
(0x0050) P0_24 P3_25 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN042 SIN3
PORTSEL
(0x0054) P0_28 P3_28 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN043 SCK3
PORTSEL
(0x0056) P0_29 P3_29 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
TOT0 TOT1 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS3_TR (8-15)
SIN046
IGGER PORTSEL
(0x005C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN047 SCS3
PORTSEL
(0x005E) P0_31 P3_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN049 SIN4
PORTSEL
(0x0062) P2_13 P3_05 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN050 SCK4
PORTSEL
(0x0064) P2_14 P0_14 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN051 SCL4 - - - - - - - -
(8-15)
(0x0066)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN052 SDA4 - - - - - - - -
(8-15)
(0x0068)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT0 TOT1 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS4_TR (8-15)
SIN053
IGGER PORTSEL
(0x006A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN054 SCS4
PORTSEL
(0x006C) P2_16 P0_15 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN077 SIN8
PORTSEL
(0x009A) P1_19 P3_08 P0_27 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN078 SCK8
PORTSEL
(0x009C) P1_20 P3_09 P0_28 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN079 SCL8 - - - - - - - -
(8-15)
(0x009E)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN080 SDA8 - - - - - - - -
(8-15)
(0x00A0)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT16 TOT17 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS8_TR (8-15)
SIN081
IGGER PORTSEL
(0x00A2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN082 SCS8
PORTSEL
(0x00A4) P1_22 P3_11 P0_30 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN084 SIN9
PORTSEL
(0x00A8) P1_23 P3_18 P0_21 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN085 SCK9
PORTSEL
(0x00AA) P1_24 P3_19 P0_23 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN086 SCL9 - - - - - - - -
(8-15)
(0x00AC)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN087 SDA9 - - - - - - - -
(8-15)
(0x00AE)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT16 TOT17 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS9_TR (8-15)
SIN088
IGGER PORTSEL
(0x00B0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN089 SCS9
PORTSEL
(0x00B2) P1_26 P3_21 P0_24 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN091 SIN10
PORTSEL
(0x00B6) P1_28 P3_12 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN092 SCK10
PORTSEL
(0x00B8) P1_29 P3_13 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN093 SCL10 - - - - - - - -
(8-15)
(0x00BA)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN094 SDA10 - - - - - - - -
(8-15)
(0x00BC)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT16 TOT17 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS10_T (8-15)
SIN095
RIGGER PORTSEL
(0x00BE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN096 SCS10
PORTSEL
(0x00C0) P1_31 P3_15 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN100 SCL11 - - - - - - - -
(8-15)
(0x00C8)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN101 SDA11 - - - - - - - -
(8-15)
(0x00CA)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT16 TOT17 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS11_T (8-15)
SIN102
RIGGER PORTSEL
(0x00CC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN105 SIN12
PORTSEL
(0x00D2) P2_05 P4_18 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN106 SCK12
PORTSEL
(0x00D4) P2_06 P1_15 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN107 SCL12 - - - - - - - -
(8-15)
(0x00D6)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
80ns 80ns
RESSEL noise noise
- - - - - -
(0-7) filter filter
disable enable
RIC_RE
RESSEL
SIN108 SDA12 - - - - - - - -
(8-15)
(0x00D8)
PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
TOT16 TOT17 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
MFS12_T (8-15)
SIN109
RIGGER PORTSEL
(0x00DA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN110 SCS12
PORTSEL
(0x00DC) P2_08 P3_23 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
MCAN5
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN133 RX5 (8-15)
(0x010A) PORTSEL
P1_17 P3_19 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN6
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN134 RX6 (8-15)
(0x010C) PORTSEL
P1_21 P3_22 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN7
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN135 RX7 (8-15)
(0x010E) PORTSEL
P4_22 P2_18 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN0
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN136 RX0 (8-15)
(0x0110) PORTSEL
P1_05 P3_09 P4_00 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN1
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN137 RX1 (8-15)
(0x0112) PORTSEL
P1_07 P3_11 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
MCAN2
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN138 RX2 (8-15)
(0x0114) PORTSEL
P1_11 P3_14 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN3
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN139 RX3 (8-15)
(0x0116) PORTSEL
P1_13 P3_16 P4_03 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
MCAN4
RESSEL PORT_
_PIN_A - - - - - -
(0-7) PIN
ND_TX
RIC_RE RESSEL
- - - - - - - -
SIN140 RX4 (8-15)
(0x0118) PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT49_
TOT49 - - - - -
(0-7) PIN UFSET
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN141 TIN48
PORTSEL
(0x011A) P1_13 P3_16 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT48_
TOT48 - - - - -
(0-7) PIN UFSET
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN142 TIN49
PORTSEL
(0x011C) P1_15 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_PI RLT1_UF PPG0_T
TOT1 - - - -
(0-7) N SET OUT0
RESSEL
RIC_RESI - - - - - - - -
(8-15)
N144 TIN0
PORTSEL
(0x0120) P1_03 P3_08 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_PI RLT0_UF PPG1_T
TOT0 - - - -
(0-7) N SET OUT0
RESSEL
RIC_RESI - - - - - - - -
(8-15)
N145 TIN1
PORTSEL
(0x0122) P1_05 P3_10 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT17_ PPG6_T
TOT17 - - - -
(0-7) PIN UFSET OUT0
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN160 TIN16
PORTSEL
(0x0140) P1_07 P3_12 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ PPG7_T
TOT16 - - - -
(0-7) PIN UFSET OUT0
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN161 TIN17
PORTSEL
(0x0142) P1_11 P3_14 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN192 EINT0
PORTSEL
(0x0180) P2_13 P0_00 P0_08 P0_20 P3_17 P2_01 P2_16 -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN193 EINT1
PORTSEL
(0x0182) P0_01 P3_00 P0_09 P0_22 P4_16 P4_27 P2_17 -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN194 EINT2
PORTSEL
(0x0184) P0_21 P4_30 P4_03 P0_23 P3_20 P2_02 P2_18 -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN195 EINT3
PORTSEL
(0x0186) P0_28 P3_28 P4_04 P0_24 P3_21 P2_03 P2_19 -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN196 EINT4
PORTSEL
(0x0188) P1_03 P0_02 P4_05 P0_25 P3_23 P2_04 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN197 EINT5
PORTSEL
(0x018A) P1_04 P0_03 P0_10 P0_26 P4_17 P4_28 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN198 EINT6
PORTSEL
(0x018C) P1_05 P3_09 P0_11 P0_27 P4_18 P2_06 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN199 EINT7
PORTSEL
(0x018E) P1_06 P4_00 P0_12 P0_29 P4_20 P2_07 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN200 EINT8
PORTSEL
(0x0190) P1_07 P3_11 P0_13 P0_30 P4_21 P4_29 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN201 EINT9
PORTSEL
(0x0192) P1_08 P4_01 P3_01 P0_31 P1_16 P2_08 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN202 EINT10
PORTSEL
(0x0194) P1_09 P4_02 P3_02 P1_00 P4_23 P4_31 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN203 EINT11
PORTSEL
(0x0196) P1_10 P0_04 P3_03 P1_01 P1_18 P3_24 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN204 EINT12
PORTSEL
(0x0198) P1_11 P3_14 P3_04 P1_02 P1_20 P3_25 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN205 EINT13
PORTSEL
(0x019A) P1_12 P0_05 P4_06 P4_08 P1_22 P3_26 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN206 EINT14
PORTSEL
(0x019C) P1_13 P3_16 P4_07 P4_09 P1_24 P3_27 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN207 EINT15
PORTSEL
(0x019E) P1_14 P0_06 P3_05 P4_10 P1_25 P2_09 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN208 EINT16
PORTSEL
(0x01A0) P1_15 P4_19 P3_06 P4_11 P4_24 P3_29 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN209 EINT17
PORTSEL
(0x01A2) P1_17 P3_19 P0_14 P3_10 P1_26 P3_30 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN210 EINT18
PORTSEL
(0x01A4) P1_19 P3_08 P0_15 P3_13 P1_27 P3_31 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN211 EINT19
PORTSEL
(0x01A6) P1_21 P3_22 P0_16 P3_15 P4_25 P2_10 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN212 EINT20
PORTSEL
(0x01A8) P1_23 P3_18 P3_07 P4_12 P1_29 P2_11 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN213 EINT21
PORTSEL
(0x01AA) P1_28 P3_12 P0_17 P4_13 P1_30 P2_12 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN214 EINT22
PORTSEL
(0x01AC) P2_00 P4_22 P0_18 P4_14 P1_31 P2_14 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN215 EINT23
PORTSEL
(0x01AE) P2_05 P0_07 P0_19 P4_15 P4_26 P2_15 - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ PPG0_T
TOT0 TOT1 - - - -
(0-7) PIN OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN216 TEXT0
PORTSEL
(0x01B0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ PPG1_T
TOT0 TOT1 - - - -
(0-7) PIN OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN217 TEXT1
PORTSEL
(0x01B2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ PPG2_T
TOT0 TOT1 - - - -
(0-7) PIN OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN218 TEXT2
PORTSEL
(0x01B4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ PPG3_T
TOT0 TOT1 - - - -
(0-7) PIN OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN219 TEXT3
PORTSEL
(0x01B6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ PPG4_T
TOT0 TOT1 - - - -
(0-7) PIN OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN220 TEXT4
PORTSEL
(0x01B8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U RLT16_ PPG6_T
- - - -
(0-7) PIN FSET UFSET OUT2
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN224 TEXT8
PORTSEL
(0x01C0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - -
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN225 TEXT9
PORTSEL
(0x01C2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - -
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN226 TEXT10
PORTSEL
(0x01C4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
FRT0 FRT1 FRT2 FRT3 FRT4 - - -
(0-7)
RESSEL
- - - - - - - -
OCU0_C (8-15)
K0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
(0-7)
RESSEL
- - - - - - - -
OCU0_CK (8-15)
1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT0_D FRT1_D FRT2_D FRT3_D FRT4_D
- - -
(0-7) OWNB OWNB OWNB OWNB OWNB
RESSEL
- - - - - - - -
IN232 OCU0_D (8-15)
(0x01D0) OWNB0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU0_D (8-15)
OWNB1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT0_F FRT1_F FRT2_F FRT3_F FRT4_F
- - -
(0-7) CMD CMD CMD CMD CMD
RESSEL
- - - - - - - -
OCU0_FC (8-15)
MD0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
RESSEL
- - - - - - - -
OCU0_FC (8-15)
MD1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT0_M FRT1_M FRT2_M FRT3_M FRT4_M
- - -
(0-7) TSF TSF TSF TSF TSF
RESSEL
- - - - - - - -
OCU0_MT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
IN232 OCU0_MT (8-15)
(0x01D0) SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT0_T FRT1_T FRT2_T FRT3_T FRT4_T
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU0_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU0_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL FRT0_Z FRT1_Z FRT2_Z FRT3_Z FRT4_Z
- - -
RESSEL
- - - - - - - -
OCU0_ZT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
IN232 (8-15)
(0x01D0) RESSEL FRT0_Z FRT1_Z FRT2_Z FRT3_Z FRT4_Z
- - -
RESSEL
- - - - - - - -
OCU0_ZT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU0_M (8-15)
SIN233
OD0 PORTSEL
(0x01D2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU0_M (8-15)
SIN234
OD1 PORTSEL
(0x01D4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU1_CK (8-15)
SIN235
0 PORTSEL
(0x01D6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
(0-7)
RESSEL
- - - - - - - -
OCU1_CK (8-15)
1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU1_D (8-15)
OWNB0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
RIC_RE - - - - - - - -
OCU1_D (8-15)
SIN235
OWNB1 PORTSEL
(0x01D6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU1_FC (8-15)
MD0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU1_FC (8-15)
MD1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
RESSEL
- - - - - - - -
OCU1_MT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU1_MT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN235
(0x01D6) - - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU1_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU1_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
RESSEL
- - - - - - - -
OCU1_ZT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN235
(0x01D6) - - -
RESSEL
- - - - - - - -
OCU1_ZT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU1_M (8-15)
SIN236
OD0 PORTSEL
(0x01D8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU1_M (8-15)
SIN237
OD1 PORTSEL
(0x01DA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
(0-7)
RESSEL
- - - - - - - -
OCU2_CK (8-15)
0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU2_CK (8-15)
SIN238
1 PORTSEL
(0x01DC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU2_D (8-15)
OWNB0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
RESSEL
- - - - - - - -
OCU2_D (8-15)
OWNB1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU2_FC (8-15)
MD0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
RIC_RE - - - - - - - -
OCU2_FC (8-15)
SIN238
MD1 PORTSEL
(0x01DC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU2_MT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU2_MT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU2_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
OCU2_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN238
(0x01DC) - - -
RESSEL
- - - - - - - -
OCU2_ZT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - -
RESSEL
- - - - - - - -
OCU2_ZT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU2_M (8-15)
SIN239
OD0 PORTSEL
(0x01DE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU2_M (8-15)
SIN240
OD1 PORTSEL
(0x01E0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU8_CK (8-15)
0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU8_CK (8-15)
1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT8_D FRT9_D FRT10_
- - - - -
(0-7) OWNB OWNB DOWNB
RESSEL
RIC_RE - - - - - - - -
OCU8_D (8-15)
SIN256
OWNB0 PORTSEL
(0x0200) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
RESSEL
- - - - - - - -
OCU8_D (8-15)
OWNB1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT8_F FRT9_F FRT10_
- - - - -
(0-7) CMD CMD FCMD
RESSEL
- - - - - - - -
OCU8_FC (8-15)
MD0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) CMD CMD FCMD
RESSEL
- - - - - - - -
OCU8_FC (8-15)
MD1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT8_M FRT9_M FRT10_
- - - - -
(0-7) TSF TSF MTSF
RESSEL
- - - - - - - -
OCU8_MT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) TSF TSF MTSF
RESSEL
RIC_RE - - - - - - - -
OCU8_MT (8-15)
SIN256
SF1 PORTSEL
(0x0200) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL FRT8_T FRT9_T FRT10_
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
OCU8_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
OCU8_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL FRT8_Z FRT9_Z FRT10_
- - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU8_ZT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN256
(0x0200) - - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU8_ZT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU8_M (8-15)
SIN257
OD0 PORTSEL
(0x0202) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU8_M (8-15)
SIN258
OD1 PORTSEL
(0x0204) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU9_CK (8-15)
0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN259
RESSEL
(0x0206) FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU9_CK (8-15)
1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
RESSEL
- - - - - - - -
OCU9_D (8-15)
OWNB0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
RESSEL
- - - - - - - -
OCU9_D (8-15)
OWNB1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) CMD CMD FCMD
RESSEL
RIC_RE - - - - - - - -
OCU9_FC (8-15)
SIN259
MD0 PORTSEL
(0x0206) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) CMD CMD FCMD
RESSEL
- - - - - - - -
OCU9_FC (8-15)
MD1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) TSF TSF MTSF
RESSEL
- - - - - - - -
OCU9_MT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) TSF TSF MTSF
RESSEL
- - - - - - - -
OCU9_MT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
OCU9_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
RIC_RE - - - - - - - -
OCU9_T1[ (8-15)
SIN259
31:0] PORTSEL
(0x0206) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU9_ZT (8-15)
SF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU9_ZT (8-15)
SF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU9_M (8-15)
SIN260
OD0 PORTSEL
(0x0208) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU9_M (8-15)
SIN261
OD1 PORTSEL
(0x020A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU10_C (8-15)
K0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
FRT8 FRT9 FRT10 - - - - -
(0-7)
RESSEL
- - - - - - - -
OCU10_C (8-15)
K1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN262
(0x020C) - - - - -
RESSEL
- - - - - - - -
OCU10_D (8-15)
OWNB0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
RESSEL
- - - - - - - -
OCU10_D (8-15)
OWNB1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) CMD CMD FCMD
RESSEL
- - - - - - - -
OCU10_F (8-15)
CMD0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN262
(0x020C) - - - - -
(0-7) CMD CMD FCMD
RESSEL
- - - - - - - -
OCU10_F (8-15)
CMD1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) TSF TSF MTSF
RESSEL
- - - - - - - -
OCU10_M (8-15)
TSF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) TSF TSF MTSF
RESSEL
- - - - - - - -
OCU10_M (8-15)
TSF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN262
(0x020C) - - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
OCU10_T (8-15)
0[31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
OCU10_T (8-15)
1[31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU10_Z (8-15)
TSF0 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN262
(0x020C) - - - - -
(0-7) TSF TSF ZTSF
RESSEL
- - - - - - - -
OCU10_Z (8-15)
TSF1 PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU10_M (8-15)
SIN263
OD0 PORTSEL
(0x020E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 1 set 0 - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
OCU10_M (8-15)
SIN264
OD1 PORTSEL
(0x0210) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS0_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN280 ICU0_IN0
PORTSEL
(0x0230) P1_03 P3_08 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS1_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN281 ICU0_IN1
PORTSEL
(0x0232) P1_04 P3_09 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU0_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN282
(0x0234) - - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU0_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS2_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN283 ICU1_IN0
PORTSEL
(0x0236) P1_05 P3_10 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS3_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN284 ICU1_IN1
PORTSEL
(0x0238) P1_06 P3_11 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU1_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN285
(0x023A) - - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU1_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS4_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN286 ICU2_IN0
PORTSEL
(0x023C) P1_07 P3_12 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
- - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN287 ICU2_IN1
PORTSEL
(0x023E) P1_08 P3_13 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU2_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN288
(0x0240) - - -
(0-7) [31:0] [31:0] [31:0] [31:0] [31:0]
RESSEL
- - - - - - - -
ICU2_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS8_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN304 ICU8_IN0
PORTSEL
(0x0260) P1_09 P3_14 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS9_L
- - - - - -
(0-7) PIN SYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN305 ICU8_IN1
PORTSEL
(0x0262) P1_10 P3_15 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU8_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN306
(0x0264) - - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU8_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS10_
- - - - - -
(0-7) PIN LSYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN307 ICU9_IN0
PORTSEL
(0x0266) P1_11 P3_16 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS11_
- - - - - -
(0-7) PIN LSYN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN308 ICU9_IN1
PORTSEL
(0x0268) P1_12 P3_17 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU9_T0[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN309
(0x026A) - - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU9_T1[ (8-15)
31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ MFS12_
- - - - - -
(0-7) PIN LSYN
RESSEL
RIC_RE - - - - - - - -
ICU10_IN (8-15)
SIN310
0 PORTSEL
(0x026C) P1_14 P3_18 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
- - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
ICU10_IN (8-15)
SIN311
1 PORTSEL
(0x026E) P1_15 P3_19 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
- - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU10_T0 (8-15)
[31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
RIC_RE - - - - - - - -
(8-15)
SIN312
(0x0270) - - - - -
(0-7) [31:0] [31:0] T[31:0]
RESSEL
- - - - - - - -
ICU10_T1 (8-15)
[31:0] PORTSEL
- - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
TOT0 - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN352 AIN8
PORTSEL
(0x02C0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
TOT1 - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN353 BIN8
PORTSEL
(0x02C2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ PPG6_T PPG6_T PPG7_T
TOT16 - - -
(0-7) PIN OUT0 OUT2 OUT0
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN354 ZIN8
PORTSEL
(0x02C4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
TOT16 - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN355 AIN9
PORTSEL
(0x02C6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_
TOT17 - - - - - -
(0-7) PIN
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN356 BIN9
PORTSEL
(0x02C8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ PPG6_T PPG6_T PPG7_T
TOT0 - - -
(0-7) PIN OUT0 OUT2 OUT0
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN357 ZIN9
PORTSEL
(0x02CA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U RLT0_U FRT0_M OCU0_
TOT0 TOT0 -
(0-7) PIN FSET FSET TSF OTD0
RESSEL
RIC_RE - - - - - - - -
PPG0_TI (8-15)
SIN376
N1 PORTSEL
(0x02F0) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG0_TI (8-15)
SIN377
N2 PORTSEL
(0x02F2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG0_TI (8-15)
SIN378
N3 PORTSEL
(0x02F4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT0 -
RESSEL
RIC_RE - - - - - - - -
PPG1_TI (8-15)
SIN379
N1 PORTSEL
(0x02F6) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG1_TI (8-15)
SIN380
N2 PORTSEL
(0x02F8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG1_TI (8-15)
SIN381
N3 PORTSEL
(0x02FA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT0 -
RESSEL
RIC_RE - - - - - - - -
PPG2_TI (8-15)
SIN382
N1 PORTSEL
(0x02FC) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG2_TI (8-15)
SIN383
N2 PORTSEL
(0x02FE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG2_TI (8-15)
SIN384
N3 PORTSEL
(0x0300) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
TOT0 TOT1 -
RESSEL
RIC_RE - - - - - - - -
PPG3_TI (8-15)
SIN385
N1 PORTSEL
(0x0302) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG3_TI (8-15)
SIN386
N2 PORTSEL
(0x0304) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG3_TI (8-15)
SIN387
N3 PORTSEL
(0x0306) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT1 -
RESSEL
RIC_RE - - - - - - - -
PPG4_TI (8-15)
SIN388
N1 PORTSEL
(0x0308) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG4_TI (8-15)
SIN389
N2 PORTSEL
(0x030A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG4_TI (8-15)
SIN390
N3 PORTSEL
(0x030C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT1 -
RESSEL
RIC_RE - - - - - - - -
PPG5_TI (8-15)
SIN391
N1 PORTSEL
(0x030E) P1_16 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG5_TI (8-15)
SIN392
N2 PORTSEL
(0x0310) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG5_TI (8-15)
SIN393
N3 PORTSEL
(0x0312) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U RLT16_ FRT8_M OCU8_
TOT0 TOT16 -
(0-7) PIN FSET UFSET TSF OTD0
RESSEL
RIC_RE - - - - - - - -
PPG6_TI (8-15)
SIN394
N1 PORTSEL
(0x0314) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG6_TI (8-15)
SIN395
N2 PORTSEL
(0x0316) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG6_TI (8-15)
SIN396
N3 PORTSEL
(0x0318) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT16 -
RESSEL
RIC_RE - - - - - - - -
PPG7_TI (8-15)
SIN397
N1 PORTSEL
(0x031A) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG7_TI (8-15)
SIN398
N2 PORTSEL
(0x031C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG7_TI (8-15)
SIN399
N3 PORTSEL
(0x031E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
TOT0 TOT16 -
RESSEL
RIC_RE - - - - - - - -
PPG8_TI (8-15)
SIN400
N1 PORTSEL
(0x0320) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG8_TI (8-15)
SIN401
N2 PORTSEL
(0x0322) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG8_TI (8-15)
SIN402
N3 PORTSEL
(0x0324) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT17 -
RESSEL
RIC_RE - - - - - - - -
PPG9_TI (8-15)
SIN403
N1 PORTSEL
(0x0326) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG9_TI (8-15)
SIN404
N2 PORTSEL
(0x0328) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG9_TI (8-15)
SIN405
N3 PORTSEL
(0x032A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT17 -
RESSEL
RIC_RE - - - - - - - -
PPG10_TI (8-15)
SIN406
N1 PORTSEL
(0x032C) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG10_TI (8-15)
SIN407
N2 PORTSEL
(0x032E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG10_TI (8-15)
SIN408
N3 PORTSEL
(0x0330) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
TOT0 TOT17 -
RESSEL
RIC_RE - - - - - - - -
PPG11_TI (8-15)
SIN409
N1 PORTSEL
(0x0332) P1_29 P3_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG11_TI (8-15)
SIN410
N2 PORTSEL
(0x0334) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG11_TI (8-15)
SIN411
N3 PORTSEL
(0x0336) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG12_TI (8-15)
SIN430
N1 PORTSEL
(0x035C) P2_06 P3_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG12_TI (8-15)
SIN431
N2 PORTSEL
(0x035E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG12_TI (8-15)
SIN432
N3 PORTSEL
(0x0360) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG13_TI (8-15)
SIN433
N1 PORTSEL
(0x0362) P2_06 P3_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG13_TI (8-15)
SIN434
N2 PORTSEL
(0x0364) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG13_TI (8-15)
SIN435
N3 PORTSEL
(0x0366) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG14_TI (8-15)
SIN436
N1 PORTSEL
(0x0368) P2_06 P3_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG14_TI (8-15)
SIN437
N2 PORTSEL
(0x036A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG14_TI (8-15)
SIN438
N3 PORTSEL
(0x036C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG15_TI (8-15)
SIN439
N1 PORTSEL
(0x036E) P2_06 P3_31 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG15_TI (8-15)
SIN440
N2 PORTSEL
(0x0370) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG15_TI (8-15)
SIN441
N3 PORTSEL
(0x0372) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG16_TI (8-15)
SIN442
N1 PORTSEL
(0x0374) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG16_TI (8-15)
SIN443
N2 PORTSEL
(0x0376) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG16_TI (8-15)
SIN444
N3 PORTSEL
(0x0378) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG17_TI (8-15)
SIN445
N1 PORTSEL
(0x037A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG17_TI (8-15)
SIN446
N2 PORTSEL
(0x037C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG17_TI (8-15)
SIN447
N3 PORTSEL
(0x037E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG18_TI (8-15)
SIN448
N1 PORTSEL
(0x0380) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG18_TI (8-15)
SIN449
N2 PORTSEL
(0x0382) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG18_TI (8-15)
SIN450
N3 PORTSEL
(0x0384) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG19_TI (8-15)
SIN451
N1 PORTSEL
(0x0386) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG19_TI (8-15)
SIN452
N2 PORTSEL
(0x0388) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG19_TI (8-15)
SIN453
N3 PORTSEL
(0x038A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG20_TI (8-15)
SIN454
N1 PORTSEL
(0x038C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG20_TI (8-15)
SIN455
N2 PORTSEL
(0x038E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG20_TI (8-15)
SIN456
N3 PORTSEL
(0x0390) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG21_TI (8-15)
SIN457
N1 PORTSEL
(0x0392) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG21_TI (8-15)
SIN458
N2 PORTSEL
(0x0394) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG21_TI (8-15)
SIN459
N3 PORTSEL
(0x0396) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG22_TI (8-15)
SIN460
N1 PORTSEL
(0x0398) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG22_TI (8-15)
SIN461
N2 PORTSEL
(0x039A) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG22_TI (8-15)
SIN462
N3 PORTSEL
(0x039C) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG23_TI (8-15)
SIN463
N1 PORTSEL
(0x039E) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG23_TI (8-15)
SIN464
N2 PORTSEL
(0x03A0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG23_TI (8-15)
SIN465
N3 PORTSEL
(0x03A2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG24_TI (8-15)
SIN466
N1 PORTSEL
(0x03A4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG24_TI (8-15)
SIN467
N2 PORTSEL
(0x03A6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG24_TI (8-15)
SIN468
N3 PORTSEL
(0x03A8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG25_TI (8-15)
SIN469
N1 PORTSEL
(0x03AA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG25_TI (8-15)
SIN470
N2 PORTSEL
(0x03AC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG25_TI (8-15)
SIN471
N3 PORTSEL
(0x03AE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG26_TI (8-15)
SIN472
N1 PORTSEL
(0x03B0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG26_TI (8-15)
SIN473
N2 PORTSEL
(0x03B2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG26_TI (8-15)
SIN474
N3 PORTSEL
(0x03B4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG27_TI (8-15)
SIN475
N1 PORTSEL
(0x03B6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG27_TI (8-15)
SIN476
N2 PORTSEL
(0x03B8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG27_TI (8-15)
SIN477
N3 PORTSEL
(0x03BA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG28_TI (8-15)
SIN478
N1 PORTSEL
(0x03BC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG28_TI (8-15)
SIN479
N2 PORTSEL
(0x03BE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG28_TI (8-15)
SIN480
N3 PORTSEL
(0x03C0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG29_TI (8-15)
SIN481
N1 PORTSEL
(0x03C2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG29_TI (8-15)
SIN482
N2 PORTSEL
(0x03C4) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG29_TI (8-15)
SIN483
N3 PORTSEL
(0x03C6) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG30_TI (8-15)
SIN484
N1 PORTSEL
(0x03C8) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG30_TI (8-15)
SIN485
N2 PORTSEL
(0x03CA) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG30_TI (8-15)
SIN486
N3 PORTSEL
(0x03CC) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U
TOT0 - - - - -
(0-7) PIN FSET
RESSEL
RIC_RE - - - - - - - -
PPG31_TI (8-15)
SIN487
N1 PORTSEL
(0x03CE) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG31_TI (8-15)
SIN488
N2 PORTSEL
(0x03D0) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
set 0 - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
PPG31_TI (8-15)
SIN489
N3 PORTSEL
(0x03D2) - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U RLT1_U OCU0_ OCU1_ PPG0_T PPG1_T PPG3_T
(0-7) PIN FSET FSET OTD0 OTD0 OUT0 OUT2 OUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN490 _HWTRG
PORTSEL
(0x03D4) 0 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT16_ OCU1_ OCU2_ PPG0_T PPG2_T PPG4_T
(0-7) PIN FSET UFSET OTD0 OTD0 OUT2 OUT0 OUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN491 _HWTRG
PORTSEL
(0x03D6) 1 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT17_ OCU2_ OCU8_ PPG1_T PPG2_T PPG4_T
(0-7) PIN UFSET UFSET OTD0 OTD0 OUT0 OUT2 OUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN492 _HWTRG
PORTSEL
(0x03D8) 2 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT0_U OCU8_ OCU9_ PPG1_T PPG3_T PPG5_T
(0-7) PIN UFSET FSET OTD0 OTD0 OUT2 OUT0 OUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN493 _HWTRG
PORTSEL
(0x03DA) 3 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN494 _HWTRG
PORTSEL
(0x03DC) 4 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN495 _HWTRG
PORTSEL
(0x03DE) 5 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN496 _HWTRG
PORTSEL
(0x03E0) 6 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN497 _HWTRG
PORTSEL
(0x03E2) 7 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN498 _HWTRG
PORTSEL
(0x03E4) 8 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN499 _HWTRG
PORTSEL
(0x03E6) 9 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN500 _HWTRG
PORTSEL
(0x03E8) 10 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT16_ OCU10_ OCU1_ PPG5_T PPG7_T PPG9_T
(0-7) PIN UFSET UFSET OTD0 OTD0 OUT2 OUT0 OUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN501 _HWTRG
PORTSEL
(0x03EA) 11 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN502 _HWTRG
PORTSEL
(0x03EC) 12 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT16_ OCU1_ OCU9_ PPG6_T PPG8_T PPG10_
(0-7) PIN FSET UFSET OTD0 OTD0 OUT2 OUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN503 _HWTRG
PORTSEL
(0x03EE) 13 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT17_ OCU2_ OCU10_ PPG7_T PPG8_T PPG10_
(0-7) PIN UFSET UFSET OTD0 OTD0 OUT0 OUT2 TOUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN504 _HWTRG
PORTSEL
(0x03F0) 14 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT17_ RLT0_U OCU8_ OCU0_ PPG7_T PPG9_T PPG11_
(0-7) PIN UFSET FSET OTD0 OTD0 OUT2 OUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN505 _HWTRG
PORTSEL
(0x03F2) 15 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT0_U RLT16_ OCU9_ OCU1_ PPG8_T PPG9_T PPG11_
(0-7) PIN FSET UFSET OTD0 OTD0 OUT0 OUT2 TOUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN506 _HWTRG
PORTSEL
(0x03F4) 16 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT17_ OCU10_ OCU2_ PPG8_T PPG10_ PPG12_
(0-7) PIN FSET UFSET OTD0 OTD0 OUT2 TOUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN507 _HWTRG
PORTSEL
(0x03F6) 17 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT0_U OCU0_ OCU9_ PPG9_T PPG10_ PPG12_
(0-7) PIN UFSET FSET OTD0 OTD0 OUT0 TOUT2 TOUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN508 _HWTRG
PORTSEL
(0x03F8) 18 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT1_U OCU1_ OCU10_ PPG9_T PPG11_ PPG13_
(0-7) PIN UFSET FSET OTD0 OTD0 OUT2 TOUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN509 _HWTRG
PORTSEL
(0x03FA) 19 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U RLT17_ OCU2_ OCU0_ PPG10_ PPG11_ PPG13_
(0-7) PIN FSET UFSET OTD0 OTD0 TOUT0 TOUT2 TOUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN510 _HWTRG
PORTSEL
(0x03FC) 20 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT0_U OCU8_ OCU1_ PPG10_ PPG12_ PPG14_
(0-7) PIN FSET FSET OTD0 OTD0 TOUT2 TOUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN511 _HWTRG
PORTSEL
(0x03FE) 21 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT1_U OCU9_ OCU2_ PPG11_ PPG12_ PPG14_
(0-7) PIN UFSET FSET OTD0 OTD0 TOUT0 TOUT2 TOUT2
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN512 _HWTRG
PORTSEL
(0x0400) 22 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT16_ OCU10_ OCU8_ PPG11_ PPG13_ PPG15_
(0-7) PIN UFSET UFSET OTD0 OTD0 TOUT2 TOUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN513 _HWTRG
PORTSEL
(0x0402) 23 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN514 _HWTRG
PORTSEL
(0x0404) 24 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN515 _HWTRG
PORTSEL
(0x0406) 25 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN516 _HWTRG
PORTSEL
(0x0408) 26 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN517 _HWTRG
PORTSEL
(0x040A) 27 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN518 _HWTRG
PORTSEL
(0x040C) 28 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN519 _HWTRG
PORTSEL
(0x040E) 29 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN520 _HWTRG
PORTSEL
(0x0410) 30 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN521 _HWTRG
PORTSEL
(0x0412) 31 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN586 _HWTRG
PORTSEL
(0x0494) 32 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN587 _HWTRG
PORTSEL
(0x0496) 33 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN588 _HWTRG
PORTSEL
(0x0498) 34 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN589 _HWTRG
PORTSEL
(0x049A) 35 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN590 _HWTRG
PORTSEL
(0x049C) 36 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN591 _HWTRG
PORTSEL
(0x049E) 37 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN592 _HWTRG
PORTSEL
(0x04A0) 38 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN593 _HWTRG
PORTSEL
(0x04A2) 39 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN594 _HWTRG
PORTSEL
(0x04A4) 40 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN595 _HWTRG
PORTSEL
(0x04A6) 41 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN596 _HWTRG
PORTSEL
(0x04A8) 42 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN597 _HWTRG
PORTSEL
(0x04AA) 43 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN598 _HWTRG
PORTSEL
(0x04AC) 44 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN599 _HWTRG
PORTSEL
(0x04AE) 45 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN600 _HWTRG
PORTSEL
(0x04B0) 46 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN601 _HWTRG
PORTSEL
(0x04B2) 47 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN602 _HWTRG
PORTSEL
(0x04B4) 48 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN603 _HWTRG
PORTSEL
(0x04B6) 49 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN604 _HWTRG
PORTSEL
(0x04B8) 50 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN605 _HWTRG
PORTSEL
(0x04BA) 51 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN606 _HWTRG
PORTSEL
(0x04BC) 52 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN607 _HWTRG
PORTSEL
(0x04BE) 53 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN608 _HWTRG
PORTSEL
(0x04C0) 54 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN609 _HWTRG
PORTSEL
(0x04C2) 55 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN610 _HWTRG
PORTSEL
(0x04C4) 56 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT0_U OCU8_ OCU2_ PPG28_ PPG30_ PPG0_T
(0-7) PIN FSET FSET OTD0 OTD0 TOUT2 TOUT0 OUT0
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN611 _HWTRG
PORTSEL
(0x04C6) 57 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT1_U OCU9_ OCU8_ PPG29_ PPG30_ PPG0_T
(0-7) PIN UFSET FSET OTD0 OTD0 TOUT0 TOUT2 OUT2
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN612 _HWTRG
PORTSEL
(0x04C8) 58 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT16_ OCU10_ OCU9_ PPG29_ PPG31_ PPG1_T
(0-7) PIN UFSET UFSET OTD0 OTD0 TOUT2 TOUT0 OUT0
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN613 _HWTRG
PORTSEL
(0x04CA) 59 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL PORT_ RLT0_U RLT1_U OCU0_ OCU1_ PPG30_ PPG31_ PPG1_T
(0-7) PIN FSET FSET OTD0 OTD0 TOUT0 TOUT2 OUT2
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN614 _HWTRG
PORTSEL
(0x04CC) 60 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT1_U RLT16_ OCU1_ OCU2_ PPG30_ PPG0_T PPG2_T
(0-7) PIN FSET UFSET OTD0 OTD0 TOUT2 OUT0 OUT0
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN615 _HWTRG
PORTSEL
(0x04CE) 61 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT16_ RLT17_ OCU2_ OCU8_ PPG31_ PPG0_T PPG2_T
(0-7) PIN UFSET UFSET OTD0 OTD0 TOUT0 OUT2 OUT2
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN616 _HWTRG
PORTSEL
(0x04D0) 62 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL PORT_ RLT17_ RLT0_U OCU8_ OCU9_ PPG31_ PPG1_T PPG3_T
(0-7) PIN UFSET FSET OTD0 OTD0 TOUT2 OUT0 OUT0
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN617 _HWTRG
PORTSEL
(0x04D2) 63 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- TOT0 TOT16 - - - - -
(0-7)
RESSEL
RIC_RE DDRHSS - - - - - - - -
(8-15)
SIN626 PI_MSTA
PORTSEL
(0x04E4) RT - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN629 MDIO
PORTSEL
(0x04EA) P0_31 P3_06 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN630 CRS
PORTSEL
(0x04EC) P1_02 P0_20 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN631 RXD0
PORTSEL
(0x04EE) P0_27 P3_04 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN632 RXD1
PORTSEL
(0x04F0) P0_28 P4_06 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN633 RXD2
PORTSEL
(0x04F2) P0_29 P4_07 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN634 RXD3
PORTSEL
(0x04F4) P0_30 P3_05 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN635 COL
PORTSEL
(0x04F6) P1_01 P0_19 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN636 RXDV
PORTSEL
(0x04F8) P0_19 P4_02 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN637 RXER
PORTSEL
(0x04FA) P0_18 P4_01 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)

S6J3350 Series

Register [3:0]
Resource 0 1 2 3 4 5 6 7
(Offset) /PORT
SEL[3:0] 8 9 10 11 12 13 14 15
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN638 RXCLK
PORTSEL
(0x04FC) P0_17 P4_00 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN639 TXCLK
PORTSEL
(0x04FE) P0_20 P4_03 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN685 ADTRG0
PORTSEL
(0x055A) P1_16 P2_10 - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
- - - - - - - -
(0-7)
RESSEL
RIC_RE - - - - - - - -
(8-15)
SIN686 ADTRG1
PORTSEL
(0x055C) P4_22 P1_08 P2_11 - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
Notes:
− When both GPIO_PORTEN.GPORTEN and PPC_PCFGR.PIE are configured as 0, the input signal is disconnected and
external interrupt cannot be detected. During disconnecting, I/O internally outputs "low" to internal logic, and if ELVR is
configured as low-level-detection, falling-edge-detection, or both-edge-detection it will be detected as external interrupt with
EIRR=1.
− "Set 0" (Set 1) means that "0" ("1") is inputted.
− OCUx_MODn is described as MODn pin in Traveo™ Platform Hardware Manual.

S6J3350 Series
7.2 Port Output Function Configuration

The port output function configuration (POF) is a function to select a function to output to a port.
A resource which supports a port output relocation has its PPC_PCFGR.POF to configure resource output.
7.2.1 Standard Configuration

Register Resource Functional Outputs
Port
(Offset) POF=0 POF=1 POF=2 POF=3 POF=4 POF=5 POF=6 POF=7
PPC_PCF GPIO_PO
GR000 P0_00 DR0:POD - - - - - - MAD1
(0x0000) 00
PPC_PCF GPIO_PO
GR001 P0_01 DR0:POD - - - - - - MAD2
(0x0002) 01
PPC_PCF GPIO_PO
GR002 P0_02 DR0:POD SCK1_0 - - - - SCL1 MAD3
(0x0004) 02
PPC_PCF GPIO_PO
GR003 P0_03 DR0:POD SOT1_0 - - - - SDA1 MAD4
(0x0006) 03
PPC_PCF GPIO_PO
GR004 P0_04 DR0:POD SCS10_0 - - - - - MAD5
(0x0008) 04
PPC_PCF GPIO_PO
GR005 P0_05 DR0:POD SCS11_0 - - - - SOT0_1 MAD6
(0x000A) 05
PPC_PCF GPIO_PO
PPG0_TO
GR006 P0_06 DR0:POD SCS12_0 - SCK0_1 - - MAD7
UT0_1
(0x000C) 06
PPC_PCF GPIO_PO
PPG0_TO
GR007 P0_07 DR0:POD SCS13_0 - SCS00_1 - - MAD8
UT2_1
(0x000E) 07
PPC_PCF GPIO_PO
PPG1_TO
GR008 P0_08 DR0:POD - - - - - MAD9
UT0_1
(0x0010) 08
PPC_PCF GPIO_PO
PPG1_TO
GR009 P0_09 DR0:POD - - - - - MAD10
UT2_1
(0x0012) 09
PPC_PCF GPIO_PO
SCS171_ PPG2_TO
GR010 P0_10 DR0:POD - - - - MAD11
1 UT0_1
(0x0014) 10
PPC_PCF GPIO_PO
PPG2_TO
GR011 P0_11 DR0:POD - - - - - MAD12
UT2_1
(0x0016) 11
PPC_PCF GPIO_PO
PPG3_TO
GR012 P0_12 DR0:POD - - - - - MAD13
UT0_1
(0x0018) 12
PPC_PCF GPIO_PO
PPG3_TO
GR013 P0_13 DR0:POD - - - - - MAD14
UT2_1
(0x001A) 13

S6J3350 Series

Port
PPC_PCF GPIO_PO
GR014 P0_14 DR0:POD - - - - - SCK4_1 MOEX
(0x001C) 14
PPC_PCF GPIO_PO
GR015 P0_15 DR0:POD - - - - - SCS40_1 MWEX
(0x001E) 15
PPC_PCF GPIO_PO
GR016 P0_16 DR0:POD - - - - - SCS41_1 MCLK
(0x0020) 16
PPC_PCF GPIO_PO
GR017 P0_17 DR0:POD - - - - - SCS43_1 MDQM0
(0x0022) 17
PPC_PCF GPIO_PO
GR018 P0_18 DR0:POD - - - MDC_1 - - MCSX2
(0x0024) 18
PPC_PCF GPIO_PO
GR019 P0_19 DR0:POD - - - - - - MCSX3
(0x0026) 19
PPC_PCF GPIO_PO
GR020 P0_20 DR0:POD - - - - - - -
(0x0028) 20
PPC_PCF GPIO_PO
M_SDATA
GR021 P0_21 DR0:POD - TXEN_0 M_DQ3 - - -
0_0
(0x002A) 21
PPC_PCF GPIO_PO
M_SDATA
GR022 P0_22 DR0:POD SCK2_0 TXD0_0 M_DQ2 SOT9_2 - -
0_2
(0x002C) 22
PPC_PCF GPIO_PO
M_SDATA
GR023 P0_23 DR0:POD SOT2_0 TXD1_0 M_DQ1 SCK9_2 - -
0_1
(0x002E) 23
PPC_PCF GPIO_PO
GR024 P0_24 DR0:POD SCS20_0 M_SSEL0 TXD2_0 M_DQ0 SCS90_2 - -
(0x0030) 24
PPC_PCF GPIO_PO
M_SDATA
GR025 P0_25 DR0:POD SCS21_0 TXD3_0 M_CS#_1 SCS91_2 - -
0_3
(0x0032) 25
PPC_PCF GPIO_PO
GR026 P0_26 DR0:POD SCS22_0 M_SCLK0 TXER_0 M_CK - - -
(0x0034) 26
PPC_PCF GPIO_PO
M_SDATA
GR027 P0_27 DR0:POD SCS23_0 - M_RWDS - - -
1_0
(0x0036) 27
PPC_PCF GPIO_PO
M_SDATA
GR028 P0_28 DR0:POD - - M_DQ4 SCK8_2 - -
1_2
(0x0038) 28

S6J3350 Series

Port
PPC_PCF GPIO_PO
M_SDATA
GR029 P0_29 DR0:POD SCK3_0 - M_DQ5 SOT8_2 - -
1_1
(0x003A) 29
PPC_PCF GPIO_PO
GR030 P0_30 DR0:POD SOT3_0 M_SSEL1 - M_DQ6 SCS80_2 - -
(0x003C) 30
PPC_PCF GPIO_PO
M_SDATA
GR031 P0_31 DR0:POD SCS30_0 MDIO_0 M_DQ7 - - -
1_3
(0x003E) 31
PPC_PCF GPIO_PO
GR100 P1_00 DR1:POD SCS31_0 - MDC_0 M_CS#_2 - - -
(0x0040) 00
PPC_PCF GPIO_PO
GR101 P1_01 DR1:POD SCS32_0 - - - - - -
(0x0042) 01
PPC_PCF GPIO_PO
GR102 P1_02 DR1:POD SCS33_0 - - - - - -
(0x0044) 02
PPC_PCF GPIO_PO
OCU0_O PPG0_TO
GR103 P1_03 DR1:POD - - - - -
TD0_0 UT0_0
(0x0046) 03
PPC_PCF GPIO_PO
OCU0_O PPG0_TO
GR104 P1_04 DR1:POD SCK0_0 - SCL0 TOT0_0 -
TD1_0 UT2_0
(0x0048) 04
PPC_PCF GPIO_PO
TRACE0_ PPG1_TO
GR105 P1_05 DR1:POD SOT0_0 - SDA0 - -
0 UT0_0
(0x004A) 05
PPC_PCF GPIO_PO
TRACE1_ PPG1_TO
GR106 P1_06 DR1:POD SCS00_0 - TX0_0 TOT1_0 -
0 UT2_0
(0x004C) 06
PPC_PCF GPIO_PO
TRACE2_ OCU1_O PPG2_TO
GR107 P1_07 DR1:POD - - - -
0 TD0_0 UT0_0
(0x004E) 07
PPC_PCF GPIO_PO
TRACE3_ OCU1_O PPG2_TO
GR108 P1_08 DR1:POD - TX1_0 TOT16_0 -
0 TD1_0 UT2_0
(0x0050) 08
PPC_PCF GPIO_PO
OCU2_O TRACE_C PPG3_TO
GR109 P1_09 DR1:POD SCK16_0 - SCL16 -
TD0_0 TL_0 UT0_0
(0x0052) 09
PPC_PCF GPIO_PO
OCU2_O TRACE_C PPG3_TO
GR110 P1_10 DR1:POD SOT16_0 - SDA16 -
TD1_0 LK_0 UT2_0
(0x0054) 10
PPC_PCF GPIO_PO
SCS160_ INDICATO OCU8_O PPG4_TO
GR111 P1_11 DR1:POD - - -
0 R0_0 TD0_0 UT0_0
(0x0056) 11

S6J3350 Series

Port
PPC_PCF GPIO_PO
SCS161_ OCU8_O
GR112 P1_12 DR1:POD - - TOT17_0 - TX2_0
0 TD1_0
(0x0058) 12
PPC_PCF GPIO_PO
OCU9_O
GR113 P1_13 DR1:POD - - - - - -
TD0_0
(0x005A) 13
PPC_PCF GPIO_PO
SYSC0_C OCU9_O PPG5_TO
GR114 P1_14 DR1:POD - - TOT48_0 TX3_0
LK_1 TD1_0 UT0_0
(0x005C) 14
PPC_PCF GPIO_PO
OCU10_O PPG5_TO INDICATO
GR115 P1_15 DR1:POD SCK17_0 - SCL17 SCK12_1
TD0_0 UT2_0 R0_1
(0x005E) 15
PPC_PCF GPIO_PO
OCU10_O SYSC0_C
GR116 P1_16 DR1:POD SOT17_0 - SDA17 TOT49_0 WOT
TD1_0 LK_0
(0x0060) 16
PPC_PCF GPIO_PO
SCS170_ PPG6_TO
GR117 P1_17 DR1:POD - - - - -
0 UT0_0
(0x0062) 17
PPC_PCF GPIO_PO
SCS171_ PPG6_TO
GR118 P1_18 DR1:POD - - - - TX5_0
0 UT2_0
(0x0064) 18
PPC_PCF GPIO_PO
PPG7_TO
GR119 P1_19 DR1:POD - - - - - -
UT0_0
(0x0066) 19
PPC_PCF GPIO_PO
PPG7_TO
GR120 P1_20 DR1:POD SCK8_0 - SCL8 - - -
UT2_0
(0x0068) 20
PPC_PCF GPIO_PO
PPG8_TO
GR121 P1_21 DR1:POD SOT8_0 - SDA8 - - -
UT0_0
(0x006A) 21
PPC_PCF GPIO_PO
PPG8_TO
GR122 P1_22 DR1:POD SCS80_0 - - - - TX6_0
UT2_0
(0x006C) 22
PPC_PCF GPIO_PO
PPG9_TO
GR123 P1_23 DR1:POD - - - - - -
UT0_0
(0x006E) 23
PPC_PCF GPIO_PO
PPG9_TO
GR124 P1_24 DR1:POD SCK9_0 - SCL9 - - -
UT2_0
(0x0070) 24
PPC_PCF GPIO_PO
PPG10_T
GR125 P1_25 DR1:POD SOT9_0 - SDA9 - - -
OUT0_0
(0x0072) 25
PPC_PCF GPIO_PO
PPG10_T
GR126 P1_26 DR1:POD SCS90_0 - - - - -
OUT2_0
(0x0074) 26

S6J3350 Series

Port
PPC_PCF GPIO_PO
PPG11_T
GR127 P1_27 DR1:POD SCS91_0 - - - - -
OUT0_0
(0x0076) 27
PPC_PCF GPIO_PO
PPG11_T
GR128 P1_28 DR1:POD - - - - - -
OUT2_0
(0x0078) 28
PPC_PCF GPIO_PO
GR129 P1_29 DR1:POD SCK10_0 - SCL10 - - - -
(0x007A) 29
PPC_PCF GPIO_PO
PPG12_T
GR130 P1_30 DR1:POD SOT10_0 - SDA10 - - -
OUT0_0
(0x007C) 30
PPC_PCF GPIO_PO
SCS100_ PPG12_T
GR131 P1_31 DR1:POD - - - - -
0 OUT2_0
(0x007E) 31
PPC_PCF GPIO_PO
PPG13_T
GR200 P2_00 DR2:POD - - - - - -
OUT0_0
(0x0080) 00
PPC_PCF GPIO_PO
PPG13_T
GR201 P2_01 DR2:POD SCK11_0 - SCL11 - - -
OUT2_0
(0x0082) 01
PPC_PCF GPIO_PO
PPG14_T
GR202 P2_02 DR2:POD SOT11_0 - SDA11 - - -
OUT0_0
(0x0084) 02
PPC_PCF GPIO_PO
SCS110_ PPG14_T
GR203 P2_03 DR2:POD - - - - -
0 OUT2_0
(0x0086) 03
PPC_PCF GPIO_PO
PPG15_T
GR204 P2_04 DR2:POD SCS111_0 - - - - -
OUT0_0
(0x0088) 04
PPC_PCF GPIO_PO
PPG15_T
GR205 P2_05 DR2:POD - - - - - -
OUT2_0
(0x008A) 05
PPC_PCF GPIO_PO
GR206 P2_06 DR2:POD SCK12_0 - SCL12 - - - -
(0x008C) 06
PPC_PCF GPIO_PO
GR207 P2_07 DR2:POD SOT12_0 - SDA12 - - - -
(0x008E) 07
PPC_PCF GPIO_PO
SCS120_
GR208 P2_08 DR2:POD - - - - - -
0
(0x0090) 08
PPC_PCF GPIO_PO
PPG14_T
GR209 P2_09 DR2:POD SCS23_1 - - - - MCSX0
OUT0_1
(0x0092) 09

S6J3350 Series

Port
PPC_PCF GPIO_PO
GR210 P2_10 DR2:POD SCS31_1 - - - - - MCSX1
(0x0094) 10
PPC_PCF GPIO_PO
GR211 P2_11 DR2:POD SCS32_1 - - - - - MDATA0
(0x0096) 11
PPC_PCF GPIO_PO
(0x0098) 12
PPC_PCF GPIO_PO
GR213 P2_13 DR2:POD - - - - - - MDATA2
(0x009A) 13
PPC_PCF GPIO_PO
GR214 P2_14 DR2:POD SCK4_0 - SCL4 - - - MDATA3
(0x009C) 14
PPC_PCF GPIO_PO
GR215 P2_15 DR2:POD SOT4_0 - SDA4 - - - MDATA4
(0x009E) 15
PPC_PCF GPIO_PO
(0x00A0) 16
PPC_PCF GPIO_PO
(0x00A2) 17
PPC_PCF GPIO_PO
(0x00A4) 18
PPC_PCF GPIO_PO
GR219 P2_19 DR2:POD SCS43_0 - - - - TX7_1 MAD0
(0x00A6) 19
PPC_PCF GPIO_PO
PPG4_TO
GR300 P3_00 DR3:POD - TXD1_1 - - - MAD15
UT0_1
(0x00C0) 00
PPC_PCF GPIO_PO
PPG4_TO
GR301 P3_01 DR3:POD SCK1_1 TXD2_1 - - - MAD16
UT2_1
(0x00C2) 01
PPC_PCF GPIO_PO
PPG5_TO
GR302 P3_02 DR3:POD SOT1_1 TXD3_1 - - - MAD17
UT0_1
(0x00C4) 02
PPC_PCF GPIO_PO
PPG5_TO
GR303 P3_03 DR3:POD SCS10_1 TXER_1 - - - MAD18
UT2_1
(0x00C6) 03
PPC_PCF GPIO_PO
GR304 P3_04 DR3:POD SCS11_1 - - - - - MAD19
(0x00C8) 04

S6J3350 Series

Port
PPC_PCF GPIO_PO
GR305 P3_05 DR3:POD SCS12_1 - - - - - MAD20
(0x00CA) 05
PPC_PCF GPIO_PO
GR306 P3_06 DR3:POD SCS13_1 MDIO_1 - - - SOT4_1 MAD21
(0x00CC) 06
PPC_PCF GPIO_PO
GR307 P3_07 DR3:POD - - - - - SCS42_1 MDQM1
(0x00CE) 07
PPC_PCF GPIO_PO
PPG6_TO OCU0_O
GR308 P3_08 DR3:POD - - - - -
UT0_1 TD0_1
(0x00D0) 08
PPC_PCF GPIO_PO
PPG6_TO OCU0_O PPG22_T
GR309 P3_09 DR3:POD SCK8_1 - TOT0_1 -
UT2_1 TD1_1 OUT0_0
(0x00D2) 09
PPC_PCF GPIO_PO
PPG7_TO OCU1_O TRACE0_ PPG22_T
GR310 P3_10 DR3:POD SOT8_1 - TX0_1
UT0_1 TD0_1 1 OUT2_0
(0x00D4) 10
PPC_PCF GPIO_PO
PPG7_TO OCU1_O TRACE1_
GR311 P3_11 DR3:POD SCS80_1 - TOT1_1 -
UT2_1 TD1_1 1
(0x00D6) 11
PPC_PCF GPIO_PO
GR312 P3_12 DR3:POD - - - TX1_1
UT0_1 TD0_1 1
(0x00D8) 12
PPC_PCF GPIO_PO
GR313 P3_13 DR3:POD SCK10_1 - TOT16_1 -
UT2_1 TD1_1 1
(0x00DA) 13
PPC_PCF GPIO_PO
PPG9_TO OCU8_O TRACE_C
GR314 P3_14 DR3:POD SOT10_1 - - -
UT0_1 TD0_1 TL_1
(0x00DC) 14
PPC_PCF GPIO_PO
SCS100_ PPG9_TO OCU8_O TRACE_C
GR315 P3_15 DR3:POD - TOT17_1 TX2_1
1 UT2_1 TD1_1 LK_1
(0x00DE) 15
PPC_PCF GPIO_PO
PPG10_T OCU9_O
GR316 P3_16 DR3:POD - - - - -
OUT0_1 TD0_1
(0x00E0) 16
PPC_PCF GPIO_PO
PPG10_T OCU9_O
GR317 P3_17 DR3:POD - - TOT48_1 - TX3_1
OUT2_1 TD1_1
(0x00E2) 17
PPC_PCF GPIO_PO
PPG11_T OCU10_O
GR318 P3_18 DR3:POD - - - - -
OUT0_1 TD0_1
(0x00E4) 18
PPC_PCF GPIO_PO
PPG11_T OCU10_O
GR319 P3_19 DR3:POD SCK9_1 - - - -
OUT2_1 TD1_1
(0x00E6) 19

S6J3350 Series

Port
PPC_PCF GPIO_PO
GR320 P3_20 DR3:POD SOT9_1 - - - - - TX5_1
(0x00E8) 20
PPC_PCF GPIO_PO
GR321 P3_21 DR3:POD SCS90_1 - - - TOT49_1 - -
(0x00EA) 21
PPC_PCF GPIO_PO
GR322 P3_22 DR3:POD SCS91_1 - - - - - -
(0x00EC) 22
PPC_PCF GPIO_PO
SCS120_
GR323 P3_23 DR3:POD - - - - - TX6_1
1
(0x00EE) 23
PPC_PCF GPIO_PO
PPG12_T
GR324 P3_24 DR3:POD SOT2_1 - - - - MDATA8
OUT0_1
(0x00F0) 24
PPC_PCF GPIO_PO
PPG12_T
GR325 P3_25 DR3:POD SCS20_1 - - - - MDATA9
OUT2_1
(0x00F2) 25
PPC_PCF GPIO_PO
PPG13_T
OUT0_1
(0x00F4) 26
PPC_PCF GPIO_PO
PPG13_T
OUT2_1
(0x00F6) 27
PPC_PCF GPIO_PO
PPG14_T
GR328 P3_28 DR3:POD - - - - - MDATA12
OUT2_1
(0x00F8) 28
PPC_PCF GPIO_PO
PPG15_T
GR329 P3_29 DR3:POD SCK3_1 - - - - MDATA13
OUT0_1
(0x00FA) 29
PPC_PCF GPIO_PO
PPG15_T
GR330 P3_30 DR3:POD SOT3_1 - - - - MDATA14
OUT2_1
(0x00FC) 30
PPC_PCF GPIO_PO
(0x00FE) 31
PPC_PCF GPIO_PO
PPG16_T
GR400 P4_00 DR4:POD - - - - - -
OUT0_0
(0x0100) 00
PPC_PCF GPIO_PO
PPG16_T
GR401 P4_01 DR4:POD - - - - TX0_2 -
OUT2_0
(0x0102) 01
PPC_PCF GPIO_PO
PPG17_T
GR402 P4_02 DR4:POD - - - - - -
OUT0_0
(0x0104) 02

S6J3350 Series

Port
PPC_PCF GPIO_PO
SCS170_ PPG17_T
GR403 P4_03 DR4:POD - - - - -
1 OUT2_0
(0x0106) 03
PPC_PCF GPIO_PO
PPG18_T
GR404 P4_04 DR4:POD - TXEN_1 SCK17_1 - TX3_2 -
OUT0_0
(0x0108) 04
PPC_PCF GPIO_PO
PPG18_T
GR405 P4_05 DR4:POD - TXD0_1 SOT17_1 - - -
OUT2_0
(0x010A) 05
PPC_PCF GPIO_PO
PPG19_T
GR406 P4_06 DR4:POD - - - - - -
OUT0_0
(0x010C) 06
PPC_PCF GPIO_PO
PPG19_T
GR407 P4_07 DR4:POD - - - - - -
OUT2_0
(0x010E) 07
PPC_PCF GPIO_PO
PPG20_T
GR408 P4_08 DR4:POD - - - - - -
OUT0_0
(0x0110) 08
PPC_PCF GPIO_PO
PPG20_T
GR409 P4_09 DR4:POD - - - - - -
OUT2_0
(0x0112) 09
PPC_PCF GPIO_PO
PPG21_T
GR410 P4_10 DR4:POD - - - - - -
OUT0_0
(0x0114) 10
PPC_PCF GPIO_PO
PPG21_T
GR411 P4_11 DR4:POD - - - - - -
OUT2_0
(0x0116) 11
PPC_PCF GPIO_PO
PPG23_T
GR412 P4_12 DR4:POD - - - - - -
OUT0_0
(0x0118) 12
PPC_PCF GPIO_PO
PPG23_T
GR413 P4_13 DR4:POD - - - - - -
OUT2_0
(0x011A) 13
PPC_PCF GPIO_PO
PPG24_T
GR414 P4_14 DR4:POD - - - - - -
OUT0_0
(0x011C) 14
PPC_PCF GPIO_PO
PPG24_T
GR415 P4_15 DR4:POD - - - - - -
OUT2_0
(0x011E) 15
PPC_PCF GPIO_PO
PPG25_T
GR416 P4_16 DR4:POD - - - - - -
OUT0_0
(0x0120) 16
PPC_PCF GPIO_PO
PPG25_T
GR417 P4_17 DR4:POD - - - - SOT12_1 -
OUT2_0
(0x0122) 17

S6J3350 Series

Port
PPC_PCF GPIO_PO
PPG26_T
GR418 P4_18 DR4:POD - - - - - -
OUT0_0
(0x0124) 18
PPC_PCF GPIO_PO
PPG26_T
GR419 P4_19 DR4:POD - - - - - -
OUT2_0
(0x0126) 19
PPC_PCF GPIO_PO
PPG27_T
GR420 P4_20 DR4:POD - - - - SOT16_1 TX4_0
OUT0_0
(0x0128) 20
PPC_PCF GPIO_PO
PPG27_T
GR421 P4_21 DR4:POD - - - - SCK16_1 -
OUT2_0
(0x012A) 21
PPC_PCF GPIO_PO
SCS161_
GR422 P4_22 DR4:POD - - - - - -
1
(0x012C) 22
PPC_PCF GPIO_PO
SCS160_ PPG28_T
GR423 P4_23 DR4:POD - - - - TX7_0
1 OUT0_0
(0x012E) 23
PPC_PCF GPIO_PO
PPG28_T
GR424 P4_24 DR4:POD - - - - - -
OUT2_0
(0x0130) 24
PPC_PCF GPIO_PO
PPG29_T
GR425 P4_25 DR4:POD - - - - - -
OUT0_0
(0x0132) 25
PPC_PCF GPIO_PO
PPG29_T
GR426 P4_26 DR4:POD - - - - - -
OUT2_0
(0x0134) 26
PPC_PCF GPIO_PO
PPG30_T
GR427 P4_27 DR4:POD - - - - - -
OUT0_0
(0x0136) 27
PPC_PCF GPIO_PO
PPG30_T
GR428 P4_28 DR4:POD - - - - - -
OUT2_0
(0x0138) 28
PPC_PCF GPIO_PO
PPG31_T
GR429 P4_29 DR4:POD - - - - - -
OUT0_0
(0x013A) 29
PPC_PCF GPIO_PO
PPG31_T
GR430 P4_30 DR4:POD - - - - - -
OUT2_0
(0x013C) 30
PPC_PCF GPIO_PO
GR431 P4_31 DR4:POD SCK2_1 - - - - - -
(0x013E) 31

S6J3350 Series
Notes:
− The hyphen indicates that setting is prohibited. If setting the port will be operated as input independent on the register value
of the GPIO_DDR.
− The register for P0_20 for POF exists though the port only supports input not supports output. The configuration of POF=0 for
the port does not affect anything.

S6J3350 Series
8. Precautions and Handling Devices

8.1 Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
8.1.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, and so on.) in excess
of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and
in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such
conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.

S6J3350 Series
8.1.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C
and 30 ˚C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125 ˚C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.

S6J3350 Series
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
8.1.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.

S6J3350 Series
8.2 Handling Devices
For Latch-Up Prevention

The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher
than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a
rapid increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take
sufficient care not to exceed the maximum rating.
Also be careful that analog power supplies (AVCC5,AVRH5) and analog inputs do not exceed the digital power supply (VCC) at
the analog system power-on and power-off times.
The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and analog supply voltages
(AVCC5,AVRH5), or turn on the digital supply voltage (VCC) and then the analog supply voltages (AVCC5,AVRH5).
About Handling Unused Pins

Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins,
such as pulling up or pulling down the voltage with resistors of 2 kilo ohms or higher.
If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and
handle them in the same way as input pins.
About Power Supply Pins

If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same
potential are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted
emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total
output current, be sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS
power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not
operate normally even within the guaranteed operating range.
Figure 8-1 Pin Assignment
In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device.
We recommend connecting a ceramic capacitor as a bypass capacitor between VCC and VSS, near this device.
About the Crystal Oscillation Circuit

Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins,
the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device.
We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground.

S6J3350 Series
About the Mode Pin (MODE)

Use mode pin MODE by directly connecting it to a VCC or VSS pin. To prevent noise from causing the device to accidentally enter
test mode, reduce the pattern length between each mode pin and a VCC or VSS pin on the printed circuit board, and connect
them with low impedance.
About the Power-on Time

To prevent the internal built-in voltage step-down circuit from malfunctioning, secure a voltage rising time of 50 µs (between 0.2
V and 2.7 V) or longer at the power-on time.
Point to Note during PLL Clock Operation

While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue operating with the free running
frequency of the internal self-oscillator circuit. This operation is outside of the guaranteed range.
Power Supply Pin Processing of an A/D Converter

Even when no A/D converter is used, establish a connection such that AVCC5=AVRH5=VCC5 and AVSS/AVRL5=VSS.
Points to Note About Using External Clocks

External clocks are not supported.
External direct clock input cannot be used.
Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter

Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC, AVRH, and AVRL) and
analog inputs (AN0 to AN63) of an A/D converter.
At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn off the digital power supply
(VCC). Perform these power-on and power-off operations without AVRH exceeding AVCC. Even when using a pin shared with an
analog input as an input port, do not allow the input voltage to exceed AVCC. (Turning on or off the analog supply voltage and
digital supply voltage simultaneously is not a problem.)
Method to Switch Off VCC12 during Power-Off Sequence

During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode (power domain 2
off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before switching off VCC12 to inactivate the
operation of VCC12 supplied domain below the operation assurance range.
About C Pin Processing

This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin for internal stabilization of the
device. For the standard values, see "Recommended operating conditions" in the latest data sheet.
Precautions on Designing a Mounting Substrate

Measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum
rating (operating temperature). Design a mounting substrate with 4 or more layers. Connect the back of the package stage and
the substrate pad with solder paste. Arrange thermal via holes on the substrate pad.
Notes on Writing to a Register Containing a Status Flag

In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to
take care not to accidentally clear the status flag.
Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the
desired value.
Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1-bit
access). In such cases, byte, half-word, or word access is used to write to the control bits and a status flag simultaneously.
However, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case).
Note: Bit instructions take this point into account for registers that support bit-band units, so it does not need to be a concern. You
need to take care when using bit instructions for registers that do not support bit-band units.

S6J3350 Series
9. Electric Characteristics
9.1 Electrical Characteristics
This chapter contains target values and information.
Target values and information are subjects to change without notice.
9.1.1 Absolute Maximum Rating
Rating
Parameter Symbol Unit Remarks
Min Max
VCC5 VSS-0.3 VSS+6.0 V
VCC53 VSS-0.3 VSS+6.0 V VCC53 ≤ VCC5
Power supply voltage*1, *2 VCC3 VSS-0.3 VSS+4.0 V VCC3 ≤ VCC5
DVCC VSS-0.3 VSS+6.0 V
VCC12 VSS-0.3 VSS+1.8 V VCC12 ≤ AVCC5
Analog supply voltage*1, *2 AVCC5 VSS-0.3 VSS+6.0 V AVCC5 ≤ VCC5
Analog reference voltage*1 AVRH VSS-0.3 VSS+6.0 V AVRH ≤ AVCC5
VI1 VSS-0.3 VCC5+0.3 V 5 V pins
VI2 VSS-0.3 DVCC+0.3 V 5 V/3 V DVCC pins
Input voltage*1
VI3 VSS-0.3 VCC3+0.3 V 3 V pins
VIE VSS-0.3 VCC53+0.3 V 5 V/3 V pins
Analog pin input voltage*1 VIA VSS-0.3 VCC5+0.3 V
VO1 VSS-0.3 VCC5+0.3 V 5 V pins
VO2 VSS-0.3 DVCC+0.3 V 5 V/3 V DVCC pins
Output voltage*1
VO3 VSS-0.3 VCC3+0.3 V 3 V pins
VO4 VSS-0.3 VCC53+0.3 V 5 V/3 V pins
*13, *A
Maximum clamp current |ICLAMP| - 4 mA
*13, *A
Total maximum clamp current Σ|ICLAMP | - 20 mA
*B
*C
IOL1 - 3.5 mA When setting is 1 mA*6, *7, *8
IOL2 - 7 mA When setting is 2 mA*6, *7, *8, *9
IOL3 - 10 mA When setting is 5 mA*9
"L"-level maximum output current*3
IOL7 - 8 mA When setting is 3 mA *10
IOLAV1 - 1 mA When setting is 1 mA*6, *7, *8
IOLAV2 - 2 mA When setting is 2 mA*6, *7, *8, *9
IOLAV3 - 5 mA When setting is 5 mA*9
"L"-level average output current*4
IOLAV7 - 3 mA When setting is 3 mA *10
*6, *10
ΣIOL1 - 50 mA
"L"-level total output current*5 *7
ΣIOL2 - 250 mA

S6J3350 Series
Rating
Min Max
*8
ΣIOL3 - 50 mA
"L"-level total output current*5 *9, *11
ΣIOL4 - 50 mA
IOH1 - -3.5 mA When setting is 1 mA*6, *7, *8
IOH2 - -7 mA When setting is 2 mA*6, *7, *8, *9
IOH3 - -10 mA When setting is 5 mA*9
"H"-level maximum output
current*3
IOH8 - -11 mA When setting is 6 mA *11
IOH9 - -21 mA When setting is 15 mA *12
IOHAV1 - -1 mA When setting is 1 mA*6, *7, *8
IOHAV2 - -2 mA When setting is 2 mA*6, *7, *8, *9
IOHAV3 - -5 mA When setting is 5 mA*9
"H"-level average output current*4 IOHAV4 - -10 mA When setting is 10 mA*9
IOHAV6 - -30 mA When setting is 30 mA*7
IOHAV8 - -6 mA When setting is 6 mA *11
IOHAV9 - -15 mA When setting is 15 mA *12
*6, *10
ΣIOH1 - -50 mA
*7
ΣIOH2 - -250 mA
"H"-level total output current*5 *8
ΣIOH3 - -50 mA
*9 *11
ΣIOH4 - -50 mA
- 2000 mW -40oC ≤ TA ≤ 105oC
Power consumption PD
1100 mW -40oC ≤ TA ≤ 125oC
oC
-40 +105 PD ≤ 2000 mW
Operating temperature TA oC
-40 +125 PD ≤ 1100 mW
oC/W TEQFP
Theta j-a1 - 17
208
oC/W TEQFP
Theta j-a2 - 19 The minimum value
176
depends on the system
TEQFP
specification of heat
144
oC/W radiation. The described
Theta j-a3 - 20 (0.5
System Thermal Resistance value is estimated under
mm
the condition which is
Pitch)
specified at “9.1.2
TEQFP Recommended operating
144 condition”.
oC/W
Theta j-a4 - 22 (0.4
mm
Pitch)
oC/W
Psi j-t1 - 0.6 TEQFP208
oC/W
Package Thermal Resistance oC/W
Psi j-t3 - 2.0 TEQFP144 (0.5 mm Pitch)
oC/W
Psi j-t4 - 2.0 TEQFP144 (0.4 mm Pitch)
oC
Storage temperature Tstg -55 +150
*1 These parameters are based on the condition that VSS = AVSS = DVSS = 0.0 V.
*2 Take care that DVCC, AVCC5 do not exceed VCC5 at, for example, the power-on time.
For S6J33xxxAx or S6J33xxxCx or S6J33xxxEx or S6J33xxxGx option,
take care that AVCC5 do not exceed VCC5 at, for example, the power-on time.
*3 The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.

S6J3350 Series
*4 The average output current is defined as the value of the average current flowing through any one of the corresponding pins for
a 10 ms period. The average value is the operation current × the operation ratio.
*5 The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6 Output of 5 V pins.
*7 Output of DVCC pins.
*8 Output of 5 V/3 V pins.
*9 Output of 3 V pins.
*10 Output of I2C.
*11 Output of P1_00 to P1_02 pins
*12 Output of P2_12 pins
*13 VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is limited by a suitable
external resistor, the ICLAMP rating supersedes the VI rating.
*A Relevant pins: All general-purpose ports and analog input pins
• Corresponding pins: all general-purpose ports
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied by connecting a limiting resistor between the +B signal and the microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated
values at any time regardless of instantaneously or constantly when the +B signal is input.
• Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential
can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the
pin, the microcontroller may operate incompletely.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not
function in the power supply voltage.
• Do not leave + B input pins open.
Example of a recommended circuit
S6J3350 series
WARNING:
− Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current
or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
*B Relevant pins: All general-purpose ports and analog input pins

• Use within recommended operating conditions.

S6J3350 Series

MCU is operational, IO is driving LOW level (i.e. NMOS transistor active), there are negative biased pulses (-B signal) applied
to active IO according to following specification (must not be exceeded).
Pulse condition specification:
U_pulse = max -40 V

T_pulse = max 1 ms
#_pulse = max 5000
Current and Power Dissipation
U_peak = -40 V
R_serial = 22 k
=> I_pin = 1.8 mA
U_out = -0.1 V (current drawn mainly over NMOS transistor)
=> I_total = 50 pins x 1.8 mA = 90 mA

=> P_total = 50 pins x (1.8 mA x 0.1V) = 9 mW
I_total and P_total are within allowed limits of extended specification.
• The - B signal should always be applied by connecting a limiting resistor between the - B signal and the microcontroller.
values at any time regardless of instantaneously or constantly when the - B signal is input.
• Do not leave - B input pins open.
S6J3350 series
WARNING:
*C Relevant pins: All general-purpose ports and analog input pins

• Use within non operation conditions. The device is not supplied (VCC5: off, VCC12: off, VCC53: off).
S6J3350 Series

MCU is non-operational, PCB is in reverse polarity condition (supply of the MCU is off), negative biased voltage level (-B
signal) is applied to inactive IO according to following specification (must not be exceeded).
Reverse polarity condition specification:
U_reverse = max -28 V

T_reverse = max 4 h
Current and Power Dissipation
U_reverse = -28 V
R_serial = 22 k
=> I_pin = 1.3 mA
U_out = -0.7 V (current drawn mainly over clamping diodes)
=> I_total = 50 pins x 1.3 mA = 65 mA

=> P_total = 50 pins x (1.3 mA x 0.7 V) = 46 mW
I_total and P_total are within allowed limits of extended specification.
• The - B signal should always be applied by connecting a limiting resistor between the - B signal and the microcontroller.
values at any time regardless of instantaneously or constantly when the - B signal is input.
• Do not leave - B input pins open.
S6J3350 series
WARNING:

S6J3350 Series
9.1.2 Recommended Operating Condition

Rating
Parameter Symbol Pin Name Unit Remarks
Min Max
4.5 5.5 *1
VCC5 VCC5 V
3 3.6 *2 *3
4.5 5.5 V *1
VCC53 VCC53
3 3.6 V
Supply voltage 4.5 5.5 *1 *3
Recommended operation DVCC DVCC V
assurance range*4 3.0 3.6 *2
4.5 5.5 *1
AVCC5 AVCC5 V
3 3.6 *2 *3
VCC3 VCC3 3 3.6 V
VCC12 VCC12 1.09 1.21 V
3.5 5.5 *1
VCC5 VCC5 V
2.7 3.6 *2 *3
2.7 5.5 *1
VCC53 VCC53 V
2.7 3.6
Supply voltage 3.5 5.5 *1 *3
DVCC DVCC V
Operation assurance range 2.7 3.6 *2
3.5 5.5 *1
AVCC5 AVCC5 V
2.7 3.6 *2 *3
VCC3 VCC3 2.7 3.6 V
VCC12 VCC12 1.09 1.21 V *5
Tolerance of up to ±
Smoothing capacitor* CS C 4.7 µF
40 %
oC
TA - -40 105 PD ≤ 2000 mW
Operating temperature oC
TA - -40 125 PD ≤ 1100 mW
*1: For S6J335xxSx or S6J335xxUx or S6J335xxTx or S6J335xxVx option.
*2: For S6J335xxBx or S6J335xxDx or S6J335xxFx or S6J335xxHx option.
*3: For S6J335xxAx or S6J335xxCx or S6J335xxEx or S6J335xxGx option.
*4: Corresponding functions for Low voltage monitoring of supply voltage are described in CHAPTER 13 Low Voltage Detection of
S6J3300 Series Hardware Manual.
The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2
Recommended Operating Condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)” and “9.1.4.12 Low Voltage
Detection (Internal Voltage)" for detection/release threshold values for these LVD channels):
LVDL0
LVDL1
LVDL2
LVDH0
LVDH1
LVDH2

S6J3350 Series
When it is used outside recommended range (this is the range of guaranteed operation), contact your sales representative.
The initial detection voltage of the external low voltage detection is 2.6 V ± 3.5 % (LVDH1/LVDH2) or 0.8125 ± 3.5 % (LVDL2).
This LVD setting and internal LVD (LVDL0/LVDL1) cannot be used to reliably generate a reset before voltage dips below
minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation
voltage.
- Please use these LVD channels with your own risk

- Please monitor the external power supplies on the PCB if needed
*5: When the voltage of Vcc12 is in the out of range against supply voltage operation assurance, the operation of circuit which
Vcc12 used as the power source becomes unstable status. In this case, the value of each registers including RESCAUSEUR
Register cannot be guaranteed, so these flags should not be used by software processing.
*: For the connections of smoothing capacitor CS, see the following diagram.
C Pin Connection Diagram
CS VSS DVSS AVSS
Notes:
− The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the electrical characteristics of the device are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges
may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating
conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are
advised to contact sales representatives beforehand.
− Required power supply sequence is the following:
{VCC5 -> AVCC5} -> [DVCC or VCC53 or VCC3 or AVCC3_DAC or VCC12]
Note that power supplies inside "[ ]" can be turned on in arbitrary order and "{ }" can be turned on in shown sequence or
simultaneously.

S6J3350 Series
Notes:
− TA: Ambient temperature (JEDEC)
− TC: Case temperature (JEDEC), the maximum measured temperature of package case top.
− Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature.
− The following condition should be satisfied in order to facilitate heat dissipation.
1. Four or more layers PCB should be used.
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (JEDEC
standard)
3. One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 %
or more. The layer can be used for system ground.
4. 35 % or more of the die stage area which is exposed at back surface of package should be soldered to a part of 1st
layer.
5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes.
Example thermal via holes on PCB
− The above figure is a schematic diagram showing PCB in section.

− Thermal via holes should closely be placed and aligned with lands.
− It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer bellow the MCU) as thermal
heat sink.

S6J3350 Series
9.1.3 DC Characteristics
(TA: Recommended operating conditions, VCC5,VCC53 = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Parameter Symbol Pin Name Conditions Unit Remarks
Min Typ Max
CMOS hysteresis
VIH1 P0_00 to P0_20, 0.7×VCC53 - VCC53+0.3 V
input level is selected
P2_09 to P2_19,
Automotive
VIH2 P3_00 to P3_07, 0.8×VCC53 - VCC53+0.3 V
P3_24 to P3_31,
P4_00 to P4_07 TTL
VIH3 2.0 - VCC53+0.3 V
CMOS hysteresis
VIH4 P1_03 to P1_16, 0.7×VCC5 - VCC5+0.3 V
P3_08 to P3_23,
Automotive
VIH5 P4_08 to P4_23 0.8×VCC5 - VCC5+0.3 V
P1_09, P1_10, TTL
VIH6 2.0 - VCC5+0.3 V
P1_15, P1_16 input level is selected
"H" level CMOS hysteresis
VIH7 P1_17 to P1_31, 0.7×DVCC - DVCC+0.3 V
Input input level is selected
P2_00 to P2_08,
voltage Automotive
VIH8 P4_24 to P4_31 0.8×DVCC - DVCC+0.3 V
RSTX
VIH9 - 0.7×VCC5 - VCC5+0.3 V
NMIX
VIH10 MD - 0.7×VCC5 - VCC5+0.3 V
JTAG_NTRST
JTAG_TCK
VIH11 - 2.7 - VCC5+0.3 V
JTAG_TDI
JTAG_TMS
P0_21 to P0_31, CMOS hysteresis
VIH12 0.7×VCC3 - VCC3+0.3 V
P1_00 to P1_02 input level is selected
TTL
VIH13 P0_21 to P0_31 2.0 - VCC3+0.3 V

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53 = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Min Typ Max
CMOS hysteresis 0.3×VCC5
VIL1 P0_00 to P0_20, Vss-0.3 - V
input level is selected 3
P2_09 to P2_19,
Automotive 0.5×VCC5
VIL2 P3_00 to P3_07, Vss-0.3 - V
input level is selected 3
P3_24 to P3_31,
P4_00 to P4_07 TTL
VIL3 Vss-0.3 - 0.8 V
CMOS hysteresis
VIL4 P1_03 to P1_16, Vss-0.3 - 0.3×VCC5 V
P3_08 to P3_23,
Automotive
VIL5 P4_08 to P4_23 Vss-0.3 - 0.5×VCC5 V
P1_09, P1_10, TTL
VIL6 Vss-0.3 - 0.8 V
CMOS hysteresis 0.3×DVC
"L" level VIL7 P1_17 to P1_31, Vss-0.3 - V
input level is selected C
Input P2_00 to P2_08,
voltage Automotive 0.5×DVC
VIL8 P4_24 to P4_31 Vss-0.3 - V
input level is selected C
RSTX
VIL9 - Vss-0.3 - 0.3×VCC5 V
NMIX
VIL10 MD - Vss-0.3 - 0.3×VCC5 V
JTAG_NTRST
JTAG_TCK
VIL11 - Vss-0.3 - 0.8 V
JTAG_TDI
JTAG_TMS
P0_21 to P0_31, CMOS hysteresis
VIL12 Vss-0.3 - 0.3×VCC3 V
P1_00 to P1_02 input level is selected
TTL
VIL13 P0_21 to P0_31 Vss-0.3 - 0.8 V
CMOS hysteresis 0.05×VC
VHYS1 P0_00 to P0_20, - - V
input level is selected C53
P2_09 to P2_19,
Automotive 0.03×VC
VHYS2 P3_00 to P3_07, - - V
P3_24 to P3_31,
P4_00 to P4_07 TTL
VHYS3 - 0.035 - V
CMOS hysteresis 0.05×VC
VHYS4 P1_03 to P1_16, - - V
P3_08 to P3_23,
Automotive 0.03×VC
VHYS5 P4_08 to P4_23 - - V
P1_09, P1_10, TTL
VHYS6 - 0.035 - V
CMOS hysteresis 0.05×D
VHYS7 P1_17 to P1_31, - - V
Hysteresis input level is selected VCC
P2_00 to P2_08,
voltage Automotive 0.03×D
VHYS8 P4_24 to P4_31 - - V
input level is selected VCC
RSTX 0.05×VC
VHYS9 - - - V
NMIX C5
0.05×VC
VHYS10 MD - - - V
C5
JTAG_NTRST
JTAG_TCK
VHYS11 - - 0.035 - V
JTAG_TDI
JTAG_TMS
P0_21 to P0_31, CMOS hysteresis 0.05×VC
VHYS12 - - V
P1_00 to P1_02 input level is selected C3
TTL
VHYS13 P0_21 to P0_31 - 0.035 - V

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Pin
Parameter Symbol Conditions Unit Remarks
Name
Min Typ Max
VCC53=4.5 V
IOH=-1.0 mA ODR[1:0]=
VOH1 VCC53 - 0.5 - VCC53 V
VCC53=3.0 V 2b00
P0_00 to P0_19, IOH=-0.5 mA
P2_09 to P2_11, VCC53=4.5 V
P2_13 to P2_19, IOH=-2.0 mA ODR[1:0]=
VOH2 VCC53 - 0.5 - VCC53 V
P3_00 to P3_07, VCC53=3.0 V 2b01
P3_24 to P3_31, IOH=-1.0 mA
P4_00 to P4_07 VCC53=4.5 V
IOH=-5.0 mA ODR[1:0]=
VOH3 VCC53 - 0.5 - VCC53 V
VCC53=3.0 V 2b10
IOH=-2.0 mA
VCC5=4.5 V
VOH4 VCC5 - 0.5 - VCC5 V
IOH=-1.0 mA
P1_03 to P1_16,
VCC5=4.5 V
VOH5 P3_08 to P3_23, VCC5 - 0.5 - VCC5 V
IOH=-2.0 mA
P4_08 to P4_23
VCC5=4.5 V
IOH=-5.0 mA
VCC5=4.5 V
"H" level VOH7 PSC_1 VCC5 - 0.5 - VCC5 V
IOH=-2.0 mA
output
VCC5=4.5 V
voltage VOH8 JTAG_TDO VCC5 - 0.5 - VCC5 V
IOH=-5.0 mA
DVCC=4.5 V
VOH10 DVCC - 0.5 - DVCC V
IOH=-1.0 mA
DVCC=4.5 V
IOH=-2.0 mA
P1_17 to P1_31,
DVCC=4.5 V
VOH12 P2_00 to P2_08, DVCC - 0.5 - DVCC V
IOH=-5.0 mA
P4_24 to P4_31
DVCC=4.5 V
IOH=-30.0 mA
DVCC=4.5 V
VOH14 DVCC - 0.5 - DVCC V Tj = -40oC
IOH=-40.0 mA
VCC3=3.0 V
IOH=-2.0 mA
VCC3=3.0 V
VOH16 P0_21 to P0_31, VCC3 - 0.5 - VCC3 V
IOH=-5.0 mA
P1_00 to P1_02
VCC3=3.0 V
IOH=-6.0 mA
VCC3=3.0 V
VOH18 VCC3 - 0. 5 - VCC3 V
IOH=-15.0 mA

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V ± 10 %, VCC3=3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Pin
Name
Min Typ Max
VCC53 = 4.5 V
VOH19
IOH = -1.0 mA ODR[1:0]
VCC53 - 0.5 - VCC53 V
= 2b00
VCC53 = 3.0 V
VOH20
IOH = -0.5 mA
VCC53 = 4.5 V
VOH21
IOH = -2.0 mA ODR[1:0]
VCC53 - 0.5 - VCC53 V
VCC53 = 3.0 V = 2b01
"H" level VOH22 P2_12 IOH = -1.0 mA
output
voltage VCC53 = 4.5 V
VOH23
IOH = -5.0 mA ODR[1:0]
VCC53 - 0.5 - VCC53 V
VCC53 = 3.0 V = 2b10
VOH24
IOH = -2.0 mA
VCC53 = 3.0 V ODR[1:0]

VOH26 VCC53 - 0.5 - Vcc53 V
IOH = -15.0 mA = 2b11

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V ± 10%, VCC3 = 3.3 V ± 0.3 V,
VSS = DVSS = AVSS = 0.0 V)
Value
Pin
Name
Min Typ Max
VCC53 = 4.5 V
IOL = 1.0 mA ODR[1:0]=2
VOL1 0 - 0.4 V
VCC53 = 3.0 V b00
P0_00 to P0_19, IOL = 0.5 mA
P2_09 to P2_11, VCC53 = 4.5 V
P2_13 to P2_19, IOL = 2.0 mA ODR[1:0]=2
VOL2 0 - 0.4 V
P3_00 to P3_07, VCC53 = 3.0 V b01
P3_24 to P3_31, IOL = 1.0 mA
P4_00 to P4_07 VCC53 = 4.5 V
IOL = 5.0 mA ODR[1:0]=2
VOL3 0 - 0.4 V
VCC53 = 3.0 V b10
IOL = 2.0 mA
VCC5 = 4.5 V
VOL4 0 - 0.4 V
IOL = 1.0 mA
P1_03 to P1_16,
VCC5 = 4.5 V
VOL5 P3_08 to P3_23, 0 - 0.4 V
IOL = 2.0 mA
P4_08 to P4_23
VCC5 = 4.5 V
VOL6 0 - 0.4 V
IOL = 5.0 mA
VCC5 = 4.5 V
VOL7 PSC_1 0 - 0.4 V
IOL = 2.0 mA
"L" level
VCC5 = 4.5 V
output VOL8 JTAG_TDO 0 - 0.4 V
IOL = 5.0 mA
voltage
P1_09, P1_10, VCC5 = 4.5 V
VOL9 0 - 0.4 V I2 C
P1_15, P1_16 IOL = 3.0 mA
DVCC = 4.5 V
VOL10 0 - 0.4 V
IOL = 1.0 mA
DVCC = 4.5 V
VOL11 0 - 0.4 V
IOL = 2.0 mA
P1_17 to P1_31,
DVCC = 4.5 V
VOL12 P2_00 to P2_08, 0 - 0.4 V
IOL = 5.0 mA
P4_24 to P4_31
DVCC = 4.5 V
VOL13 0 - 0.55 V
IOL = 30.0 mA
DVCC = 4.5 V
VOL14 0 - 0.55 V Tj = -40oC
IOL = 40.0 mA
VCC3 = 3.0 V
VOL15 0 - 0.4 V
IOL = 2.0 mA
VCC3 = 3.0 V
VOL16 P0_21 to P0_31, 0 - 0.4 V
IOL = 5.0 mA
P1_00 to P1_02
VCC3 = 3.0 V
VOL17 0 - 0.4 V
IOL = 6.0 mA
VCC3 = 3.0 V
VOL18 0 - 0.4 V
IOL = 15.0 mA

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V,

Value
Pin
Name
Min Typ Max
VCC53 = 4.5 V
VOL19
IOL = 1.0 mA ODR[1:0]
0 - 0.4 V
= 2b00
VCC53 = 3.0 V
VOL20
IOL = 0.5 mA
VCC53 = 4.5 V
VOL21
IOL = 2.0 mA ODR[1:0]
0 - 0.4 V
VCC53 = 3.0 V = 2b01
"L" level VOL22 P2_12 IOL = 1.0 mA
output
voltage VCC53 = 4.5 V
VOL23
IOL = 5.0 mA ODR[1:0]
0 - 0.4 V
VCC53 = 3.0 V = 2b10
VOL24
IOL = 2.0 mA
VCC53 = 3.0 V ODR[1:0]

VOL26 0 - 0.4 V
IOL = 15.0 mA = 2b11

S6J3350 Series

Value
Min Typ Max
P0_00 to P0_20,
VCC5 = VCC53 =
P1_03 to P1_31, 5 V pins
DVCC =
P2_00 to P2_19, -5 - +5 µA 5 V/3 V
Input leakage AVCC = 5.5 V
IIL P3_00 to P3_31, pins
current VSS < VI < VCC
P4_00 to P4_31
P0_21 to P0_31, VCC3 = 3.6 V
-10 - +10 µA 3 V pins
P1_00 to P1_02 VSS < VI < VCC3
RUP1 RSTX, NMIX - 25 50 100 kΩ
P0_00 to P0_20,
P1_03 to P1_31, 5 V pins
Pull-up resistor
RUP2 P2_00 to P2_19, 25 50 100 kΩ 5 V/3 V
selected
P3_00 to P3_31, pins
Pull-up
P4_00 to P4_31
resistor
P0_21 to P0_31, Pull-up resistor
RUP3 17 50 66 kΩ 3 V pins
P1_00 to P1_02 selected
JTAG_TDI,
RUP4 JTAG_TMS, - 25 50 100 kΩ
JTAG_TCK
P0_00 to P0_20,
P1_03 to P1_31, 5 V pins
Pull-down resistor
Rdown1 P2_00 to P2_19, 25 50 100 kΩ 5 V/3 V
selected
Pull-down P3_00 to P3_31, pins
resistor P4_00 to P4_31
P0_21 to P0_31, Pull-down resistor
Rdown2 17 50 66 kΩ 3 V pins
P1_00 to P1_02 selected
Rdown3 JTAG_NTRST - 25 50 100 kΩ
P0_00 to P0_31,
P1_00 to P1_16,
CIN1 P2_09 to P2_19, - - 5 15 pF
P3_00 to P3_31,
P4_00 to P4_23
Input
When
capacitance
using
P1_17 to P1_31,
IOH/IOL
CIN2 P2_00 to P2_08, - - 15 45 pF
30.0mA,
P4_24 to P4_31
and
40.0mA

S6J3350 Series

VCC12 = 1.15 V ± 0.06 V, VSS = DVSS = AVSS = 0.0 V)
Value
Pin
Name
Min Typ Max
TA = -40 ~ 105C
- 315 775 mA CPU:240 MHz, HPM:120 MHz
Normal
(CPU:200 MHz, HPM:200 MHz)
operation
TA = -40 ~125C
- 210 665 mA
CPU:180 MHz, HPM:90 MHz,
ICC12
TA = -40 ~ 105C
VCC12
- 320 780 mA CPU:240 MHz, HPM:120 MHz
Flash (CPU:200 MHz, HPM:200 MHz)
write/erase
TA = -40 ~ 125C
- 215 670 mA
CPU:180 MHz, HPM:90 MHz,
Timer/ Stop
ICCH12 - - 420 mA
Mode
Normal
- 25 45 mA
operation
ICC5
Flash
- - 60 mA
write/erase
TA = 25 C. 4 MHz crystal for
main oscillator.
- 370 810 µA
PD1 = ON, PD4_0 = ON, PD4_1 =
ON
TA = 25 C. 4 MHz crystal for main
oscillator.
- 360 780 µA
PD1 = ON, PD4_0 = ON or PD4_1
Power = ON
supply TA = 25 C. 4 MHz crystal for
current - 350 750 µA main oscillator.
PD1 = ON
TA = 25 C. 8 MHz crystal for main
oscillator
- 450 890 µA
PD1 = ON, PD4_0 = ON, PD4_1 =
VCC5 ON
ICCT5 Timer mode
main oscillator.
- 440 860 µA
= ON
- 430 830 µA main oscillator.
PD1 = ON
TA = 25 C. 32 kHz crystal for sub
oscillator
- 110 430 µA
PD1 = ON, PD4_0 = ON, PD4_1 =
ON
oscillator.
- 100 400 µA
= ON
- 90 370 µA oscillator.
PD1 = ON

S6J3350 Series
(TA: Recommended operating conditions, VCC5,VCC53, DVCC = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V,
Value
Pin
Name
Min Typ Max
TA = 25 C.
- 100 400 µA PD1 = ON, PD4_0 = ON, PD4_1
= ON
Power
supply ICCH5 VCC5 Stop mode TA = 25 C.
- 90 370 µA PD1 = ON, PD4_0 = ON or
current
PD4_1 = ON
- 80 340 µA TA = 25 C.
PD1 = ON

S6J3350 Series

VCC12 = 1.15 V ± 0.06 V, VSS = DVSS = AVSS =0.0 V)
Value
Pin
Name
Min Typ Max
- 345 630 µA main oscillator
PD1 = ON, PD4_0 = ON, PD4_1
= ON
PD1 = ON, PD4_0 = ON or
PD4_1 = ON
TA = 25C. 4 MHz crystal for
PD1 = ON
- 420 705 µA main oscillator
PD1 = ON, PD4_0 = ON, PD4_1
= ON
ICCT5 Timer mode main oscillator.
- 415 700 µA
PD4_1 = ON
Power TA = 25 C. 8 MHz crystal for
supply VCC5 - 410 695 µA main oscillator.
current * PD1 = ON
TA = 25 C. 32 kHz crystal for
- 80 135 µA sub oscillator
PD1 = ON, PD4_0 = ON, PD4_1
= ON
- 75 130 µA sub oscillator.
PD4_1 = ON
PD1 = ON
TA = 25 C.
- 75 130 µA PD1 = ON, PD4_0 = ON, PD4_1
= ON
ICCH5 Stop mode TA = 25 C.
- 70 125 µA PD1 = ON, PD4_0 = ON or
PD4_1 = ON
- 65 120 µA TA = 25 C.
PD1 = ON
* Electric Characteristics for S6J335xxxE.

S6J3350 Series

Value
Min Typ Max
DVCC = 4.5V
High current output
IOH = -30.0mA
drive capacity Phase- Delta-VOH13 - - 90 mV *
P1_17 to Maximum deviation of
to-phase deviation1
P1_31, VOH13
P2_00 to DVCC = 4.5V
High current output
P2_08 IOL = 30.0mA
drive capacity Phase- Delta-VOL13 - - 90 mV *
Maximum deviation of
to-phase deviation2
VOL13
*: If P1_17 to P1_20 is turned on simultaneously, the maximum deviation of VOH13 / VOL13 for each pin is defined. Same for other
channels.of P1_21 to P1_24, P1_25 to P1_28, P1_29 to P1_31 and P2_00, P2_01 to P2_04, and P2_05 to P2_08 .

S6J3350 Series
9.1.4 AC Characteristics
9.1.4.1 Source Clock Timing
(TA: Recommended operating conditions, Vcc5 = 5.0 V ± 10 %, VSS = DVSS = AVSS = 0.0 V)
Value
Min Typ Max
Source oscillation
FC X0, X1 - 3.6 - 16.0 MHz
clock frequency
Source oscillation
tCYL X0, X1 - 62.5 - 277.8 ns
clock cycle time
CAN PLL jitter
tPJ - - -10 - 10 ns
(when locked)
Internal Slow CR
FCRS - - 50 100 150 kHz
oscillation frequency
Internal Fast CR 2.40 4.00 5.61- MHz Before trim
FCRF - -
oscillation frequency 3.20 4.00 4.81 MHz After trim
Notes:
− The maximum/minimum values have been standardized with the main clock and PLL clock in use.
− Jitter of source oscillator must be smaller than 300ppm.
− Enough evaluation and adjustment are recommended using oscillator on your system board.
− X0 and X1 clock timing

tCYL
X0
CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
Ideal clock
Slow
PLL output
Fast

S6J3350 Series
9.1.4.2 Sub Clock Timing

(TA: Recommended operating conditions, Vcc5 = 5.0 V ±10 %, VSS = DVSS = AVSS = 0.0 V)
Value
Min Typ Max
Source oscillation
FCL X0A, X1A - - 32.768 - kHz
clock frequency
Source oscillation
tLCYL X0A, X1A - - 30.52 - µs
clock cycle time
− X0A and X1A clock timing

tLCYL
X0A

S6J3350 Series
9.1.4.3 Internal Clock Timing

 This chapter shows the TARGET characteristics for internal clock timing at the current stage.
 In the column symbol, same clock names as described in CHAPTER 5: CLOCK SYSTEM of Traveo™ Platform Hardware
Manual are used.
 Corresponding functions for these clocks are described in CHAPTER 5: CLOCK CONFIGURATION of S6J3300 series
hardware manual.
(TA: Recommended operating conditions, VCC5 = 5.0 V ±10 %, VCC12 = 1.15 V ±0.06 V, VSS = 0.0 V)
Value
Max *1 Max *2 Max *3
FSSCG0 480 400 360 MHz SSCG0 output clock *4
FPLL0 480 400 360 MHz PLL0 output clock *4
FCLK_CPU0 240 200 180 MHz
FCLK_SHE 240 200 180 MHz
FCLK_FCLK 80 66.7 90 MHz
FCLK_ATB 120 100 90 MHz
FCLK_DBG 120 100 90 MHz
FCLK_HPM 120 200 180 MHz
FCLK_HPM2 60 100 90 MHz
FCLK_DMA 120 200 180 MHz
FCLK_MEMC 120 200 180 MHz
FCLK_EXTBUS 40 40 30 MHz
FCLK_SYSC1 40 40 60 MHz
FCLK_HAPP0A0 40 40 30 MHz Unused
FCLK_HAPP0A1 40 40 30 MHz Unused
FCLK_HAPP1B0 80 50 60 MHz
FCLK_HAPP1B1 40 50 30 MHz Unused
FCLK_LLPBM 240 200 180 MHz
Internal clock
FCLK_LLPBM2 120 100 90 MHz
frequency
FCLK_LCP 80 50 60 MHz
FCLK_LCP0 40 40 30 MHz
FCLK_LCP0A 80 66.7 60 MHz
FCLK_LCP1 40 40 30 MHz Unused
FCLK_LCP1A 80 66.7 60 MHz
FCLK_LAPP0 40 40 30 MHz Unused
FCLK_LAPP0A 40 40 30 MHz Unused
FCLK_LAPP1 40 40 30 MHz Unused
FCLK_LAPP1A 40 40 30 MHz Unused
FCLK_TRC 100 100 100 MHz
FCLK_CD1 200 200 200 MHz
FCLK_CD1A0 100 100 100 MHz Unused
FCLK_CD1B0 100 100 100 MHz Unused
FCLK_CD2 200 200 200 MHz Unused

S6J3350 Series
Value
Max *1 Max *2 Max *3
Internal clock
frequency
FCLK_HSSPI 200 200 200 MHz
FCLK_SYSC0H 80 66.7 60 MHz
FCLK_COMH 80 66.7 60 MHz
FCLK_RAM0H 80 66.7 60 MHz
FCLK_RAM1H 80 66.7 60 MHz
FCLK_SYSC0P 80 66.7 60 MHz
FCLK_COMP 80 66.7 60 MHz
Notes:
- *1: Target maximum clock frequencies when CPU clock = 240 MHz
- *4: The PLLx/SSCGx cannot set under 200 MHz
- Note that Ta = 125 condition is not supported in *1 and *2 use case.
Please set to *3 when device Ta = 125.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions.
- On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
- This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
- "Unused" means a clock source which doesn’t have any supply destinations. Configure these clocks to a lower clock frequency
than the described maximum.

S6J3350 Series
− Operation assurance range

Relationship between the internal clock frequency and supply voltage
Power supply VCC5 [V]
5.5 Recommended guaranteed

operation range
4.5
3.5 Guaranteed
operation range
PLL guaranteed
2 4 Maximum frequency operation range
Frequency [MHz] of each clock
Power supply VCC12 [V]
1.21
1.09
2 4 Maximum frequency
Frequency [MHz] of each clock
Note: CPU will be reset, when the power supply voltage is equal to or less than LVD setting voltage.

S6J3350 Series
− Relationship between the oscillation clock frequency and internal clock frequency
Internal Operation Clock Frequency

PLL Clock
Main
Clock Multiplied Multiplied Multiplied Multiplied Multiplied Multiplied
by 1 by 2 by 15 by 30 by 40 by 60
4 2 4 8 … 60 120 160 240
Oscillation
clock 8 4 8 16 … 120 240
frequency
[MHz] 16 8 16 32 … 240
− Oscillation circuit example
X0 X1
C1 C2
Note:
For the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching
evaluation before starting design.
AC characteristics are specified by the following measurement reference voltage values.

− Input signal waveform − Output signal waveform
Hysteresis input pin (Automotive) Output pin
0.8VCC5 2.4V
0.5VCC5 0.8V
Hysteresis input pin (CMOS Schmitt)
0.7VCC5
0.3VCC5
0.7VCC3
0.3VCC3
Hysteresis input pin (TTL)
2.0V
0.8V

S6J3350 Series
9.1.4.4 Reset Input

(TA: Recommended operating conditions, Vcc5 = 5.0 V ±10 %, VSS = 0.0 V)
Value
Min Max
Reset
10 - µs
input time
tRSTL RSTX -
Width for reset
1 - µs
input removal
tRSTL
RSTX
0.2Vcc 0.2Vcc

S6J3350 Series
9.1.4.5 Power-on Conditions

(TA: Recommended operating conditions, VSS = 0.0 V)
Value
Pin
Name
Min Typ Max
Level detection
- VCC5 - 2.2 2.4 2.6 V
voltage
Level detection
- VCC5 - - 100 - mV
hysteresis width
*1
Level detection time - - - - - 40 μs
*2
Power off time tOFF VCC5 - 100 - - μs
VCC5: *3
Power ramp rate dV/dt VCC5 - - 1 V/µs
1.5V to 2.6V
Maximum ramp rate

VCC5:
guaranteed to not *4
|dV/dt| VCC5 Between 2.4V - - 50 mV/µs
generate power-on
and 4.5V
reset
*1: This specification is at 1V/μs of power ramp rate.
*2: VCC5 must be held below 1.5V for a minimum period of tOFF.
*3: Power ramp rate must be 1V/us or less from 1.5V to 2.6V.
Power-on can detect by satisfying power ramp rate when power off time is satisfied.
*4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is between 2.4V and
4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is suppressed. The power-on does not detect in
any power fluctuation between 4.5V and 5.5V.
Notes:
When using S6J3350, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at
power up and any brownout event.
 Power off time, Power ramp rate
tOFF
VCC
2.6V
1.5V 1.5V dV/dt
 Maximum ramp rate guaranteed to not generate power-on reset
5.5V
VCC 4.5V
|dV/dt|
|dV/dt|
2.4V

S6J3350 Series
9.1.4.6 Multi-Function Serial

UART (asynchronous serial interface) timing (SMR:MD2-0 = 0b000, 0b001)
(1) External Clock Selected (BGR: EXT = 1)

(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ±10 % / 3.3 V ± 0.3 V ,
Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ±0.06 V)
Value
Min Max
SCK0 to SCK4, 2tCLK_LCPnA*1

- ns
SCK8 to SCK12 +10
Serial clock
tSLSH
"L" pulse width
SCK16 to SCK17 2tCLK_COMP +10 - ns

- ns
SCK8 to SCK12 +10
Serial clock
tSHSL -
"H" pulse width
SCK16 to SCK17 2tCLK_COMP +10 - ns
SCK falling time tF - 5 ns

SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SCK rising time tR - 5 ns
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
tR tSHSL tF
tSLSH
SCK
VIH VIH VIH
VIL VIL VIL
External clock selected

S6J3350 Series
CSIO timing (SMR:MD2-0 = 0b010)
(1) Normal Synchronous Transfer (SCR: SPI = 0) and Mark Level "H" of Serial Clock Output (SMR: SCINV = 0)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ±0.3V, Vcc5 = DVcc = 5.0 V ± 10 % / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10% / 3.3 V ±0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Value
Min Max
SCK0, SCK1, SCK2_1,

SCK3_1, SCK4, 8tCLK_LCPnA*1 - ns
Serial clock SCK8 to SCK12
tSCYC -
cycle time
SCK16 to SCK17 8tCLK_COMP - ns
SCK0, SCK1, SCK2_1,

SCK3_1, SCK4,
SCK8 to SCK12,
SCK ↓ → SOT SCK16 to SCK17 Master
tSLOVI Mode -30 +30 ns
delay time SOT0, SOT1, SOT2_1,
SOT3_1, SOT4, (CL = 20pF,
SOT8 to SOT12, IOL = -5mA,
SOT16 to SOT17 IOH = 5mA)
SCK0, SCK1, SCK2_1,

Valid SIN → SCK ↑ SCK3_1, SCK4,
tIVSHI 40 - ns
setup time SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SIN3_1, SIN4,
SCK ↑→ Valid SIN SIN8 to SIN12,
tSHIXI 0 - ns
hold time SIN16 to SIN17
Serial clock
tSCYC SCK2_0, SCK3_0 2tCLK_LCPnA*1 - ns
cycle time
SCK ↓ → SOT SCK2_0, SCK3_0, Master

tSLOVI -7.5 +7.5 ns
delay time SOT2_0, SOT3_0 Mode
(CL = 20pF, -
IOL = -10mA,
Valid SIN → SCK ↑
tIVSHI IOH = 10mA) 10 - ns
setup time
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
SCK ↑→ Valid SIN
tSHIXI 0 - ns
hold time

S6J3350 Series
Value
Min Max
SCK0 to SCK4,
4tCLK_LCPnA*1 - ns
SCK8 to SCK12
Serial clock
tSHSL
"H" pulse width
-
SCK0 to SCK4, *1
4tCLK_LCPnA - ns
SCK8 to SCK12
Serial clock
tSLSH
"L" pulse width
SCK0 to SCK4,
SCK8 to SCK12, Slave
SCK ↓→ SOT SCK16 to SCK17 Mode
tSLOVE (CL = 20pF, - 40 ns
delay time SOT0 to SOT4,
SCK0 to SCK4,
tIVSHE SCK8 to SCK12, 10 - ns
setup time
SCK16 to SCK17
SIN0 to SIN4,
SCK ↑ → Valid SIN
tSHIXE SIN8 to SIN12, 10 - ns
hold time
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time tF SCK8 to SCK12, - 5 ns
SCK16 to SCK17
SCK0 to SCK4,
SCK rising time tR SCK8 to SCK12, - 5 ns
SCK16 to SCK17
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
− This table provides the alternate current standard for CLK synchronous mode.
− CL is the load capability value connected to the pin at the test time.
− The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual.

S6J3350 Series
tSCYC
SCK VOH
VOL
tSLOVI
SOT VOH
VOL
tIVSHI tSHIXI
SIN VIH VIH

VIL VIL
Master mode
tSLSH tSHSL
SCK VIH VIH VIH

VIL VIL
tR
tF tSLOVE
SOT VOH
VOL
tIVSHE tSHIXE
SIN VIH VIH

VIL VIL
Slave mode

S6J3350 Series
(2) Normal Synchronous Transfer (SCR: SPI = 0) and Mark Level "L" of Serial Clock Output (SMR: SCINV = 1)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ±10% / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Value
Min Max
SCK0, SCK1, SCK2_1,
Serial clock SCK3_1, SCK4, 8tCLK_LCPnA*1 - ns
tSCYC SCK8 to SCK12 -
cycle time
SCK0, SCK1, SCK2_1,

SCK3_1, SCK4,
SCK8 to SCK12,
SCK ↑ → SOT SCK16 to SCK17 Master
tSHOVI -30 +30 ns
delay time SOT0, SOT1, SOT2_1, Mode
SOT3_1, SOT4, (CL = 20pF,
SCK0, SCK1, SCK2_1,

Valid SIN → SCK ↓ SCK3_1, SCK4,
tIVSLI 40 - ns
setup time SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SCK ↓ → Valid SIN SIN3_1, SIN4,
tSLIXI 0 - ns
hold time SIN8 to SIN12,
SIN16 to SIN17

S6J3350 Series
Value
Min Max
Serial clock
cycle time
SCK ↓ → SOT SCK2_0, SCK3_0, Master
tSHOVI Mode -7.5 +7.5 ns
delay time SOT2_0, SOT3_0
(CL = 20pF, -
Valid SIN → SCK ↑ IOL = -10mA,
tIVSLI 10 - ns
setup time SCK2_0, SCK3_0, IOH = 10mA)
SCK ↑→ Valid SIN SIN2_0, SIN3_0
tSLIXI 0 - ns
hold time
SCK0 to SCK4,
Serial clock 4tCLK_LCPnA*1 - ns
tSHSL SCK8 to SCK12
"H" pulse width
SCK0 to SCK4,
tSLSH SCK8 to SCK12
"L" pulse width
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↑ → SOT SCK16 to SCK17
tSHOVE - 40 ns
delay time SOT0 to SOT4, Slave
SOT8 to SOT12, Mode
SOT16 to SOT17 (CL = 20pF,
Valid SIN → SCK ↓ SCK0 to SCK4, IOL = -5mA,
tIVSLE 10 - ns
setup time SCK8 to SCK12, IOH = 5mA)
SCK16 to SCK17
SCK ↓ → Valid SIN SIN0 to SIN4,
tSLIXE SIN8 to SIN12, 10 - ns
hold time
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time tF SCK8 to SCK12, - 5 ns
SCK16 to SCK17
SCK0 to SCK4,
SCK rising time tR SCK8 to SCK12, - 5 ns
SCK16 to SCK17
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:

S6J3350 Series
tSCYC
SCK VOH
VOL
tSHOVI
SOT VOH
VOL
tIVSLI tSLIXI
SIN VIH VIH

VIL VIL
Master mode
tSHSL tSLSH
SCK VIH VIH

VIL VIL VIL
tF
tR tSHOVE
SOT VOH
VOL
tIVSLE tSLIXE
SIN VIH VIH

VIL VIL
Slave mode

S6J3350 Series
(3) SPI Supported (SCR: SPI = 1), and Mark Level "H" of Serial Clock Output (SMR: SCINV = 0)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10% / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10% / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Value
Min Max
SCK0, SCK1, SCK2_1,
tSCYC -
cycle time SCK8 to SCK12
SCK0, SCK1, SCK2_1,

SCK3_1, SCK4,
SCK8 to SCK12,
tSHOVI -30 +30 ns
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0, SCK1, SCK2_1, Master

Valid SIN → SCK ↓ SCK3_1, SCK4, Mode
tIVSLI 40 - ns
setup time SCK8 to SCK12, (CL = 20pF,
SCK16 to SCK17 IOL = -5mA,
SIN0, SIN1, SIN2_1, IOH = 5mA)
SCK ↓ → Valid SIN SIN3_1, SIN4,
tSLIXI 0 - ns
SIN16 to SIN17
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17 4tCLK_LCPnA*1 -
- ns
SOT → SCK ↓ SOT0, SOT1, SOT2_1, 30
tSOVLI SOT3_1, SOT4,
delay time
SOT8 to SOT12,
SOT16 to SOT17
SCK16 to SCK17 4tCLK_COMP*1 -
- ns -
SOT16 to SOT17 30
Serial clock
cycle time
SCK ↑ → SOT SCK2_0, SCK3_0,
tSHOVI Master -7.5 +7.5 ns
Mode
tIVSHI (CL = 20pF, 10 - ns -
setup time SCK2_0, SCK3_0,
IOL = -10mA,
SCK ↑→ Valid SIN SIN2_0, SIN3_0
tSHIXI IOH = 10mA) 0 - ns
hold time
*1
SOT → SCK ↓ SCK2_0, SCK3_0, tCLK_LCPnA -
tSOVLI - ns
delay time SOT2_0, SOT3_0 7.5

S6J3350 Series
Value
Min Max
SCK0 to SCK4,
tSHSL SCK8 to SCK12
"H" pulse width
SCK0 to SCK4, *1
Serial clock 4tCLK_LCPnA - ns
tSLSH SCK8 to SCK12
"L" pulse width
SCK0 to SCK4,
SCK8 to SCK12,
tSHOVE - 40 ns
Slave
SOT8 to SOT12,
Mode
SOT16 to SOT17
(CL = 20pF,
Valid SIN → SCK ↓ SCK0 to SCK4, IOL = -5mA,
tIVSLE 10 - ns
SCK16 to SCK17
SCK ↓ → Valid SIN SIN0 to SIN4,
tSLIXE 10 - ns
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time tF SCK8 to SCK12 - 5 ns
SCK16 to SCK17
SCK0 to SCK4,
SCK rising time tR SCK8 to SCK12 - 5 ns
SCK16 to SCK17
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
For details, see Traveo™ Platform Hardware Manual.
tSCYC
SCK VOH
VOL
VOL
tSOVLI tSHOVI
VOH VOH
SOT
VOL VOL
tIVSLI tSLIXI
VIH VIH
SIN
VIL VIL
Master mode

S6J3350 Series
tSLSH tSHSL
SCK VIH VIH VIH

VIL VIL VIL
tF tR tSHOVE
*
VOH VOH
SOT
VOL VOL
tIVSLE tSLIXE
VIH VIH
SIN
VIL VIL
* Changes when writing to the TDR register

Slave mode

S6J3350 Series
(4) SPI Supported (SCR: SPI = 1), and Mark Level "L" of Serial Clock Output (SMR: SCINV = 1)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10 % / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Value
Min Max
SCK0, SCK1, SCK2_1,
tSCYC -
cycle time SCK8 to SCK12
SCK0, SCK1, SCK2_1,

SCK3_1, SCK4,
SCK8 to SCK12,
SCK ↓ -> SOT SCK16 to SCK17
tSLOVI -30 +30 ns
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
Master
SCK0, SCK1, SCK2_1,
Valid SIN -> SCK ↑ Mode
tIVSHI SCK3_1, SCK4, 40 - ns
setup time (CL = 20pF,
SCK8 to SCK12,
IOL = -5mA,
SCK16 to SCK17
IOH = 5mA)
SIN0, SIN1, SIN2_1,
SCK ↑ -> Valid SIN SIN3_1, SIN4,
tSHIXI 0 - ns
SIN16 to SIN17
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17 4tCLK_LCPnA*1 -
- ns
SOT -> SCK ↑ SOT0, SOT1, SOT2_1, 30
tSOVHI
delay time SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK16 to SCK17
4tCLK_COMP -30 - ns
SOT16 to SOT17
Serial clock
cycle time
SCK ↓ -> SOT SCK2_0, SCK3_0,
tSLOVI Master -7.5 +7.5 ns
Valid SIN -> SCK ↑ Mode
tIVSHI (CL = 20pF, 10 - ns -
SCK ↑ -> Valid SIN SIN2_0, SIN3_0 IOL = -10mA,
tSHIXI IOH = 10mA) 0 - ns
hold time
*1
SOT -> SCK ↑ SCK2_0, SCK3_0, tCLK_LCPnA -
tSOVHI - ns
delay time SOT2_0, SOT3_0 7.5

S6J3350 Series
Value
Min Max
SCK0 to SCK4,
tSHSL SCK8 to SCK12
"H" pulse width
-
SCK0 to SCK4, *1
Serial clock 4tCLK_LCPnA - ns
tSLSH SCK8 to SCK12
"L" pulse width
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↓ -> SOT SCK16 to SCK17
tSLOVE - 40 ns
Slave
SOT8 to SOT12,
Mode
SOT16 to SOT17
(CL = 20pF,
Valid SIN -> SCK ↑ SCK0 to SCK4, IOL = -5mA,
tIVSHE 10 - ns
SCK16 to SCK17
SCK ↑ -> Valid SIN SIN0 to SIN4,
tSHIXE 10 - ns
SIN16 to SIN17
SCK0 to SCK4,
SCK falling time tF SCK8 to SCK12 - 5 ns
SCK16 to SCK17
SCK0 to SCK4,
SCK rising time tR SCK8 to SCK12 - 5 ns
SCK16 to SCK17
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
tSCYC
VOH
SCK VOH
VOL
tSOVHI tSLOVI
SOT VOH VOH

VOL VOL
tIVSHI tSHIXI
SIN VIH VIH

VIL VIL
Master mode

S6J3350 Series
tSHSL tSLSH
SCK VIH VIH VIH

VIL VIL VIL
tR tF tSLOV
* E
SOT VOH VOH

VOL VOL
tIVSHE tSHIXE
SIN VIH VIH

VIL VIL
* Changes when writing to the TDR register

Slave mode

S6J3350 Series
(5) Serial Chip Select Used (SCSCR: CSEN = 1)

◼ Mark level "H" of serial clock output (SMR, SCSFR: SCINV = 0)
◼ Inactive level "H" of serial chip select (SCSCR, SCSFR: CSLVL = 1)
Vcc53 = 5.0 V ± 10% / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ± 0.06 V)
Value
Min Max
SCS ↑ → SCK ↓ SCK0, SCK1, SCK2_1,
tCSSI tCSSU*1-15 - ns
setup time SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SCS0x, SCS1x,
SCK ↑ → SCS ↑
tCSHI SCS2x_1, Master tCSHD*2+0 - ns
hold time
SCS3x_1, SCS4, Mode
SCS8x to SCS12x, (CL = 20pF,
SCS16x to SCS17x IOL = -5mA,
SCS0x, SCS1x, IOH = 5mA)
SCS2x_1, tCSDS*3-15
- ns
SCS SCS3x_1, SCS4, +5tCLK_LCPnA*4
tCSDI
deselect time SCS8x to SCS12x
tCSDS*3-15
SCS16x to SCS17x - ns
+5tCLK_COMP
SCS ↑ → SCK ↓
tCSSI Master tCSSU*1-10 - ns
Mode
SCK ↑ → SCS ↑ SCS2x_0, SCS3x_0
tCSHI (CL = 20pF, tCSHD*2+0 - ns
hold time
IOL = -10mA, *3-10
SCS tCSDS
tCSDI SCS2x_0, SCS3x_0 IOH = 10mA) - ns
deselect time +5tCLK_LCPnA*4
SCK0 to SCK4,
SCK8 to SCK12 4tCLK_LCPnA*4
- ns
SCS ↓ → SCK ↓ SCS0x to SCS4x, +15
tCSSE
setup time SCS8x to SCS12x
SCK16 to SCK17, 4tCLK_COMP
- ns
SCS16x to SCS17x +15
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↑ → SCS ↑ SCK16 to SCK17,
tCSHE Slave 0 - ns
hold time SCS0x to SCS4x,
Mode
SCS8x to SCS12x,
(CL = 20pF,
SCS16x to SCS17x
IOL = -5mA,
SCS0x to SCS4x, 4tCLK_LCPnA*4
IOH = 5mA) - ns
SCS SCS8x to SCS12x +15
tCSDE
deselect time 4tCLK_COMP
+15
SCS ↓ → SOT SCS0x to SCS4x,
tDSE - 40 ns
delay time SCS8x to SCS12x,
SCS16x to SCS17x,
SCS ↑ → SOT SOT0 to SOT4,
tDEE 0 - ns
SOT16 to SOT17

S6J3350 Series
Value
Min Max
SCK0, SCK1, SCK2_1,
Master
SCK3_1, SCK4,
mode
SCK8 to SCK12,
round 4tCLK_LCPnA*4 4tCLK_LCPnA*4
SCS0x, SCS1x, ns
operation +0 +15
SCS2x_1,
(CL =
SCS3x_1, SCS4,
20pF,
SCS8x to SCS12x
IOL = -5mA,
SCK ↓ → SCS ↓ SCK16 to SCK17 4tCLK_COMP
IOH = 5mA) 4tCLK_COMP +0 ns
clock switching tSCC SCS16x to SCS17x +15
time Master
mode
round
SCK2_0, SCK3_0, operation 4tCLK_LCPnA*4 4tCLK_LCPnA*4
ns
SCS2x_0, SCS3x_0 (CL = +0 +10
20pF,
IOL = -10mA,
IOH = 10mA)
*1: tCSSU = SCSTR: CSSU[7:0] x serial chip select timing operating clock
*2: tCSHD = SCSTR: CSHD[7:0] x serial chip select timing operating clock
*3: tCSDS = SCSTR: CSDS[15:0] x serial chip select timing operating clock
For details on *1, *2, and *3 above, see the Traveo™ Platform Hardware Manual.
*4 tCLK_LCPnA n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
− This is the AC characteristic in CLK synchronized mode.
− CL is the load capacitance applied to pins during testing.
VOH VOH
SCS output VOL VOL tCSDI
tCSSI tCSHI
SCK output VOH

VOL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
Master mode

S6J3350 Series
VIH VIH
SCS input VIL VIL tCSDE
tCSSE tCSHE
SCK input VIH

VIL tDEE
SOT
(Normal synchronous
transfer) tDSE VOL
SOT VOH
VOL
(SPI compatible)
Slave mode
SCSx output
tSCC
SCSy output
VOL
SCK output VOL
Clock switching example by master mode round operation

(x,y=0, 1, 2, 3: x and y are different value)

S6J3350 Series

◼ Serial clock output signal detect level "L" (SMR, SCSFR: SCINV = 1)
◼ Serial chip select inactive level "H" (SCSCR, SCSFR: CSLVL = 1)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ±0.3 V, Vcc5 = DVcc = 5.0 V ± 10% / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15V ± 0.06 V)
Value
Min Max
SCS ↓→ SCK ↑ SCK0, SCK1, SCK2_1,
SCK8 to SCK12,
SCK16 to SCK17
SCS0x, SCS1x,
SCK ↓→ SCS ↑
hold time
SCS3x_1, SCS4, mode
SCS2x_1, tCSDS*3-15
- ns
tCSDI
tCSDS*3-15
+5tCLK_COMP
SCS ↓→ SCK ↑
Mode
SCK ↓→ SCS ↑ SCS2x_0, SCS3x_0
hold time
IOL = -10mA, *3-10
SCS tCSDS
SCK0 to SCK4,
- ns
SCS ↓ → SCK ↑ SCS0x to SCS4x, +15
tCSSE
- ns
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↓ → SCS ↑ SCK16 to SCK17,
tCSHE Slave 0 - ns
mode
SCS8x to SCS12x,
(CL = 20pF,
SCS16x to SCS17x
IOL = -5mA,
IOH = 5mA) - ns
tCSDE
+15
SCS ↓ → SOT SCS0x to SCS4x,
tDSE - 40 ns
SCS16x to SCS17x,
SCS ↑ → SOT SOT0 to SOT4,
tDEE 0 - ns
SOT16 to SOT17

S6J3350 Series
Value
Min Max
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4, Master
SCK8 to SCK12, mode
4tCLK_LCPnA*4 4tCLK_LCPnA*4
SCS0x, SCS1x, round ns
+0 +15
SCS2x_1, operation
SCS3x_1, SCS4, (CL = 20pF,
SCK ↑ → SCS ↓ SCK16 to SCK17 IOH = 5mA) 4tCLK_COMP
4tCLK_COMP +0 ns
time Master
mode
round
ns
SCS2x_0, SCS3x_0 (CL = +0 +10
20pF,
IOL = -10mA,
IOH = 10mA)
*1: t
CSSU = SCSTR: CSSU[7:0] x serial chip select timing operating clock
Notes:
VOH VOH
SCS output VOL
VOL tCSDI
tCSSI tCSHI
VOH
SCK output VOL
SOT
(Normal synchronous
transfer)
SOT
(SPI compatible)
Master mode

S6J3350 Series
VIH VIH
SCS input
VIL VIL tCSDE
tCSSE tCSHE
VIH
SCK input VIL tDEE
SOT
(Normal synchronous VOL
transfer) tDSE
VOH
SOT
VOL
(SPI compatible)
Slave mode
SCSx output tSCC
SCSy output
VOL
SCK output VOH


S6J3350 Series

◼ Serial clock output signal detect level "H" (SMR, SCSFR: SCINV = 0)
◼ Serial Chip select inactive level "L" (SCSCR, SCSFR: CSLVL = 0
Value
Min Max
SCS ↑ → SCK ↓ SCK0, SCK1, SCK2_1,
SCK8 to SCK12,
SCK16 to SCK17
SCS0x, SCS1x,
SCK ↑ → SCS ↓
hold time
SCS3x_1, SCS4, mode
SCS2x_1, tCSDS*3-15
- ns
tCSDI
tCSDS*3-15
+5tCLK_COMP
SCS ↑ → SCK ↓
Mode
SCK ↑ → SCS ↓ SCS2x_0, SCS3x_0
hold time
IOL = -10mA, *3-10
SCS tCSDS
SCK0 to SCK4,
SCK8 to SCK12 4tCLK_LCPnA*4
- ns
SCS ↑ → SCK ↓ SCS0x to SCS4x, +15
tCSSE
- ns
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↑ → SCS ↓ SCK16 to SCK17,
tCSHE Slave 0 - ns
mode
SCS8x to SCS12x,
(CL = 20pF,
SCS16x to SCS17x
IOL = -5mA,
IOH = 5mA) - ns
tCSDE
+15
SCS ↑ → SOT SCS0x to SCS4x,
tDSE - 40 ns
SCS16x to SCS17x,
SCS ↓ → SOT SOT0 to SOT4,
tDEE 0 - ns
SOT16 to SOT17

S6J3350 Series
Value
Min Max
SCK0, SCK1, SCK2_1,
SCK8 to SCK12 mode
4tCLK_LCPnA*4 4tCLK_LCPnA*4
SCS0x, SCS1x, round ns
+0 +15
SCS2x_1, operation
SCK ↓ → SCS ↑ IOH = 5mA)
SCK16 to SCK17 4tCLK_COMP
clock switching tSCC 4tCLK_COMP +0 ns
time
Master
mode
round
SCK2_0, SCK3_0, 4tCLK_LCPnA*4 4tCLK_LCPnA*4
operation ns
SCS2x_0, SCS3x_0 +0 +10
(CL = 20pF,
IOL = -10mA,
IOH = 10mA)
*1: t
CSSU = SCSTR: CSSU[7:0] x serial chip select timing operating clock
Notes:
For details, see the Traveo™ Platform Hardware Manual
tCSDI
VOH VOH
SCS
output VOL
tCSSI tCSHI
SCK output VOH

VOL
SOT
(Normal
synchronous
transfer)
SOT
(SPI
compatible)
Master mode

S6J3350 Series
tCSDE
VIH
SCS input VIH
VIL
tCSSE tCSHE
VIH
SCK input VIL tDEE
SOT
(Normal synchronous
transfer) tDSE VOL
SOT VOH
(SPI compatible) VOL
Slave mode
SCSx output tSCC
SCSy output VOH
SCK output VOL


S6J3350 Series

◼ Serial clock output signal detect level "L" (SMR, SCSFR: SCINV = 1)
◼ Serial Chip select inactive level "L" (SCSCR, SCSFR: CSLVL = 0)
(TA: Recommended operating conditions, Vcc3 = 3.3 V ±0.3 V, Vcc5 = DVcc = 5.0 V ± 10 % / 3.3V ± 0.3 V,
Value
Min Max
SCS ↑ → SCK ↑ SCK0, SCK1, SCK2_1,
SCK8 to SCK12,
SCK16 to SCK17
SCS0x, SCS1x,
SCK ↓ → SCS ↓
hold time
SCS3x_1, SCS4, mode
SCS2x_1, tCSDS*3-15
- ns
tCSDI
tCSDS*3-15
+5tCLK_COMP
SCS ↑ → SCK ↑
Mode
SCK ↓ → SCS ↓ SCS2x_0, SCS3x_0
hold time
IOL = -10mA, *3-10
SCS tCSDS
SCK0 to SCK4,
SCK8 to SCK12 4tCLK_LCPnA*4+1
- ns
SCS ↑ → SCK ↑ SCS0x to SCS4x, 5
tCSSE
SCK16 to SCK17, 4tCLK_COMP+
- ns
SCS16x to SCS17x 15
SCK0 to SCK4,
SCK8 to SCK12,
SCK ↓ → SCS ↓ SCK16 to SCK17, Slave
tCSHE 0 - ns
hold time SCS0x to SCS4x, mode
SCS0x to SCS4x, IOH = 5mA) 4tCLK_LCPnA*4+1
SCS - ns
tCSDE SCS8x to SCS12x 5
deselect time
SCS16x to SCS17x 4tCLK_COMP+15 - ns
SCS ↑ → SOT SCS0x to SCS4x,
tDSE - 40 ns
SCS16x to SCS17x,
SCS ↓ → SOT SOT0 to SOT4,
tDEE 0 - ns
SOT16 to SOT17

S6J3350 Series
Value
Min Max
SCK0, SCK1, SCK2_1,
SCK8 to SCK12, mode
4tCLK_LCPnA*4
SCS0x, SCS1x, round 4tCLK_LCPnA*4+0 ns
+15
SCS2x_1, operation
SCK ↑ → SCS ↑ SCK16 to SCK17, IOH = 5mA) 4tCLK_COMP
4tCLK_COMP+0 ns
time Master
mode
round
ns
SCS2x_0, SCS3x_0 (CL = +0 +10
20pF,
IOL = -10mA,
IOH = 10mA)
*1: tCSSU = SCSTR: CSSU[7:0] x serial chip select timing operating clock
*3:
tCSDS = SCSTR: CSDS[15:0] x serial chip select timing operating clock
*4 tCLK_LCPnA n = 0: ch.0 to ch.4, n = 1: ch.8 to ch.12
Notes:

S6J3350 Series
tCSDI
VOH
SCS output VOH
VOL
tCSHI
tCSSI
VOH
SCK output VOL
SOT
(Normal synchronous transfer)
SOT
(SPI compatible)
Master mode
tCSDE
SCS input VIH VIL

tCSSE tCSHE
VIH
SCK input tDEE
VIL
SOT
(Normal synchronous
transfer) tDSE VOL
SOT VOH
VOL
(SPI compatible)
Slave mode
SCSx output tSCC
SCSy output VOH
SCK output VOH


S6J3350 Series
LIN interface (v2.1) (LIN communication control interface (v2.1)) timing (SMR: MD2-0 = 0b011)
(1) External Clock Selected (BGR: EXT = 1)

(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10% / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10% / 3.3 V ±0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V ±0.06 V)
Value
Min Max
SCK0 to SCK4,
tCLK_LCPnA*1+10 - ns
SCK8 to SCK12
Serial clock
tSLSH
"L" pulse width
SCK16 to SCK17 tCLK_COMP +10 - ns
SCK0 to SCK4,
tCLK_LCPnA*1+10 - ns
SCK8 to SCK12
Serial clock
tSHSL -
"H" pulse width
SCK16 to SCK17 tCLK_COMP +10 - ns
SCK falling time tF - 5 ns

SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SCK rising time tR - 5 ns
*1: n = 0: ch.0 to ch.4, n = 1: ch.8 to ch.12
tR tSHSL tF
tSLSH
SCK VIH VIH VIH

VIL VIL VIL
External clock selected

S6J3350 Series
I2C timing (SMR: MD2-0 = 0b100)

(TA: Recommended operating conditions, Vcc5 = Vcc53 = 5.0 V ±10 %, VCC12 = 1.15V ±0.06 V, VSS = 0.0 V)
Standard Fast
Mode Mode
Min Max Min Max
SCL0, SCL1, SCL4,
SCL clock
fSCL SCL8 to SCL12, 0 100 0 400 kHz
frequency
SCL16 to SCL17
SDA0, SDA1, SDA4
SDA8 to SDA12,
Repeat "start"
SDA16 to SDA17,
condition hold time tHDSTA 4.0 - 0.6 - µs
SCL0, SCL1, SCL4,
SDA↓ → SCL↓
SCL8 to SCL12,
SCL16 to SCL17
Period of "L" for
tLOW 4.7 - 1.3 - µs
SCL clock SCL0, SCL1, SCL4,
SCL8 to SCL12,
Period of "H" for SCL16 to SCL17
tHIGH 4.0 - 0.6 - µs
SCL clock
Repeat "start"
condition setup time tSUSTA CL = 50pF, 4.7 - 0.6 - µs
SCL↑ → SDA↓ R=
(Vp/IOL)*1
Data hold time SDA0, SDA1, SDA4
tHDDAT SDA8 to SDA12, 0 3.45*2 0 0.9*3 µs
SCL↓ → SDA↓↑
SDA16 to SDA17,
SCL0, SCL1, SCL4,
Data setup time SCL8 to SCL12,
tSUDAT 250 - 100 - ns
SDA↓↑ → SCL↑ SCL16 to SCL17
"Stop" condition
setup time tSUSTO 4.0 - 0.6 - µs
SCL↑ → SDA↑
Bus-free time
between "stop"
tBUF - 4.7 - 1.3 - µs
condition and "start"
condition
Noise filter tSP - tNFT*4 - tNFT*4 - ns
Notes: Only ch.16 and ch.17 are standard mode/high-speed mode correspondence. In ch.0, ch.1, ch.4, and ch.8 to ch.12, only a
standard mode is correspondence.
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL
signal.
*3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the
device satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tNFT = (NFCR: NFT[4:0]+1) x 2 x tCLK_LCP0A (ch.0, ch.1, ch4)

tNFT = (NFCR: NFT[4:0]+1) x 2 x tCLK_LCP1A (ch.8 to ch.12)
tNFT = (NFCR: NFT[4:0]+1) x 2 x tCLK_COMP (ch.16 to ch.17)

S6J3350 Series
SDA
tSUDAT tSUSTA
tLOW tBUF
SCL
tHDSTA tHDDAT tHIGH tHDSTA tSP tSUSTO

S6J3350 Series
9.1.4.7 Timer Input

(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10 %,
Value
Min Max
4tCLK_LCPnA*1 ≥100
4tCLK_LCPnA*1
PPG0_TIN1 to ns
- - ns
PPG31_TIN1 4tCLK_LCPnA*1 <100
100
ns
ICU0_IN0 to ICU2_IN0, 4tCLK_LCPnA*2 ≥100
ICU8_IN0 to 4tCLK_LCPnA*2
ns
ICU10_IN0, - - ns
ICU0_IN1 to ICU2_IN1, 4tCLK_LCPnA*2 <100
100
ICU8_IN1 to ICU10_IN1 ns
tTWH, FRT0_TEXT to 4tCLK_LCPnA*3 ≥100

Input pulse width 4tCLK_LCPnA*3
tTWL FRT4_TEXT, ns
- - ns
FRT8_TEXT to 4tCLK_LCPnA*3 <100
FRT10_TEXT 100
ns
4tCLK_LCPnA*4 ≥100
4tCLK_LCPnA*4
TIN0 to TIN1, ns
- - ns
TIN16 to TIN17 4tCLK_LCPnA*4 <100
100
ns
4tCLK_COMP 4tCLK_COMP ≥100 ns
TIN48 to TIN49 - - ns
100 4tCLK_COMP <100 ns
*1: n = 0: unit.0 to unit.5, unit.12 to unit.31, n = 1: unit.6 to unit.11
*2: n = 0: unit.0 to unit.2, n = 1: unit.8 to unit.10
*3: n = 0: ch.0 to ch.4, n = 1: ch.8 to ch.10
*4: n = 0: ch.0 to ch.1, n = 1: ch.16 to ch.17
− Timer input timing

PPGx_TIN1
tTIWH tTIWL
ICUx_IN0/1
FRTx_TEXT
VIH VIH
TINx
VIL VIL

S6J3350 Series
9.1.4.8 QPRC timing
(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10 %,
Value
Min Max
AIN pin "H" width tAHL AIN8 to AIN9 -
AIN pin "L" width tALL AIN8 to AIN9 -
BIN pin "H" width tBHL BIN8 to BIN9 -
BIN pin "L" width tBLL BIN8 to BIN9 -
AIN8 to
Time from AIN pin "H" level PC_Mode2 or
tAUBU AIN9,
to BIN rise PC_Mode3
BIN8 to BIN9
AIN8 to
Time from BIN pin "H" level PC_Mode2 or
tBUAD AIN9,
to AIN fall PC_Mode3
BIN8 to BIN9
AIN8 to
Time from AIN pin "L" level PC_Mode2 or
tADBD AIN9,
to BIN fall PC_Mode3
BIN8 to BIN9
AIN8 to
Time from BIN pin "L" level PC_Mode2 or
tBDAU AIN9,
to AIN rise PC_Mode3
BIN8 to BIN9
AIN8 to
Time from BIN pin "H" level PC_Mode2 or
tBUAU AIN9,
to AIN rise PC_Mode3
BIN8 to BIN9
4tCLK_LCP1
AIN8 to 4tCLK_LCP1
Time from AIN pin "H" level PC_Mode2 or - ns A
tAUBD AIN9, A
100 ns
to BIN fall PC_Mode3 ≥
BIN8 to BIN9
AIN8 to
Time from BIN pin "L" level PC_Mode2 or
tBDAD AIN9,
to AIN fall PC_Mode3
BIN8 to BIN9
AIN8 to
Time from AIN pin "L" level PC_Mode2 or
tADBU AIN9,
to BIN rise PC_Mode3
BIN8 to BIN9
ZIN pin "H" width tZHL ZIN8 to ZIN9 QCR: CGSC = "0"
ZIN pin "L" width tZLL ZIN8 to ZIN9 QCR: CGSC = "0"
AIN8 to
AIN9,
Time from determined ZIN level
tZABE BIN8 to QCR: CGSC = "1"
to AIN/BIN rise and fall
BIN9,
ZIN8 to ZIN9
AIN8 to
Time from AIN/BIN rise and fall AIN9,
time tABEZ BIN8 to QCR: CGSC = "1"
to determined ZIN level BIN9,
ZIN8 to ZIN9

S6J3350 Series
tAHL tALL
AIN
tAUBU tBUAD tADBD tBDAU
BIN
tBHL tBLL
tBHL tBLL
BIN
tBUAU tAUBD tBDAD tADBU
AIN
tAHL tALL

S6J3350 Series
ZIN
ZIN
AIN/BIN

S6J3350 Series
9.1.4.9 Trigger Input

(TA: Recommended operating conditions, Vcc3 = 3.3 V ±0.3V, Vcc5 = DVcc = 5.0 V ± 10 %,
Vcc53 = 5.0 V ± 10% / 3.3 V ± 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15V ± 0.06 V)
Value
Min Max
EINT0 to EINT23 - 100 - ns
tTRGH, ADTRG0 to 5tCLK_LCP1A 5tCLK_LCP1A ≥100 ns
Input pulse width - - ns
tTRGL ADTRG1 100 5tCLK_LCP1A <100 ns
EINT0 to EINT23 - 1 - µs Stop mode
− Trigger input timing
tTRGH tTRGL
EINTx VIH VIH

ADTRGx VIL VIL

S6J3350 Series
9.1.4.10 NMI Input

(TA: Recommended operating conditions, Vcc5 = 5.0 V ± 10 %, VSS = 0.0 V)
Value
Min Max
Input pulse width tNMIL NMIX - 300 - ns
− NMIX input timing
tNMIL
NMIX VIH VIH

VIL VIL

S6J3350 Series
9.1.4.11 Low Voltage Detection (External Voltage)

Low-voltage detection (external low-voltage detection)
(TA: Recommended operating conditions, VSS = AVSS = 0.0 V)

Value
Min Typ Max
3.5 *3 - 5.5 *3
VDP5 VCC5 - V
Supply voltage range 2.7 *4 - 3.6 *4
VDP3 VCC3 - 2.7 - 3.6 V
*1 3.6 *3 4.0 *3 4.4 *3 When power-
VCC5 V supply voltage
*1 *5
Detection voltage 2.3 *4 2.6 *4 2.9 *4 falls
VDLBT
(before trimming) and detection
VCC3 *1 *5 2.3 2. 6 2.9 V level is set
initially
*1 3.86 *3 4.0 *3 4.14 *3 When power-
*1 *5 2.51 *4 2.6 *4 2.69 *4 falls
Detection voltage
VDLAT and detection
(after trimming)
VCC3 *1 *5 2.51 2.6 2.69 V level is set
initially
Typ±3.5%
When power-
Hysteresis width VHYS VCC5 - - 100 - mV supply voltage
rises
Low-voltage
Td - - - - 40 μs
detection time
Power supply voltage
- VCC5 - -2 - 2 V/ms *2
regulation
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low-voltage
detection by detecting voltage (VDL)
*4: For S6J335xxAx or S6J335xxBx or S6J335xxCx or S6J335xxDx or S6J335xxEx or S6J335xxFx or S6J335xxGx or
S6J335xxHx option.
*5: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (2.7V).
Notes:
− The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2
Recommended operating condition.
LVDH1(VCC5)
LVDH2(VCC3)
− Please use these LVD channels with your own risk.
− Please monitor the external power supplies on the PCB if needed.
− For S6J335xxSC or S6J335xxUC or S6J335xxTC or S6J335xxVC options:
Depending on the threshold setting, LVDH1 can always detect VCC5 low voltage before the supply drops below the level
defined in 9.1.2 Recommended Operating Condition. Please refer to S6J3300 series Hardware Manual for available list of
LVDH1 threshold settings.

S6J3350 Series
Low-voltage detection (1.15 V power supply low-voltage detection)

Value
Min Typ Max
Supply voltage range VRDP12 VCC12 - 1.09 - 1.21 V
When power-
Detection voltage *1 *2
VRDLBT VCC12 0.7125 0.8125 0.9125 V supply voltage
(before trimming) *
falls
When power-
Detection voltage *1 *2 supply voltage
VRDLAT VCC12 0.7841 0.8125 0.8410 V
(after trimming) falls
Typ±3.5%
When power-
Hysteresis width VRHYS - - - 75 - mV supply voltage
rises
Low-voltage detection
TRd - - - - 30 μs
time
*1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the
detection may occur or be canceled after the supply voltage has passed the detection voltage range.
*2: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.09V).
Notes:
− The detection/release threshold values of LVDL2 channel is potentially below supply range defined in 9.1.2 Recommended
Operating Condition.
− Please use this LVDL2 channel with your own risk.
− Please monitor the external power supplies on the PCB if needed.

S6J3350 Series
9.1.4.12 Low Voltage Detection (Internal Voltage)

Low-voltage detection (internal low-voltage detection for LVDL0)
Value
Min Typ Max
Supply voltage range VRDP5 - - 1.05 - 1.21 V
When power-
*1 *2
Detection voltage VRDL - 0.75 0.85 0.95 V supply voltage
falls
When power-
rises
Low-voltage detection *3
TRd - - - - 30 μs
time
*2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage,
as these detection levels are below the minimum guaranteed MCU operation voltage (1.05V).
*3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may
occur or be canceled.
Notes:
operating condition.
Low-voltage detection (internal low-voltage detection for LVDL1)

Value
Min Typ Max
Supply voltage range VRDP5 - - 1.05 - 1.21 V
When power-
Detection voltage *1 *2
VRDLBT - 0.775 0.875 0.975 V supply voltage
(before trimming)
falls
When power-
Detection voltage *1 *2 supply voltage
VRDLAT - 0.844 0.875 0.906 V
(after trimming) falls
Typ±3.5%
When power-
rises
Low-voltage detection *3
TRd - - - - 30 μs
time
*2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage,
as these detection levels are below the minimum guaranteed MCU operation voltage (1.05V).
*3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may
occur or be canceled.
Notes:
operating condition.

S6J3350 Series
9.1.4.13 High Current Output Slew Rate

(TA: Recommended operating conditions,
VCC5,VCC53,DVCC = 5.0 V ± 10 %, VCC3 = 3.3 V ± 0.3 V, VCC12 = 1.15 V ± 0.06 V, VSS = DVSS = AVSS = 0.0 V)
Value
Min Typ Max
Load
Output rise / fall P1_17 to P1_31,
tR2,tF2 - 15 - 100 ns capacitance
time P2_00 to P2_08
85pF
VH=VOL8+0.9 x (VOH8-VOL8)
VL=VOL8+0.1 x (VOH8-VOL8)

S6J3350 Series
9.1.4.14 External bus interface timing

Clock output timing
(External load capacitance 16 pF)
Value
Min Max
Cycle time tCYC MCLK 2mA is 62.5 - ns
Clock high width *1 tCHCL MCLK selected in dHtcyc - 7 dHtcyc + 7 ns
ODR bit in
Clock low width *2 tCLCH MCLK PPC_PCFGR dLtcyc - 7 dLtcyc + 7 ns
register.
*1: If division-ratio is even value, dH is equivalent to 0.5.
Otherwise, dH is calculated as the following.
dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429.
*2: If division-ratio is even value, dL is equivalent to 0.5.
Otherwise, dL is calculated as the following.
dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571.
− Clock output timing

S6J3350 Series
Common timing between read and write

Value
Min Max
Cycle time
tCYC MCLK 62.5 - ns
(without MRDY)
If using MRDY,
Cycle time set MCLK to
tCYC MCLK 2mA is selected in 62.5 - ns
(with MRDY) 20 MHz or
ODR bit in
less.
PPC_PCFGR register.
MCLK,
CS delay time tCSO 0.5 18 ns
MCSX0 to MCSX3
MCLK,
Address delay time tAO 0.5 18 ns
MAD00 to MAD23
RDY setup time tRDYS MCLK, MRDY "CMOS Schmitt input" 21 - ns
and "Disable noise
RDY hold time tRDYH MCLK, MRDY filter" are selected in 0 - ns
PPC_PCFGR register.
Notes: This is Target Spec.
− External bus I/F common timing

S6J3350 Series
Read timing
Value
Min Max
MOEX,
Data setup time tDSR MDATA00 to "CMOS Schmitt input" 21+tcyc - ns
MDATA15 and "Disable noise
MOEX, filter" are selected in
Data hold time tDHR MDATA00 to PPC_PCFGR register. 0 - ns
MDATA15
2mA is selected in
MOEX delay time tRDO MCLK, MOEX ODR bit in 0.5 18 ns
PPC_PCFGR register.
− External bus I/F read timing

S6J3350 Series
Write timing
Value
Min Max
MWEX delay time tWEO MCLK, MWEX 0.5 18 ns
Byte mask delay MCLK,
tWRO 0.5 18 ns
time MDQM0 to MDQM1
MCLK, 2mA is selected in
Data delay time tDO MDATA00 to ODR bit in 0.5 18 ns
MDATA15 PPC_PCFGR register.
MCLK,
Data delay time
tDOZ MDATA00 to - 18 ns
(Hi-Z output)
MDATA15
− External bus I/F write timing

S6J3350 Series
9.1.4.15 DDR-HSSPI
(1) DDR-HSSPI Interface Timing (SDR Mode)

(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Min Max
10 -
when
HSSPI clock cycle tcyc M_SCLK0 ns
20 - Quad Page
Program
M_SCLK↑ ->
tspcnt - 0 31.5 ns
delayed sample clock↑
M_SDATA -> M_SLCK↑ M_SDATA0_0-3
tisdata *1 - ns
Input setup time M_SDATA1_0-3
M_SCLK↑ -> M_SDATA M_SDATA0_0-3 (CL = 20pF,
tihdata *1 - ns
Input hold time M_SDATA1_0-3 IOL = -10mA,
M_SCLK↑ -> M_SDATA M_SDATA0_0-3 IOH = 10mA),
toddata - tcyc/2 + 2 ns
Output delay time M_SDATA1_0-3
M_SCLK↑ -> M_SDATA M_SDATA0_0-3
tohdata tcyc/2 - 3 - ns
Output hold time M_SDATA1_0-3
M_SCLK↑ -> M_SSEL -
todsel M_SSEL0, 1 12.00+(SS2 - ns
Output delay time
CD+0.5)* tcyc
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 tcyc - 2 - ns
Output hold time
− SS2CD [1:0] should be configured as 01, 10, or 11.
− For *1, the delay of the delay sample clock can be configured (DLP function).

S6J3350 Series
tcyc
VOH
M_SCLK0
G_SCLK0 VOH
tspcnt
delayed VOH
sample clock
tisdata tihdata
VIH VIH
G_SDATA0_0-3,
M_SDATA0_0-3,
valid
M_SDATA1_0-3
G_SDATA1_0-3
(input timing) VIL VIL
toddata tohdata
VOH VOH
G_SDATA0_0-3,
M_SDATA0_0-3, valid
M_SDATA1_0-3
G_SDATA1_0-3
(output timing) VOL VOL
todsel tohsel
VOH VOH
GSSEL0,
M_SSEL0,1 1
valid
(output timing)
VOL VOL

S6J3350 Series
(2) DDR-HSSPI Interface Timing (DDR Mode)

Value
Min Max
HSSPI clock cycle tcyc M_SCLK0 12.5 - ns
M_SCLK↑ ->
tspcnt 0 31.5 ns
tisdata *1 - ns
Input setup time M_SDATA1_0-3
M_SLCK↑ -> M_SDATA M_SDATA0_0-3
tihdata *1 - ns
Input hold time M_SDATA1_0-3
M_SCLK↑ -> M_SDATA (CL = 20pF,
M_SDATA0_0-3
toddata IOL = -10mA, - tcyc/4 + 1.5 ns
Output delay time M_SDATA1_0-3
IOH = 10mA),
tohdata Tcyc/4 - 1.0 - ns
Output hold time M_SDATA1_0-3
M_SCLK↑ -> M_SSEL -
todsel M_SSEL0, 1 15.75+(SS2CD - ns
Output delay time
+0.5)*tcyc
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 0.75*tcyc - 2.0 - ns
Output hold time
− For *1, the delay of the delay sample clock can be configured (DLP function)

S6J3350 Series
tcyc
VOH
M_SCLK0
G_SCLK0 VOH
VOL
tspcnt
delayed VOH
sample clock
tisdata tihdata
VIH VIH
G_SDATA0_0-3,
M_SDATA0_0-3, valid
M_SDATA1_0-3
G_SDATA1_0-3
(input timing) VIL VIL toddata
toddata tohdata tohdata
VOH VOH
G_SDATA0_0-3,
M_SDATA0_0-3, valid valid
M_SDATA1_0-3
G_SDATA1_0-3
(output timing) VOL VOL
todsel tohsel
VOH VOH
GSSEL0, 1
M_SSEL0,1 valid
(output timing)
VOL VOL

S6J3350 Series
9.1.4.16 Hyper BUS
(1) Hyper Bus Write Timing (HyperFlash)

Value
Min Max
Hyper Bus clock cycle tCKCYC M_CK 10.0 - ns
CS↑↓ -> CK↑
tCSS M_CS#_1,2 tCKCYC -2.0 - ns
Chip Select setup time
DQ -> CK↑↓ (CL = 20pF,
tIS M_DQ7-0 1.25 - ns
Input setup time IOL = -10mA,
CK↑↓ -> DQ IOH = 10mA),
tIH M_DQ7-0 1.25 - ns
Input hold time
CK↓ -> CS↑
tCSH M_CS#_1,2 tCKCYC/2 - ns
Chip select hold time
Notes: This is Target Spec
tCSHI
G_CS#_1,2 VOH
M_CS#_1,2 VOL
tCKCYC
tCSS tCSH tCSS
G_CK VOH
M_CK VOL
tDSV tDSZ
G_RWDS
M_RWDS
tIS tIH
VIH
G_DQ7~0 CA0 CA0 CA1 CA1 CA2 CA2 Dn Dn
47-40 39- 31-24 23-16 15-8 7-0 15-8 7-0
M_DQ7~0 32
VIL

S6J3350 Series
(2) Hyper Bus Write Timing (HyperRAM)

Value
Min Max
Hyper Bus clock cycle tCKCYC M_CK 10.0 - ns
CS↑↓ -> CK↑

tCSS M_CS#_1,2 tCKCYC - 2.0 - ns
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Input setup time
CK↑↓ -> DQ (CL = 20pF,
tIH M_DQ7-0 IOL = -10mA, 1.25 - ns
Input hold time
CK↓ -> CS↑ IOH = 10mA),
RWDS↓-> CK↓
tDMV M_RWDS 1 - ns
Data Mask Valid
CK↑ -> RWDS↑↓
tRIV M_RWDS - 6 ns
Refresh Indicator Valid
CK↑ -> RWDS(Hi-z)
tRIH M_RWDS 0 - ns
Refresh Indicator Hold
tCSM tCSHI
tRWR tPO
G_CS#_1,2 VIH
M_CS#_1,2 VIL
tCKCYC tCSH
tCSS tCSS
G_CK VOH
M_CK
VOL
tRIH tDMV
tRIV
G_RWDS tIS tIH
M_RWDS VOH
VOL
tIS
tIH
G_DQ7~0 VIH
M_DQ7~0 CA0 CA0 CA1 CA1 CA2 CA2 Dn Dn
47-40 39- 31-24 23-16 15-8 7-0 15-8 7-0
32
VIL

S6J3350 Series
(3) Hyper Bus Read Timing (HyperFlash)

Value
Min Max
Hyper Bus clock cycle tRDSCYC M_CK 10.0 - ns
CS↑↓ -> CK↑

tCSS M_CS#_1,2 tRDSCYC -2.0 - ns
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Setup time (CL = 20pF,
CK↑↓ -> DQ IOL = -10mA,
tIH M_DQ7-0 IOH = 10mA), 1.25 - ns
Hold time
CK↓ -> CS↑
tCSH M_CS#_1,2 tRDSCYC / 2 - ns
RDS↑↓> DQ
tDSS M_DQ7-0 -0.8 - ns
Setup time
RDS↑↓> DQ
tDSH M_DQ7-0 -0.8 - ns
Hold time
tCSHI
tACC
VOH
G_CS#_1,2
VOL
M_CS#_1,2
tCSS tCSH tCSS
G_CK VOH
M_CK VOL
tDSV tCKDS
tRDSCYC tDSZ
tDQLZ
G_RWDS VOH tOZ
M_RWDS
tIH
tIS tDSH tDSS
VIH VOH
G_DQ7~0 CA0 CA0 CA1 CA1 CA2 CA2 Dn Dn Dn+1 Dn+1
47-40 39- 31-24 23-16 15-8 7-0 15-8 7-0 15-8 7-0
M_DQ7~0 32
VIL VOL

S6J3350 Series
(4) Hyper Bus Read Timing (HyperRAM)

(TA: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3V, VSS = DVSS = AVSS = 0.0 V)
Value
Min Max
Hyper Bus clock cycle tRDSCYC M_CK 10.0 - ns
CS↑↓ -> CK↑
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Setup time
CK↑↓ -> DQ
tIH M_DQ7-0 1.25 - ns
Hold time
CK↓ -> CS↑ (CL = 20pF,
tCSH M_CS#_1,2 tRDSCYC /2 - ns
Chip select hold time IOL = -10mA,
RWDS↑↓> DQ (valid) IOH = 10mA),
Setup time
RWDS↑↓> DQ (invalid)
Hold time
CK↑ -> RWDS↑↓
tRIV M_RWDS - 6 ns
CK↑ -> RWDS(Hi-z)
tRIH M_RWDS 0 - ns
tCSM tCSHI
tRWR tPO
G_CS#_1,2 VOH
M_CS#_1,2 VOL
tCSS tCSH tCSS

G_CK VOH
M_CK VOL
tRIH tCKDS
tRIV tDSZ
tDQLZ tRDSCYC
G_RWDS VOH tOZ

M_RWDS
tIS
tIH tDSH tDSS
VIH VOH
G_DQ7~0 CA0 CA0 CA1 CA1 CA2 CA2 Dn Dn Dn+1 Dn+1
47-40 39- 31-24 23-16 15-8 7-0 15-8 7-0 15-8 7-0
M_DQ7~0 32
VIL VOL

S6J3350 Series
9.1.4.17 Ethernet AVB
(1) Ethernet Receive Timing

(TA: Recommended operating conditions, Vcc53 = Vcc3 = 3.3 V ± 0.3 V, VSS = DVSS = AVSS = 0.0 V)
Value
Min Max
RXCLK cycle tRXCYC RXCLK 40.0 - ns -
RXER
tRXCYC -
RX setup time tRXS RXDV 10.0 - ns
30ns
RXD0-3 -
RXER
RX hold time tRXH RXDV 0 - ns -
RXD0-3
tRXCYC
VIH VIH
RXCLK
tRXS
VIH tRXH
RXER
RXDV valid
RXD0-3
VIL

S6J3350 Series
(2) Ethernet Transmit Timing

Value
Min Max
TXCLK cycle tTXCYC TXCLK 40.0 - ns -
COL/CRS input setup COL
tCRXS 12.0 - ns -
time CRS
(CL = 20pF,
COL/CRS input hold COL IOL = -5mA,
tCRXH 0.5 - ns -
time CRS IOH = 5mA),
TXER
Tx delay time tTXD TXEN 0.5 25 ns -
TXD0-3
tTXCYC
VIH VIH VIH VIH

TXCLK
tCRXS
VIH tCRXH
COL
valid
CRS
VIL tTXD
tTXD
VOH
TXER
TXDV valid
TXEN TXD0-3
VOL

S6J3350 Series
(3) MDIO Timing

Value
Min Max
MDC cycle tMDCYC MDC 400.0 - ns
(CL = 20pF,
MDIO input setup time tMDIS MDIO 100.0 - ns
IOL = -5mA, -
MDIO input hold time tMDIH MDIO IOH = 5mA), 0.0 - ns
MDIO output delay time tMDOD MDIO 10.0 190.0 ns
tMDCYC
VOH VOH VOH VOH

MDC
VOL
tMDIS
VIH tMDIH
MDIO
valid
(in)
VIL tMDOD
tMDOD
VOH
MDIO
valid
(out)
VOL

S6J3350 Series
9.1.4.18 Port Noise Filter

(TA: Recommended operating conditions, VCC5,VCC53,DVCC5 = 5.0 V ± 10 %, VSS = DVSS = AVSS = 0.0 V)
Value
Min Max
Width for input
- ALL GPIO - - 17 ns −
removal
* Input pulse width less than at least 17nm is removed when Port noise filter is enabled.

S6J3350 Series
9.1.4.19 Power and Reset Sequence

VCC5 and VCC12 sequence
Value
Min Max
Wait time from LVDH1
level detection to falling tFV12 VCC12 - 0.6 - ms −
VCC12
VCC12 stabilization
tRV12 VCC12 - - 14.2 ms −
time during power-on
VCC5
VDLAT
tFV12
PSC_1
VOH7
tRV12
VCC12 VRDLBT+VRHYS
VRDLAT
RSTX No timing specification of VCC12 and RSTX
Note:
− VDLAT VRDLAT, VRDLBT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)".
VOH7 is referred to "9.1.3 DC Characteristics".
− LVDH1 reset need to be “always enable”. For details, see the Traveo™ Platform Hardware Manual.
− The above sequence needs not to be applied in the following cases the application enters PSS mode:
“VCC12 is controlled by PSC_1 at entry and exit from PSS mode”(Normal Sequence).

S6J3350 Series
Case1) "PSC_1 H --> L --> H transition by VCC5”
Note:
− RSTX controlled by VCC5.
− VCC12 and AVCC5 controlled by PSC_1.
− VCC53, VCC3, AVCC3_DAC and DVCC controlled by PSC_1. Can be controlled by VCC5 GPIO also.
− VDLAT, VDLBT and VHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)".
VRDLAT, VRDLBT and VRHYS are referred to “9.1.4.12 Low Voltage Detection (Internal Voltage)".
VOH7, VIL9 and VIH9 are referred to "9.1.3 DC Characteristics".
tRV12, tFV12RST and tRV12RST are referred to “9.1.4.19 Power and Reset Sequence".
*1: Battery Disconnect: All supplies fall together.
*2: VCC12 can be fully depleted or not full depleted.
*3: DVCC, VCC53 and VCC3 can start before or after VCC12.
*4: VCC5 is higher than level detection voltage: VDLAT+VHYS
VCC5 is lower than level detection voltage: VDLBT+VHYS
VDLAT, VDLBT and VHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)".
*5: VCC5 is higher than level detection voltage: VRDLAT+VRHYS
VCC5 is lower than level detection voltage: VRDLBT+VRHYS
VRDLAT, VRDLBT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)".

S6J3350 Series
Case2-1) "PSC_1 H --> L --> H transition by User Program”
VCC5 > VDLAT
VCC5
PSC_1
VCC12 VRDLAT VRDLAT+VRHYS
RSTX No timing specification of VCC12 and RSTX
PSC_1
Transition PSC_1=L VCC12=OFF
=H
VCC12=ON
Note:
− VCC12 controlled by PSC_1.
− VCC12 can be fully deplete

S6J3350 Series
Case2-2) "PSC_1 H --> L --> H transition by User Program”
Note:
− VCC12 and AVCC5 controlled by PSC_1.
− VCC53, VCC3, AVCC3_DAC and DVCC controlled by PSC_1. Can be controlled by VCC5 GPIO also.
*1: VCC12 can be fully depleted or not full depleted.

S6J3350 Series
VCC12 and RSTX Sequence

Value
Min Max
RSTX -> VCC12 fall VCC12,
tFV12RST 5 - us −
interval time RSTX
-
VCC12 -> RSTX rise VCC12,
tRV12RST 35 - us −
interval time RSTX
VCC5 > VDLAT *1
VCC5
H
PSC_1
tFV12RST tRV12RST
VRDLAT+VRHYS
VRDLAT
VCC12
VIL9 VIH9
RSTX
Note:
− If the sequence given in VCC5 and VCC12 sequence" cannot be applied, this sequence can be applied.
− VDLAT VRDLAT, VRDLAT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)".
VIL9 and VIH9 is referred to "9.1.3 DC Characteristics".
− This sequence is applied in case of VCC12 power on/off and assertion of RSTX is controlled by application.
− This sequence is applied under the condition VCC5 > VDLAT and PSC_1 = H.

S6J3350 Series
RSTX and MODE Sequence

(TA: Recommended operating conditions, Vcc5 = 5.0 V ± 10 % / 3.3 V ± 0.3V, VSS = 0.0 V)
Value
Min Max
RSTX↑ -> MODE↑ RSTX,
tMOD - -5 5 ns −
delay time MODE
Reset and mode input
10 - us −
time RSTX,
tRSTMDL -
Width for reset and MODE
1 - us −
mode input removal
0.7*VCC5
RSTX RSTX
MODE
tRSTMDL
0.7*VCC5
MODE
0.2*VCC5 0.2*VCC5
tMOD
Note:
− If the sequence given in "VCC5 and VCC12 sequence" and "VCC12 and RSTX Sequence" cannot be applied, this sequence
can be applied.
− Connect RSTX signal and MODE signal outside of the MCU and shorten the trace length between MCU and these two signal
lines.
− The following assumptions are made with regard to the workaround described above.
1. After the reset the MCU state is equivalent to the “cold start state” usually reached by power-on-reset.
2. Debugger interface and PC writer interface are not enabled.
3. The RAM retention cannot be guaranteed when applying this workaround
4. Pin PSC_1 will be driven low while RSTX is active (RSTX at low level)

S6J3350 Series
9.1.5 A/D Converter

9.1.5.1 Electrical Characteristics
(TA: Recommended operating conditions, VCC5 = 5.0 V ± 10 %, VCC12 = 1.15 V ± 0.06 V, VSS = AVSS = 0.0 V)
Conditions
Parameter Symbol Pin Name Unit Remarks
Min Typ Max
Resolution - - - - 12 bit −
*6
- - ±12 LSB − *3
Total Error - -
- - ±15 *7 LSB −
Integral Non linearity - - - - ±4.0 LSB − *4
Differential Non linearity - - - - ±1.9 LSB − *4
AVRL AVRL
- V
-11.5LSB *6 +12.5LSB *6
Zero transition voltage VZT AN0 to AN63
AVRL AVRL
- V − *5
-14.5LSB *7 +15.5LSB *7
AVRH AVRH
- V
-13.5LSB *6 +10.5LSB *6
Full-scale transition voltage VFST AN0 to AN63
AVRH AVRH
- V −
-16.5LSB *7 +13.5LSB *7
Sampling time tSMP - 0.3 - - µs − *1
Compare time tCMP - 0.8 - 26 µs − *1
A/D conversion time tCNV - 1. 1 - - µs − *1
Resumption Time - - - - 1 µs −
AN0 to AN30,
-1.0 - 1.0 µA
AN32 to AN38 AVSS≤
Analog port input current IAIN
AN31, − VAIN≤AVCC5
-2.0 - 2.0 µA
AN39 to AN63
Analog input voltage VAIN AN0 to AN63 AVRL - AVRH V −
4.5 *6 - 5.5 *6
AVRH AVRH5 V − AVcc5 ≥ AVRH
Reference voltage 3.0 *7 - 3.6 *7
AVRL AVRL5/AVSS - 0.0 - V −
IA - 500 900(Target) µA − 1unit

AVCC5
IAH - 1.0 200(Target) µA − *2
Power supply current - 1.0 3.5(Target) *6 mA − 1unit

IR
AVRH5 - 1.0 2.5(Target) *7 mA − 1unit
IRH - - 9.0(Target) µA − *2
Variation between channels - AN0 to AN63 - - 4.0 LSB −

*1: Time per channel
*2: Definition of the power supply current (when Vcc5 = AVcc5 = 5.0 V) while the A/D converter is not operating and in stop mode
*3: Total Error is a comprehensive static error that includes the linearity after trimming by software. 1LSB = (AVRH-AVRL)/4096
*4: 1LSB = (VFST-VZT)/4094
*5: 1LSB = (AVRH-AVRL)/4096
*7: For S6J335xxAx or S6J335xxBx or S6J335xxCx or S6J335xxDx or S6J335xxEx or S6J335xxFx or S6J335xxGx or
S6J335xxHx option.

S6J3350 Series
9.1.5.2 Notes on A/D converters
About the Output Impedance of an External Circuit for Analog Input

When the external impedance is too high, the analog voltage sampling time may become insufficient. In this case, we recommend
attaching a capacitor (about 0.1 µF) to an analog input pin.
Analog input circuit model
Comparator
R
C
Analog input
Sampling ON
R C
12-bit A/D 3.9 kiloohms (max) 11.0 pF (max) (4.5 V ≤ AVCC5 ≤ 5.5 V)
Note: Use the numerical values provided here simply as a guide.

S6J3350 Series
9.1.5.3 Glossary
Resolution: Analog change that can be identified by an A/D converter
Integral linearity error: Deviation of the straight line connecting the zero transition point ("0000 0000 0000" <--> "0000 0000 0001")
and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from actual conversion characteristics
includes zero transition error, full-scale transition error, and non linearity error.
Differential linearity error: Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB
Total error: Difference between the actual value and the theoretical value. The total error
Total error
FFF
FFE Actual conversion 1.5LSB

characteristics
{1 LSB (N - 1) + 0.5LSB}
FFD
Digital output
VNT
004
(Actually-measured
value)
003
Actual conversion
002 characteristics (measured value)
Ideal characteristics
001
0.5LSB
AVRL Analog input AVRH
VNT- {1 LSB × (N-1) + 0.5LSB}

Total error of digital output N = [LSB]
1LSB
AVRH - AVRL
1LSB(Ideal value) = [V]
4096
N: A/D converter digital output value.
VZT(Ideal value) = AVRL + 0.5LSB[V]
VFST(Ideal value) = AVRH - 1.5LSB[V]
VNT: Voltage at which the digital output changes from "(N – 1)" to "N".

S6J3350 Series
Integral linearity error Differential linearity error
FFF Ideal characteristics
FFE Actual conversion N+1 Actual conversion

characteristics characteristics
FFD {1 LSB (N - 1) + VZT}
VFST
Digital output
(measured
Digital output
N
value)
004 VNT
(measured value)
003 N-1
Actual conversion V(N+1)T
characteristics (measured
002 VNT(measured value)
value)
Ideal characteristics (measured value)
001 N-2
Actual conversion
VZT (measured value) characteristics
AVRL Analog input AVRH AVRL Analog input AVRH
VNT- {1 LSB × (N-1) + VZT}

Integral linearity error of digital output N = [LSB]
1LSB
V(N+1)T- VNT
Differential linearity error of digital output N = -1 LSB [LSB]
1LSB
VFST - VZT
1LSB = [V]
4094
VZT: Voltage for which digital output changes from "0x000" to "0x001"
VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF".

S6J3350 Series
9.1.6 FLASH Memory

9.1.6.1 Electrical Characteristics
Rating
Parameter Unit Remarks
Min Typ Max
Large sector*1
- 120 180 ms
Internal preprogramming time included
8kB sector*1
Sector erase time - 120 180 ms
4kB sector*2
- 120 180 ms
16bit write time(Program) - 30 60 µs System-level overhead time excluded*1
Page mode write time(Program) - 320 600 µs System-level overhead time excluded*1
32bit write time(Work) - 30 60 µs System-level overhead time excluded*2
Temperature at write/erase time
Erase count / 1,000/20
- - - Average temperature TA = +85 degrees
Data retention time(Program) years
Celsius
1,000/20
years
Data retention time(Work) years
Celsius
100,000/5
years
*1: Guaranteed value for up to 1,000 erases
9.1.6.2 Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc5) is prohibited.
In the application system where Vcc5 might be shut down while writing or erasing, be sure to turn the power off by using an
external voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL), hold Vcc5 at 2.7V or more within
the duration calculated by the following expression:
Td*1 [μs] + ( 1 / FCRF*2[MHz] ) x 1029 + 25 [μs]
*1: See "9.1.4.11 Low Voltage Detection (External Voltage)"
*2: See "9.1.4.1 Source Clock Timing"

S6J3350 Series
10. Acronyms
Acronym Description Acronym Description
A/D converter Analog digital converter LLPP Low latency peripheral port
ADC Analog digital converter LVD Low voltage detector
AHB Advanced high performance bus MCU Microcontroller unit
Advanced microcontroller bus MFS Multi-function serial interface
AMBATM
architecture NF Noise filter
APB Advanced peripheral bus NMI Non maskable interrupt
ATCM TCM-A port OCU Output compare unit
AXI Advanced extensible interface OSC Oscillator
B0TCM TCM B0 port PCM Pulse coded module
B1TCM TCM B1 port PLL Phase locked loop
BBU Bit banding unit PONR Power on reset
BDR Boot description record PPC Port pin configuration
BTL Bridge-tied load PSS Power saving state
CAN Control are network PWM Pulse width modulation
CD Clock domain RAM Random access memory
CPU Central processing unit RIC Resource input configuration
CR CR Oscillator ROM Read only memory
CRC Cyclic redundancy check RTC Real time clock
CSV Clock supervisor Low voltage detection and reset for
DAC Digital analog converter RVD
RAM retention
DAP Debug access port SCT Source clock timer
DED Dual error detection SEC Single error correction
DMA Direct memory access Single error correction and dual error
SECDED
DMAC DMA controller detection
EAM Exclusive access memory SHE Secure Hardware Extension
ECC Error correction code SMC Stepper motor controller
ETM Embedded trace macro SMIX Sound mixer
EXT-IRC External interrupt controller SRAM Static RAM
FIQ Fast interrupt request SWFG Sound waveform generator
FPU Floating point unit SW-WDT Software watchdog timer
FRT Free run timer SYSC System controller
GPIO General purpose I/O TCFLASH FLASH connected to TCM
HPM High performance matrix TCM Tightly coupled memory
HW-WDT Hardware watchdog timer TCRAM RAM connected to TCM
I/O Input or output TPU Timing protection unit
I2S Inter-IC sound UDC Up-down counter
ICU Input capture unit VIC Vectored interrupt controller
IPCU Inter-processor communication unit VRAM Video RAM
IRC Interrupt controller WDR Watchdog description record
IRQ Interrupt request WDT Watchdog timer
ISR Interrupt service routine WFG Waveform generator
JTAG Joint test action group WorkFLASH Work FLASH memory

S6J3350 Series
11. Ordering Information
Part Number *1 Package

S6J335EKSCSE2000A
S6J335EKSESE20000 208-pin plastic TEQFP(LEW208)
S6J335EKBESE20000
S6J335EJBESE20000 176-pin plastic TEQFP(LEV176)

S6J3350 Series
12. Errata
This section describes the errata for the S6J3350 Series. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
S6J335Dxxx
S6J335Exxx
S6J335 Qualification Status

Product Status: Production
Errata Summary
The following table defines the errata applicability to available S6J3350 Series devices.
Items Part Number Fix Status
S6J335Dxxx
MCAN wrong message transmission Not be planned.
S6J335Exxx
1. MCAN wrong message transmission

■ Problem Definition
There is a possibility a message with an ID (arbitration field) and a format and DLC (control field) is transmitted which was
not configured by the application. The message itself is syntactically correct and can be received by other nodes.
The occurrence of the limitation requires a certain relationship in time between a transmission request for sending a
message and the coincidence of noise in the 3rd bit of intermission field which is treated as the start of new message
transmission (SoF).
■ Trigger Condition
Under the following conditions a message with wrong ID, format and DLC is transmitted:
• M_CAN is in state "Receiver" (PSR.ACT = "10"), no pending transmission.
• A new transmission is requested after sample point of 2nd bit of intermission but before the 3rd bit of
Intermission is reached.
• The CAN bus is sampled dominant at the third bit of Intermission which is treated as SoF (see ISO11898-1:2015
Section 10.4.2.2).
■ Scope of Impact
Under the conditions listed above it may happen, that:
• The shift register is not loaded with ID, format, and DLC of the requested message.
• The M_CAN will start arbitration with wrong ID, format, and DLC.
• In case the ID won arbitration, a CAN message with valid CRC is transmitted.
• In case this message is acknowledged, the ID stored in the Tx Event FIFO is the ID of the requested Tx
message and not the ID of the message transmitted on the CAN bus
• Neither an error is detected by the transmitting node nor at the receiving node.

S6J3350 Series
■ Workaround
Workaround 1:
This workaround avoids submitting a transmission request in the critical time window of about one bit time before the sample
point of the 3rd bit of intermission field when on other pending transmission request exists:
• Request a new transmission if another transmission is already pending or when the M_CAN / M_TTCAN is not in
state "Receiver" (when PSR.ACT ≠ "10").
• If no pending transmission request exists, the application software needs to evaluate the Rx Interrupt flags
IR.DRX, IR.RF0N, IR.RF1N which are set at the last bit of EoF when a received and accepted message gets
valid.
• A new transmission may be requested by writing to TXBAR once the Rx interrupt occurred and the application
waited another 3 bit times before submitting its Tx request. Note the Rx interrupt is generated at the last bit of
EoF which is followed by three bits of Intermission.
• The application has to take care that the transmission request for the CAN Protocol Controller is activated before
the critical window of the following reception is reached.
A supplemental action can be applied in order to detect messages which contain wrong ID and control filed information:
• A checksum covering arbitration and control fields can be added to the data field of the message to be
transmitted, to detect frames transmitted with wrong arbitration and control fields.
Workaround 2:
This workaround ensures that always at least one pending Tx request exists. If that is the case, the application may launch
its Tx requests at any time without suffering from the limitation.
• Define a low priority message with DLC = 0 that can be sent without harm. E.g. loses arbitration against all other
application messages, does not pass any acceptance filter of nodes in the same network. DLC = 0 shall reduce
latency for other application messages.
• Configure sufficient Tx buffers – at least two - for this message type thus that there is always another one waiting
to be sent. E.g. an application that cannot react quickly enough with the time a single message of this type is
sent, more than 2 Tx buffer may become necessary.
• The application uses the standard interfaces of the CAN / CAN FD stack to feed these messages.
• Whenever Tx confirmation is indicated for the second but last message of this type with pending Tx request, the
application needs to submit at least one new Tx request. Note Tx confirmation is a standard feature in the
AUTOSAR SW architecture.
• Before initially leaving INIT state of the M_CAN IP by clearing CCCR.INIT bit, make sure to activate a Tx request
after having cleared CCCR.CCE. This will ensure that the conditions for the occurrence of the limitation when
synchronizing to the CAN bus the first time after RESET are prevented.
■ Fix Status
Not be planned.

S6J3350 Series
13. Appendix
13.1 Application 1: JTAG Tool Connection
This is an application example of JTAG tool connection. See the relevant application note 002-03898 in detail.

S6J3350 Series
14. Major Changes

Page Section Change Results
Rev.*A
7 2.Function List Revised Chip ID and Revision as below:
2.2Optional function Error)
Function Digit Revision Chip ID
S,U,T,V B 0x10120000
A,C,E,G B 0x1012A000
B,D,F,H B 0x10122000
Correct)
Function Digit Revision
S,U,T,V C 0x10122100
A,C,E,G C 0x10128100
B,D,F,H C 0x10120100
10 3.Product Revised 4 MHz to 16 MHz as below:
Description Error)
3.2Product −A wide range of 3.6 - 4 MHz is available for main oscillator
description
Correct)
−A wide range of 3.6 - 16 MHz is available for main oscillator
13 3. Product Added Note of a function as below:

Description Multi-Functional Serial (MFS)
3.2 Product
description Correct)
16 4.1 Pin Assignment Deleted 176Pin Function as below:

30 4.1.2 TEQFP-176 Error)
32 Pin Assignment 176Pin Function
PPG22_TOUT0_0, 70
38 P32, P38 PPG22_TOUT2_0, 71
6. Port Description PPG16/17/18/19/20/21_TIN1_0, 69
RX7_1, 174
6.1 Port description
TX7_1, 175
list
Correct)
176Pin Function
PPG22_TOUT0_0, -
PPG22_TOUT2_0, -
PPG16/17/18/19/20/21_TIN1_0, -
RX7_1, -
TX7_1, -
30 6. Port Description Deleted 144Pin Function as below:
6.1 Port description Error)
list 144Pin Function
RX7_1, 142
TX7_1, 143
Correct)
144Pin Function
RX7_1, -
TX7_1, -

S6J3350 Series

161 8.Precautions and Revised as below:
Handling Devices Error)
8.1.1Precautions for (1) Preventing Over-Voltage and Over-Current Conditions
Product Design Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try
to prevent such overvoltage or over-current conditions at the design stage.
Correct)
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device and in extreme cases leads to permanent damage of the device. Try
to prevent such overvoltage or over-current conditions at the design stage.
Handling Devices Error)
8.1.2Precautions for Surface Mount Type
Package Mounting
Correct)
Surface Mount Type
165 9.Electric Deleted Remarks comment as below:

Characteristics Error)
9.1.1 Absolute Supply voltage
Maximum Rating Operation assurance range, DVCC, Remarks “DVCC≤VCC5”
Correct)
Power supply voltage, DVCC, Remarks “”
165 8.2Handling Devices Added Note of a function as below:
Method to Switch off VCC12 during Power-off Sequence
During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering
PSS mode (power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs
to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain
below the operation assurance range.
165 9.Electric Added Note of a comment as below:

166 Characteristics Maximum clamp current, Total maximum clamp current
9.1.1 Absolute
Maximum Rating Correct)
*13 VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is
limited by a suitable external resistor, the ICLAMP rating supersedes the VI rating.
167 9.Electric Revised Warning of a comment as below:

9.1.1 Absolute Note:
Maximum Rating − Application of stress (e.g., voltage, current, temperature) exceeding the absolute maximum rating may cause
damage to the semiconductor device. Therefore, make sure that nothing exceeds the rating.
Correct)
WARNING:
− Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

S6J3350 Series

168 9.Electric Revised Rating Min Spec as below:
9.1.2Recommended Power supply voltage, VCC5 , Rating, Min, 2.6
Power supply voltage, VCC3 , Rating, Min, 2.6
operating condition
Correct)
168 9.Electric Added comment as below:
169 Characteristics Supply voltage Operation assurance range,VCC12, VCC12
9.1.2Recommended
operating condition Correct)
*5:When the voltage of Vcc12 is in the out of range against supply voltage operation assurance, the operation of
circuit which
Vcc12 used as the power source becomes unstable status. In that case, the value of each registers including
RESCAUSEUR
Register cannot be guaranteed, so these flags should don't care by software processing
168 9.Electric Revised device revision from B to C as below:
169 Characteristics Error)
221 9.1.2Recommended S6J335xxSB , S6J335xxUB, S6J335xxTB, S6J335xxVB,
241 operating condition S6J335xxBB, S6J335xxDB, S6J335xxFB, S6J335xxHB,
9.1.4.11Low Voltage S6J335xxAB, S6J335xxCB, S6J335xxEB, S6J335xxGB
Detection (External
Voltage) Correct)
9.1.5 A/D converter S6J335xxSC, S6J335xxUC, S6J335xxTC, S6J335xxVC,
S6J335xxBC, S6J335xxDC, S6J335xxFC, S6J335xxHC,
S6J335xxAC, S6J335xxCC, S6J335xxEC, S6J335xxGC
173 9.Electric Delete VOH25 Spec as below:
9.1.3 DC VOH25
characteristics
Correct)
Non
175 9.Electric Delete VOL25 Spec as below:

9.1.3 DC VOL25
characteristics
Correct)
Non

S6J3350 Series

186 9.Electric Revised as below:
9.1.4.5 Power-on Pin Value
Name
Conditions Min Typ Max
Power off time - VCC5 - 50 - - ms *2
VCC5:
Power ramp rate dV/dt VCC5 0.2V to - - 1 V/µs *3
2.6V
VCC5:
Undetected Between *4
|dV/dt| VCC5 - - 50 mV/µs
power ramp rate 2.4V and
4.5V
Correct)
Pin Value
Name Min Typ Max
Power off time - VCC5 - 100 - - μs *2
VCC5: *3
Power ramp rate dV/dt VCC5 - - 1 V/µs
1.5V to 2.6V
Maximum ramp VCC5:
rate guaranteed Between *4
|dV/dt| VCC5 - - 50 mV/µs
to not generate 2.4V and
power-on reset 4.5V

S6J3350 Series

9.1.4.5 Power-on *1: This specification is at 1V/μs of power ramp rate.
Conditions *2: VCC5 must be held below 0.2V for a minimum period of tOFF.
*4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is
between 2.4V and 4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is
suppressed. The power-on does not detect in any power fluctuation between 4.5V and 5.5V.
Notes:
When using S6J3350, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external
reset (RSTX) at power up and any brownout event.
tOFF
VCC
2.6V
0.2V 0.2V dV/dt
Correct)
*1: This specification is at 1V/μs of power ramp rate.
*2: VCC5 must be held below 1.5V for a minimum period of tOFF.
*4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is
between 2.4V and 4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is
suppressed. The power-on does not detect in any power fluctuation between 4.5V and 5.5V.
Notes:
When using S6J3350, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external
reset (RSTX) at power up and any brownout event.
tOFF
VCC
2.6V
1.5V 1.5V dV/dt

S6J3350 Series

221 9.Electric Revised Max of Low-voltage detection time as below:
Characteristics Low-voltage detection (external low-voltage detection)
9.1.4.11 Low Error)
Voltage Detection Low-voltage detection
Td - - - - 30 μs
time
(External Voltage)
Correct)
Low-voltage detection
Td - - - - 40 μs
time

Characteristics Low-voltage detection (1.15 V power supply low-voltage detection)
9.1.4.11 Low Error)
Voltage Detection Value
(External Voltage) Min Typ Max
Detection 0.784 0.8125 0.841 When

voltage power-supply
VRDLAT VCC12 *1 V voltage falls
(after trimming) Typ±3.5%
0.888 0.95 0.984
Correct)
Value
Min Typ Max
Detection When
voltage power-supply
VRDLAT VCC12 *1 0.7841 0.8125 0.8410 V voltage falls
(after trimming) Typ±3.5%

Characteristics Low-voltage detection (internal low-voltage detection for LVDL0)
9.1.4.12Low Voltage Error)
Detection (Internal Parameter Symbol
Pin
Conditions
Value
Unit Remarks
Name Min Typ Max
Voltage)
Supply voltage
VRDP5 - - 1.05 - 1.21 V
range
When power-
rises
Correct)
Pin Value
Name Min Typ Max
Supply voltage
VRDP5 - - 1.05 - 1.21 V
range
When power-
rises

S6J3350 Series

9.1.4.12Low Voltage Sym Pin Conditio Value
bol Name ns Min Typ Max
Detection (Internal
Supply voltage
Voltage) VRDP5 - - 1.05 - 1.21 V
range
When
power-
Detection *1
VRDL - 0.75 0.85 0.95 V supply
voltage
voltage
falls
When
power-
Hysteresis
VRHYS - - - 75 - mV supply
width
voltage
rises
Low-voltage
TRd - - - - 30 μs
detection time
*1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed
the detection voltage range, the detection may occur or be canceled after the supply voltage has
passed the detection voltage range.
Correct)
Value
Parameter Symbol Pin Name Conditions Unit
Min Typ Max
Supply voltage
VRDP5 - - 1.05 - 1.21 V
range
*1
Detection voltage VRDL - 0.75 0.85 0.95 V
Hysteresis width VRHYS - - - 75 - mV
Low-voltage
TRd - - - - 30 μs
detection time
*2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum
guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed
MCU operation voltage.
*3: After the brown-out event where the voltage level dips below the detection threshold for less
than this time, the detection may occur or be canceled.

S6J3350 Series

9.1.4.12Low Voltage Value
Min Typ Max
Detection (Internal
Supply voltage
Voltage) VRDP5 - - 1.05 - 1.21 V
range
Detection voltage *1
VRDLBT - 0.775 0.875 0.975 V
(before trimming)
VRDLAT - 0.844 0.875 0.906 V
(after trimming)
Low-voltage
TRd - - - - 30 μs
detection time
Correct)
Value
Min Typ Max
Supply voltage
VRDP5 - - 1.05 - 1.21 V
range
VRDLBT - 0.775 0.875 0.975 V
(before trimming)
VRDLAT - 0.844 0.875 0.906 V
(after trimming)
Low-voltage
TRd - - - - 30 μs
detection time

S6J3350 Series

9.1.4.15 DDR- (16-1) DDR-HSSPI Interface Timing (SDR mode)
HSSPI Value
Min Max
HSSPI clock cycle tcyc M_SCLK0 10 - ns
M_SCLK↑ ->
tspcnt - 0 tcyc ns
M_SDATA -> delayed
M_SDATA0_0-3
sample clock↑ tisdata 3.5 - ns
M_SDATA1_0-3
Input setup time
delayed sample clock↑ -
M_SDATA0_0-3 (CL = 20pF,
> M_SDATA tihdata 2.0 - ns
M_SDATA1_0-3 IOL=-10mA,
Input hold time
M_SCLK↑ -> M_SDATA M_SDATA0_0-3 IOH=10mA),
Output delay time toddata M_SDATA1_0-3 - 6.5 ns tcyc -3.5ns
Output hold time tohdata M_SDATA1_0-3 3.5 - ns
M_SCLK↑ -> M_SSEL
todsel M_SSEL0, 1 - 5.5 ns tcyc -4.5ns
Output delay time
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 4.5 - ns
Output hold time
Correct)
(1)DDR-HSSPI Interface Timing (SDR mode)
Value
Min Max
10 -
HSSPI clock cycle M_SCLK0 when Quad

tcyc ns
20 - Page
Program
M_SCLK↑ ->
tspcnt - 0 31.5 ns
M_SDATA ->
M_SDATA0_0-3
M_SLCK↑ tisdata *1 - ns
M_SDATA1_0-3
Input setup time
M_SCLK↑ -> (CL = 20pF,
M_SDATA0_0-3
M_SDATA tihdata *1 - ns
M_SDATA1_0-3 IOL=-10mA,
Input hold time
M_SCLK↑ -> IOH=10mA),
M_SDATA0_0-3
M_SDATA toddata - tcyc/2 + 2 ns
M_SDATA1_0-3
Output delay time
M_SCLK↑ ->
M_SDATA0_0-3
M_SDATA tohdata tcyc/2 - 3 - ns
M_SDATA1_0-3
Output hold time
-12.00+
M_SCLK↑ -> M_SSEL
todsel M_SSEL0, 1 (SS2CD+0.5)* - ns
Output delay time
tcyc
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 tcyc - 2 - ns
Output hold time

− For *1, the delay of the delay sample clock can be configured (DLP function)..

S6J3350 Series

9.1.4.15 DDR- (16-2) DDR-HSSPI Interface Timing (DDR mode)
HSSPI Value
Min Max
HSSPI clock cycle tcyc M_SCLK0 10 - ns
M_SCLK↑ ->
delayed sample clock↑ tspcnt 0 tcyc ns
M_SDATA -> delayed
M_SDATA0_0-3
sample clock↑ tisdata 1.0 - ns
M_SDATA1_0-3
Input setup time
M_SDATA0_0-3
-> M_SDATA tihdata 1.0 - ns
M_SDATA1_0-3 (CL = 20pF,
Input hold time
M_SCLK↑ -> IOL=-10mA,
M_SDATA0_0-3
M_SDATA toddata IOH=10mA), - 3.5 ns tcyc/2-1.5ns
M_SDATA1_0-3
Output delay time
M_SCLK↑ ->
M_SDATA0_0-3
M_SDATA tohdata 1.5 - ns
M_SDATA1_0-3
Output hold time
M_SCLK↑ -> M_SSEL
todsel M_SSEL0, 1 - 7.0 ns tcyc -3.0ns
Output delay time
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 3.0 - ns
Output hold time
Correct)
(2)DDR-HSSPI Interface Timing (DDR mode)
Value
Min Max
HSSPI clock cycle tcyc M_SCLK0 12.5 - ns
M_SCLK↑ ->
delayed sample clock↑ tspcnt 0 31.5 ns

Input setup time tisdata M_SDATA1_0-3 *1 - ns
M_SLCK↑ -> M_SDATA M_SDATA0_0-3

Input hold time tihdata M_SDATA1_0-3 *1 - ns
(CL = 20pF,
M_SCLK↑ -> M_SDATA M_SDATA0_0-3 IOL=-10mA, tcyc/4 +
Output delay time toddata M_SDATA1_0-3 - ns
IOH=10mA), 1.5
Output hold time tohdata M_SDATA1_0-3 Tcyc/4 - 1.0 - ns
M_SCLK↑ -> M_SSEL -15.75+

todsel M_SSEL0, 1 - ns
Output delay time
(SS2CD+0.5)*tcyc
M_SCLK↑ -> M_SSEL
tohsel M_SSEL0, 1 0.75*tcyc - 2.0 - ns
Output hold time

− For *1, the delay of the delay sample clock can be configured (DLP function)

S6J3350 Series

9.1.4.16 Hyper BUS (16-1) Hyper Bus Write Timing (HyperFlash)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 (CL = 20pF, 3.0 - ns
IOL=-10mA,
CK↓ -> CS↑ IOH=10mA),
tCSH M_CS#_1,2 0 - ns
Correct)
(1)Hyper Bus Write Timing (HyperFlash)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 tCKCYC -2.0 - ns
Chip Select setup time (CL = 20pF,
IOL=-10mA,
CK↓ -> CS↑ IOH=10mA),

9.1.4.16 Hyper BUS (16-2) Hyper Bus Write Timing (HyperRAM)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 3.0 - ns
(CL = 20pF,
CK↓ -> CS↑
tCSH M_CS#_1,2 IOL=-10mA, 0 - ns
IOH=10mA),
RWDS↓-> CK↓
tDMV M_RWDS 0 - ns
Data Mask Valid
Correct)
(2) Hyper Bus Write Timing (HyperRAM)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 tCKCYC - 2.0 - ns
(CL = 20pF,
CK↓ -> CS↑
tCSH M_CS#_1,2 IOL=-10mA, tCKCYC/2 - ns
IOH=10mA),
RWDS↓-> CK↓
tDMV M_RWDS 1 - ns
Data Mask Valid

S6J3350 Series

9.1.4.16 Hyper BUS (16-3) Hyper Bus Read Timing (HyperFlash)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 3.0 - ns
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Input setup time
CK↑↓ -> DQ
tIH M_DQ7-0 1.25 - ns
Input hold time
(CL = 20pF,
CK↓ -> CS↑ IOL=-10mA,
Chip select hold time IOH=10mA),
RDS↑↓> DQ (valid)
RDS transition to DQ tDSS M_DQ7-0 -0.8 +0.8 ns
valid
RDS↑↓> DQ (invalid)
RDS transition to DQ tDSH M_DQ7-0 -0.8 +0.8 ns
invalid
Correct)
(3) Hyper Bus Read Timing (HyperFlash)
Value
Min Max
CS↑↓ -> CK↑
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Setup time
CK↑↓ -> DQ
tIH M_DQ7-0 (CL = 20pF, 1.25 - ns
Hold time
IOL=-10mA,
CK↓ -> CS↑
tCSH M_CS#_1,2 IOH=10mA), tRDSCYC / 2 - ns
RDS↑↓> DQ
Setup time
RDS↑↓> DQ
Hold time

S6J3350 Series

9.1.4.16 Hyper BUS (16-4) Hyper Bus Read Timing (HyperRAM)
Value
Min Max
CS↑↓ -> CK↑
tCSS M_CS#_1,2 3.0 - ns
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Input setup time
CK↑↓ -> DQ
tIH M_DQ7-0 1.25 - ns
Input hold time
CK↓ -> CS↑
(CL = 20pF,
RWDS↑↓> DQ (valid) IOL=-10mA,
RWDS transition to DQ tDSS M_DQ7-0 IOH=10mA), -0.8 +0.8 ns
valid
RWDS transition to DQ tDSH M_DQ7-0 -0.8 +0.8 ns
invalid
CK↑ -> RWDS↑↓
tRIV M_RWDS - 6 ns
CK↑ -> RWDS(Hi-z)
tRIH M_RWDS 0 - ns
Correct)
(4) Hyper Bus Read Timing (HyperRAM)
Value
Min Max
CS↑↓ -> CK↑
DQ -> CK↑↓
tIS M_DQ7-0 1.25 - ns
Setup time
CK↑↓ -> DQ
tIH M_DQ7-0 1.25 - ns
Hold time
CK↓ -> CS↑
tCSH M_CS#_1,2 (CL = 20pF, tRDSCYC /2 - ns
IOL=-10mA,
RWDS↑↓> DQ (valid) IOH=10mA),
Setup time
Hold time
CK↑ -> RWDS↑↓
tRIV M_RWDS - 6 ns
CK↑ -> RWDS(Hi-z)
tRIH M_RWDS 0 - ns

238 Characteristics Error)
239 9.1.4.17 Ethernet (18-1) Ethernet Receive Timing
AVB (18-2) Ethernet Transmit Timing
(18-3) MDIO Timing
Correct)
(1)Ethernet Receive Timing
(2) Ethernet Transmit Timing
(3) MDIO Timing

S6J3350 Series

248 11.Ordering Revised part number as below:
Information Error)
Part number
S6J335EKSB*******
Correct)
Part number
S6J335EKSC*******
Rev.*B
13 3.Product Description Revised as below:
3.2 Product Error)
Description 12bit resolution, 2 unit
The description of the A/D converter function should be referred in the S6J3300 hardware manual. Though the
chapter of I/O port in Traveo™ Platform Hardware Manual describes another A/D converter function, do not refer
it.
Correct)
12bit resolution, 2 unit(Unit0 is possible to select channels 0-31. Unit1 is possible to select channels 32-63.)
The description of the A/D converter function should be referred in the S6J3300 hardware manual. Though the
chapter of I/O port in Traveo™ Platform Hardware Manual describes another A/D converter function, do not refer
it.
A/D Channel Control Register (ADC12Bn_CHCTRL0)[bit5:0] ANIN[5:0] : Analog Input Selection bits.
This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).
14 3.Product Description Revised as below:
3.2.Product description
Correct)
PSC (PSC_1) output is used for external 1.2V power supply module control and automatically switched with the
following condition.
"High": Request to supply VCC12
- "Power ON Reset" is released
Power Supply
- CPU wakes up from PSS shutdown mode
Control
"Low": Request to stop supplying VCC12
(PSC)
- CPU transfers from RUN mode to PSS shutdown mode.
For timing chart of output signals include PSC in detail, see the "S6J3300 hardware manual" and chapter "State
Transition"
21 4.Package and Pin Revised as below:

22 Assignment 4.2.3.TEQFP144
4.2.Package Error)
Dimensions Figure 4 6: TEQFP144
Figure 4 7: TEQFP144
The package dimension of TEQFP144 (0.4mm Pitch) is the provisional version.
Correct)
Figure 4 6: TEQFP144 (0.5mm Pitch)
Figure 4 7: TEQFP144 (0.4mm Pitch)
The package dimension of TEQFP144 (0.4mm Pitch) is the formal version.

S6J3350 Series

29 6.Port Description Revised the below:
30 6.1 Port Description Error)
ADC Analog [0 to 63] input pin
Correct)
ADC Unit0 [ch.0 to ch.31] input pin
ADC Unit1 [ch.32 to ch.63] input pin
161 8.Precautions and Revised the below:
Handling Devices Processing and Protection of Pins
8.1.1.Precautions for Error)
Product Design (1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such
overvoltage or over-current conditions at the design stage.
Correct)
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device and in extreme cases leads to permanent damage of the device. Try to prevent such
overvoltage or over-current conditions at the design stage.

Handling Devices
8.2.Handling Devices Correct)
Method to Switch Off VCC12 during Power-Off Sequence
During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode
(power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before
switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance
range.

S6J3350 Series

9.1.2 Recommended The detection/release threshold values of following LVD channels are potentially below supply range defined in
operating condition 9.1.2 Recommended operating condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)” and
“9.1.4.12 Low Voltage Detection (Internal Voltage)" for detection/release threshold values for these LVD
channels):
LVDL0
LVDL1
LVDL2
LVDH0
LVDH1
LVDH2
Correct)
The detection/release threshold values of following LVD channels are potentially below supply range defined in
9.1.2 Recommended operating condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)” and
“9.1.4.12 Low Voltage Detection (Internal Voltage)" for detection/release threshold values for these LVD
channels):
LVDL0
LVDL1
LVDL2
LVDH0
LVDH1
LVDH2
Detection voltage of the external low voltage detection reset (initial) is 2.6V±3.5%*2 *3 or 4.0V±3.5%*1.
This detection voltage level setting is below the minimum operation assurance voltage (2.7V *2 *3 or 4.0V*1) .
Between this detection voltage and the minimum operation assurance voltage,
MCU functions are not guaranteed except for the low voltage detector.
Note that although the detection level is below the minimum operation guarantee voltage,
the LVD reset factor flag is set as the voltage drops below the detection level.
9.1.4.1.Source clock Notes:
timing − The maximum/minimum values have been standardized with the main clock and PLL clock in use.
Correct)
Notes:
− The maximum/minimum values have been standardized with the main clock and PLL clock in use.
− Enough evaluation and adjustment are recommended using oscillator on your system board.

S6J3350 Series

9.1.4.3.Internal clock - Note that Ta=125 condition is not supported in this product type.
timing
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following
restrictions.
‐On the presumption that the modulation mode of SSCG_PLL is used with down spread,
‐This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
Correct)
- Note that Ta=125 condition is not supported in this product type.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following
restrictions.
‐On the presumption that the modulation mode of SSCG_PLL is used with down spread,
‐This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
‐"Unused" means a clock source which doesn’t have any supply destinations. Configure it as disable with
performing at the lower clock frequency than the described maximum.
185 9.Electric Added Oscillation clock frequency as below:

Characteristics
Correct)
9.1.4.3.internal clock
Internal Operation Clock Frequency
timing PLL Clock
Main
Multiplied Multiplied Multiplied Multiplied Multiplied Multiplied
Clock
by 1 by 2 by 15 by 30 by 40 by 60
4 2 4 8 … 60 120 160 240

Oscillation
clock 8 4 8 16 … 120 240
frequency
[MHz]
16 8 16 32 … 240

S6J3350 Series

9.1.4.6Multi-Function I2C timing (SMR:MD2-0=0b100)
Serial (TA: Recommended operating conditions, Vcc5=Vcc53=5.0 V ±10%, VCC12=1.15V ±0.06V, VSS=0.0 V)
Standard High-Speed
Mode Mode
Min Max Min Max
SCL0, SCL1, SCL4,

CL=50pF,
SCL clock frequency fSCL SCL8 to SCL12, 0 100 0 400 kHz
R=(Vp/IOL)*1
SCL16 to SCL17
Correct)
I2C timing (SMR:MD2-0=0b100)
(TA: Recommended operating conditions, Vcc5=Vcc53=5.0 V ±10%, VCC12=1.15V ±0.06V, VSS=0.0 V)
Standard Fast
Mode Mode
Min Max Min Max
SCL0, SCL1, SCL4,

CL=50pF,
SCL clock frequency fSCL SCL8 to SCL12, 0 100 0 400 kHz
R=(Vp/IOL)*1
SCL16 to SCL17
Error)
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the
Correct)
*3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the
222 9.Electric Added *5 and *5 sentences as below:
9.1.4.11.Low Voltage Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Typ Max
Detection (External
3.86 *3 4.0 *3 4.14 *3 When power-supply
Voltage) VCC5 *1 V voltage falls
Detection voltage 2.51 *4 2.6 *4 2.69 *4
VDLAT and detection level
(after trimming)
*1
is set initially
VCC3 2.51 2.6 2.69 V
Typ±3.5%
Correct)
Value
Min Typ Max
3.86 *3 4.0 *3 4.14 *3 When power-supply

VCC5 *1 V voltage falls
Detection voltage 2.51 *4 2.6 *4 2.69 *4
VDLAT and detection level
(after trimming)
*1
is set initially
VCC3 2.51 2.6 2.69 V
Typ±3.5% *5
*5: This detection voltage level setting is below the minimum operation assurance voltage (2.7V*4 or 4.0V*3) .

S6J3350 Series

Value
Unit Remarks
Min Typ Max
Detection (External
Voltage) When power-supply
Detection voltage
(after trimming)
Typ±3.5%
Correct)
Value
Min Typ Max
When power-supply
Detection voltage
(after trimming)
Typ±3.5% *2
*2: This detection voltage level setting is below the minimum operation assurance voltage .
Value
Unit Remarks
Min Typ Max
Detection (Internal
When power-supply
Voltage) Detection voltage
VRDLAT - *1 0.844 0.875 0.906 V voltage falls
(after trimming)
Typ±3.5%
Correct)
Value
Min Typ Max
When power-supply
Detection voltage
VRDLAT - *1 0.844 0.875 0.906 V voltage falls
(after trimming)
Typ±3.5% *2
Rev. *C
1 Features Error)
 General purpose I/O port : up to 146
Correct)
 General purpose I/O port : up to 148

S6J3350 Series

4 1.Overview Error)
1.2 Document Document
Document Type Definition Primary User
definition Code
Investigator
S6J3350 The function and its characteristics
and hardware 002-10634
Datasheet are specified quantitatively.
engineer
S6J3300 The function and its operation of Software
002-10185
hardware manual S6J3300 series are described. engineer
Traveo™ Platform The function and its operation of Software
002-07884
Hardware Manual CPU core platform are described. engineer
The reference software, sample Software and
Under
Application note application, the reference board hardware
consideration
design and so on are explained. engineer
Correct)
Document
Document Type Definition Primary User
Code
Investigator
S6J3350 The function and its characteristics
and hardware 002-10634
Datasheet are specified quantitatively.
engineer
S6J3300 The function and its operation of Software
002-10185
hardware manual S6J3300 series are described. engineer
Traveo™ Platform The function and its operation of Software
002-07884
Hardware Manual CPU core platform are described. engineer
002-04455
002-04446
The reference software, sample Software and 002-09716
Application note application, the reference board hardware 002-04452
design and so on are explained. engineer 002-04096
002-12061
002-02495

S6J3350 Series

5 2.Function List Error)
2.1 Product lineup
Function S6J3310 S6J3320 S6J3330 S6J3340 Remark
General
Option See 2.2.2
Purpose I/O
12bit-A/D
2 unit - 48 input ports (Max) See 2.2.2
converter
Correct)
Function S6J3310 S6J3320 S6J3330 S6J3340 Remark
General
Option See 2.2.3
Purpose I/O
12bit-A/D
2 unit - 48 input ports (Max) See 2.2.3
converter
7 2. Function List Error)

2.2.1 Basic option -
Correct)
Notes:
The main RAM size is configured as follows according to Digit.
E : TCRAM 128KB + System-RAM 384KB
D : TCRAM 128KB + System-RAM 256KB
C : TCRAM 128KB + System-RAM 128KB
B : TCRAM 64KB + System-RAM 128KB
8 2.Function List Error)

2.2.2 ID Function Digit Revision Chip ID JTAG ID
S,U,T,V C 0x10122100 0x1000B5CF
A,C,E,G C 0x10128100 0x1000B5CF
B,D,F,H C 0x10120100 0x1000B5CF
Correct)
S,U,T,V C 0x10122100 0x1000B5CF
D 0x10122200
A,C,E,G C 0x10128100
D 0x10128200
B,D,F,H C 0x10120100
D 0x10120200

S6J3350 Series

10 3.Product Description Error)
3.2 Product description Power Domain (PD)
The product series supports the power off control of PD1, PD2 (including PD3 and 5) and PD6.
Correct)
The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0,
PD4_1 and PD6.
19 4.Package and Pin Error)

Assignment -
4.2.1 TEQFP208 Correct)
Revised PKG figure.
Added PKG Code.
Assignment -
Revised PKG figure.
Added PKG Code.
22 Assignment -
Revised PKG figure.
Added PKG Code.
25 5.IO Circuit Type Error)
5.1. I/O Circuit Type Type N
Correct)
Type N

S6J3350 Series

167 9. Electric Error)
Characteristics Power consumption PD - 1500 mW
9.1.1 Absolute -40 105 oC PD≤2000mW
Maximum Rating Operating temperature TA
-40 125 oC PD≤1200mW
Correct)
- 2000 mW -40oC≤TA≤105oC
Power consumption PD
- 1100 mW -40oC≤TA≤125oC
-40 105 oC PD≤2000mW
Operating temperature TA
-40 125 oC PD≤1100mW
Characteristics TA - -40 105 oC PD≤2000mW
Operating temperature
9.1.2 TA - -40 125 oC PD≤1200mW
Recommended
operating condition Correct)
TA - -40 105 oC PD≤2000mW
Operating temperature
TA - -40 125 oC PD≤1100mW
169 9.Electric Error)

Characteristics S6J335xxSC, S6J335xxUC, S6J335xxTC, S6J335xxVC,
9.1.2Recommended S6J335xxBC, S6J335xxDC, S6J335xxFC, S6J335xxHC,
operating condition S6J335xxAC, S6J335xxCC, S6J335xxEC, S6J335xxGC
Correct)
S6J335xxSx, S6J335xxUx, S6J335xxTx, S6J335xxVx,
S6J335xxBx, S6J335xxDx, S6J335xxFx, S6J335xxHx,
S6J335xxAx, S6J335xxCx, S6J335xxEx, S6J335xxGx

S6J3350 Series

Characteristics LVDL0
9.1.2 LVDL1
Recommended LVDL2
operating condition LVDH0
LVDH1
LVDH2
Detection voltage of the external low voltage detection reset (initial) is 2.6V±3.5%*2 *3 or
4.0V±3.5%*1.
This detection voltage level setting is below the minimum operation assurance voltage (2.7V*2 *3 or
4.0V*1) .
Note that although the detection level is below the minimum operation guarantee voltage, the LVD
reset factor flag is set as the voltage drops below the detection level.
Correct)
LVDL0
LVDL1
LVDL2
LVDH0
LVDH1
LVDH2
When it is used outside recommended range (this is the range of guaranteed operation), contact
your sales representative.
The initial detection voltage of the external low voltage detection is 2.6V±3.5% or 4.0V±3.5%.
This LVD setting and internal LVD (LVDL0/LVDL1) cannot be used to reliably generate a reset
before voltage dips below
minimum guaranteed MCU operation voltage, as these detection levels are below the minimum
guaranteed MCU operation
voltage.

S6J3350 Series

179 Characteristics TA=25C. Power only supplies to
9.1.3 DC Backup RAM and system
- 370 810 µA
controllers. When using 4MHz
characteristics
crystal for main oscillator.
ICCT5 Timer mode TA=25C. Power only supplies to
Backup RAM and system
VCC5
- 360 780 µA controllers. When shutting down
16kB Backup RAM and using
4MHz crystal for main oscillator.
TA=25C. Power only supplies to
ICCH5 Stop mode - 100 400 µA Backup RAM and system
controllers.
Correct)
TA=25C. 4MHz crystal for main
oscillator
- 370 810 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
oscillator.
- 360 780 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
oscillator
- 450 890 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
Timer
ICCT5 VCC5 oscillator.
mode - 440 860 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
TA=25C. 32kHz crystal for sub
oscillator
- 110 430 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
oscillator.
- 100 400 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
TA=25C.
- 100 400 µA PD1=ON, PD4_0=ON,
PD4_1=ON
TA=25C.
ICCH5 VCC5 Stop mode
- 90 370 µA PD1=ON, PD4_0=ON or
PD4_1=ON
TA=25C.
- 80 340 µA
PD1=ON

S6J3350 Series

Characteristics Power off time VCC5 - 100 - - μs *2
9.1.4.5 Power-on
Conditions Correct)
Power off time tOFF VCC5 - 100 - - μs *2
223 9.Electric Error)

248 Characteristics S6J335xxSC, S6J335xxUC, S6J335xxTC, S6J335xxVC,
9.1.4.11Low Voltage S6J335xxAC, S6J335xxBC, S6J335xxCC, S6J335xxDC,
Detection (External S6J335xxEC, S6J335xxFC, S6J335xxGC, S6J335xxHC
Voltage) Correct)
9.1.5 A/D converter S6J335xxSx, S6J335xxUx, S6J335xxTx, S6J335xxVx,
S6J335xxAx, S6J335xxBx, S6J335xxCx, S6J335xxDx,
S6J335xxGx, S6J335xxFx, S6J335xxGx, S6J335xxHx

S6J3350 Series

223 9. Electric Low-voltage detection (external low-voltage detection)
9.1.4.11 Low Pin Value
Voltage Detection Name Min Typ Max
(External Voltage) Supply 3.5 *3 - 5.5 *3
voltage VDP5 VCC5 - V
range 2.7 *4 - 3.6 *4
3.6 *3 4.0 *3 4.4 *3 When power-

Detection
VCC5 *1
V supply voltage
voltage *4 *4 *4
VDLBT 2.3 2.6 2.9 falls and
(before
detection level is
trimming) VCC3 *1
2.3 2. 6 2.9 V set initially
When power-
3.86 *3 4.0 *3 4.14 *3
Detection *1
supply voltage
VCC5 V
voltage falls and
VDLAT 2.51 *4 2.6 *4 2.69 *4
(after detection level is
trimming) *1
set initially
VCC3 2.51 2.6 2.69 V
Typ±3.5% *5
*5: This detection voltage level setting is below the minimum operation assurance voltage (2.7V*4
or 4.0V*3) .Between this detection voltage and the minimum operation assurance voltage,
Correct)
Pin Value
Name Min Typ Max
Supply 3.5 *3 - 5.5 *3
VDP5 VCC5 - V
*4
voltage 2.7 - 3.6 *4
range VDP3 VCC3 - 2.7 - 3.6 V
*1
3.6 *3
4.0 *3
4.4 *3 When power-
Detection
voltage *1 *5
VDLBT 2.3 *4 2.6 *4 2.9 *4 falls and
(before
detection level
trimming) VCC3 *1 *5
2.3 2. 6 2.9 V
is set initially
*1
When power-
3.86 *3 4.0 *3 4.14 *3
Detection supply voltage
VCC5 V
voltage *1 *5 *4 *4 *4
falls and
VDLAT 2.51 2.6 2.69
(after detection level
trimming) *1 *5
is set initially
VCC3 2.51 2.6 2.69 V
Typ±3.5%
*5: These LVD settings cannot be used to reliably generate a reset before voltage dips below
guaranteed MCU operation voltage(2.7V).

S6J3350 Series

224 9. Electric Low-voltage detection (1.15 V power supply low-voltage detection)
(External Voltage) Supply
voltage VRDP12 VCC12 - 1.09 - 1.21 V
range
Detection
When power-
voltage *1
(before
falls
trimming)
Detection When power-

voltage *1
supply voltage
VRDLAT VCC12 0.7841 0.8125 0.841 V
(after falls
trimming) Typ±3.5% *2
Correct)
Pin Value
Name Min Typ Max
Supply
voltage VRDP12 VCC12 - 1.09 - 1.21 V
range
Detection
When power-
voltage *1 *2
(before
falls
trimming)

voltage *1 *2
supply voltage
VRDLAT VCC12 0.7841 0.8125 0.841 V
(after falls
trimming) Typ±3.5%
*2: These LVD settings cannot be used to reliably generate a reset before voltage dips below
guaranteed MCU operation voltage (1.09V).

S6J3350 Series

225 9. Electric Low-voltage detection (internal low-voltage detection for LVDL1)
(Internal Voltage) Supply
voltage VRDP5 - - 1.05 - 1.21 V
range
When power-
Detection *1
voltage
falls *3
When power-
Detection *1
supply voltage
VRDLAT - 0.844 0.875 0.906 V
voltage falls
Typ±3.5% *2 *3
When power-
Hysteresis
VRHYS - - - 75 - mV supply voltage
width
rises
Low-
voltage
TRd - - - - 30 μs *4
detection
time

S6J3350 Series

Correct)
Value
Pin
Name
Min Typ Max
Supply
voltage VRDP5 - - 1.05 - 1.21 V
range
Detection
When power-
voltage *1 *2
(before
falls
trimming)

voltage *1 *2
supply voltage
VRDLAT - 0.844 0.875 0.906 V
(after falls
trimming) Typ±3.5%
When power-
Hysteresis
VRHYS - - - 75 - mV supply voltage
width
rises
Low-
voltage
TRd - - - - 30 μs *3
detection
time
245 Characteristics -
246 9.1.4.19 Power Correct)
247 and Reset Newly added
Sequence
255 11. Ordering Error)
Information Part Number Package
208-pin plastic TEQFP
S6J335EKSC*******
(TEQFP208)
Correct)
208-pin plastic TEQFP
S6J335EKSx*******
(LEW208)
*1: x is selected from the following parameter.
x : C, D (Revision)

S6J3350 Series

Rev. *D
6 2. Function List CAN-FD RAM (ECC supported)
2.1 Function list Error)
16KB/ch
It equivalents to 128 message buffer per channel of CCAN module
Correct)
16KB/ch
It equivalents to 128 message buffer per channel of MCAN module
2.2.1 Basic option Flash RAM
Digit
E 4,160KB 112KB 512KB 16+16KB
D 3,136KB 112KB 384KB 16+16KB
C 2,112KB 112KB 256KB 16+16KB
B 1,600KB 112KB 192KB 16+16KB
Correct)
Flash RAM
Digit
E 4,160KB 112KB 512KB 16+16KB
D 3,136KB 112KB 384KB 16+16KB

2.2.1 Basic option Notes:
C : TCRAM 128KB + System-RAM 128KB
B : TCRAM 64KB + System-RAM 128KB
Correct)
Notes:
12 3. Product Error)
Description Power Supply 3V external power supply should be controlled by GPIO.
3.2 Product Correct)
description Power Supply 3V external power supply could be controlled by GPIO.
47 7. Port configuration Error)

7.1 Resource Input -
Configuration Correct)
Module The Resource which are available through only one port does not have the multiplexer implemented
i.e. No RIC_RESIN register.

S6J3350 Series

Characteristics VCC12≤ VCC53
9.1.1 Absolute VCC12≤ VCC3
Power supply voltage*1, *2 VCC12 VSS-0.3 VSS+1.8 V VCC12≤ DVCC
Maximum Rating
VCC12≤ AVCC5
Correct)
Power supply voltage*1, *2 VCC12 VSS-0.3 VSS+1.8 V VCC12≤ AVCC5
Characteristics Total maximum clamp current Σ|ICLAMP | - 50 mA SPECIAL SPEC*A
9.1.1 Absolute
*B
*C
Characteristics -
9.1.1 Absolute Correct)
Maximum Rating
oC/W TEQFP
Theta j-a1 - 17
208
The minimum value
depends on the
oC/W TEQFP system specification
Theta j-a2 - 19
176 of heat radiation. The
System
TEQFP described value is
Thermal
144 estimated under the
Resistance Theta j-a3 - 20 oC/W
(0.5mm condition which is
Pitch) specified at “9.1.2
TEQFP Recommended
144 operating condition”.
oC/W
Theta j-a4 - 22
(0.4mm
Pitch)
oC/W
Package oC/W
Thermal oC/W
Psi j-t3 - 2.0 TEQFP144 (0.5mm Pitch)
Resistance oC/W
Psi j-t4 - 2.0 TEQFP144 (0.4mm Pitch)
171 9. 1 Electric Correct)
Characteristics Newly added
*B Relevant pins: All general-purpose ports and analog input pins
*C Relevant pins: All general-purpose ports and analog input pins

S6J3350 Series

Characteristics − In the case of use in VCC5 = AVCC5 = DVCC of conditions, please launch the power supply in
9.1.2 the following sequence.
Recommended Required power supply sequence is the following:
operating condition VCC5 -> [DVCC or VCC53 or AVCC5 or VCC3] -> VCC12
Note that power supplies inside "[ ]" can be turned on in arbitrary order.
Corresponding Part number is S6J335xxSC or S6J335xxUC or S6J335xxTC or S6J335xxVC or
S6J335xxBC or S6J335xxDC or S6J335xxFC or S6J335xxHC.
− In the case of use in VCC5 = AVCC5 < DVCC of conditions, please launch the power supply in
the following sequence.
Required power supply sequence is the following:
VCC5 -> DVCC -> [VCC53 or AVCC5 or VCC3] -> VCC12.
Note that power supplies inside "[ ]" can be turned on in arbitrary order.
Corresponding Part number is S6J335xxAC or S6J335xxCC or S6J335xxEC or S6J335xxGC.
Correct)
- Required power supply sequence is the following:
{VCC5 -> AVCC5} -> [DVCC, VCC12, VCC3, AVCC3_DAC]
Note that power supplies inside "[ ]" can be turned on in arbitrary order and "{ }" can be turned on in
shown sequence or simultaneously.

Characteristics -
9.1.2 Correct)
Recommended Note:
operating condition −TA: Ambient temperature (JEDEC)
−TC: Case temperature (JEDEC), the maximum measured temperature of package case top.
−Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature.
−The following condition should be satisfied in order to facilitate heat dissipation.
1. Four or more layers PCB should be used.
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or
more. (JEDEC standard)
3. One layer of middle layers at least should be used for dedicated layer to radiate heat with
residual copper rate 90% or more. The layer can be used for system ground.
4. 35% or more of the die stage area which is exposed at back surface of package should be
soldered to a part of 1st layer.
5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10
thermal via holes.
Example thermal via holes on PCB
<Figure>
− The above figure is a schematic diagram showing PCB in section.

− Thermal via holes should closely be placed and aligned with lands.
− It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer
bellow the MCU) as thermal heat sink.

S6J3350 Series

Characteristics Value
Pin
9.1.3 DC Paramet Symb Conditio
Nam Unit Remarks
er ol ns
characteristics e Min Typ Max
TA=-40 ~ 105C
CPU:240MHz,
100
- 500 mA HPM:120MHz
0
Normal (CPU:200MHz,
operation HPM:200MHz)
TA=-40 ~125C
- 550 950 mA CPU:180MHz,
HPM:90MHz,
ICC12
Power TA=-40 ~ 105C
VCC
supply CPU:240MHz,
12 105
current - 550 mA HPM:120MHz
Flash 0
(CPU:200MHz,
write/era
HPM:200MHz)
se
TA=-40 ~ 125C
100
- 600 mA CPU:180MHz,
0
HPM:90MHz,
Timer/
ICCH12 Stop - - 650 mA
Mode
Correct)
Value
Pin
Name
Min Typ Max
TA=-40 ~ 105C
CPU:240MHz,
- 320 800 mA HPM:120MHz
Normal (CPU:200MHz,
TA=-40 ~125C
- 220 690 mA CPU:180MHz,
HPM:90MHz,
Power ICC12
TA=-40 ~ 105C
supply VCC12
CPU:240MHz,
current
- 350 850 mA HPM:120MHz
Flash (CPU:200MHz,
write/erase HPM:200MHz)
TA=-40 ~ 125C
- 250 740 mA CPU:180MHz,
HPM:90MHz,
Timer/ Stop
ICCH12 - - 430 mA
Mode
251 9.1.4.19 Power and Correct)
Reset Sequence Newly added
Case-1, Case2-1 and Case2-2

S6J3350 Series

Characteristics Rating
Min Typ Max*3
9.1.6.1 Electrical
Large sector*1
Characteristics - 120 480 ms Internal preprogramming time
included
8kB sector*1
Sector erase time - 120 480 ms Internal preprogramming time
included
4kB sector*1
- 120 480 ms Internal preprogramming time
included
16bit write System-level overhead time
- 30 384 µs
time(Program) excluded*1
- 30 384 µs
- 30 384 µs
256bit write 512 System-level overhead time
- 40 µs
Page mode write 4096 System-level overhead time
- 320 µs
384 System-level overhead time
32bit write time(Work) - 30 µs
excluded*1
Correct)
Rating
Min Typ Max*3
Large sector*1
included
8kB sector*1
Sector erase time - 120 180 ms Internal preprogramming time
included
4kB sector*1
included
- 30 60 µs
- 30 60 µs
- 30 60 µs
256bit write 70 System-level overhead time
- 40 µs
Page mode write 600 System-level overhead time
- 320 µs
60 System-level overhead time
32bit write time(Work) - 30 µs
excluded*1
262 12. Appendix Error)
12.1 Application 1: -
JTAG tool Correct)
connection Newly added this section

S6J3350 Series

Rev. *E
4 1. Overview Error)
1.2 Document Table 1-1
Definition
Correct)
Table 1-1: Document Definition
2.1 Function List Table 2-1
Correct)
Table 2-1: Function Lineup
2.2.1 Basic option Figure 2-1
Correct)
Figure 2-1: Option and Part Number for S6J3350 Series
2.2.1 Basic option Revision: Revision version
Correct)
Revision:
Digit Description
Fixed Operation frequency of embedded Program Flash and CPU,
C
Fixed Stabilization time for sub oscillator
D Fixed TCFLASH Sector Write Permission and Data Retention after Reset
E Leakage current improvement
2.2.3 Restriction Table 2-2
Correct)
Table 2-2: Pin Restriction
10 3. Product Error)
Description Table 3-1
3.2 Product
Description Correct)
Table 3-1: Product Features
16 4. Package and Pin Error)
Assignment Figure 4-1: TEQFP-208
4.1.1 TEQFP-208
Pin Assignment Correct)
Figure 4-1: TEQFP-208 (S6J335xKyz *1)
*1: x, y ,z are selected from the following parameter.

x : E, D (Memory Size)
y : S, A, B, U, C, D, T, E, F, V, G, H (Option)
z : C, D, E (Revision)

S6J3350 Series

4.1.2 TEQFP-176
Figure 4-2: TEQFP-176 (S6J335xJyz *1)

Assignment -
4.1.2 TEQFP-176
Figure 4-2:
Revised Pin Assignment figure
4.1.3 TEQFP-144
Figure 4-3: TEQFP-144 (S6J335xHyz *1)


S6J3350 Series

9.1.3 DC Paramete Symb Pin Condition
Unit Remarks
r ol Name s
characteristics Min Typ Max
TA=-40 ~ 105C
CPU:240MHz, HPM:120MHz
- 320 800 mA
Normal (CPU:200MHz,
TA=-40 ~125C
- 220 690 mA
CPU:180MHz, HPM:90MHz,
ICC12
TA=-40 ~ 105C
VCC1
2 - 350 850 mA
Flash (CPU:200MHz,
TA=-40 ~ 125C
- 250 740 mA
Timer/
Mode
Normal
- 45 85 mA
operation
ICC5
Flash
- - 100 mA
write/erase
TA=25C. 4MHz crystal for
main oscillator.
- 370 810 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
Power main oscillator.
- 360 780 µA
supply PD1=ON, PD4_0=ON or
current PD4_1=ON
PD1=ON
main oscillator
- 450 890 µA
PD1=ON, PD4_0=ON,
VCC5 PD4_1=ON
Timer TA=25C. 8MHz crystal for
ICCT5
mode main oscillator.
- 440 860 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
TA=25C. 32kHz crystal for
sub oscillator
- 110 430 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
sub oscillator.
- 100 400 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON

S6J3350 Series

182 9. Electric Correct)
9.1.3 DC Paramete Symb Pin Condition
Unit Remarks
r ol Name s
characteristics Min Typ Max
TA=-40 ~ 105C
- 315 775 mA
Normal (CPU:200MHz,
TA=-40 ~125C
- 210 665 mA
ICC12
TA=-40 ~ 105C
VCC1
2 - 320 780 mA
Flash (CPU:200MHz,
TA=-40 ~ 125C
- 215 670 mA
Timer/
Mode
Normal
- 25 45 mA
operation
ICC5
Flash
- - 60 mA
write/erase
main oscillator.
- 370 810 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
Power main oscillator.
- 360 780 µA
supply PD1=ON, PD4_0=ON or
current PD4_1=ON
PD1=ON
main oscillator
- 450 890 µA
PD1=ON, PD4_0=ON,
VCC5 PD4_1=ON
Timer TA=25C. 8MHz crystal for
ICCT5
mode main oscillator.
- 440 860 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
sub oscillator
- 110 430 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
sub oscillator.
- 100 400 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON

S6J3350 Series

Characteristics -
9.1.3 DC
characteristics Correct)
Value
Paramete Symbo Pin Condition
Unit Remarks
r l Name s
Min Typ Max

main oscillator
- 345 630 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
main oscillator.
- 340 625 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
main oscillator
- 420 705 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
Timer
ICCT5 main oscillator.
mode - 415 700 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
Power TA=25C. 8MHz crystal for
supply VCC5 - 410 695 µA main oscillator.
current * PD1=ON
sub oscillator
- 80 135 µA
PD1=ON, PD4_0=ON,
PD4_1=ON
sub oscillator.
- 75 130 µA
PD1=ON, PD4_0=ON or
PD4_1=ON
PD1=ON
TA=25C.
- 75 130 µA PD1=ON, PD4_0=ON,
PD4_1=ON
ICCH5 Stop mode TA=25C.
- 70 125 µA PD1=ON, PD4_0=ON or
PD4_1=ON
- 65 120 µA TA=25C.
PD1=ON
* Electric Characteristics for S6J335xxxE.
262 11. Ordering Error)
Information x : C,D (Revision)
Correct)
X : C,D, E (Revision)
Rev. *F

S6J3350 Series

5 2: Function List Function: CRC
2.1. Function List Error)
1 unit
Correct)
4 units
6 2: Function List Function: DDR HSSPI
2.1. Function List Error)
2 ch
Correct)
1 ch
2.2.2 ID Function Digit Revision Chip ID JTAG ID
S,U,T,V C 0x10122100 0x1000B5CF
D 0x10122200
A,C,E,G C 0x10128100
D 0x10128200
B,D,F,H C 0x10120100
D 0x10120200
Correct)
S,U,T,V C 0x10122100 0x1000B5CF
D, E 0x10122200
A,C,E,G C 0x10128100
D, E 0x10128200
B,D,F,H C 0x10120100
D, E, 0x10120200
10 3: Product Description Feature: Clock
3.2. Product Error)
Description -
Correct)
Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value)
10 3: Product Description Error)
3.2. Product -
Description
Correct)
Feature: Embedded CR oscillation
− 0.35 ms to 0.8 ms for 4 MHz (Fast clock)
− 0.43 ms to 1.28 ms for 100 kHz (Slow clock)

S6J3350 Series

10 3: Product Description Feature: Reset
3.2. Product Error)
Based on Cortex R5F platform
Description
− INITX
− SRSTX
Correct)
RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)
− Occurrence factor: Simultaneously inputting “L” level to RSTX pin and inputting “L” level to MD pin
− Release factor: Inputting “H” level to RSTX pin
− SRSTX (and nSRST pin)
The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR
has no effect.
11 3: Product Description Feature: PLL / SSCG PLL
3.2. Product Error)
Description Down spread mode is only supported and available.
Correct)
Product supports down spread and center spread modes with the conditions defined in 9.1.4.3 "Internal Clock
Timing".
12 3: Product Description Feature: Embedded Program/Work Flash Memory
3.2. Product Error)
Description Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.
7-wait-cycle: 80MHz or less.
Correct)
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.
12 3: Product Description Feature: Security
3.2. Product Error)
Description Chip erase function is available for flash memory.
The function of "MK_CEER" is not supported. (MK_CEER = not selectable)
For details, see the platform manual and chapter "Security"
Correct)
-

S6J3350 Series

13 3: Product Description Feature: Multi-Functional Serial (MFS)
3.2. Product Error)
Description Some ports of MFS have the dedicated I/O for I2C.
See Port description list in detail.
When the voltage supply of I2C interface is 5.0 V, it cannot use the I/O cells of 3.3 V voltage supply for the I2C
terminal.
Correct)
Only 2 ports of MFS have the dedicated I/O for I2C.
See I2C timing in 9.1.4.6 Multi-Function Serial in detail.
The I2C is not designed to be hot swappable.
13 3: Product Description Feature: Hyper BUS I/F
3.2. Product Error)
Description The following register is not supported and cannot be used.
− Interrupt Status Register (HYPERBUSIn_ISR)
Correct)
The following register is not supported and cannot be used.
− Interrupt Enable Register (HYPERBUSIn_IEN)
− Interrupt Status Register (HYPERBUSIn_ISR)

S6J3350 Series

Characteristics Rating
Min Typ Max*3
9.1.6.1 Electrical
Large sector*1
Characteristics - 120 180 ms
8kB sector*1
4kB sector*1
- 120 180 ms

Data retention time(Program)*3 years
Celsius
1,000/20
years
Data retention time(Work)*3 years
Celsius
100,000/5
years
*3: Target Value
Correct)
Rating
Min Typ Max
*1
Large sector
- 120 180 ms
8kB sector*1
4kB sector*2
- 120 180 ms

Data retention time(Program) years
Celsius
1,000/20
years
Data retention time(Work) years
Celsius
100,000/5
years

S6J3350 Series

Rev. *G
176 9. Electric Added the Hysteresis voltage as below.
Characteristics
9. 1.3 DC Correct)
Min Typ Max
P0_00 to
CMOS hysteresis
P0_20, 0.05×V
VHYS1 input level is - - V
P2_09 to CC53
selected
P2_19,
P3_00 to
P3_07,
P3_24 to Automotive
0.03×V
VHYS2 P3_31, input level is - - V
CC53
P4_00 to selected
P4_07 TTL
VHYS3 input level is - 0.035 - V
selected
P1_03 to CMOS hysteresis
0.05×V
CC5
P3_08 to selected
P3_23, Automotive
0.03×V
VHYS5 P4_08 to input level is - - V
CC5
P4_23 selected
P1_09,
TTL
P1_10,
Hysteresis P1_15,
selected
voltage P1_16
P1_17 to CMOS hysteresis
0.05×D
VCC
P2_00 to selected
P2_08, Automotive
0.03×D
VHYS8 P4_24 to input level is - - V
VCC
P4_31 selected
RSTX 0.05×V
VHYS9 - - - V
NMIX CC5
0.05×V
VHYS10 MD - - - V
CC5
JTAG_NTRS
T
VHYS11 JTAG_TCK - - 0.035 - V
JTAG_TDI
JTAG_TMS
P0_21 to
CMOS hysteresis
P0_31, 0.05×V
VHYS12 input level is - - V
P1_00 to CC3
selected
P1_02
TTL
P0_21 to
P0_31
selected

S6J3350 Series

Rev. *H
4 1. Overview Added the Document Definition as below.
1.2 Document
Definition Error)
The function and its
Investigator and
S6J3350 Datasheet characteristics are specified 002-10634
hardware engineer
quantitatively.
The function and its operation
S6J3300 Hardware
of S6J3300 series are Software engineer 002-10185
Manual
described.
Traveo™ Platform
of CPU core platform are Software engineer 002-07884
Hardware Manual
described.
Correct)
This document.
The function and its Investigator and

S6J3350 Datasheet 002-10634
characteristics are specified hardware engineer
quantitatively.
S6J3300 Series 32-bit
Microcontroller Traveo™
Family Hardware Manual
S6J3300 Hardware
Software engineer 002-10185
Manual The function and its operation
of S6J3300 series are
described.
32-Bit Microcontroller
Traveo™ Family S6J33xx,
S6J34xx, S6J35xx Series
Hardware Manual Platform
Traveo™ Platform Part
Software engineer 002-07884
Hardware Manual
of CPU core platform are
described.
14 3: Product Description Deleted as below

3.2. Product
Description -Note: The description of the preliminary documentation will be changed without any notification.

S6J3350 Series

188 9. Electric Added the *4 in “Remarks” column
Characteristics
9.1.4.3 Internal Clock Error)
Timing SSCG0 output clock
SSCG1 output clock
SSCG2 output clock
SSCG3 output clock
PLL0 output clock
PLL1 output clock
PLL2 output clock
PLL3 output clock
Correct)
SSCG0 output clock *4
PLL0 output clock *4
189 9. Electric Added the below *4 sentence.

Characteristics
9.1.4.3 Internal Clock Error)
Timing (none)
Correct)
*4: The PLLx/SSCGx cannot set under 200MHz.
196, 9. Electric Modified the shading document name as below.

199, Characteristics
202, 9.1.4 AC Error)
205, Characteristics For details, see the hardware manual.
208,
211, Correct)
214, For details, see the Traveo™ Platform Hardware Manual.
217,
248
228 9. Electric Modified the shading document name as below.
Characteristics
9.1.4 AC Error)
Characteristics Please refer to Product Hardware Manual for available list.
Correct)
Please refer to S6J3300 series Hardware Manual for available list.

S6J3350 Series

261 11. Ordering Revised as below.
Information
Error)
S6J335EKSx******* 208-pin plastic TEQFP(LEW208)
Correct)
S6J335EKSCSE2000A
S6J335EKSESE20000 208-pin plastic TEQFP(LEW208)
S6J335EKBESE20000
S6J335EJBESE20000 176-pin plastic TEQFP(LEV176)
Rev. *I
11 3. Product Description Added the below
3.2 Product
Description Correct)
Table 3-1: Feature Description
Product A/D Converter AN39 to AN63 are not support for S6J335xxAx, S6J335xxCx, S6J335xxEx, and
Features S6J335xxGx option.

S6J3350 Series

13 CHAPTER 3: Deleted the shading parts as below:
Product
Description Error)
3.2.1. Ethernet Functions Remark
Direct Memory Access Interface.
- partial store and forward
- force max amba burst tx/rc
- Priority Queueing (Screening)
MAC Transmit Block
- half-duplex
- collision
- back_pressure
MAC Filtering Block
- VLAN tag
- Wakeup On Lan
IEEE 1588 and IEEE 802.1AS Support
MAC PFC Priority Based Pause Frame Support
802.1Qav Support – Credit Based Shaping
PHY Interface
- GMII
- SGMII
- TBI
- 10 M
- 1000 M
SGMII Operation
Jumbo Frames
Correct)
Functions Remark
MAC Transmit Block
- half-duplex
- collision
- back_pressure
MAC Filtering Block
- Wakeup On Lan
PHY Interface
- GMII
- SGMII
- TBI
- 1000 M
SGMII Operation
Jumbo Frames

S6J3350 Series

37 6. Port Description Revised the below
6.1 Port Description
List Error)
Package Pin Number
Port Name Description TEQFP TEQFP TEQFP Remark
144 176 208
Correct)
Package Pin Number
144 176 208

List Error)
Package Pin Number
144 176 208
Correct)
Package Pin Number
144 176 208

List Error)
Package Pin Number
144 176 208
Correct)
Package Pin Number
144 176 208

S6J3350 Series

List Error)
Package Pin Number
144 176 208
Correct)
Package Pin Number
144 176 208
258 to 12. Errata Added section “12. Errata”.

259
Rev. *J
6 2. Function List Revised the shading parts as below:
2.2. Optional Function
Figure 2-1: Option and Part Number for S6J3310/20/30/40 Series
Error)
Option:
Digit SHE MK_CEER* VCC DVCC
: : : : :
Correct)
Option:
Digit SHE MK_CEER* VCC5 DVCC
: : : : :

S6J3350 Series

9 3. Product Description Revised the shading parts as below:
3.2. Product
Description Table 3-1: Product Features
Error)
Feature Description
− 0.35 ms to 0.8 ms for 4 MHz (Fast clock)
− 0.43 ms to 1.28 ms for 100 kHz (Slow clock)
Correct)
Feature Description
− 30 us or more for 4 MHz (Fast CR clock)
− 30 us or more for 100 kHz (Slow CR clock)

S6J3350 Series

10 3. Product Description Revised the shading parts as below:
3.2. Product
Description Table 3-1: Product Features
Error)
Feature Description
PLL
− Sound system clock
− Sound frequency master clock
− Peripherals
− Display clock
− Trace clock
PLL / SSCG PLL
SSCG
− CPU core
− GDC core
− Hyper BUS
− DDR-HSSPI
Product supports down spread and center spread modes with the conditions
defined in 9.1.4.3 “Internal Clock Timing”.
Correct)
Feature Description
PLL
− Sound system clock
− Sound frequency master clock
− Peripherals
− Display clock
− Trace clock
SSCG
PLL / SSCG PLL − CPU core
− GDC core
− Hyper BUS
− DDR-HSSPI
Product supports down spread and center spread modes with the conditions
defined in 9.1.4.3 “Internal Clock Timing”.
Stabilization time is as follows.

− 100 us for PLL
− 200 us for SSCG

S6J3350 Series

14 4. Package and Pin Removed the shading parts as below:
Assignment
4.1.1. TEQFP-208 Pin Package Pin 103
Assignment
Error)
X1A / P1_12 / EINT13_0 / PPG4_TOUT2_0 / OCU8_OTD1_0 / ICU9_IN1_0 / TOT17_0 / TX2_0 / SCS161_0
Correct)
X1A / P1_12 / EINT13_0 / OCU8_OTD1_0 / ICU9_IN1_0 / TOT17_0 / TX2_0 / SCS161_0
Assignment
Assignment
Error)
Correct)
Assignment
Assignment
Error)
Correct)
35 6. Port Description Removed the shading parts as below:
6.1. Port Description
List Error)
Package Pin Number
144 176 208
Correct)
Package Pin Number
144 176 208

S6J3350 Series

38 6. Port Description Revised the shading parts as below:
6.1. Port Description
List Error)
Package Pin Number
144 176 208
Correct)
Package Pin Number
144 176 208

S6J3350 Series

125 7. Port Configuration Removed the shading parts as below:
7.1 Resource Input
Configuration Module Error)
7.1.1. RIC (0-7) PIN UFSET FSET OTD0 OTD0 TOUT2 TOUT0 TOUT0
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN521 _HWTRG3
PORTSEL
(0x0412) 1 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN522 _HWTRG3
PORTSEL
(0x0414) 2 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
: : : : : : : : : : :
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN585 _HWTRG3
PORTSEL
(0x0492) 1 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN586 _HWTRG3
PORTSEL
(0x0494) 2 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
Correct)
RESSEL
RIC_RE ADC12B0 - - - - - - - -
(8-15)
SIN521 _HWTRG3
PORTSEL
(0x0412) 1 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
RESSEL
RIC_RE ADC12B1 - - - - - - - -
(8-15)
SIN586 _HWTRG3
PORTSEL
(0x0494) 2 - - - - - - - -
(0-7)
PORTSEL
- - - - - - - -
(8-15)
138 CHAPTER 7: Port Revised the shading parts as below:

Configuration
7.2. Port Output Error)
Function Configuration Register Resource Functional Outputs
Port
(Offset) POF = 0 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7
7.2.1. Standard
PPC_PC GPIO_PO
OCU8_OT PPG4_TO
Configuration FGR112 P1_12 DR1:POD1 SCS161_0 - -
D1_0
TOT17_0
UT2_0
TX2_0
(0x0058) 2
Correct)
Port
(Offset) POF = 0 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7
PPC_PC GPIO_PO
OCU8_OT
FGR112 P1_12 DR1:POD1 SCS161_0 - - TOT17_0 - TX2_0
D1_0
(0x0058) 2

S6J3350 Series

152 9. Electric Added the shading parts as below:
Characteristics
9.1. Electrical Error)
Characteristics *2 Take care that DVCC, AVCC5 do not exceed VCC5 at, for example, the power-on time.
9.1.1. Absolute
*2 Take care that DVCC, AVCC5 do not exceed VCC5 at, for example, the power-on time.
For S6J33xxxAx or S6J33xxxCx or S6J33xxxEx or S6J33xxxGx option,
take care that AVCC5 do not exceed VCC5 at, for example, the power-on time.
173 9. Electric Revised the shading parts as below:

Characteristics
9.1. Electrical Error)
Characteristics - "Unused" means a clock source which doesn’t have any supply destinations. Configure it as disable with
9.1.4. AC performing at the lower clock frequency than the described maximum.
Characteristics
9.1.4.3. Internal Clock Correct)
Timing - "Unused" means a clock source which doesn’t have any supply destinations. Configure these clocks to a
lower clock frequency than the described maximum.

S6J3350 Series
Document History
Document Title: S6J3350 Series 32-bit Microcontroller Traveo™ Family
Document Number: 002-10634
Revision ECN Submission Date Description of Change
** 5063970 01/25/2016 New Spec.
Correct device revision, Chip ID, LVD spec, DDR-HSSPI spec, and Hyper BUS spec
*A 5203759 04/05/2016
For detail, see “Major Changes”.
Additional Internal operation clock frequency comments, LVD comments, and ADC Units vs
channel comments
The package dimension of TEQFP144 (0.4mm Pitch) correct from the provisional version to the
*B 5371721 07/25/2016
formal version.
TYPO: I2C Fast Mode
For detail, see “Major Changes”
- ID add
-ICCT, ICCH spec add
*C 5622195 02/07/2017 -Power and RSTX sequence add
-Ordering Information revise
-Delete product lineup of flash memory size 2MB and 1.5MB(Digit C and B)
-Special spec of total maximum clamp current add
-Icc12, Icch12 spec change
*D 5782707 06/26/2017
-Power sequence add
-Flash write/erase spec change
-Revision change
-Power supply current for S6J33xxxxE add
*E 5952291 10/31/2017
-Ordering Information change
-Function list and Product Description change

*F 5971701 11/22/2017
-Hysteresis voltage add in DC Characteristics

*G 6069450 02/19/2018
-Document Definition change

-PLLx/SSCGx minimum clock frequencies add in Internal Clock Timing.
*H 6166795 05/07/2018
-Ordering Information change

S6J3350 Series
Revision ECN Submission Date Description of Change
- Add an option limitation for Description of A/D Converter of Product Description.

- Update Ethernet Support Functions.
*I 6300353 09/05/2018 - Update Base timer allocation
- Added 12. Errata
- Updated some sentences.

*J 6943828 08/05/2020
For detail, see “Major Changes”.

S6J3350 Series
Sales, Solutions, and Legal Information

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© Cypress Semiconductor Corporation, 2016-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
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reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
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other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-
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authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement..
Document Number: 002-10634 Rev. *J August 5, 2020 Page 307 of 307

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Continuity of document content

Continuity of ordering part numbers

◼ Security and Safety

Document Number: 002-10634 Rev. *J Page 2 of 307

1.2 Document Definition

Document Number: 002-10634 Rev. *J Page 3 of 307

Document Number: 002-10634 Rev. *J Page 4 of 307

Function Description Remarks

Document Number: 002-10634 Rev. *J Page 5 of 307

2.2 Optional Function

Ordering options 7 digit

Identifier: Automotive MCU

Document Number: 002-10634 Rev. *J Page 6 of 307

Document Number: 002-10634 Rev. *J Page 7 of 307

Function TEQFP176 TEQFP144

Document Number: 002-10634 Rev. *J Page 8 of 307

3.2 Product Description

Document Number: 002-10634 Rev. *J Page 9 of 307

See the Traveo™ Platform Hardware Manual in detail.

Stabilization time is as follows.

To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,

Document Number: 002-10634 Rev. *J Page 10 of 307

Document Number: 002-10634 Rev. *J Page 11 of 307

Document Number: 002-10634 Rev. *J Page 12 of 307

The following functions are not supported.

Document Number: 002-10634 Rev. *J Page 13 of 307

4. Package and Pin Assignment

*1: x, y, z are selected from the following parameters:

Document Number: 002-10634 Rev. *J Page 14 of 307

4.1.2 TEQFP-176 Pin Assignment

PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0

PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0

*1: x, y, z are selected from the following parameters:

Document Number: 002-10634 Rev. *J Page 15 of 307

4.1.3 TEQFP-144 Pin Assignment

PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9

*1: x, y, z are selected from the following parameters:

Document Number: 002-10634 Rev. *J Page 16 of 307

4.2 Package Dimensions

b 0.17 0.22 0.27

L 0.45 0.60 0.75

Document Number: 002-10634 Rev. *J Page 17 of 307

b 0.17 0.22 0.27

L 0.45 0.60 0.75

Document Number: 002-10634 Rev. *J Page 18 of 307

b 0.17 0.22 0.27

L 0.45 0.60 0.75

Document Number: 002-10634 Rev. *J Page 19 of 307

Figure 4-7: TEQFP144 (0.4mm Pitch)

0.20 C A-B D 0.20 C A-B D BOTTOM VIEW

Document Number: 002-10634 Rev. *J Page 20 of 307

D − External 1.2 V regulator control

E − General-purpose I/O port

Document Number: 002-10634 Rev. *J Page 21 of 307

Type Circuit Remarks

Document Number: 002-10634 Rev. *J Page 22 of 307

Type Circuit Remarks

O − CMOS hysteresis input

P − General-purpose I/O port with analog input

Document Number: 002-10634 Rev. *J Page 23 of 307

Type Circuit Remarks

Document Number: 002-10634 Rev. *J Page 24 of 307