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    Che Eni
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    This document outlines the requirements for Assignment 2 Report 2, which involves designing an 8-bit Arithmetic Logic Unit (ALU) in Verilog using if-else statements and case statements. The report must include an introduction, literature review on Verilog, ALUs, and the two modeling methods, detailed design of the ALU code with explanations, functional verification with test data, expected outputs, simulation results, performance comparison, RTL view, resource consumption for each method, and a conclusion. It provides a marking scheme allocating a total of 20 marks across 6 criteria assessing these report elements.

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    This document outlines the requirements for Assignment 2 Report 2, which involves designing an 8-bit Arithmetic Logic Unit (ALU) in Verilog using if-else statements and case statements. The report must include an introduction, literature review on Verilog, ALUs, and the two modeling methods, detailed design of the ALU code with explanations, functional verification with test data, expected outputs, simulation results, performance comparison, RTL view, resource consumption for each method, and a conclusion. It provides a marking scheme allocating a total of 20 marks across 6 criteria assessing these report elements.

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    © All Rights Reserved
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    1 views1 page

    Assignment 2

    Uploaded by

    Che Eni
    This document outlines the requirements for Assignment 2 Report 2, which involves designing an 8-bit Arithmetic Logic Unit (ALU) in Verilog using if-else statements and case statements. The report must include an introduction, literature review on Verilog, ALUs, and the two modeling methods, detailed design of the ALU code with explanations, functional verification with test data, expected outputs, simulation results, performance comparison, RTL view, resource consumption for each method, and a conclusion. It provides a marking scheme allocating a total of 20 marks across 6 criteria assessing these report elements.

    Copyright:

    © All Rights Reserved
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    Assignment 2 – Report 2 (20 marks)

    Design and an 8-bit Arithmetic and Logic Unit (ALU) using the following methods in Verilog.
    1. If-else Statement
    2. Case statement

    The report should cover the 1) introduction, 2) literature review for Verilog, ALU and both
    Verilog modelling methods, 3) detailed design of the ALU’s Verilog code with explanation, 4)
    Functional verification – test data used for the functional verification, expected output,
    simulation results, performance comparison, RTL view, resource consumptions for both
    methods, and discussion, and 5) Conclusion.

    The marking scheme is as follows.

    No. Criteria Marks


    1 Introduction and Literature review 4
    2 Detailed design of the systems modeled 4
    3 RTL view and the Resource Consumption of the systems 4
    modeled
    4 Simulation results 4
    5 Functional Verification, Performance evaluation and discussion 3
    6 Conclusion 1
    Total 20

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