LG 50PB560B Chassis PD41C

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
PLASMA TV
SERVICE MANUAL
CHASSIS : PD41C
MODEL : 50PB560B 50PB560B-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL68062601 (1404-REV00) Printed in Korea

CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SPECIFICATION........................................................................................ 4
ADJUSTMENT INSTRUCTION................................................................. 6
BLOCK DIAGRAM................................................................................... 14
EXPLODED VIEW .................................................................................. 15
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © 2014 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
such as WATER PIPE,
shock.
To Instrument's CONDUIT etc.
exposed
Leakage Current Cold Check(Antenna Cold Check)
METALLIC PARTS
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied all of the PDP TV with PD41C chassis.
2. Requirement for Test

Each part is tested as below without special appointment.
(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
(1) Performance: LGE TV test method followed
(2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
4. Module General Specification

- 50" HD
No Item Specification Remark
1 Display Screen Device 127 cm (50 inch) wide Color Display Module PDP
2 Aspect Ratio 16:9
3 PDP Module PDP50T6####,
RGB Closed (Well) Type, Glass Filter (43%)
Pixel Format: 1024 horiz. By 768 ver.
4 Operating Environment 1) Temp. : 0 ~ 40 deg LGE SPEC
2) Humidity : 20 ~ 80%
5 Storage Environment 1) Temp. : -20 ~ 60 deg
2) Humidity : 10 ~ 90 %
6 Input Voltage AC100 ~ 240V, 50/60Hz Maker LG
5. Model General Specification
No Item Specification Remark
1 Market Albania, Austria, Belgium, Bosnia, Bulgaria, Coratia, 36 Country
Czech, Denmark, Estonia, Finland, France, Germany,
Greece, Hungary, Ireland, Italy, Kazakhstan, Latvia,
Lithuania, Luxembourg, Morocco, Netherlands,
Norway, Poland, Portugal, Romania, Russia, Serbia,
Slovenia, Spain, Sweden, Slovakia, Switzerland,
Turkey, Ukraine, UK
Australia, New Zealand, Malaysia, Indonesia, Non-EU
Singapore, South Africa, Israel, Iran, Vietnam, Kenya,
Asia,Non-EU analog, CHINA(cormmercial)
2 Broadcasting system 1) PAL/SECAM BG Programme Coverage (EU)
2) PAL/SECAM DK Digital TV
3) PAL I / II - PD41B are not support SECAM L/L`
4) SECAM L/L’ - Only PD41B support DVB-T2/S2
5) DVB T Analogue TV
6) DVB C VHF: E2 to E12, UHF: E21 to E69,
7) DVB T2 CATV: S1 to S20, HYPER: S21 to S47
8) DVB S2
1) PAL/SECAM BG Programme Coverage (NON-EU)
2) PAL/SECAM DK Digital TV
3) PAL I VHF 04 to 13, UHF 27 to 69
4) NTSC M Analogue TV
5) DVB T VHF/UHF 1 to 78, CATV 01 to 71
3 Receiving system Analog : Upper Heterodyne
Digital : COFDM
4 Scart Jack (1EA) PAL, SECAM EU ONLY
5 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr
6 RGB Input (1EA) RGB-PC Commercial Model ONLY
7 RS232C (1EA) SVC Commercial Model ONLY
8 AV (2EA) CVBS ( Hybrid :1) EU model have 1 AV ( Hybrid)
9 HDMI Input (2 or 3EA) HDMI-PC HDMI/PC/MHL 1
HDMI-DTV
HDMI-MHL
10 Audio Input (1EA) DVI Audio, Component L/R Input
11 SPDIF Out (1 EA) SPDIF Out
12 USB (1EA) for SVC, S/W Download, DivX
13 LAN only DVB-T2 (UK, Irend) Model
14 PCMCI (1EA) DVB-T/C Decryption Interface, CI+ EU ONLY
ADJUSTMENT INSTRUCTION
1. Application Range 3. Main PCB check process
This spec. sheet applies to PD41C chassis applied PDP TV * APC - After Manual-Insult, executing APC
all models manufactured in TV factory.
* Boot file Download
(1) Execute ISP program “Mstar ISP Utility” and then click
2. Designation “Config” tab.
(1) T he adjustment is according to the order which is (2) Set as below, and then click “Auto Detect” and check “OK”
designated and which must be followed, according to the message
plan which can be changed only on agreeing. If “Error” is displayed, Check connection between computer,
(2) Power adjustment : Free Voltage. jig, and set.
(3) Magnetic Field Condition: Nil. (3) Click “Read” tab, and then load download file (XXXX.bin)
(4) Input signal Unit: Product Specification Standard. by clicking “Read”
(5) Reserve after operation: Above 5 Minutes (Heat Run)
Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz
(6) A djustment equipments : Color Analyzer (CA-210 or
CA-110), DDC Adjustment Jig equipment, SVC remote
controller.
(7) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15
(4) Click “Connect” tab. If “Can’t ” is displayed, Check
- In case of keeping module is in the circumstance of 0°C, it connection between computer, jig, and set.
should be placed in the circumstance of above 15°C for 2
hours.
- In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above
15°C for 3 hours.
■A fter RGB Full White in HEAT-RUN Mode, the receiver must
be operated prior to the adjustment.
■ Enter into HEAT-RUN MODE
1) Press the POWER ON KEY on R/C for adjustment.
2) OSD display and screen display PATTERN MODE. (5) Click “Auto” tab and set as below.
● Set is activated HEAT run without signal generator in this (6) Click "Run".
mode. (7) After downloading, check "OK" message.
● Single color pattern ( WHITE ) of HEAT RUN MODE uses to
check panel.
● Caution : If you turn on a still screen more than 20 minutes
(Especially digital pattern, cross hatch pattern), an
after image may be occur in the black level part of
the screen.
(8) Push The “IN STOP KEY” – For memory initialization.
Case1 : Software version up
1) After downloading S/W by USB , Multi-vision set will reboot
automatically
2) Push “In-stop” key
3) Push “Power on” key
4) Function inspection
5) After function inspection, Push “In-stop” key.
Case2 : Function check at the assembly line

1) When TV set is entering on the assembly line, Push “In-
stop” key at first.
2) Push “Power on” key for turning it on.
-> If you push “Power on” key, TV set will recover channel
information by itself.
3) After function inspection, Push “In-stop” key.
* USB DOWNLOAD(*.epk file download) 3.1. ADC Process
(1) Put the USB Stick to the USB socket 3.1.1. ADC
(2) Automatically detecting update file in USB Stick ■ Enter Service Mode by pushing “ADJ” key,
- If your downloaded program version in USB Stick is Low, ■ Enter Internal ADC mode by pushing “►” key at “5. ADC
it didn’t work. Calibration”
- B ut your downloaded version is High, USB data is
automatically detecting
(3) Show the message “Copying files from memory”
(4) Updating is staring.
* Caution : Using ‘power on’ button of the Adjustment R/C ,

power on Multi-vision.
* ADC Calibration Protocol (RS232)

(5) U pdating Completed, The Multi-vision will restart NO Enter ADC adjust
automatically. Adjust MODE
(6) I f your Multi-vision is turned on, check your updated Item Adjust ‘Mode In’ ADC Adjust
version and Tool option. (explain the Tool option, next
stage) CMD 1 A A
CMD 2 A D
* After downloading, have to adjust TOOL OPTION again. Data 0 0 1
1) Push "IN-START" key in service remote controller.
2) Select "Tool Option 1" and Push “OK” button. 0 0
3) P unch in the number. (Each of models has their When transfer the Automatically adjustment
number.) ‘Mode In’, (The use of a internal
4) Completed selecting Tool option. Carry the command. pattern)
50PB560B-Z* - Adjust Sequence

HD/FHD HD ▪aa 00 00 [Enter Adjust Mode]
▪xb 00 40 [Component1 Input (480i)]
Tool option 1 16393
▪ad 00 10 [Adjust 480i Comp1]
Tool option 2 2577 ▪aa 00 90 End Adjust mode
Tool option 3 10497 * Required equipment : Adjustment R/C.
Tool option 4 13136
3.2. Function Check
Tool option 5 51218
3.2.1. Check display and sound
Tool option 6 8464 ■ Check Input and Signal items. (cf. work instructions)
1) TV
2) AV (SCART/ CVBS)
3) COMPONENT (480i)
4) HDMI
5) PC Audio In
*D isplay and Sound check is executed
by Remote controller.
* Caution : Not to push the INSTOP KEY after completion if

the function inspection.
4. Total Assembly line process 4.2. Adjustment Preparation
● Required Equipment
4.1. POWER PCB Assy voltage adjustment - Remote controller for adjustment
(Vs voltage adjustment)
- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same
product : CH 11 (PDP)
4.1.1.Test equipment : D.M.M 1EA * Please adjust CA-210, CA-100+ by CS-1000 before measur-
ing
4.1.2. Condition for adjustment - Auto W/B adjustment instrument(only for Auto adjust-
- No signal with the snow noise in RF mode ment)
- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO
4.1.3. Connection Diagram for Measuring W/B EQUIPMENT.
: refer to below
Before Adjust of White Balance, Please press
4.1.4. Adjustment method POWER ONLY key
4.1.4.1. Vs adjustment
(1) Connect + terminal of D. M..M. to Vs TP, connect -terminal - Adjust Process will start by execute RS232C Command.
to GND. ● Color temperature standards according to CSM and Module
(2) After turning VR901, voltage of D.M.M adjustment as same
as Vs voltage which on label of panel right/top ( deviation CSM PLASMA
; ±0.5V) Cool 11000K
Medium 9300K
4.1.4.2. Va adjustment
(1) Connect + terminal of D. M..M. to Va TP, connect -terminal Warm 6500K
to GND.
(2) After turning VR502, voltage of D.M.M adjustment as same ● CS-1000/CA-100+/CA-210(CH 10) White balance adjust-
as Va voltage which on label of panel right/top ( deviation ment coordinates and color temperature.
; ±0.5V) CSM Color Coordination Temp ± Color
96$'-867
x y Coordination
COOL 0.276 0.283 11000K 0.002

MEDIUM 0.286 0.289 9300K 0.002
WARM 0.313 0.329 6500K 0.002
* Connecting picture of the measuring instrument

(On Automatic control)
96$'-867 - Inside PATTERN is used when W/B is controlled.
Connect to auto controller or push Adjustment R/C
POWER-ON -> Enter the mode of White-Balance, the
pattern will come out.
* Auto-control interface and directions * After You finish all adjustments, Press “In-start” button and
1) Adjust in the place where the influx of light like floodlight compare Tool option and Area option value with its BOM, if it
around is blocked. (Illumination is less than 100Lux). is correctly same then unplug the AC cable.
2) Adhere closely the Color Analyzer ( CA210 ) to the If it is not same, then correct it same with BOM and unplug
module less than 10cm distance, keep it with the surface AC cable.
of the Module and Color Analyzer’s Prove vertically. For correct it to the model’s module from factory JIG model.
(80~100°). * Push The “IN STOP KEY” after completing the function
3) Aging time inspection. And Mechanical Power Switch must be set “ON”
- After aging start, keep the power on (no suspension of * To check the coordinates of White Balance, you have to
power supply) and heat-run over 5 minutes. measure at the below conditions.
- Using ‘no signal’ or ‘full white pattern’ or the others, - Picture mode : Vivid, Energy Saving : Off, Below the Ad-
check the back light on. vanced control, Dynamic Contrast : Off, Dynamic Colour : Off
Colour Temp.
■ Auto adjustment Map(RS-232C)
RS-232C COMMAND Cool 30
[ CMD ID DATA ] Medium 0
Wb 00 00 White Balance Start
Warm 30
Wb 00 ff White Balance End
-> Picture Mode change : Vivid -> Vivid(User)
RS-232C M CENTER M
COMMAND I (DEFAULT) A
[CMD ID DATA] N X 4.3. DDC EDID Write (HDMI 256Byte)
Cool Mid Warm Cool Mid Warm -> Not used any more, Use Auto D/L
■ Connect HDMI Signal Cable to HDMI Jack.
R Gain jg Ja jd 00 172 192 192 192
■ Write EDID DATA to EEPROM(24C02) by using DDC2B
G Gain jh Jb je 00 172 192 192 192 protocol.
B Gain ji Jc jf 00 192 192 172 192 ■ Check whether written EDID data is correct or not.
* For SVC main Ass’y, EDID have to be downloaded to Insert
R Cut 64 64 64 128 Process in advance.
G Cut 64 64 64 128
B Cut 64 64 64 128 4.4. EDID DATA
(1) All Data : HEXA Value
* Caution (2) Changeable Data :
- Color Temperature : COOL, Medium, Warm. * : Serial No : Controlled / Data:01
- One of R Gain/G Gain/ B Gain should be kept on 0xC0, ** : Month : Controlled / Data:00
and adjust other two lower than C0. (when R/G/B Gain *** : Year : Controlled
are all C0, it is the FULL Dynamic Range of Module) **** : Check sum
* Manual W/B process using adjusts Remote control.

■ After enter Service Mode by pushing “ADJ” key,
■ Enter White Balance by pushing “►” key at “6. White
Balance”.
■ Stick the sensor to the center of the screen and select
each items(Red/Green/Blue Gain) using ▲/▼(CH +/-)
key on R/C.
■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.
■ Adjust three modes all(Cool/Medium/Warm) : Fix the one
of R/G/B Gain and Change the others.
■ When the adjustment is completed, Enter “COPY ALL”.
■ Exit adjustment mode using EXIT key on R/C.
4.5. EDID DATA Auto Download

(1) Press Adj. key on the Adj. R/C,
(2) Select EDID D/L menu.
(3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is
failure, NG is displayed.
(5) If Download is failure, Re-try downloads.
* Caution : Never connect HDMI & D-sub Cable when EDID

downloaded.
■ Edid data and Model option download (RS232 Zender) * Checksum: Changeable by total EDID data.
NO Enter EDID data and EDID C/S data 2D-HD
download MODE Model option download HDMI
Item download ‘Mode In’ download check sum Block 0 0x3D
CMD 1 A A (Hex) Block 1 0x24(HDMI1)
CMD 2 A E
Data 0 0 00
0 10 4.5. EDID DATA Auto Download
When transfer the Automatically download (1) Press Adj. key on the Adj. R/C,
‘Mode In’, (The use of a internal (2) Select EDID D/L menu.
Carry the command. Data) (3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is
failure, NG is displayed.
- Manual Download (5) If Download is failure, Re-try downloads.
* Caution
● Use the proper signal cable for EDID Download
- Digital EDID : Pin3 exists 4.6 LNB voltage and 22KHz tone check
(1) Test method
* Caution 1) Press "Power on" button of a service R/C.(Baud rate :
- Never connect HDMI & D-sub Cable at the same time. 115200 bps)
- Use the proper cables below for EDID Writing. 2) Connect cable between satellite ANT and test JIG.
- Download HDMI1, HDMI2 separately because HDMI1 is 3) Connect RS232-C Signal Cable.
different from HDMI2. 4) Write LNB ON control command through RS-232-C.
5) check LED light ‘ON’ at 18V menu.
For HDMI EDID 6) check LED light ‘ON’ at 22KHz tone menu.
DVI-D to HDMI or HDMI to HDMI 7) Write LNB OFF control command through RS-232-C.
8) check LED light ‘OFF’ at 18V menu.
9) check LED light ‘OFF’ at 22KHz tone menu.
(2) RS-232 command for test LNB

Command Set ACK
LNB On [A][I][ ][Set ID][ ][30][Cr] [O][K][x] or NG : [N][G][x]
No. Item Condition Hex Data LNB Off [A][I][ ][Set ID][ ][40][Cr] [O][K][x] or NG : [N][G][x]
1 Manufacturer ID GSM 1E6D (3) Test result

- After send LNB On command, ‘18V LED’ and ‘22KHz
2 Version Digital : 1 01
tone LED’ should be ON.
3 Revision Digital : 3 03 - After send LNB Off command, ‘18V LED’ and ‘22KHz tone
LED’ should be OFF.
* HD EDID data
- HD HDMI1 EDID data 4;Y 46Y k}iTzYGG
tGi
{
55NK}# 55NK}
Wrqh RQ Wrqh#Rii
ck}iGGGqpnGGe
<Remark>
After the measurement conditions witnessed in the last state.
Copyright © 2014 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
4.7. GND & Hi-pot test 5. Model name & Serial number Download
■ GND TEST = P OWER CORD GND and SIGNAL CABLE
GND
5.1. Model name & Serial number D/L
■ Press “Power on” key of service remocon.(Baud rate :
■ Hi-pot TEST = POWER CORD GND and LIVE&NUETRAL
115200 bps)
■ Test Process
■ Connect RS232 Signal Cable to RS-232 Jack.
1. Check the POWER CABLE and SIGNAL CABLE
■ Write Serial number by use RS-232.
insertion condition.
■ Must check the serial number at signal test of customer sup-
2. Connect the AV JACK Tester
port. (Refer to below).
3. Controller(GWS103-4) on
4. GND TEST(Auto)
- If Test is failed, Buzzer operate
- If Test is passed, execute next process(HI-pot test)
- Remove A/V CORD from A/V JACK BOX
5. HI-POT test(Auto)
- If Test is failed, Buzzer operate
- If Test is passed, GOOD Lamp on and move to next
process automatically.
■ Checkpoint
(1) Test voltage
1) 3 Poles 5.2. Signal TABLE
- GND: 1.5KV/min at 100mA
CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY
- SIGNAL: 3KV/min at 100mA
2) 2 Poles CMD: A0h
- SIGNAL: 3KV/min at 100mA LENGTH : 85~94h (1~16 bytes)
(2) TEST time: 1 second ADH : EEPROM Sub Address high (00~1F)
(3) TEST POINT ADL : EEPROM Sub Address low (00~FF)
1) 3 Poles Data : Write data
- GND Test = P OWER CORD GND and SIGNAL CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
CABLE GND. Delay : 20ms
- Hi-pot Test = POWER CORD GND and LIVE &
NEUTRAL. 5.3. Command Set
2) 2 Poles
- Hi-pot Test = Accessible Metal and LIVE & NEUTRAL. No. 1
(4) LEAKAGE CURRENT: At 0.5mArms Adjust mode EEPROM WRITE
CMD(hex) A0h
LENGTH(hex) 84h+n
Description n-bytes Write (n = 1~16)
* Description
FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart,
0, Phase
Data write : Model Name and Serial Number write in EEP-
(Tuner GND is separated) ROM,.
5.4. Method & Notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
* Manual Download (Model Name and Serial Number) ■ Check the method of RS232C Command
- If the TV set is downloaded By OTA or Service man, (1) into the main ass’y mode (RS232 : aa 00 00)
Sometimes model name or serial number is initialized.( Not
CMD1 CMD2 Data 0
always)
- There is impossible to download by bar code scan, so It A A 0 0
need Manual download.
(2) c heck the key download for transmitted command
1) Press the ‘instart’ key of ADJ remote controller. (RS232 : ci 00 10)
2) Go to the menu ‘5.Model Number D/L’ like below photo.
CMD1 CMD2 Data 0
3) Input the Factory model name or Serial number like
photo. C 1 1 0
(3) result value

- normally status for download : OKx
- abnormally status for download : NGx
■ Check the method of CI+ Key value (RS232)

(1) into the main ass’y mode (RS232 : aa 00 00)
CMD1 CMD2 Data 0
A A 0 0
4) Check the model name Instart menu -> Factory name
displayed. (2) check the mothed of CI+ key by command
5) Check the Diagnostics (DTV country only) -> Buyer (RS232 : ci 00 20)
model displayed
CMD1 CMD2 Data 0
C I 2 0
(3) result value

i 01 OK 1d1852d21c1ed5dcx
└──> CI+ Key Value
7. Download MAC Address, CI+ Key

and widevine Key.
- Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).
6. Download CI+ Key (EU model only) -> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA).
* Connect TV SET and PC which download keys Writing pro-
gram by RS232C-Cable * C onnect TV SET and PC which download keys Writing
(1) Start “CIKeyl.exe”Program and Click (3) Button to connect program by RS232C-Cable
TV and PC. 1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
(2) Click (5) to download CI+ Key. connect TV and PC.
(3) When download succeed, you can see “OK” on (6) 2) Click (4) to download MAC Address.
3) Click (5) to download CI+ Key.
4) When download succeed, you can see “OK” on (6)
* Each Chassis has it’s own MAC Address. Please be careful

of download.
■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)
CMD1 CMD2 Data 0
A A 0 0
(2) c heck the key download for transmitted command

(RS232 : ci 00 10)
CMD1 CMD2 Data 0

C I 1 0
(3) result value
- normally status for download : OKx
- abnormally status for download : NGx
8. SW Download Guide.
* Put a *.bin to USB Stick and Turn on TV
(1) Put the USB Stick to the USB socket

(2) Automatically detecting update file in USB Stick
* If your downloaded program version in USB Stick is Low,
it didn’t work.
B ut your downloaded version is High, USB data is auto-
matically detecting.
(3) Show the message “Copying files from memory”
(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ
Remote-control.
* IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OP-
TION MENU.
(6) When TV turn on, check the Updated version on
Diagnostics MENU.
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Copyright © 2014 LG Electronics. Inc. All rights reserved.

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COMP/AV
SPDIF Out
172mV
Video Audio
- 14 -
Front DSP tjsr
CVBS {hz\^ZZ
End
SCART OkGhtwP
(EU) CVBS pYz
Rear AV
CVBS
BLOCK DIAGRAM
COMP1/AV1/PC AUDIO L/R py

(AJ/JA) L/R
Audio RX/TX
L/R
Front
End
UART
HDMI 1 TMDS/DDC
540mV
HDMI
/MHL
RX USB2.0
/PC
k}y
LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
560
300
305
303
304
LV1
301
302
120
205
A9
601
203
A10
200
201
520
202
A2
204
580
240
400
900
910
<Full SCART> +3.3V
EU
JK100
PSC008-02
R104
10K
PDP L14
EAX65405603
GROWTH
AV2_CVBS_DET
R105 1K
EU
SHIELD SC1/COMP1_DET
R171 1K
23
AV/SC1_CVBS_IN
AV_DET
C111
VA101
22 R117 C109
R170 75 27pF 220pF
EU
COM_GND 0 EU 50V 50V
21 EU EU EU
SYNC_IN AV2_R_IN1 EU
L102
20 CM2012FR22KT
SYNC_OUT 220nH
JP112
JP113
JP114
JP115
EU DTV/MNT_VOUT
19 EU
VA102
SYNC_GND2 R147 C139 C140
EU
18 75 68pF 68pF
R166 50V
SYNC_GND1 0 EU 50V
17 EU
RGB_IO AV2_L_IN1
EU R123 33 SC_FB_DSUB_VSYNC
16
VA105
R119
EU
R_OUT
SC_DSUB_R+ 75
15 EU EU
VA106
RGB_GND R106
75
14
R_GND SC_ID_DSUB_HSYNC
13 R114
VA100
R120
D2B_OUT EU 10K 2.7K
12 EU EU
G_OUT
11 EU AV2_L_IN
VA103
D2B_IN R108 SC_DSUB_G+ AV/SC1_L_IN

75
10 C117 R121 R126
G_GND R115 10K
1000pF 470K 12K
9 50V P_17V
ID
8 AV2_R_IN
B_OUT
AV/SC1_R_IN
JIG_GND
VA104
7 EU C118 R124
AUDIO_L_IN R168 EU
R107 SC_DSUB_B+ 1000pF R116 10K R127
6 0 75 470K 12K
IC101
50V
B_GND AZ4580MTR-E1
5
AUDIO_GND
AV_COMMON EU
4 OUT1 VCC
AUDIO_L_OUT R169 EU 1 8
3 0 R138
AUDIO_R_IN 2K C113 C114 R149
EU 10uF 27pF 15K IN1- 2 7 OUT2
2
AUDIO_R_OUT 10V 50V EU
Q101 EU
1 C107 C108 MMBT3904(NXP)
5600pF 5600pF EU SCART1_Lout IN1+ 3 6 IN2-
R137 R145
50V 50V 470 6.8K R154 EU
EU EU EU EU 330pF 220K 5.6K 5.6K
C120 R158 EU VEE 4 5 IN2+ R153
EU EU SCART1_Rout
220K 330pF
C115 R159 C119
27pF R148 R152 EU EU
EU 50V 15K 6.8K
DTV_R_OUT EU EU EU
R139
2K C112
EU 10uF
10V
Q102
MMBT3904(NXP)
EU R140
470
EU
SCART1_MUTE
C138
0.1uF
READY
<CI SLOT> +5V_CI_ON

<3.3V_CI> <CI DETECT> +3.3V_CI
+3.3V_CI OR_GARE_CI_TI
IC104-*1
OR_GARE_CI_PHILIPS SN74LVC1G32DCKR
+3.3V +3.3V_CI IC104
74LVC1G32GW A VCC
1 5
C100 C101 B 1 5 VCC
22uF 0.1uF L101 /CI_CD2 B
10V 16V 120-ohm
2
EU EU EU A 2
BUF1_FE_TS_DATA[0-7] /CI_CD1 GND

3 4
Y
AR109
GND 3 4 Y R125
10K
BUF1_FE_TS_DATA[0-7]
BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[7] +5V C136 C137 EU

0.1uF 0.1uF
BUF1_FE_TS_DATA[6] BUF2_FE_TS_DATA[6] JK102 16V 16V
READY EU
BUF1_FE_TS_DATA[5] BUF2_FE_TS_DATA[5]
R151
10067972-000LF CI_DET
BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[4] 10K R102 R134
EU 33 EU 100 35 EU AR103
33 47
EU EU PCM_D[3] /PCM_CD
AR108 /CI_CD1 36
37 3 PCM_D[4] EU
BUF1_FE_TS_DATA[3] BUF2_FE_TS_DATA[3] EU
AR100 33 38 4 PCM_D[5]
BUF2_FE_TS_DATA[2] CI_TS_DATA[4]
BUF1_FE_TS_DATA[2] PCM_D[6] R133
CI_TS_DATA[5] 39 5 10K
BUF1_FE_TS_DATA[1] BUF2_FE_TS_DATA[1] PCM_D[7] EU
CI_TS_DATA[6] 40 6
BUF2_FE_TS_DATA[0]
BUF1_FE_TS_DATA[0]
EU 33 CI_TS_DATA[7] 41
42
7
8
R130
R131
33 EU
33 EU
/PCM_CE <CI ENABLE> +5V_CI_ON
BUF2_FE_TS_DATA[0-7] R111 43 9 CI_ADDR[10] +5V
10K CI_OE +5V
IC102
AR110 EU 44 10 CI_ADDR[11]
CI_IORD Close to mstar AP2151WG-7
45 11 CI_ADDR[9]
BUF1_FE_TS_SYN BUF2_FE_TS_SYN CI_IOWR L100
46 12 CI_ADDR[8] BLM18PG121SN1D
BUF1_FE_TS_VAL_ERR BUF2_FE_TS_VAL_ERR BUF2_FE_TS_SYN R135
CI_ADDR[13] 10K IN OUT EU
BUF1_FE_TS_CLK BUF2_FE_TS_CLK 47 13 5 1
BUF2_FE_TS_DATA[0-7]
BUF2_FE_TS_DATA[0] CI_ADDR[14] EU
48 14 EU
BUF2_FE_TS_DATA[1] EU
49 15 GND R1674
EU 33 BUF2_FE_TS_DATA[2]
CI_WE
2 C103
READY 50 16 R132 100 1uF 100K
EU /PCM_IRQA 25V
BUF2_FE_TS_DATA[3] R112 EU EU
EU 51 17 C104
AR105 33 0 R128 0 0.1uF EN FLG
52 18 4 3
CI_OE /PCM_OE 16V PCM_5V_CTL
53 19 READY
CI_WE /PCM_WE BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_DATA[4]
54 20 BUF2_FE_TS_CLK
CI_IORD /PCM_IORD BUF2_FE_TS_DATA[5] R109 55 21 CI_ADDR[12]
CI_IOWR /PCM_IOWR BUF2_FE_TS_DATA[6] 10K
EU 56 22 CI_ADDR[7]
EU BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_DATA[7] CI_ADDR[6]
AR106 33 57 23
CI_ADDR[12] PCM_A[12] R100 EU 33 58 24 CI_ADDR[5]
PCM_RST
CI_ADDR[13] PCM_A[13] +5V 59 25 CI_ADDR[4]
/PCM_WAIT
CI_ADDR[14] PCM_A[14] R101 EU 33 CI_ADDR[3]
60 26
REG /PCM_REG R129 EU 10K
REG
CI_TS_CLK
R155
R156
EU 100
EU 33
61 27 CI_ADDR[2]
CI_ADDR[1]
<CI SWITCH> +3.3V_CI +3.3V_CI
CI_TS_VAL 62 28
EU R157 EU 33 EU IC100
AR107 33 Close to mstarCI_TS_SYNC 63 29 AR104
33
CI_ADDR[0]
R165
EU
CI_ADDR[8] PCM_A[8] R110 AR111 TC74LCX244FT C105
0 64 30 EU PCM_D[0] 10K 0.1uF
Close to mstar C102 2pF 100
CI_ADDR[9] PCM_A[9] READY PCM_D[1] 16V
65 31 1/16W
AR102 33
CI_ADDR[10] PCM_A[10] CI_TS_DATA[0] 66 32 PCM_D[2] EU 1OE VCC AR112
EU CI_ADDR[5] CI_DET
1
EU
20
100
CI_ADDR[11] PCM_A[11] CI_TS_DATA[1] 67 33 1A1 2OE
1/16W
CI_ADDR[0-14] CI_ADDR[4] PCM_A[0] 2 19
CI_TS_DATA[2] EU
68 34 CI_ADDR[7]
2Y4
3 18
1Y1
CI_ADDR[0]
CI_TS_DATA[3] 1A2
4 17
2A4
G2
2 69 G1
1 CI_ADDR[6] PCM_A[1] PCM_A[7] CI_ADDR[1]
R150 2Y3
5 16
1Y2
10K CI_ADDR[2]
EU R103 1A3 2A3
+5V 100 PCM_A[2] 6 15

PCM_A[6] CI_ADDR[3]
EU PCM_D[0-7] 2Y2 1Y3
/CI_CD2 PCM_D[0-7] 7 14
1A4 2A2
8 13
PCM_A[3] PCM_A[5]
2Y1 1Y4
9 12
GND 2A1
10 11
PCM_A[4]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14 2013-08-06
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART,CI Slot 1 10
Copyright © 2014 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
<HDMI/MHL> <COMPONENT> <SPDIF>
JK208
VA211
PPJ234-22
VA208
[YL/GN]FIX +3.3V
VA212
R251
1 75
5V_DET_HDMI_2
5V_HDMI_3 [YL/GN]SWITCH SPDIF-JACK-FOXCONN
COMP2_Y+ R259 SPDIF-JACK-SOLTEAM
3 10K R266 JK204-*1
BODY_SHIELD AV_CVBS_DET JK204
[YL/GN]SHUNT 1K JST1223-001 2F01TC1-CLM97-4F
2
VA210
20 GND GND 1
[BL]EARTH
1
+5V
Fiber Optic
R252
Fiber Optic
R209 100 R265
HPD4 4 75 10K
19 R238
1.8K [BL]SWITCH COMP2_DET VCC VCC 2
2
COMP2_Pb+
18 R244 5
3.3K R267 C219
VA209
[RD1]EARTH 1K 0.1uF R285
17 D201 R231 VINPUT 16V 100 VIN
ESD_HDMI R253 3
3
33 6 75 SPDIF_OUT
DDC_SDA_4
4
16 5V_HDMI_3 +5V +3.3V_ST [RD1]SWITCH 4
COMP2_Pr+ C220
DDC_SCL_4 10pF
8 FIX_POLE 50V
SHIELD
15 R246
33 [RD1]SHUNT
A1
A2
14
A1
A2
ESD_HDMI_SEMTECH 7
COMP2_L_IN
CEC_REMOTE MMBD6100 MMBD6100 [WH]SWITCH R256 10K
13 D212
1 10
VA216
D211
1000pF
9 R254
CK-_HDMI3 470K R262
C204
C
12 [RD2]SHUNT 12K
50V
2 9
CK+_HDMI3 10
11 COMP2_R_IN
10
CK+ 3 8 [RD2]SWITCH R257 10K
D0- 4 7 11 R255
1000pF
VA217
9 [RD2]FIX R263
D0-_HDMI3 R247 R248 470K 12K
C205
50V
8
D0_GND 5 6 2.7K 2.7K 12
D0+_HDMI3
D0+
7 IC208 DDC_SDA_4
6
D1- RCLAMP0524PA
D1_GND ESD_HDMI_SEMTECH DDC_SCL_4
5 1 10
D1+ D1-_HDMI3
4 2 9
D2- D1+_HDMI3
3 3 8
D2_GND
2
1
D2+
4 7
D2-_HDMI3 <SIDE USB>
5 6
D2+_HDMI3
+5V_USB
IC209 JK203
JK201 RCLAMP0524PA
MHL_CD_SENSE <AV (Growth & SCA)> 3AU04S-305-ZC-(LG)
READY ZD200 READY
C206 SD05 C200 C201 C230
D210 R222 0.1uF 10uF 10uF
0.047uF 5V 16V 10V 10V
300K
1
5.6V 25V GROWTH
USB DOWN STREAM

READY
MHL Spec JK202
PPJ231-01
2
SIDE_USB_DM
AV2_R_IN1 R286
4 0 GROWTH AV2_R_IN
R287
3
SIDE_USB_DP
5 AV2_L_IN1 0 GROWTH
<CEC> R203
AV2_L_IN
4
7 0 GROWTH AV2_CVBS_DET
D213
5
R234
R268 8 0 GROWTH RCLAMP0502BA
100 AV/SC1_CVBS_IN
CEC_REMOTE CEC_REMOTE_S7
READY
6 R230
75
GROWTH
<FOR COMMERCIAL>
<RS232C> +3.3V_ST <Mstar Debug 4P>

P602
12507WS-04L
+3.3V_ST 3
4
JP241
R278 R279
10K 10K
PM_TXD
R283 22 +3.3V_ST
MAX3232
C229
R284 22 PM_RXD 0.1uF P603
IC206 16V 12505WS-04A00
MAX3232CDR 1
VCC MAX3232
C1+
16 1 MAX3232 3
RGB_DDC_SCL
C228
4
0.1uF RGB_DDC_SDA
GND V+ 16V 5
15 2
USA
R277 C225
100 DOUT1 C1- 0.1uF
14 3 16V
MAX3232
USA
R276 100 RIN1 C2+
13 4 MAX3232
C226
0.1uF
ROUT1 C2- 16V
12 5
USA
DIN1 V-
6 M6 11 6
1 M1 DIN2 DOUT2
10 7
3 M3_DETECT
ROUT2 RIN2
9 8
MAX3232
4 M4
C227
0.1uF
5 M5_GND 16V
PEJ038-4G6
JK214

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK INTERFACE
2 10

<L14 TUNER T2/C/S2> <+3.3V_LNA>
+3.3V_TU +3.3V_LNA
L300
UBW2012-121F
C319 C320 C322

22uF 0.1uF 22uF
TU_KR 10V 16V 10V
TU300-*1
TDJH-H101F
TU300 TU302 TU301
1
B1[+3.3V]
NC_1
TDJH-G101D TDJM-K101F TDJM-G101D
2
RF_SWITCH_CTL
3
IF_AGC DVB-T/C_Tuner TU_CO DVB-T2/C/S2_Tuner +3.3V_LNA R322
close to Tuner 1K
SCL RF_SWITCH_CTL
4
SDA B1[+3.3V] B1[+3.3V] B1[+3.3V] C312 R323
5 1 1 1
RF_SWITCH_CTL 0.1uF
16V
20K
RF_SWITCH_CTL
IF[P]
6 C307
IF[N] NC_1 RF_SW_CTL NC_1 100pF
0.1uF
C324
7 2 2 2 50V
NC_2
8 should be guarded by ground
NC_3 IF_AGC AIF_AGC AIF_AGC
9 3 3 3
+3.3V_TU
C306 IF_AGC_MAIN
0.1uF
A1 B1 SCL SCL_RF SCL_RF 16V R306 R310 R312
A1 B1 4 4 4
0 R309 33 1K 1K
47 TU_SCL
SDA SDA_RF SDA_RF

C308
47pF
SHIELD 5 5 5 50V R308 33
TU_SDA
C309
IF[P] AIF[P] AIF[P] R304 47pF
6 6 6 10 50V
IF_P_MSTAR
IF[N] AIF[N] AIF[N]

7 7 7 IF_N_MSTAR
NC_2 NC_1 NC_2 R305

8 8 8 C327
C328
10
READY READY
NC_3 NC_2 NC_3 10pF 10pF
9 9 9
NC_3 NC_4
10 10 +3.3V_TU
A1 B1 NC_4 B2[+3.3V]
A1 B1 11 11 C300 C301
47 ERROR ERROR
100pF
50V
0.1uF F_NIM
16V AR300 0
12 12
TU_GND_B
TU_GND
FE_TS_ERR
GND_1 GND_1
BUF1_FE_TS_CLK
SHIELD 13 13
BUF1_FE_TS_SYN
BUF1_FE_TS_VAL_ERR
MCLK MCLK
14 14
SYNC SYNC
15 15
VAILD
<+3.3V_S2_DE>
16 VALID
16 BUF1_FE_TS_DATA[0-7]
D0 D0
F_NIM
AR301 0
17 17 BUF1_FE_TS_DATA[0] +3.3V_TU +3.3V_S2_DE
BUF1_FE_TS_DATA[1]
D1 D1 BUF1_FE_TS_DATA[2]
18 18 BUF1_FE_TS_DATA[3] F_NIM
TU303 D2 D2
L301
BLM18PG121SN1D
19 19
TDJK-T101F D3
C321
0.1uF
F_NIM
C323
F_NIM
C326
20 D3 16V 10uF 0.1uF
TU_BR_PA 20 10V 16V
D4 D4
F_NIM
AR302 0
B1[+3.3V] 21 21 BUF1_FE_TS_DATA[4]
1 D5 BUF1_FE_TS_DATA[5]
22 D5 BUF1_FE_TS_DATA[6]
GND seperation for DVB-T2, SVBTVD tuner
RF_S/W_CTL 22 BUF1_FE_TS_DATA[7]
2
TU_GND
D6 D6
IF_AGC 23
DVB-T/C_Tuner
23
3
0 READY
0 READY
0 READY
0 READY
0 READY
D7 D7
R324
R325
R326
R327
R328
R329
SCL 24 24
0
4 RESET_DEMOD F_NIM +3.3V_S2_DE
25 RESET_DEMOD R300
SDA 25 10
DEMOD_RESET
5 B2[+3.3V]
F_NIM
C302
26 B3[+3.3V] 0.1uF
IF[P] 26 16V
6 SCL_DEMOD
F_NIM
C310
F_NIM
C313
SCL_DEMOD F_NIM +3.3V_S2_DE 100pF 0.1uF
IF[N] 27 27 R301 22 50V 16V
DEMOD_SCL READY
7 B3[+1.1V]
C303
20pF R330
2.2K
28 B4[+1.1V] 50V +1.2V_TU
NC_1 28 F_NIM
8 NC_5 F_NIM
C311
100pF
50V
C314
0.1uF
16V
29 F22_OUTPUT R302 +3.3V_S2_DE F_NIM F_NIM
NC_2 29 51
LNB_TX
9 SDA_DEMOD
30 SDA_DEMOD F_NIM
R303 22
READY
R331
30 C304 DEMOD_SDA 2.2K
TUNER OPT1 OPT2 OPT3 OPT4
20pF
50V
LNB F_NIM
A1 B1 TU_GND_B
31 LNB_OUT TU300 TDJH-G101D DVB-T/C HNIM X W/O AD
A1 B1 A1 B1
C305
0.1uF
16V
A1 B1 GND F_NIM
X
47 32 TU300-1 TDJH=H101F ATSC HNIM W/O AD
47
TU301 TDJM-G101D DVB-S2/T2 HNIM X W/O AD
SHIELD
SHIELD A1 B1
A1 B1 TU302 TDJM-K101F DVB-T2
TU_GND
47
TU_GND_B
TU_GND
TU_GND_B
TU303 TDJK-T101F
TU_GND
SBTVD
TU_GND_B
47

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Tuner
3 10
TUNER

<HDMI& AV/COMP > <GPIO & CI> <VCC &GND> IC1202
LGE2132(M1A_256M)
IC1202 IC1202
LGE2132(M1A_256M) LGE2132(M1A_256M)
R4 NON_BRAZIL U3
AVDD_AU33 AVDD_AU33 AUVRM AUVRM
NON_BRAZIL NON_BRAZIL L11 A6
CI_TS_DATA[0-7] AVDD_DDR0_CLK GND_1
M4 T6 DTV/MNT_VOUT +3.3V Y1 V10 L13 A13
ARC0 CVBSOUT1 LNB_CTL GPIO78 TS0CLK/GPIO92 CI_TS_DATA[0] CI_TS_CLK AVDD_DDR1_CLK GND_2
W7 V5 W4 T14 M11 A15
D0-_HDMI3 RXC0N CVBS0 GPIO79 TS0DATA[0]/GPIO82 CI_TS_DATA[1] AVDD_DDR0_CMD GND_3
Y8 U5 0.047uF C448 33 R425 for SYSTEM EEPROM T13 K13 A18
D0+_HDMI3 RXC0P CVBS1 AV/SC1_CVBS_IN R485 R486 TS0DATA[1]/GPIO83 CI_TS_DATA[2] AVDD_DDR1_CMD GND_4
W8 T5 0.047uF C449 33 R426 10K 10K K17 U13 +1.5V_DDR C5 B12
D1-_HDMI3 RXC1N CVBS2 COMP2_Y+ I2C_SCL I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84 CI_TS_DATA[3] AVDD_DDR0_D_1 GND_5
Y9 V4 READY READY J15 V15 K12 B14
D1+_HDMI3 RXC1P VCOM 0.047uF C413 68 R481 I2C_SDA I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85 CI_TS_DATA[4] AVDD_DDR0_D_2 GND_6
D2-_HDMI3
AA9 I2S_I/F DEMOD_I2C U8 U12 L12 B16
RXC2N DEMOD_SDA SDAM2/GPIO55 TS0DATA[4]/GPIO86 CI_TS_DATA[5] AVDD_DDR0_D_3 GND_7
W9 E4 T7 V13 C6 B17
D2+_HDMI3 RXC2P I2S_OUT_BCK/GPIO165 AUD_SCK DEMOD_SCL SCKM2/GPIO56 TS0DATA[5]/GPIO87 CI_TS_DATA[6] AVDD_DDR1_D_1 GND_8
AA7 F4 U7 U14 K14 B19
CK-_HDMI3 RXCCKN I2S_OUT_MCK/GPIO163 AUD_MASTER_CLK_0 P_SCL SCKM0/GPIO58 TS0DATA[6]/GPIO88 CI_TS_DATA[7] AVDD_DDR1_D_2 GND_9
Y7 F7 22 R404 V7 T11 BUF1_FE_TS_DATA[0-7] L14 B20
CK+_HDMI3 RXCCKP I2S_OUT_SD/GPIO166 AUD_LRCH P_SDA SDAM0/GPIO59 TS0DATA[7]/GPIO89 AVDD_DDR1_D_3 GND_10
N2 F5 0 R454 22 R406 F6 T12 B5 C9
CEC_REMOTE_S7 CEC/GPIO6 I2S_OUT_WS/GPIO164 AUD_LRCK AMP_SCL I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91 CI_TS_SYNC AVDD_DRAM_1 GND_11
E3 0 R455 22 R420 G6 V12 B6 C10
DDCDA_CK/GPIO27 MODEL_OPT_7 AMP_SDA I2S_IN_SD/GPIO160 TS0VALID/GPIO90 CI_TS_VAL AVDD_DRAM_2 GND_12
E2 C4 22 R421 AA4 Y14 R8 C21
DDCDA_DA/GPIO28 USB0_DM TU_SCL I2C_SCKM1/GPIO80 TS1CLK/GPIO103 BUF1_FE_TS_CLK AVDD_NODIE AVDD_DVI_USB_MPLL_1 GND_13
W6 Y12 MODEL_OPT_3 Y4 Y16 BUF1_FE_TS_DATA[0] R9 D9
R487 R488
DDC_SCL_4 DDCDC_CK/GPIO31 USB1_DM 10K 10K TU_SDA I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93 BUF1_FE_TS_DATA[1] AVDD_DVI_USB_MPLL_2 GND_14
AA6 B4 READY READY AA15 L7 E20
DDC_SDA_4 DDCDC_DA/GPIO32 USB0_DP SIDE_USB_DM TUNER_I2C TS1DATA[1]/GPIO94 VDD33 AVDD_MOD_1 GND_15
L4 AA12 J6 Y13 BUF1_FE_TS_DATA[2] L8 F9
HOTPLUGA/GPIO23 USB1_DP SIDE_USB_DP AV_CVBS_DET ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95 BUF1_FE_TS_DATA[3] AVDD_MOD_2 GND_16
Y6 K6 AA16 P8 F11
HPD4 HOTPLUGC/GPIO25 AV2_CVBS_DET EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96 AVDD_NODIE AVDD_NODIE GND_17
F1 J2 W12 BUF1_FE_TS_DATA[4] K9 F13
RXA0N BIN0M TS1DATA[4]/GPIO97 VDD33 AVDD_PLL GND_18
G3 J3 EU C418 68 EU R428 G7 AA13 BUF1_FE_TS_DATA[5] R5 F15
0.047uF
RXA0P BIN0P SC_DSUB_B+ COMP2_DET I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98 BUF1_FE_TS_DATA[6] AVDD_DMPLL AVDD3P3_DMPLL GND_19
G1 K3 0.047uF EU C419 33 EU R429 W14 +1.10V_VDDC P11 F17
RXA1N GIN0M TS1DATA[6]/GPIO99 BUF1_FE_TS_DATA[7] AVDDL_MOD GND_20
G2 J1 0.047uF EU C416 68 EU R437 J4 W13 +1.10V_VDDC C7 F19
RXA1P GIN0P SC_DSUB_G+ DEMOD_RESET ET_COL/GPIO60 TS1DATA[7]/GPIO100 DVDD_DDR_1 GND_21
H3 K2 0.047uF EU C417 33 EU R438 J5 Y15 M13 F21
RXA2N RIN0M MODEL_OPT_0 ET_TXD[1]/GPIO61 TS1SYNC/GPIO102 BUF1_FE_TS_SYN 1uF DVDD_DDR_2 GND_22
H2 K1 0.047uF EU C414 68 EU R435 W15 R6 G8
RXA2P RIN0P SC_DSUB_R+ TS1VALID/GPIO101 BUF1_FE_TS_VAL_ERR DVDD_NODIE GND_23
F3 M6 0.047uF EU C415 33 EU R436 H19 A7 G9
RXACKN HSYNC0 MODEL_OPT_1 LCK/GPIO194 C411 DVDD_RX_1_1 GND_24
F2 L6 G20 B3 R414 33 M12 G10
RXACKP VSYNC0 SC_ID_DSUB_HSYNC MODEL_OPT_2 LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13 /SPI_CS DVDD_RX_1_2 GND_25
G19 A3 R407 33 B7 G11
SC_FB_DSUB_VSYNC /MHL_OCP_DET LHSYNC/GPIO196 PM_SPI_SCK/GPIO1 SPI_SCK DVDD_RX_2_1 GND_26
U4 L2 G21 A4 R405 22 M14 G12
EAR_OUTL BIN1M AMP_MUTE LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0 EU SCART1_MUTE DVDD_RX_2_2 GND_27
T4 L3 C3 N11 G13
EAR_OUTR BIN1P PM_SPI_SDI/GPIO2 SPI_SDI +1.10V_VDDC VDDC_1 GND_28
2.2uF C403 P2 M1 J17 A2 R413 33 N12 G14
AV/SC1_L_IN AUL1 GIN1M UART2_RX/GPIO69 PM_SPI_SDO/GPIO3 SPI_SDO VDDC_2 GND_29
R2 M2 J16 N13 G15
AUL2 GIN1P SC1/COMP1_DET UART2_TX/GPIO70 VDDC_3 GND_30
2.2uF C456 T1 N1 E8 B1 N14 G16
COMP2_L_IN AUL3 RIN1M MHL_OCP_EN UART3_TX/GPIO52 RP VDDC_4 GND_31
2.2uF C404 R3 N3 D7 C2 N15 G17
AV/SC1_R_IN AUR1 RIN1P /AMP_RESET UART3_RX/GPIO53 TN VDDC_5 GND_32
R1 M3 U6 C1 P12 G18
AUR2 SOGIN1 MODEL_OPT_4 GPIO46[CTS] TP VDDC_6 GND_33
2.2uF C458 T3 0.047uF C437 68 R433 V6 B2 P13 H7
COMP2_R_IN AUR3 COMP2_Pb+ RF_SWITCH_CTL GPIO47[RTS] RN VDDC_7 GND_34
U2 0.047uF C439 33 R434 K15 P14 H8
SCART1_Lout AUOUTL0 UART_TXD UART1_TX/GPIO48 VDDC_8 GND_35
V3 0.047uF C430 68 R445 L16 D2 L9 H9
SCART1_Rout AUOUTR0 COMP2_Y+ UART_RXD UART1_RX/GPIO49 SPDIF_IN/GPIO161 5V_DET_HDMI_2 VDD33 VDDP GND_36
T2 0.047uF C433 33 R446 D1 H10
AUVAG SPDIF_OUT/GPIO162 SPDIF_OUT GND_37
0.047uF C428 68 R443 H5 AA10 H11
1uF 4.7uF COMP2_Pr+ USB1_CTL ET_TX_EN/GPIO63 AVDD5V_MHL AVDD5V_MHL GND_38
C421 C422 0.047uF C429 33 R444 K5 D8 H12
MODEL_OPT_5 ET_RXD[0]/GPIO65 HWRESET SOC_RESET GND_39
MODEL_OPT_6 K4 E5 H13
BLM18SG121TN1D ET_MDC/GPIO66 IRIN/GPIO5 IR GND_40
AUVRM USB1_OCD H6 G4 22 R415 H14
L403 ET_MDIO/GPIO67 DDCA_CK/UART0_RX RGB_DDC_SCL GND_41
CI_DET L5 G5 22 R416 H15
PCM_A[0-14] ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX RGB_DDC_SDA +3.3V GND_42
H16
PCM_A[0] GND_43
U17 J18 H17
PCM_A[1] PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71 GND_44
R18 K18 H18
BLM18PG121SN1D
V17 K16 J7
R16 L18 J8
PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74 GND_47
0.1uF
PCM_A[4] U16 L17 AR400 J9
L410
22 NON_A_DEMODE
C468
PCM_A[5] PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75 PCM_5V_CTL GND_48
T17 AGC 1.25V J10
<BRAZIL OPT> BRAZIL
IC1202-*1
LGE2131(M1A_128M)
PCM_A[6]
PCM_A[7]
W18
U20
PCMADR[5]/NF_AD[5]/GPIO106
PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
T8
T9
PF_ALE 100 OHM SERIAL
A_DEMODE 0ohm
GND_49
GND_50
J11
J12
U3
A6
AUVRM AVDD_AU33
R4
L11
PCM_A[8] PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142 /PF_CE0 GND_51
BRAZIL
A13
A15
GND_1
GND_2
GND_3
AVDD_DDR0_CLK
AVDD_DDR1_CLK
AVDD_DDR0_CMD
L13
M11 Y19 U9 J13
IC1202-*1
LGE2131(M1A_128M)
A18
B12
B14
GND_4
GND_5
AVDD_DDR1_CMD
AVDD_DDR0_D_1
K13
C5
K12
PCM_A[9] PCMADR[8]/GPIO113 NF_CLE/GPIO141 /PF_CE1 GND_52
Y1 V10
B16
B17
GND_6
GND_7
GND_8
AVDD_DDR0_D_2
AVDD_DDR0_D_3
AVDD_DDR1_D_1
L12
C6 AA19 U11 R469 J14
W4
GPIO78
GPIO79
TS0CLK/GPIO92
TS0DATA[0]/GPIO82
T14
T13
B19
B20
C9
GND_9
GND_10
AVDD_DDR1_D_2
AVDD_DDR1_D_3
K14
L14
B5
PCM_A[10] PCMADR[9]/GPIO115 NF_RBZ/GPIO147 /F_RB 10K GND_53
K17
J15
U8
I2C_SCKM3/I2C_DDCR_CK/GPIO77
I2C_SDAM3/I2C_DDCR_DA/GPIO76
TS0DATA[1]/GPIO83
TS0DATA[2]/GPIO84
TS0DATA[3]/GPIO85
U13
V15
U12
C10
C21
GND_11
GND_12
GND_13
AVDD_DRAM_1
AVDD_DRAM_2
AVDD_DVI_USB_MPLL_1
B6
R8 AA20 V9 Close to MSTAR K8
T7
U7
SDAM2/GPIO55
SCKM2/GPIO56
TS0DATA[4]/GPIO86
TS0DATA[5]/GPIO87
V13
U14
D9
E20
F9
GND_14
GND_15
AVDD_DVI_USB_MPLL_2
AVDD_MOD_1
R9
L7
L8
PCM_A[11] PCMADR[10]/GPIO119 NF_REZ/GPIO144 /PF_OE GND_54
V7
F6
SCKM0/GPIO58
SDAM0/GPIO59
TS0DATA[6]/GPIO88
TS0DATA[7]/GPIO89
T11
T12
F11
GND_16
GND_17
AVDD_MOD_2
AVDD_NODIE
P8
W21 U10 K10
G6
AA4
I2S_IN_BCK/GPIO159
I2S_IN_SD/GPIO160
TS0SYNC/GPIO91
TS0VALID/GPIO90
V12
Y14
BRAZIL
IC1202-*1
F13
F15
GND_18
GND_19
AVDD_PLL
AVDD3P3_DMPLL
K9
R5
PCMADR[11]/GPIO117 NF_WEZ/GPIO145 /PF_WE R471 100 GND_55

Y4
I2C_SCKM1/GPIO80
I2C_SDAM1/GPIO81
TS1CLK/GPIO103
TS1DATA[0]/GPIO93
Y16 LGE2131(M1A_128M) F17
F19
GND_20
GND_21
AVDDL_MOD
DVDD_DDR_1
P11
C7
PCM_A[12] V20 T10 K11
J6
K6
ET_TXD[0]/GPIO62
TS1DATA[1]/GPIO94
TS1DATA[2]/GPIO95
AA15
Y13
AA16 E11
F21
G8
GND_22
GND_23
DVDD_DDR_2
DVDD_NODIE
M13
R6
IF_AGC_MAIN
G7
EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
TS1DATA[4]/GPIO97
W12
AA13
B_DDR3_A[0]
B_DDR3_A[1]
F12
D10
G9
G10
G11
GND_24
GND_25
DVDD_RX_1_1
DVDD_RX_1_2
A7
M12
B7
PCM_A[13] PCMADR[12]/GPIO109 NF_WPZ/GPIO199 /PF_WP GND_56
J4
I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98
TS1DATA[6]/GPIO99
W14
W13
B_DDR3_A[2]
B_DDR3_A[3]
B10
E15
G12
GND_26
GND_27
DVDD_RX_2_1
DVDD_RX_2_2
M14
Y17 C469 L10
J5
ET_COL/GPIO60
ET_TXD[1]/GPIO61
TS1DATA[7]/GPIO100
TS1SYNC/GPIO102
Y15
W15
B_DDR3_A[4]
B_DDR3_A[5]
B11
F14
G13
G14
GND_28
GND_29
VDDC_1
VDDC_2
N11
N12
PCMADR[13]/GPIO112 AR401 GND_57

H19
G20
G19
LCK/GPIO194
LDE/GPIO195
TS1VALID/GPIO101
PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
B3
A3
B_DDR3_A[6]
B_DDR3_A[7]
B_DDR3_A[8]
C11
D14
A12
G15
G16
G17
G18
GND_30
GND_31
GND_32
VDDC_3
VDDC_4
VDDC_5
N13
N14
N15
P12
PCM_A[14] V18 W2 22 0.047uF M5
LHSYNC/GPIO196 PM_SPI_SCK/GPIO1 B_DDR3_A[9] GND_33 VDDC_6
G21 A4 F16 H7 P13
J17
LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
PM_SPI_SDI/GPIO2
C3
A2
B_DDR3_A[10]
B_DDR3_A[11]
D13
D15
H8
GND_34
GND_35
VDDC_7
VDDC_8
P14
PCM_D[0-7] PCMADR[14]/GPIO111 IF_AGC 25V GND_58

J16
E8
UART2_RX/GPIO69
UART2_TX/GPIO70
UART3_TX/GPIO52
PM_SPI_SDO/GPIO3
RP
B1
B_DDR3_A[12]
B_DDR3_A[13]
B_DDR3_A[14]
C12
E13
H9
H10
H11
GND_36
GND_37
GND_38
VDDP
AVDD5V_MHL
L9
AA10
R419 V19 W1 M7
D7
U6
V6
UART3_RX/GPIO53
GPIO46[CTS]
TN
TP
C2
C1
B2
B_DDR3_BA[0]
A9
D16
H12
H13
GND_39
GND_40
PCM_D[0-7] /PCM_CD PCMCD_N/GPIO135 SIFM GND_59
K15
L16
GPIO47[RTS]
UART1_TX/GPIO48
UART1_RX/GPIO49
RN
SPDIF_IN/GPIO161
D2
D1
B_DDR3_BA[1]
B_DDR3_BA[2]
A10
C13
BRAZIL
H14
H15
H16
GND_41
GND_42
GND_43
22 EU W19 W3 M8
PCM_D[0] /PCM_CE
H17
H5
K5
ET_TX_EN/GPIO63
SPDIF_OUT/GPIO162
D8
B_DDR3_MCLK
B_DDR3_MCLKZ
B13
E17
IC1202-*1
LGE2131(M1A_128M) H18
J7
GND_44
GND_45 PCMCE_N/GPIO120 SIFP GND_60
K4
H6
L5
ET_RXD[0]/GPIO65
ET_MDC/GPIO66
ET_MDIO/GPIO67
HWRESET
IRIN/GPIO5
DDCA_CK/UART0_RX
E5
G4
G5
B_DDR3_MCLKE
B_DDR3_ODT
B8
C8 M4 T6
J8
J9
J10
GND_46
GND_47
GND_48
U18 V2 M9
U17
ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX
J18
B_DDR3_RASZ
B_DDR3_CASZ
B9
D11
W7
Y8
ARC0
RXC0N
CVBSOUT1
CVBS0
V5
U5
J11
J12
GND_49
GND_50
PCM_D[1] PCMDATA[0]/GPIO131 IM ANALOG SIF GND_61
R18
V17
R16
PWM0/GPIO71
PWM1/GPIO72
PWM2/GPIO73
K18
K16
L18
B_DDR3_WEZ
B_RESET
F10
W8
Y9
AA9
RXC0P
RXC1N
RXC1P
CVBS1
CVBS2
VCOM
T5
V4 BRAZIL
J13
J14
K8
GND_51
GND_52
GND_53
V16 V1 M10
U16
T17
PWM3/GPIO74
PWM4/GPIO75
L17
B_DDR3_CS0
D12 W9
AA7
RXC2N
RXC2P I2S_OUT_BCK/GPIO165
E4
F4
IC1202-*1
LGE2131(M1A_128M) K10
K11
GND_54
GND_55
PCM_D[2] PCMDATA[1]/GPIO132 IP Close to MSTAR GND_62
W18
U20
Y19
NF_ALE/GPIO146
NF_CEZ/GPIO142
T8
T9
U9
B_DDR3_DQSL
B_DDR3_DQSU
A19
B18
Y7
N2
E3
RXCCKN
RXCCKP
CEC/GPIO6
I2S_OUT_MCK/GPIO163
I2S_OUT_SD/GPIO166
I2S_OUT_WS/GPIO164
F7
F5
U19 D5
L10
M5
M7
GND_56
GND_57
GND_58
W17 N4
AA19
AA20
PCMADR[8]/GPIO113
PCMADR[9]/GPIO115
NF_CLE/GPIO141
NF_RBZ/GPIO147
U11
V9
B_DDR3_DQML
C16
D21
E2
W6
DDCDA_CK/GPIO27
DDCDA_DA/GPIO28 USB0_DM
C4
Y12
T20
T21
LVA4P/TTL_B[0]/HCONV/GPIO170
LVA4M/TTL_B[1]/E_O/GPIO171
SAR0/GPIO35
SAR1/GPIO36
F8
E7
M8
M9
GND_59
GND_60
PCM_D[3] PCMDATA[2]/GPIO133 GND_63
W21
V20
Y17
PCMADR[10]/GPIO119
PCMADR[11]/GPIO117
PCMADR[12]/GPIO109
NF_REZ/GPIO144
NF_WEZ/GPIO145
NF_WPZ/GPIO199
U10
T10
B_DDR3_DQMU
B_DDR3_DQSBL
C18
C17
AA6
L4
Y6
DDCDC_CK/GPIO31
DDCDC_DA/GPIO32
HOTPLUGA/GPIO23
USB1_DM
USB0_DP
USB1_DP
B4
AA12
T19
R21
R20
LVA3P/TTL_B[2]/FB/GPIO172
LVA3M/TTL_B[3]/OPT_P/GPIO173
LVACKP/TTL_B[4]/MCLK/GPIO174
SAR2/GPIO37
SAR3/GPIO38
SAR4/GPIO39
E6
D6
M10
N4
N5
GND_61
GND_62
GND_63
Y20 AA2 Close to MSTAR N5
V18
PCMADR[13]/GPIO112
PCMADR[14]/GPIO111 IF_AGC
W2
B_DDR3_DQSBU
F1
HOTPLUGC/GPIO25
RXA0N BIN0M
J2 R19
LVACKM/TTL_B[5]/GCLK/GPIO175
LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
W10 N6
GND_64
GND_65
PCM_D[4] PCMDATA[3]/GPIO125 XIN GND_64
DTV_IF
V19 W1 A20 G3 J3 P20 Y10 N7
W19
U18
PCMCD_N/GPIO135
PCMCE_N/GPIO120
PCMDATA[0]/GPIO131
SIFM
SIFP
IM
W3
V2
B_DDR3_DQL[0]
B_DDR3_DQL[1]
B_DDR3_DQL[2]
A16
C19
G1
G2
RXA0P
RXA1N
RXA1P
BIN0P
GIN0M
GIN0P
K3
J1 P19
LVA2M/TTL_B[7]/POL/GPIO177
LVA1P/TTL_G[0]/EPI0+/GPIO178
GPIO_PM[14]/GPIO21
PM_LED/GPIO4
GPIO_PM[0]/GPIO7
P3
Y3
N8
N9
GND_66
GND_67
GND_68
R15 Y2 C462 N6
V16
W17
Y20
PCMDATA[1]/GPIO132
PCMDATA[2]/GPIO133
IP
V1
AA2
B_DDR3_DQL[3]
B_DDR3_DQL[4]
C15
C20
C14
H3
H2
F3
RXA2N
RXA2P
RIN0M
RIN0P
K2
K1
M6
N20
N21
N19
LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
Y5
W11
D3
N10
P4
P5
GND_69
GND_70
PCM_D[5] PCMDATA[4]/GPIO124 XOUT 0.1uF GND_65
R15
AA18
T15
PCMDATA[3]/GPIO125
PCMDATA[4]/GPIO124
PCMDATA[5]/GPIO123
XIN
XOUT
Y2
B_DDR3_DQL[5]
B_DDR3_DQL[6]
B_DDR3_DQL[7]
B21
B15
F18
F2
U4
RXACKN
RXACKP
HSYNC0
VSYNC0
L6
L2
M21
M20
M19
LVA0M/TTL_G[3]/EPI1-/GPIO181
LVB4P/TTL_G[4]/EPI2+/GPIO182
LVB4M/TTL_G[5]/EPI2-/GPIO183
GPIO_PM[4]/GPIO11
GPIO_PM[7]/GPIO14
GPIO_PM[8]/GPIO15
AA3
W5
D4
P6
P7
P9
GND_71
GND_72
GND_73
AA18 IF_N_MSTAR N7
Y21
W20
PCMDATA[6]/GPIO122
PCMDATA[7]/GPIO121
B_DDR3_DQU[0]
B_DDR3_DQU[1]
D19
D17
T4
P2
EAR_OUTL
EAR_OUTR
BIN1M
BIN1P
L3
M1
L20
LVB3P/TTL_G[6]/EPI3+/GPIO184
LVB3M/TTL_G[7]/EPI3-/GPIO185
PWM_PM/GPIO200
PM_UART_TX/GPIO_PM[1]/GPIO8
L15
Y11
P10
P15
GND_74
GND_75
PCM_D[6] PCMDATA[5]/GPIO123 C461 GND_66
V21
Y18
T16
PCMIORD_N/GPIO116
PCMIOWR_N/GPIO114
PCMIRQA_N/GPIO110
B_DDR3_DQU[2]
B_DDR3_DQU[3]
B_DDR3_DQU[4]
E21
E19
D20
R2
T1
R3
AUL1
AUL2
AUL3
GIN1M
GIN1P
RIN1M
M2
N1
N3
L19
K20
K21
LVBCKP/TTL_R[0]/EPI4+/GPIO186
LVBCKM/TTL_R[1]/EPI4-/GPIO187
PM_UART_RX/GPIO_PM[5]/GPIO12
P16
P17
P18
GND_76
GND_77
GND_78
T15 0.1uF N8
R17
T18
PCMOE_N/GPIO118
PCMREG_N/GPIO128
B_DDR3_DQU[5]
B_DDR3_DQU[6]
D18
F20
R1
T3
AUR1
AUR2
RIN1P
SOGIN1
M3 K19
J21
LVB2P/TTL_R[2]/EPI5+/GPIO188
LVB2M/TTL_R[3]/EPI5-/GPIO189 R10
R11
GND_79
GND_80
PCM_D[7] PCMDATA[6]/GPIO122 IF_P_MSTAR GND_67
W16
U15
PCM_RESET/GPIO134
PCMWAIT_N/GPIO105
PCMWE_N/GPIO198
B_DDR3_DQU[7]
ZQ
E9
U2
V3
AUR3
AUOUTL0
AUOUTR0
J20
J19
LVB1M/TTL_R[5]/EPI6-/GPIO191
R12
R13
GND_81
GND_82
GND_83
Y21 N9
T2
AUVAG
H20
LVB0M/TTL_R[7]/EPI7-/GPIO193 R14
K7
GND_84
GND_EFUSE PCMDATA[7]/GPIO121 READY READY GND_68
W20 C425 C426 N10
/PCM_IORD PCMIORD_N/GPIO116 33pF 33pF GND_69
V21 P4
/PCM_IOWR PCMIOWR_N/GPIO114 GND_70
Y18 P5
/PCM_IRQA PCMIRQA_N/GPIO110 GND_71
T16 P6
/PCM_OE PCMOE_N/GPIO118 GND_72
R17 P7
/PCM_REG PCMREG_N/GPIO128 GND_73
T18 P9
PCM_RST PCM_RESET/GPIO134 GND_74
W16 P10
/PCM_WAIT PCMWAIT_N/GPIO105 GND_75
U15 P15
/PCM_WE PCMWE_N/GPIO198 GND_76
P16
GND_77
P17
C451 8pF GND_78
P18
GND_79
R10
GND_2 X-TAL_2
3
GND_80
R447
R11
1M
X400 GND_81
24MHz R12
GND_82
X-TAL_1 GND_1
2
R13
GND_83
C452 8pF R14
GND_84
K7
GND_EFUSE
#POWER FOR MAIN#

<LVDS & PM/SAR>
<VDDC 1.05V> +1.10V_VDDC
<Normal Power 3.3V>
+1.10V_VDDC
+3.3V VDD33 DECAP FOR SOC IC1202
(HIDDEN - UCC) LGE2132(M1A_256M)
L401
0.1uF
0.1uF
0.1uF
BLM18PG121SN1D
0.1uF
0.1uF
0.1uF
0.1uF
10uF
10uF
10uF
1uF
1uF
U19
NON_BRAZIL D5
0.1uF
0.1uF
0.1uF
LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35 KEY1

0.1uF
RXA0-
10uF
C435 10uF
T20 F8
+3.3V_ST RXA0+ LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36 KEY2
C455
C457
C465
C474
C478
C480
T21 E7
C467
C472
C482
C484
C487
C490
RXA1- LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37 PM_MODEL_OPT_0

T19 E6
C434
LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38 17V_DET

C438
C440
C441
RXA1+
R21 D6
C431
<SOC_RESET> RXA2-
RXA2+
R20
LVACKP/TTL_B[4]/MCLK/GPIO174
LVACKM/TTL_B[5]/GCLK/GPIO175
SAR4/GPIO39 VS_DET
R19 W10 0 R482

RXACK- LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20 MHL_CD_SENSE
C4002 SHOULD NEAR MAIN IC P20 Y10
RXACK+ LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21 /VBUS_EN
C497 P3
10uF R408 PM_LED/GPIO4 PM_LED
<STby 3.3V> D400
10V 10
SOC_RESET RXA3-
RXA3+
P19
N20
LVA1P/TTL_G[0]/EPI0+/GPIO178
LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
GPIO_PM[0]/GPIO7
Y3
Y5
/FLASH_WP
100 R417 AC_DET
<DDR3 1.5V> AVDD_NODIE

BAW56 GEANDE
R403 C402
RXA4-
N21
N19
LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
W11
D3
100 R400
DISP_EN
+3.3V_ST RXA4+ LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11 RL_ON 220 R410
100K 0.1uF M21 AA3
L400 RXB0- LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14 5V_ON
M20 W5
BLM18PG121SN1D RXB0+ LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15 VS_ON
M19 D4
C401 C412 RXB1- LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200 LED_R/BUZZ
C407 0.1uF 0.1uF L20 L15
+1.10V +1.10V_VDDC RXB1+ LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8 PM_TXD
10uF Y11
+1.5V_DDR 10V PM_UART_RX/GPIO_PM[5]/GPIO12 PM_RXD
L404 L19
RXB2- LVBCKP/TTL_R[0]/EPI4+/GPIO186
BLM18PG121SN1D AVDD_DMPLL K20
+3.3V RXB2+ LVBCKM/TTL_R[1]/EPI4-/GPIO187
K21
L406 RXBCK- LVB2P/TTL_R[2]/EPI5+/GPIO188
K19
C409 C410 BLM18PG121SN1D RXBCK+ LVB2M/TTL_R[3]/EPI5-/GPIO189
0.1uF J21
10uF
C4003
C4004
0.1uF
0.1uF
0.1uF
RXB3- LVB1P/TTL_R[4]/EPI6+/GPIO190
C436
10uF
C442
C444
C445
C446
C491
C492
10uF
C493
10uF
10V
0.1uF
J20
1uF
C408
C432
C423 RXB3+ LVB1M/TTL_R[5]/EPI6-/GPIO191

0.1uF
0.1uF
0.1uF
10uF 0.1uF J19

10V RXB4- LVB0P/TTL_R[6]/EPI7+/GPIO192
H20
AVDD_AU33 R464 R474 R450 R451 RXB4+ LVB0M/TTL_R[7]/EPI7-/GPIO193
L407 2.2K 2.2K 2.2K 2.2K R452 R453
BLM18PG121SN1D 1.8K 1.8K
I2C_SDA
C424 C427 I2C_SCL
0.1uF 10uF
10V P_SDA
P_SCL
UART_RXD
UART_TXD

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN 4 10

<KEY/IR> <LVDS>
P501
12507WR-10L
TF05-51S
27 MO_HD
P503
R518
52
100
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
IR
1
+3.3V_ST C517 D502
10pF 20V
50V 2
R540 R542
10K 10K R517
100
KEY1 3
R516
100
KEY2 4
20V
20V
C535 C534 5
0.1uF 0.1uF
D504
D503
16V 16V
RXBCK+
RXBCK-
RXACK+
RXACK-
RXB4+
RXB4-
RXB3+
RXB3-
RXB2+
RXB2-
RXB1+
RXB1-
RXB0+
RXB0-
RXA4+
RXA4-
RXA3+
RXA3-
RXA2+
RXA2-
RXA1+
RXA1-
RXA0+
RXA0-
6
104060-8017
R514
22
MO_FHD
LED_R/BUZZ
7
P500
D505
C520
20V
81
10pF
50V
+3.3V_ST 8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
9
C547 C521 D501

0.1uF 1000pF 10
16V 50V 20V
11
470pF
C518
READY
R520 R519
0 0
470pF
C519
READY
UART_TXD
P_SDA
DISP_EN
P_SCL
RXB4+
RXB4-
RXB3+
RXB3-
RXBCK+
RXBCK-
RXB2+
RXB2-
RXB1+
RXB1-
RXB0+
RXB0-
RXA4+
RXA4-
RXA3+
RXA3-
RXACK+
RXACK-
RXA2+
RXA2-
RXA1+
RXA1-
RXA0+
RXA0-
UART_RXD
* LCI: LVDS Connection Indicator
<NAND Flash>
1GBit <SERIAL FLASH> <NVRAM>
IC504 PCM_A[0-7]
H27U1G8F2CTR-BC
IC504-*1 IC504-*4
+3.3V TC58NVG0S3ETA0BBBH TC58NVG1S3HTA00
NC_1 NC_29
NC_1
NC_2
1
2
Toshiba_OS_1G_old 48
47
NC_29
NC_28
NC_1
NC_2
1
2
Toshiba_OS_2G_new
48
47
NC_29
NC_28
OS:256KB
1 48 NC_3 NC_27 NC_3 NC_27
+3.3V
NC_4
NC_5
3
4
46
45
NC_26
I/O8
NC_4
NC_5
3
4
46
45
NC_26
I/O8
+3.3V_ST +3.3V_ST Winbond_OS +3.3V_ST IC503-*1
NC_2 NC_28 NC_6
5 44
I/O7 NC_6
5 44
I/O7
M24256-BRMN6TP
2 47 RY/BY
6
7
43
42
I/O6 RY/BY
6
7
43
42
I/O6
IC505
RE I/O5 RE I/O5
NC_3 NC_27 CE
8
9
41
40
NC_25 CE
8
9
41
40
NC_25 W25Q80BVSSIG E0
1 8
VCC
3 46 NC_7
10 39
NC_24 NC_7
10 39
NC_24
R564 R569
ST_OS
NC_8 NC_23 NC_8 NC_23
NC_4 NC_26
11 38 11 38
27K 4.7K E1 WC
4 45 AR518 VCC_1
VSS_1
12
13
37
36
VCC_2
VSS_2
VCC_1
VSS_1
12
13
37
36
VCC_2
VSS_2 READY C556 2 7
22 NC_9
14 35
NC_22 NC_9
14 35
NC_22 CS VCC 0.1uF E2 SCL
NC_5 I/O7
NC_10
15 34
NC_21 NC_10
15 34
NC_21
/SPI_CS 1 8 3 6
5 44 PCM_A[7] CLE
ALE
16 33
NC_20
I/O4
CLE
ALE
16 33
NC_20
I/O4
17 32 17 32 VSS SDA
WE
18 31
I/O3 WE
18 31
I/O3 4 5
R565 R568 NC_6 I/O6 PCM_A[6] WP
19 30
I/O2 WP
19 30
I/O2
DO[IO1] HOLD[IO3]
1K 4.7K 6 43 NC_11
20 29
I/O1 NC_11
20 29
I/O1
2 7
NC_12
21 28
NC_19 NC_12
21 28
NC_19
SPI_SDO +3.3V
R/B I/O5 PCM_A[5]
NC_13
22 27
NC_18 NC_13
22 27
NC_18
/F_RB 7 42 NC_14
NC_15
23 26
NC_17
NC_16
NC_14
NC_15
23 26
NC_17
NC_16
24 25 24 25
RE I/O4 %WP[IO2] CLK IC503-*2

8 41 PCM_A[4] /FLASH_WP 3 6 SPI_SCK R1EX24256BSAS0A
/PF_OE IC504-*2
TC58NVG1S3ETA00
IC504-*5
H27U2G8F2DTR-BD
CE NC_25 NC_1 NC_29 NC_1 NC_29

R575 A0
1 8
VCC
/PF_CE0 9 40 NC_2
1
2
Toshiba_OS_2G_old 48
47
NC_28 NC_2
1
2
Hynix_OS_2G_new 48
47
NC_28
GND DI[IO0] 33 C552
ATMEL_OS_new
NC_7 NC_24
NC_3
NC_4
3 46
NC_27
NC_26
NC_3
NC_4
3 46
NC_27
NC_26
4 5 SPI_SDI A1
2 7
WP 0.1uF
4 45 4 45
10 39 NC_5
5 44
I/O8 NC_5
5 44
I/O7
C554 NC_6
6 43
I/O7 NC_6
6 43
I/O6
A2
3 6
SCL IC503
NC_8 NC_23 10uF10V RY/BY
7 42
I/O6 R/B
7 42
I/O5
AT24C256C-SSHL-T(Cu)
11 38 RE
CE
8 41
I/O5
NC_25
RE
CE
8 41
I/O4
NC_25 VSS SDA

C550 NC_7
9 40
NC_24 NC_7
9 40
NC_24
4 5
0.1uF VCC_1 VCC_2 NC_8
10 39
NC_23 NC_8
10 39
NC_23
12 37 11 38 11 38
A0 VCC
VCC_1
VSS_1
12 37
VCC_2
VSS_2
VCC_1
VSS_1
12 37
VCC_2
VSS_2
1 8
13 36 13 36
VSS_1 VSS_2 C555 NC_9
14 35
NC_22 NC_9
14 35
NC_22 IC503-*3
13 36 0.1uF NC_10
15 34
NC_21 NC_10
15 34
NC_21
BR24G256FJ-3
CLE
16 33
NC_20 CLE
16 33
NC_20 A1 WP
NC_9 NC_22 ALE
17 32
I/O4 ALE
17 32
I/O3 2 7
Rohm
A0 VCC
14 35 WE
WP
18 31
I/O3
I/O2
WE
WP
18 31
I/O2
I/O1
1 8
ATMEL_OS_old R573
19 30 19 30
NC_10 NC_21
NC_11
20 29
I/O1 NC_11
20 29
I/O0
A1 WP A2 SCL 22
15 34
NC_12
NC_13
21
22
28
27
NC_19
NC_18
NC_12
NC_13
21
22
28
27
NC_19
NC_18
OS:8MB 2 7 3 6 I2C_SCL
CLE NC_20
NC_14
23 26
NC_17 NC_14
23 26
NC_17
A2 SCL R574
16 33 AR519 NC_15
24 25
NC_16 NC_15
24 25
NC_16
IC505-*1
3 6
GND SDA 22
/PF_CE1 22 MX25L8006EM2I-12G GND SDA
4 5 I2C_SDA
4 5
ALE I/O3 PCM_A[3]
PF_ALE 17 32 MX_OS
CS# VCC
IC504-*3 IC504-*6 1 8
WE I/O2 PCM_A[2]
H27U2G8F2CTR TC58NVG0S3HTA00
/PF_WE 18 31 NC_1
1 48
NC_29 NC_1
1
Toshiba_OS_1G_new
48
NC_29
SO/SIO1
2 7
HOLD#
Hynix_OS_2G_old
NC_2 NC_28 NC_2 NC_28
2 47 2 47
WP I/O1 PCM_A[1] NC_3
3 46
NC_27 NC_3
3 46
NC_27
WP# SCLK
/PF_WP 19 30 NC_4
4 45
NC_26 NC_4
4 45
NC_26 3 6
NC_5 I/O7 NC_5 I/O8
5 44 5 44
NC_11 I/O0 PCM_A[0]

NC_6
6 43
I/O6 NC_6
6 43
I/O7
GND
4 5
SI/SIO0
20 29 R/B
RE
7 42
I/O5
I/O4
RY/BY
RE
7 42
I/O6
I/O5
8 41 8 41
CE NC_25 CE NC_25
R556 R567 NC_12 NC_19 NC_7
9 40
NC_24 NC_7
9 40
NC_24
3.3K 1K 21 28 NC_8
10
11
39
38
NC_23 NC_8
10
11
39
38
NC_23
VCC_1 VCC_2 VCC_1 VCC_2

12 37 12 37
NC_13 NC_18 VSS_1
13 36
VSS_2 VSS_1
13 36
VSS_2
22 27 NC_9
14 35
NC_22 NC_9
14 35
NC_22
NC_10 NC_21 NC_10 NC_21

15 34 15 34
NC_14 NC_17 CLE

16 33
NC_20 CLE
16 33
NC_20
23 26 ALE
WE
17 32
I/O3
I/O2
ALE
WE
17 32
I/O4
I/O3
18 31 18 31
WP I/O1 WP I/O2
NC_15 NC_16 NC_11
19 30
I/O0 NC_11
19 30
I/O1
24 25 NC_12
20
21
29
28
NC_19 NC_12
20
21
29
28
NC_19
NC_13 NC_18 NC_13 NC_18

22 27 22 27
NC_14 NC_17 NC_14 NC_17
23 26 23 26
NC_15 NC_16 NC_15 NC_16
24 25 24 25

Memory.LVDS,IR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 5 10

POWER <ST-BY>
<Power Wafer>
+3.3V_ST +5V_ST --> 3.3Vst 5V_ST --> MULTI 5V

P600
SMAW200-H18S1 P_17V
R624
READY
15K
+5V_ST +5V
1 2 +5V_ST Q604
+3.3V_ST DMP2130L
3 4 L600
120OHM
3A Diode_FET
D
5 6 +3.3V_ST
7 8 VS_DET C608 C610
R609 10uF 0.1uF R664
9 10 C606 10V 16V C620 C621 C709 C708 R671
5%
1/16W
100
READY
0.1uF R657 G 0.1uF 0.1uF 10K

R601 R600 11 12 16V +5V_ST IC603 10K 0.01uF 10uF 16V 16V READY
VS_ON READY READY
L602
10K 10K AP7361-Y-13 50V 10V
120
13 14 Vo=0.8*(1+R1/R2)
17V_DET 10K
RL_ON 15 16 AC_DET R616
17 18 C607 C633 3.3K EN OUT
5V_ON 0.1uF 1000pF 1 5 READY
R606
4.7K
16V
10K
4.7K
R639
50V C603
R604
19 C600 2.2uF
GND R619 10V
D602
1uF 2 Q604-*1
5V
25V 1 AO3435
R617 AOS_FET
10K C
D
ADJ/NC IN
3 4 1% R1 B Q603
RL_ON MMBT3904(NXP)
R659
10K G
C601 C602 E
0.1uF 10uF
16V 10V
R618
1.6K
1%
R2
R620
1.6K
1%
<MUTI>
+5V->+3.3V_DDR --> +1.5V_DDR +5V->+3.3V --> +1.2V_TU

+3.3V_DDR
+1.5V_DDR ->+3.3V_TU IC601
+1.2V_TU
+3.3V_TU
Current Limit : 1.1A Current Limit : 1.1A Current Limit : 1.1A AP7361-Y-13
+5V
120-ohm
IC1203 IC608 F_NIM

120-ohm
L604
+5V AZ1117EH-ADJTRG1 AP1117E33G-13 R612

2A
L618
IC605 +3.3V_DDR +3.3V_TU

2A
+3.3V 3.3K EN OUT

AP1117E33G-13 1 F_NIM 5
IN OUT IN ADJ/GND F_NIM
IN ADJ/GND C605 GND
ADJ/GND OUT L606 R615
120-ohm 1uF 2 F_NIM
OUT C616 2A 1
C618 R675 READY 10uF 25V
C611 10uF R602 1 D601 10V F_NIM R613
10uF 10V 6.8K 2.5V ADJ/NC IN 11K
10V 1/16W R662 D600 3 4 1%
1% C619 1
R608
1
10uF 5V R1
10V
R603 C617 READY F_NIM F_NIM
1.2K 10uF C612 C614
C627 1/16W 10V F_NIM 0.1uF 10uF
10uF 1% 16V
10V R614 10V
20K
1% Vo=0.8*(1+R1/R2)
R2
+12V_LNB
BLM18PG121SN1D
P_17V
17V->+12V LNB Max 1.3A
L608
22.0uH
LNB
L617
EAP61606601
LNB IC614
C703 LNB
TPS54231D
LNB
SMAB34
R685
120K
0.1uF
D6000
1%
LNB LNB R1
50V C705 C706
40V
10uF 10uF
BOOT PH 25V 25V
LNB
1 8
VIN GND
2 7
LNB
-->3.12V EN COMP R1
LNB
READY
LNB LNB 3 6 6.8K

R681
1%
16K
C700 C701 LNB

10uF 0.01uF SS VSENSE R686 R2
4 5 C704
25V 50V 470pF 1.6K
LNB 2A
LNB
50V LNB 1%
R692
LNB3.6K
C702
0.01uF C707
50V 15pF
LNB 50V
R610
51K
*NOTE 13
R683
1K
LNB_CTL
Vout=0.8*(1+R1/R2)

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Power 6 10

<HW_OPT> MODEL OPTION
PIN NAME PIN NO. LOW HIGH
AVDD_DDR0 AVDD_DDR0
MODEL_OPT_0 J5 MO_FHD MO_HD
EXT_DDR
MODEL_OPT_1 MO_S/W_AJ
R1201
EXT_DDR
+1.5V_DDR AVDD_DDR0 H19 MO_S/W_NON_AJ

R1232
1K 1%
EXT_DDR
1K 1%
L1202
CB2012PK501T MODEL_OPT_2 G20 MO_DVB_T/C MO_DVB_T2/C/S2
C1202 EXT_DDR
C1201 EXT_DDR
C1204 EXT_DDR
C1203 EXT_DDR
1uF EXT_DDR
1uF EXT_DDR
1uF EXT_DDR
1uF EXT_DDR
A-MVREFDQ A-MVREFCA MODEL_OPT_3 G19
0.1uF
1000pF
MO_M120
0.1uF
MO_M120_NON(Default)
1000pF
1%
EXT_DDR
EXT_DDR
1%
EXT_DDR
R1202
C1218
C1219
C1238
C1241
R1238
10uF
C1251
MODEL_OPT_4 U6 MO_128M+128M_NON MO_128M+128M

1K
+3.3V
1K
MODEL_OPT_5 K5
MO_DVB_T2/C/S2
MO_S/W_TW MO_S/W_EU/AJ
MO_128M+256M
MO_128M+128M
+3.3V
1K
1K
1K
1K
1K
1K
1K
1K
MO_S/W_AJ
MODEL_OPT_6 K4 MO_128M+256M_NON MO_128M+256M
READY
MO_HD
READY
MODEL_OPT_7 L5 MO_DUALSTREAM_NON(Default) MO_DUALSTREAM
R1218
R1220
R1242
R1240
R1241
R1224
R1227
R1216
CLose to DDR3 CLose to Saturn7M IC CLose to DDR3
* Dual Stream is only Korea 3D spec
R1211 READY 100
IF_AGC_SEL MODEL_OPT_0
EAN61859702 MODEL_OPT_1
IC1202 R1213 READY 0
IC1201 LGE2132(M1A_256M) RF_SWITCH_CTL MODEL_OPT_2
NT5CB128M16FP-DI MODEL_OPT_3
NON_BRAZIL MODEL_OPT_4
Nanya_256M MODEL_OPT_5
E11
M8 N3 B_DDR3_A[0] A-MA0 MODEL_OPT_6
A-MVREFCA VREFCA A0 A-MA0 F12
P7 B_DDR3_A[1] A-MA1 MODEL_OPT_7
A1 A-MA1 D10
P3 A-MA2
B_DDR3_A[2]
Memory OPTION
MO_128M+256M_NON
MO_128M+128M_NON
MO_S/W_NON_AJ
A2 A-MA2 B10
1K
H1 N2 B_DDR3_A[3] A-MA3
1K
1K
1K
1K
1K
A-MVREFDQ A-MA3 E15
1K
1K
VREFDQ A3
MO_DVB_T/C
P8 B_DDR3_A[4] A-MA4 Memory Auto
A4 A-MA4 B11 MODEL_OPT_4 MODEL_OPT_6
MO_FHD
EXT_DDR P2 A-MA5
R1203 A5 A-MA5
B_DDR3_A[5]
F14 INT+EXT Det
R1225
L8 R8 B_DDR3_A[6] A-MA6
R1217
R1215
A-MA6 C11
R1219
R1221
R1222
ZQ A6
R1223
R1226
240 R2 B_DDR3_A[7] A-MA7 128M Only 0 0 0
A7 A-MA7 D14
AVDD_DDR0 1% T8 B_DDR3_A[8] A-MA8
A8 A-MA8 A12
B2 R3 B_DDR3_A[9] A-MA9
VDD_1 A9 A-MA9 F16 256M Only
EXT_DDR
C1205 10uF D9 L7 B_DDR3_A[10] A-MA10 1 0 0
VDD_2 A10/AP A-MA10 D13
EXT_DDR
C1207 0.1uF G7 R7 B_DDR3_A[11] A-MA11
VDD_3 A11 A-MA11 D15
EXT_DDR
C1208 0.1uF K2 N7 B_DDR3_A[12] A-MA12 128M+128M 0 1 0
VDD_4 A12/BC A-MA12 C12
EXT_DDR
C1210 0.1uF K8 T3 B_DDR3_A[13] A-MA13
VDD_5 A13 A-MA13 E13
EXT_DDR
C1211 0.1uF N1 B_DDR3_A[14] A-MA14 128M+256M 0 0 1
EXT_DDR VDD_6
C1212 0.1uF N9 M7
EXT_DDR VDD_7 NC_6 A9
C1213 0.1uF R1 B_DDR3_BA[0] A-MBA0
EXT_DDR VDD_8 D16
C1214 0.1uF R9 M2 B_DDR3_BA[1] A-MBA1
VDD_9 BA0 A-MBA0 A-MCK A10
EXT_DDR
R1235
C1215 0.1uF N8 B_DDR3_BA[2] A-MBA2

A-MBA1
1%
BA1
EXT_DDR M3
56
C1216 0.1uF A-MBA2 EXT_DDR C13

BA2
A1 C1209 EXT_DDR B_DDR3_MCLK A-MCK
VDDQ_1 B13
R1236
A8 J7 B_DDR3_MCLKZ A-MCKB
0.01uF E17 <CHIP Config(LED_R/BUZZ)>
1%
VDDQ_2 CK
C1 K7 50V B_DDR3_MCLKE A-MCKE
56
VDDQ_3 CK Boot from SPI CS1N(EXT_FLASH) 1’b0

C9 K9 EXT_DDR
D2
VDDQ_4 CKE A-MCKE
B_DDR3_ODT
B8
A-MODT
Boot from SPI_CS0N(INT_FLASH) 1’b1
VDDQ_5 A-MCKB C8
E9 L2
A/B_DDR3_CS B_DDR3_RASZ
B9
A-MRASB <CHIP Config>
VDDQ_6 CS
F1
VDDQ_7 ODT
K1
A-MODT
B_DDR3_CASZ
D11
A-MCASB (PAD_PM_SPI_DI,PAD_PM_LED,PAD_PWM_PM)
H2 J3 B_DDR3_WEZ A-MWEB
VDDQ_8 RAS A-MRASB AVDD_DDR0 LG-NonOS : 3’b000 51 boot from SPI
H9 K3 LG-OS : 3’b001 MIPS boot from SPI
VDDQ_9 CAS A-MCASB R1231 F10
L3 B_RESET A-MRESETB
WE A-MWEB 10K
J1
NC_1 EXT_DDR D12
J9 T2 B_DDR3_CS0 A/B_DDR3_CS
NC_2 RESET A-MRESETB
L1
NC_3 A19
L9 B_DDR3_DQSL A-MDQSL +3.3V_ST
NC_4 B18
T7 F3 B_DDR3_DQSU A-MDQSU
A-MA14 NC_5 DQSL A-MDQSL
G3
DQSL A-MDQSLB C16
B_DDR3_DQML A-MDML
D21
4.7K
A9 C7 B_DDR3_DQMU A-MDMU
R1243 4.7K
R1245 4.7K
VSS_1 DQSU A-MDQSU
B3 B7
READY
READY
VSS_2 DQSU A-MDQSUB C18
E1 B_DDR3_DQSBL A-MDQSLB
R1244
VSS_3 C17
G8 E7 B_DDR3_DQSBU A-MDQSUB
VSS_4 DML A-MDML
J2 D3 Hynix_256M_New
IC1201-*2 Hynix_256M_old
VSS_5 DMU A-MDMU H5TQ2G63FFR-PBC

IC1201-*1
H5TQ2G63DFR-PBC A20
J8 B_DDR3_DQL[0] A-MDQL0
VSS_6 M8
VREFCA A0
N3
M8 N3 A16 LED_R/BUZZ
M1 E3 A1
A2
P7
P3
VREFCA A0
A1
P7
P3 B_DDR3_DQL[1] A-MDQL1
VSS_7 DQL0 A-MDQL0 H1
VREFDQ A3
N2
P8
H1
VREFDQ
A2
A3
N2 C19
M9 F7 A4
A5
P2 A4
P8
P2 B_DDR3_DQL[2] A-MDQL2
PM_LED
VSS_8 DQL1 A-MDQL1 L8
ZQ A6
A7
R8
R2
L8
ZQ
A5
A6
R8
R2
C15
P1 F2 B2
A8
T8
R3
A7
A8
T8
B_DDR3_DQL[3] A-MDQL3
VSS_9 DQL2 A-MDQL2 D9
VDD_1 A9
L7
B2
VDD_1 A9
R3
C20
P9 F8 G7
K2
VDD_2
VDD_3
A10/AP
A11
R7
N7
D9
G7
K2
VDD_2
VDD_3
A10/AP
A11
L7
R7
N7 B_DDR3_DQL[4] A-MDQL4 SPI_SDI
VDD_4 A12/BC
VSS_10 DQL3 A-MDQL3 K8
N1
VDD_5 A13
T3
K8
VDD_4
VDD_5
A12/BC
A13
T3 C14
T1 H3 N9
VDD_6
VDD_7 NC_5
M7
N1
N9
VDD_6
M7 B_DDR3_DQL[5] A-MDQL5
VSS_11 DQL4 A-MDQL4 R1
R9
VDD_8
VDD_9 BA0
M2
R1
R9
VDD_7
VDD_8
NC_5
M2
B21
T9 H8 BA1
N8
M3
VDD_9 BA0
BA1
N8
B_DDR3_DQL[6] A-MDQL6
VSS_12 DQL5 A-MDQL5 A1
VDDQ_1
BA2
A1
BA2
M3
B15 AUD_MASTER_CLK R1249
4.7K
4.7K
4.7K
G2 A8
C1
VDDQ_2
VDDQ_3
CK
CK
J7
K7
A8
C1
VDDQ_1
VDDQ_2 CK
J7
K7 B_DDR3_DQL[7] A-MDQL7
DQL6 A-MDQL6 C9
D2
VDDQ_4 CKE
K9
C9
VDDQ_3
VDDQ_4
CK
CKE
K9 F18
H7 D2
A-MDQU0
READY
E9
VDDQ_5
VDDQ_6 CS
L2
E9
VDDQ_5
L2 B_DDR3_DQU[0] 200
DQL7 A-MDQL7 F1
H2
VDDQ_7
VDDQ_8
ODT
RAS
K1
J3
F1
H2
VDDQ_6
VDDQ_7
CS
ODT
K1
J3
D19 AUD_MASTER_CLK_0
B1 H9
VDDQ_9 CAS
K3
L3
H9
VDDQ_8
VDDQ_9
RAS
CAS
K3
B_DDR3_DQU[1] A-MDQU1
R1248
R1246
R1247
VSSQ_1 J1
NC_1
WE
J1
WE
L3
D17
B9 D7 J9
L1
NC_2
NC_3
RESET
T2
J9
L1
NC_1
NC_2 RESET
T2
VSSQ_2 DQU0 A-MDQU0 L9
T7
NC_4
F3
L9
NC_3
NC_4
E21
D1 C3 NC_6 DQSL
DQSL
G3
T7
NC_6 DQSL
F3
G3 B_DDR3_DQU[3] A-MDQU3
VSSQ_3 DQU1 A-MDQU1 A9
VSS_1 DQSU
C7
A9
DQSL
C7
E19
D8 C8 B3
E1
VSS_2 DQSU
B7
B3
VSS_1
VSS_2
DQSU
DQSU
B7
VSSQ_4 DQU2 A-MDQU2 G8
VSS_3
VSS_4 DML
E7
E1
G8
VSS_3
E7 D20
E2 C2 J2
J8
VSS_5
VSS_6
DMU
D3
J2
J8
VSS_4
VSS_5
DML
DMU
D3
VSSQ_5 DQU3 A-MDQU3 M1
M9
VSS_7 DQL0
E3
F7
M1
VSS_6
VSS_7 DQL0
E3 D18
E8 A7 P1
VSS_8
VSS_9
DQL1
DQL2
F2
M9
P1
VSS_8 DQL1
F7
F2 B_DDR3_DQU[6] A-MDQU6
VSSQ_6 DQU4 A-MDQU4 P9
T1
VSS_10
VSS_11
DQL3
DQL4
F8
H3
P9
T1
VSS_9
VSS_10
DQL2
DQL3
F8
H3
F20
F9 A2 T9
VSS_12 DQL5
H8
G2
T9
VSS_11
VSS_12
DQL4
DQL5
H8
VSSQ_7 DQU5 A-MDQU5 DQL6
DQL7
H7 DQL6
G2
H7
R1239
G1 B8 B1
B9
VSSQ_1
D7
B1
VSSQ_1
DQL7
VSSQ_8 DQU6 A-MDQU6 D1

D8
VSSQ_2
VSSQ_3
DQU0
DQU1
C3
C8
B9
D1
VSSQ_2
VSSQ_3
DQU0
DQU1
D7
C3 E9 240
G9 A3 E2
VSSQ_4
VSSQ_5
DQU2
DQU3
C2
D8
E2
VSSQ_4 DQU2
C8
C2 ZQ
VSSQ_9 DQU7 A-MDQU7 E8
F9
VSSQ_6
VSSQ_7
DQU4
DQU5
A7
A2
E8
F9
VSSQ_5
VSSQ_6
VSSQ_7
DQU3
DQU4
DQU5
A7
A2
G1 B8
VSSQ_8 DQU6 G1 B8
G9 A3 VSSQ_8 DQU6
VSSQ_9 DQU7 G9
VSSQ_9 DQU7
A3
1%
PM MODEL OPTION
+3.3V_ST
PM_MODEL_OPT_0
HIGH : LCD
LOW :: PDP
R1250
10K
READY
PM_MODEL_OPT_0
R1251
10K

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. External_DDR 7 10

DVB-S2 LNB Part Allegro
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A

3A
+12V_LNB
2A
D804-*1
Max 1.3A
40V
LNB_SX34
need to connect S-tuner D802
LNB D804
3.5A
LNB_OUT TP1 TP5
SP-7850_15
LNB_CTL
LNB
30V 40V
15uH
L801
LNB_TX TP2 DEMOD_SCL TP3 LNB C810
10uF
DEMOD_SDA TP4 25V
C804 C806 C807 C808 LNB
0.01uF 10uF 10uF 10uF
0.1uF
50V 25V 25V 25V
LNB LNB LNB LNB
close to Boost pin(#1)
C809
LNB
close to VIN pin(#15)
C811
[EP]GND
0.1uF
BOOST
GNDLX
50V
NC_3
NC_2
LNB
LX
D801
close to TUNER MBR230LSFT1G
20
19
18
17
16
LNB_OUT
30V VCP 1 15 VIN LNB
D803
LNB C805 LNB THERMAL
0.1uF LNB 2 14 GND R805
21 39K
40V
C800 C801 C802 R802 C803 LNB 50V
18pF D800 18pF 33pF 2.2K 0.22uF NC_1 3 13 VREG
1W LNB 25V IC801 C813 1/16W
LNB LNB LNB LNB 1%
LNB D803-*1 TDI A8303SESTR-T
4 12 ISET
LNB_SX34 LNB
LNB 0.1uF
SIGN10335
40V TDO 5 11 TCAP
0.22uF
10
6
Close to Tuner 9
Surge protectioin
IRQ
SCL
SDA
ADD
TONECTRL
LNB
C812
33
33
R803 33
LNB
LNB
R806
LNB
R804
LNB_TX
DEMOD_SDA
DEMOD_SCL

ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR Satellite LNB 8 10
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.15V_Normal & +5V_USB with OCP
+5V
C902 C903
10uF 10uF
16V
[EP]GND
PGND_2
PGND_1
PGOOD
VIN_2
VIN_1
R905 +5V
READY 100K +1.10V
V7V
C900
100pF
50V C905 L900
24
23
22
21
20
19
0.047uF 4.7uH
EN BST 25V
C901
+3.3V R902 4700pF 1 18
4.7K 50V THERMAL C909 C908
COMP 25 LX_2 R1 22uF 10uF
2 17 C907
R913 10V 10V
READY SS LX_1 2.6K 470pF
R903 3 16 1% 50V
0 ROSC FB
4 IC900 15
READY
R900
READY EN_SW2 TPS65282REGR SW_IN_2 R2
4.7K R901 5 14
USB1_CTL
4.7K
EN_SW1
6
4A 13
SW_IN_1
R914
5.6K
1%
10
11
12
+5V
C906
7
MHL_OCP_EN_OLD 10uF
+5V_USB 10V
FAULT2
FAULT1
SW_OUT2
RLIM
AGND
SW_OUT1
R904 R906
10K 10K
R909 5V_HDMI_3 AVDD5V_MHL
15K
1%
0
R912
R907
R908
D901
MBR230LSFT1G 10
30V C904
READY
R910 10uF
100K 10V
/MHL_OCP_DET
USB1_OCD
Vout=0.8*(1+R1/R2)
+3.3V
R917 R920
2.7K 10K
Q901
E C
MHL_OCP_EN_OLD
Q900 C
R918
10K B R922
B
/VBUS_EN 20K
(Active Low) E R921

10K
Q902 C
R919
10K B
MHL_OCP_EN
(Active High) E

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Dual DC DC 9 10

<AUDIO AMP>
+3.3V +3.3V_AMP
L1002
AMP_COIL_GET AMP_COIL_GET AMP_COIL_GET AMP_COIL_GET
BLM18PG121SN1D L1004-*1 L1005-*1 L1006-*1 L1007-*1
10.0uH 10.0uH 10.0uH 10.0uH
AMP_COIL_TAIYO AMP_COIL_TAIYO AMP_COIL_TAIYOAMP_COIL_TAIYO

L1004-*2 L1005-*2 L1006-*2 L1007-*2
10.0uH 10.0uH 10.0uH 10.0uH
P_17V_AMP P_17V P_17V_AMP_2 P_17V
R1009
L1000 L1001
470
UBW2012-121F UBW2012-121F
C1010 4700pF
AMP_COIL_ABCO Close to Speaker
0.047uF
C1011
L1005
C1000 C1002 10uH
0.1uF 0.1uF
C1012 2200pF
SPK_L+
50V 50V
C1015
0.033uF
50V
R1010
C1008 4700pF P_17V_AMP 18
50V
C1007 R1008 C1025
330pF C1031 C1035
0.047uF 470 50V 0.1uF 2200pF
C1017 C1019
PVDD_AB_2
PVDD_AB_1
0.1uF 10uF 50V 50V
PLL_FLTP
PLL_FLTM
+3.3V_AMP 50V 35V
SSTIMER
VR_ANA
C1029
BST_A
OUT_A
0.47uF
AVSS
PBTL
NC_2
NC_1
C1026
50V
C1032
C1036 SPEAKER_L
330pF 2200pF
0.1uF 50V
[EP] 50V
12
11
10
9
8
7
6
5
4
3
2
1
50V
AVDD 13 48 PGND_AB_2 R1011
18
C1003 R1007 2K A_SEL_FAULT PGND_AB_1
THERMAL
14 47
0.1uF MCLK OUT_B
46
49
16V 15 SPK_L-
R1006 18K OSC_RES 16 45 NC_6 50V L1007
TAS5733
IC1000
1% DVSSO 17 44 NC_5 0.033uF AMP_COIL_ABCO
C1023 10uH
AUD_MASTER_CLK VR_DIG 18 43 BST_B
R1002 PDN BST_C
19 42
AMP_MUTE
100 C1001 C1004 LRCLK 20 41 NC_4 AMP_COIL_ABCO
+3.3V_AMP 4.7uF C1006 50V L1004
1000pF 0.1uF SCLK 21 40 NC_3 0.033uF
10V 10uH
50V SDIN 22 39 OUT_C C1024
SPK_R+
SDA 23 38 PGND_CD_2
R1004 R1005 SCL PGND_CD_1 SPEAKER_R
R1012
1/16W
2.2K 2.2K 24 37
C1033 C1037
C1030
25
26
27
28
29
30
31
32
33
34
35
36
0.1uF 2200pF
18
AUD_LRCK
0.47uF 50V
AUD_SCK 50V 50V
RESET
STEST
DVDD
DVSS
GND
AGND
VREG
GVDD_OUT
BST_D
PVDD_CD_1
PVDD_CD_2
OUT_D
AUD_LRCH C1027
330pF C1038
AMP_SDA P_17V_AMP_2 50V
C1034 2200pF
AMP_SCL 50V
0.1uF
C1028 50V
C1013
C10141uF 25V
0.1uF 330pF
33 R1003
/AMP_RESET 50V
C1018 C1020
0.1uF 10uF
R1013
1/16W
+3.3V_AMP 50V 35V
18
C1005 SPK_R-
ZD1000
0.1uF C1016 0.033uF L1006

16V 50V
5V
READY
10uH
C1009 AMP_COIL_ABCO
0.1uF
16V
WAFER-ANGLE
SPK_L+
4
SPK_L-
3
SPK_R+
2
SPK_R-
1
P1000

ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR Audio amp 10 10
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

L14 Trouble shooting guide
Please check system, after power Off/On one time
1. Power-Up Boot Fail Trouble Shooting

2. No OSD Trouble Shooting
3. Digital TV Video Trouble Shooting
4. Analog TV Video Trouble Shooting
5. Component Video Trouble Shooting
6. RGB Video : N/A
7. AV Video Trouble Shooting
8. HDMI Video Trouble Shooting
9. All Source Audio Trouble Shooting
10. Digital TV Audio Trouble Shooting
11. Analog TV Audio Trouble Shooting
12. Component / RGB / AV Audio Trouble Shooting
13. HDMI Audio Trouble Shooting
14. USB Trouble Shooting
Copyright © 2014 LG Electronics Inc. All rights reserved. LGE Internal Use Only
(Front-end) (System + Scalar)
Serial_Flash NANDFlash
1MB 128MB
DVB-T/C IF
PAL/NTSC DVB-T/C, ATV
FHD/HD
LVDS
IF
IF SPDIF
DVB-T2/C DVB-T/C, ATV
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
(Only support Satellite model) I2S
EXT_IN
Satellite
DVB-S2/T2/C IF HDMI_C
TS[0-7] DVB-T2, S2 USB2.0 Side(1)
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
AV1_LR EXT_IN SCART(AV1)_LR EXT_IN
I2S TAS5733
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
HDMI_Side (C port) Side USB
N Y
Check P600 All Voltage Level
Check Power connector Replace Power board
(3.5/5V_ST)
Y IC600 +3.3V_ST check (MPLL / NODIE)
Check All Voltage Level N Replace one of Bead, IC400

at Bead, RL_ON, IC400 output & Recheck
Check Voltage Level 3.3 at IC603, N Replace of the IC603 N

L602(+3.3V_ST) & Recheck
Check Voltage Level 3.3V at R608 N Replace of the IC605 N

(+3.3V_DDR) & Recheck
Y Check SW Redownload or replace
Check Voltage Level 1.5V N Replace of the IC1203 N

at L604(+1.5V_DDR) & Recheck
Check Voltage Level 3.3V at L606 N Replace of the IC608 N

(+3.3V_TU) & Recheck
N N
Check X400 Clock 24MHz Replace X400
Y Check Main chip and Soc_Reset

Signal from PM GPIO
Check signal transition N N
Maybe Serial Flash Memory problem
at IC505 DC
AC
Y
N
Check signal transition N Maybe NAND Flash Memory or
IC504 IC400 have troubles
Check DDR Memory
Y
/Replace one
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
I2S TAS5733
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
Check P600 N Check GPIO Path of PM
5V_ON(Pin 17)
Check P600 N
VS_ON(Pin 12) Check GPIO Path of PM
Check P600 N Y
VS_ON(Pin 12) Check Power connector Replace Power board
Check 5V Voltage Level N Replace one of L600

at L600 & Recheck
Y
Check P500/P503 N Maybe IC400
(RXAC-), (RXAC+), (RXBC-),
has troubles
(RXBC+), Display Enable
N
Check LVDS Cable Replace Cable
Check PDP Module
Electrical Specifications
Power Supply Sequence
Check CAS
Input Signal Timing Specification
Control Signal Register
It should satisfy the Pixel Clock on CAS.
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
I2S TAS5733
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
Check RF Cable
Check Tuner Power N Replace one of Bead

(1.2, 3.3V) & Recheck * Tuner I2C check
* ChangeTuner type at adjust menu
Y
Check IF Signal waveform and signal N Check IF voltage level : 320~350mV

strength & Quality Maybe Tuner has problems
N
Check TS Signal waveform and Check TS waveform
signal strength & Quality Maybe Tuner has problems
Maybe Mstar IC
has problems
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
I2S TAS5733
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
Check RF Cable
Check Tuner Power Voltage N Replace one of

(3.3V, 1.2V) Bead & Recheck
Check IF Signal waveform and signal N

Maybe Tuner has problems
strength & Quality
Maybe Mstar IC
has problems
5. Component Video Trouble Shooting
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
I2S TAS5733
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
5. Component &SCART Video Trouble Shooting
Check Signal Format

Is it supported signal?
Check Component Cable
N
Check Component Jack JK208 Replace Jack
Y
Check Component Signal
R251/R252/R253
VA28,VA210,VA209
N
R106,R108,R107 Replace one of
VA106,VA103,VA104 Resister& Recheck
(Termination resistor)
Y
Check Component Signal
R433/R434/R445/R446/R443/R444 N
Replace it
R428,R429,R437,R438,R435,R436
Main IC Input
Maybe Mstar IC400

has problems
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
AV1_LR EXT_IN SCART(AV1)_LR EXT_IN I2S_S7R
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
Check Signal Format

Check AV Cable
N
Check Jack JK202/JK208 Replace Jack
N Replace one of
Check CVBS Signal
Resister
R234,R230,R251,425,426
& Recheck
Check Video GND(V COM) N Replace one of

C413, R481
VCOM& Recheck
Maybe Mstar IC400

has problems
8. HDMI Video Trouble Shooting
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
8. HDMI (MHL) Video Trouble Shooting
Check Signal Format

Check HDMI/MHL Cable
Check HDMI Jack N

Replace Jack
JK201
N
If MHL Problem, Replace It & Recheck
Check detecting MHL signal
R222 : 5V, R922: 3.3V, R912:4.9V
Check I2C Signal N

Replace It & Recheck
R231/R246/R247/R248
Maybe Mstar IC400

has problems
Make sure you can’t hear any audio
N
Check Speaker Replace Speaker
N
Check Connector P1000 Replace Connector
N Replace one of N
Check Signal Maybe TAS5733 has problems.
Capacitor, Register
L1004,L1005,L1006,L1007 Replace It
& Recheck
Check IC1000 Power N

17V, 3.3V
Check Reset signal N

R1003
Y * Amp. I2C check
Check Mstar S7R I2S Output N

R406,R420
Maybe Mstar IC1202

has problems
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
N Follow procedure digital TV video

Check video output
trouble shooting
N Maybe Mster internal audio DSP has

Follow procedure All source audio
problems.
trouble shooting
Replace It
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
N Follow procedure analog TV video

Check video output
trouble shooting
N Replace one of IC608,IC601

Check Tuner Power
& Recheck
N
Check SIF Signal Maybe Tuner has problems
N Maybe Mstar audio block has

problems.
trouble shooting < SIF waveform – sample >
Replace It
- Defend on the input signal.
12. Component / RGB / AV Audio Trouble Shooting
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
12. Component / AV Audio Trouble Shooting
N Follow procedure external input

Check Video Output
video trouble shooting
N
Check Jack JK208 / JK202 Replace Jack

problems.
trouble shooting
Replace It
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
N
Follow procedure HDMI video
Check video output
trouble shooting

problems.
trouble shooting
Replace it
1MB 128MB
DVB-T/C IF
FHD/HD
LVDS
IF
IF SPDIF
TS[0-7] TS[0-7]
PAL/NTSC DVB-T2
Main IC
EXT_IN
Satellite
IF
(External Input)
(Audio Out)
<NON-EU> <EU>
AV1 SCART(AV1)
STA380
COMP_LR COMP_LR
& AV2_LR & AV2_LR
Hybrid Hybrid
COMP& AV2 COMP& AV2
(USB)
UI_HW_PORT
Check USB 2.0 Cable
Y
Check USB device
If device is 2.5 inch HDD,
Check power adaptor
N
Check JK203 Replace Jack
Check 5V voltage level N

Replace IC900 & Recheck
Maybe Mstar IC400

has problems. Replace It.
• Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)

LG 50PB560B Chassis PD41C

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Copyright:

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LG 50PB560B Chassis PD41C

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Available Formats

Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 50PB560B 50PB560B-ZA

P/NO : MFL68062601 (1404-REV00) Printed in Korea

SAFETY PRECAUTIONS ......................................................................... 3

EXPLODED VIEW .................................................................................. 15

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

always perform an AC leakage current check on the exposed

2. Requirement for Test

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

4. Module General Specification

Case2 : Function check at the assembly line

(4) Updating is staring.

* Caution : Using ‘power on’ button of the Adjustment R/C ,

* ADC Calibration Protocol (RS232)

50PB560B-Z* - Adjust Sequence

* Caution : Not to push the INSTOP KEY after completion if

COOL 0.276 0.283 11000K 0.002

* Connecting picture of the measuring instrument

* Manual W/B process using adjusts Remote control.

4.5. EDID DATA Auto Download

* Caution : Never connect HDMI & D-sub Cable when EDID

(2) RS-232 command for test LNB

1 Manufacturer ID GSM 1E6D (3) Test result

5.4. Method & Notice

(3) result value

■ Check the method of CI+ Key value (RS232)

(3) result value

7. Download MAC Address, CI+ Key

* Each Chassis has it’s own MAC Address. Please be careful

■ Check the method of RS232C Command

(2) c heck the key download for transmitted command

CMD1 CMD2 Data 0

(1) Put the USB Stick to the USB socket

Only for training and service purposes

Copyright © 2014 LG Electronics. Inc. All rights reserved.

COMP1/AV1/PC AUDIO L/R py

LGE Internal Use Only

D2B_IN R108 SC_DSUB_G+ AV/SC1_L_IN

<CI SLOT> +5V_CI_ON

BUF1_FE_TS_DATA[0-7] /CI_CD1 GND

BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[7] +5V C136 C137 EU

+5V 100 PCM_A[2] 6 15

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2014 LG Electronics Inc. All rights reserved.

USB DOWN STREAM

<RS232C> +3.3V_ST <Mstar Debug 4P>

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2014 LG Electronics Inc. All rights reserved.

C319 C320 C322

SDA SDA_RF SDA_RF

IF[N] AIF[N] AIF[N]

NC_2 NC_1 NC_2 R305

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright © 2014 LG Electronics Inc. All rights reserved.

<BRAZIL OPT> BRAZIL

PCMADR[11]/GPIO117 NF_WEZ/GPIO145 /PF_WE R471 100 GND_55

PCMADR[13]/GPIO112 AR401 GND_57

PCM_D[0-7] PCMADR[14]/GPIO111 IF_AGC 25V GND_58

#POWER FOR MAIN#

LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35 KEY1

* Caution : Using ‘power on’ button of the Adjustment R/C ,

* Caution : Not to push the INSTOP KEY after completion if

* Connecting picture of the measuring instrument

* Caution : Never connect HDMI & D-sub Cable when EDID

7. Download MAC Address, CI+ Key

* Each Chassis has it’s own MAC Address. Please be careful

(2) c heck the key download for transmitted command