Verification of Open-Source Memory Compiler Framework with a Practical PDK
Chao Geng, Daiki Ishikawa, Shoya Kudo, Shigetoshi Nakatake
Dept. of Information and Media Engineering
The University of Kitakyushu
Fukuoka, Japan
e-mail: naka-lab@kitakyu-u.ac.jp
Abstract—An open-source memory compiler has recently
drawn the attention of academic researchers involved in Static
Random Access Memory (SRAM) designs. Since simulation
results for circuits implemented by practical Process Design
Kits (PDKs) have rarely been reported so far, the effectiveness
and the reliability for circuit implementation by compiler still
needs to be further verified. This paper presents an SRAM
circuit implemented in a 0.6m/±2.5V CMOS process with the
compiler framework. We present pre- and post-layout
simulation results with respect to the functionality and various
performance parameters of our SRAM circuit, and the
simulation results are thoroughly analyzed. A summary for
our SRAM circuit demonstrates the effectiveness and the
reliability of the compiler to design an SRAM in a fabricable
technology process, showing a promising result for the
compiler to be verified on a fabricated chip.
Keywords-memory compiler, PDK, SRAM circuit, post-layout
simulation
I. INTRODUCTION
Modern IC designs pay more and more attention to
SRAM circuit as it plays a significant role in optimizing
system performance [1] [2]. Specifically, for the System-on-
Chip (SoC), Application-specific Integrated Circuit (ASIC),
and microprocessor, SRAM is a critical component
embedded with the systems that affects drastically the overall
area and power as well as speed [3] [4]. In the past decades,
several memory-oriented commercial tools have emerged to
customize the SRAM design. However, these tools have the
following limitations: They serve as the black box to users
without knowing the details; they lack flexibility as users
cannot modify the configuration of the base cells; they are
dependent of technology process and thus the portability
over other processes are poor. For the academic researchers
involved in memory related projects, most importantly,
licensing issue is a great obstacle due to the expensive cost.
Although several non-commercial tools are also available,
they either can only generate simply memory structures, or
provide no public releases for methodologies and design
flows.
Aiming to overcome the above limitations, in 2016,
Guthaus et al. developed an open-source memory compiler
[5], referred as to OpenRAM, to meet a variety of
requirements for the sizes, configurations, and technologies
in SRAM designs. OpenRAM provides a framework that
incorporates multiple methodologies for the design
generation (Verilog model, SPICE netlist, GDSII layout
data), characterization (timing, power), and verification
(DRC, LVS, PEX). Its feasibility is demonstrated by SRAM
designs in a generic 45nm technology (FreePDK45) and a
fabricable 0.5m technology (SCMOS). Based on
OpenRAM project, authors in work [6] proposed a novel
differential single-port 12T bitcell with improved read
reliability for high-density and high-speed SRAMs, where
component configurations can be freely customized, and
SRAMs can be easily realized with the help of OpenRAM.
OpenRAM is improved subsequently by several works.
Authors in work [7] proposed a replica-based timing
speculative SRAM to detect read timing failures and to
protect from incorrect write operations, while maintaining
energy- and area-efficient. Aiming to optimize high-
performance word line driver topologies for SRAMs, the
work [8] proposed an analytical optimization methodology
using a delay model that includes gate delay, wire resistance,
and wire capacitance. The work [9] proposed a word-line
buffer insertion optimization algorithm that place and size
the buffers to reduce word line and overall SRAM delay. To
enhance the throughput and flexibility of SRAM, the work
[10] proposed a parameterized bitcell that can support any
combination of read, write, and read-write ports, which in
turn makes OpenRAM suitable for multi-port configurations
and high-performance systems.
OpenRAM has brought about inspiring results to
academic researchers, though, its portability across
technology nodes, effectiveness and reliability to SRAM
design still need to be further verified with a practical PDK.
On the one hand, the existing works and progress made are
all from the same research group, practical PDKs or
fabricable technology processes that they apply are very few
and also FreePDK45 process is non-fabricable, the
effectiveness and the reliability of OpenRAM is less
adequately demonstrated as compared to a mature
commercial memory compiler. On the other hand, simulation
results for SRAM circuits designed with a practical PDK by
OpenRAM have rarely been reported by far. To this end, we
implement an SRAM circuit in a 0.6m/±2.5V CMOS
process with OpenRAM framework. After an SRAM design
is generated from OpenRAM, we import our design into
Cadence for circuit simulation and layout verification with
the tool interface that the framework provides. In this paper,
we present pre- and post-layout simulation results with
respect to the functionality and various performance
parameters of our SRAM circuit. The simulation results are
thoroughly analyzed, which shows a correct function and a
good performance. Furthermore, a summary for the
simulation results and an OPenRAM report demonstrates the
effectiveness and the reliability of OPenRAM framework to
design an SRAM in a fabricable technology process. Our
realized SRAM circuit also contributes to the further
verification of OpenRAM framework by silicon
measurements, after a chip is fabricated.
The rest of the paper is organized as follows. Section Ⅱ
mainly introduces an SRAM architecture and methodologies
used in OpenRAM. Section Ⅲ describes our design flow for
an SRAM circuit based on OpenRAM framework. Section
Ⅳ presents pre- and post-layout simulation results of an
SRAM circuit for the functionality and various performance
parameters. Finally, Section Ⅴ concludes this work.
II. OPENRAM FRAMEWORK
In this section, we mainly introduce an SRAM
architecture and methodology associated with the circuit
implementation in OpenRAM.
A. An SRAM Architecture in OpenRAM
As shown in Fig. 1, the SRAM architecture is composed
of a bitcell array and peripheral circuit arrays including
control logic, address decoder, wordline driver, precharge,
column multiplexer, write driver, and sense amplifier. The
SRAM shown has 4-bit address and 8-bit input/output data.
Note that the bit number for address and data can be set
arbitrarily in OpenRAM. A bitcell array with the word
number, m, and the word size, n, has m×n bitcells. As seen in
Fig. 1 (a), it shows a 16×8 bitcell array, where the horizontal
line is wordline and the vertical line is bitline, each bitcell
placed in a tile has two bitlines.
Figure 1. AN SRAM architecture in OpenRAM.
As seen in Fig.1 (b), OpenRAM adopts a 6T cell (circuit
in black) as the bitcell that is most commonly used in SRAM,
where two inverters (N1, P1, and, N2, P2) are cross-coupled,
and each output of the inverters respectively connects an
access transistor (N3 or N4). The wordline rwwl connects to
the gates of the access transistors and is shared by bitcells in
same row. The bitlines, rwbl and its complement rwbl_bar,
also connect to the access transistors and are shared by
bitcells in same column. The default 6T cell is a single-port
(rw) bitcell as it only supports a read or write operation in an
access time. By adding the circuit in red and the circuit in
blue for a write-only port (w) and a read-only (r) port,
respectively, a 6T cell can be extended to a multi-port bitcell
(rw/w, rw/r, and w/r). The newest version of OpenRAM
provides multi-port bitcell so that an SRAM circuit can be
accessed simultaneously by multiple read or write operations,
such feature is very useful in high-performance SRAMs for
multi-core microprocessors. OpenRAM provides user with a
parameterized bitcell, though, we can replace it with our own
custom-designed one for the performance improvement and
the area efficiency.
Address codes are decoded by an address decoder, and
then wordline driver drives the row select signal and the
associated wordline can be asserted. Fig. 1 (c) shows a 4-16
decoder that can select the associated row from 16 rows.
Precharge (see Fig. 1 (d)) circuit is used to charge the bitlines
of a bitcell to VDD in a read operation. Column multiplexer
(see Fig. 1 (e)) is used to select the associated word when
there are many words in a row, it is an optional module in the
architecture and is usually used in multi-bank SRAM
implementation. Write driver (see Fig. 1(f)) is used to drive
the input data into memory during a write operation and each
bit has one driver. Sense amplifier (see Fig. 1(g)) is a latch-
type amplifier used to sense the voltage swing on the bitlines
during a read operation. The more sensitive it is to the
voltage swing, the less read access time of SRAM.
Control logic and replica bitline receive external signals,
clock signal clk0, chip select signal csb0, and write enable
signal web0. csb0 and web0 are both active low, SRAM
circuit works only if csb0 is in low voltage. Control logic
adopts the Replica Bit Line (RBL) technique to optimize the
Sense Amplifier Enable (SAE) signal timing, and to prevent
read failures.
For a write operation: In a clock cycle, at the time of
positive clock edge, if both csb0 and web0 are low voltage
(GND), address and input datas are captured, and then input
datas are sent to bitlines. When the associated row is selected
by an address decoder and the wordline turns to be high
voltage (VDD), the datas are written into memory cells with
delays from the negative clock edge.
For a read operation: In a clock cycle, at the time of
positive clock edge, if csb0 is low voltage and web0 is high
voltage, address is captured. Then, bitlines are precharged to
VDD and the associated wordline turns to be high voltage as
in the write operation. Assume that storage value in a bitcell
(see 6T cell in Fig. 1 (b)) is 1, i.e., values at nodes Q and
Q_bar are 1 and 0, respectively. The bitline rwbl remains
VDD through the current path from P1 to N3，whereas the
bitline rwbl_bar discharges to GND through the current path
from N4 to N2. Thus, storage value 1 is passed to bitlines by
making rwbl 1 and rwbl_bar 0, respectively. If storage value
is 0, due to the inverse electrical behavior, rwbl and
rwbl_bar would be 0 and 1, respectively. Next, sense
amplifier can sense the values on bitlines as long as there is a work we implement a single-port (rw) 96-bit SRAM circuit
minor voltage difference. Finally, the stored datas in all with 4-bit address (16 words) and 6-bit input/output data (6-
accessed bitcells are simultaneously read out by a word per bit word size), which utilizes a 0.6m/±2.5V CMOS process.
time. Likewise, output datas also have delays from the As we apply our SRAM circuit to a Programmable Logic
negative clock edge. Array (PLA), a large memory size is not our main concern.
B. Methodology Used in OpenRAM for An SRAM Design Besides, this work aims to demonstrate the effectiveness and
reliability of OpenRAM to generate SRAM designs.
Methodology used in OpenRAM for an SRAM design is
Our design requirements are defined in the configuration
shown in Fig. 2. A technology library for PDK needs to be
file as aforementioned in last section. Main challenges are
available before the circuit implementation, it consists of
design migration for base cells from reference technologies
netlist and layout files for base cells, SPICE device models
(FreePDK45 or SCMOS) to our technology, and
for different corners, a tech configuration file in Python,
modification to the tech configuration file. A custom-
along with other Python files for PDK environment setup.
designed library including netlists and layouts is
User can set up the library for a specific technology based on
implemented for base cells like 6T bitcell, D-type flip-flop,
the reference implementations for FreePDK45 and SCMOS
sense amplifier, write driver and tri-gate. Replica bitcell and
technologies. Base cells are essential elements to constitute
dummy bitcell are also designed because RBL technique is
an SRAM which can be premade cells by foundry or
used in OpenRAM for the read reliability improvement.
handmade cells by user. SPICE device models are used in a
During the dynamic generation of SRAM circuit, replica
characterizer for circuit simulation. The tech configuration
bitcell array is fixed to output a 0 value, and dummy bitcell
file is used to set up GDS layer map, DRC/LVS rules,
array is placed with bitlines disconnected for wordline load
analytical characterization parameters and SPICE simulation
and lithography regularity. If multi-port bitcell configuration
parameters. The SRAM design is defined in a configuration
is applied, then, bitcell, replica and dummy bitcells (1rw/1r,
file where user specifies parameters associated with the word
1rw/1w) need to be designed as well.
size, the number of words, port types for bitcell
configuration, PVT (process corner, voltage, temperature)
for characterization, and verification tools.
An SRAM is generated by the technology library and
configuration file based on a Python-implemented memory
compiler framework. The generated results consist of
logical, physical, timing/power modules, a datasheet for
design report, a log file, and a configuration file copy.
Specifically, characterizer uses analytical model or spice
model to generate the timing/power modules, analytical
characterization is default as it is close-accurate to estimate
the timing/power and can speed up the process. Memory
characterizer finally uses a netlist with the extracted
parasitics to perform post-layout simulation and obtain more
accurate timing/power modules.

Figure 3. Bitcell layouts in (a) SCMOS 0.35m technology and in (b) our
0.6m technology.

Our implementation is based on the reference

Figure 2. Methodology used in OpenRAM for an SRAM design.
III. DESIGN FLOW FOR SRAM CIRCUIT
This section describes our design flow for an SRAM
circuit based on the methodology used in OpenRAM. In this
implementations provided by OpenRAM. An example case
of bitcell layouts in SCMOS 0.35m technology and in our
0.6m technology is shown in Fig. 3. Both layouts are same
configuration but with different transistor dimensions. Our
bitcell and other base cells are carefully designed to meet
DRC requirements.
Next, we need to modify a Python file for the tech
configuration. In the file of a reference technology, we need
to replace the GDS layer number with ours while remaining
the layer name same. Correct mapping relationship must be
satisfied when two technologies use different layer names.
For example, in this work the GDS layer number for layers
p-implant and n-implant are replaced with that of layers
VTPE and VTNE, respectively. Then, we also need to
modify the parameters of DRC rules with respect to spacing, analyze the experimental results for our design. Our SRAM
enclosure and extension. For example, the minimum spacing circuit is implemented in a 0.6m/±2.5V CMOS process
of layer implant to transistor channel is 0.07m in the with a 0.38-mm2 layout area and a 96-bit memory size. Fig.
reference technology, but it is changed to 0.5 m for our 4 shows the SRAM layout embedded in a chip layout where
technology. The modification to DRC rules needs to be done SRAM is combined with a PLA for a research project, and a
by careful handling and OPenRAM considers the most buffer array is used to drive the output lines of SRAM for
common DRC rules for various technologies. Finally, readability improvement. We omit the introduction to PLA
parameters for analytical model such as unit wire resistance herein as we only focus on the implementation of SRAM in
this work.
and wire capacitance, gate delay and leakage power, need to
be updated as well based on those values in our technology.
Once above procedures are finished, the memory compiler
can generate an SRAM circuit. OPenRAM provides various
tool interfaces for circuit simulation and physical verification
as well as parasitic extraction. In this work, we use Cadence
spectre for circuit simulation and Mentor calibre for physical
verification.
IV. EXPERIMENTAL RESULTS
This section shows the functionality and performance of
our SRAM circuit generated by OPenRAM. We also present
values of various performance parameters from pre-
simulation and post-layout simulation as well as OPenRAM
analytical characterization. Post-layout simulation is
performed by using an SRAM netlist with parasitics Figure 4. SRAM layout embedded in a chip layout.
extracted from calibre PEX. Finally, we summarize and

Figure 5. Post-layout simulation for the functionality of our SRAM circuit.

bit address and 6-bit input/output data. During csb0 is active

A. Simulation Results for the Functionality
Post-layout simulation results for the functionality of our
SRAM circuit is consistent with that of pre-simulation and is
shown in Fig. 5. The circuit operates by a clock signal clk0 in
a 2-MHz frequency, csb0 controls enable or disable of the
circuit, web0 controls the read or write operation by a
scheme as introduced in section Ⅱ. Besides, the circuit has 4-
in low voltage, we control signal web0 to realize the write
operation followed by the read operation and repeat it by
three times, each operation spends 8 clock cycles. In the
write and read operations, address bits change synchronously
with the positive clock edge from 0000 to 0111 with a 1-bit
step size. In the first write operation, we apply input data
ranging from 000000 to 000111 with a 1-bit step size to
synchronously follow the positive clock edge. For the second
and third write operations, however, random input data is
applied. Then, in the read operation we check each output
dada after each negative clock edge, as shown by digital
codes (1 represents high voltage 2.5V, and 0 represents low
voltage -2.5V) in red in Fig. 5. We verify that during the read
operation, each output dada is consistent with the input dada
to the same address, and output pattern is always consistent
with the input patten being written into memory array during
the write operation. During csb0 is high voltage, the circuit is
disabled and therefore there is no output pattern.
Consequently, simulation results demonstrate the
functionality of our SRAM circuit is correct. Note that for a
write or read operation in a clock cycle, there is always a
delay from the negative clock edge when data is written in or
read out. Besides, we can also observe the output pattern
during the write operation, this is because the newest
OPenRAM version omits oeb0 signal that is used to disable
the output during the write operation, in order to reduce the
hardware overhead. But this does not affect the functionality
of SRAM circuit when employed in our research project, we
do not care the output during the write operation.
(a)
(b)
Figure 6. Pre- and post-layout simulation results for write delay (a) and read delay (b) of an SRAM circuit.
B. Simulation Results for Performance Parameters
Write delay and read delay are critical parameters to
evaluate the performance of an SRAM circuit, the smaller it
is, the higher speed and throughput the SRAM circuit can
achieve. Their results measured from pre- and post-layout
simulation are shown in Fig. 6 (a) and (b), respectively. For a
write delay, pre- and post-layout simulation results are
respectively 5.2ns and 5.7ns, and the difference is 500ps. For
a read delay, pre- and post-layout simulation results are
respectively 5.7ns and 6.7ns, and the difference is 1ns. The
differences of delays are very small as compared to our
tolerance 125ns that ensures not to break the functionality of
SRAM. Besides, as the clock signal of the circuit operates at
2MHz, we can derive that write/read time are simply the sum
of write/read delay time and a three fourth of a clock cycle
time (the time from address available to data stored or
output). Therefore, write time of pre- and post-layout
simulation is 380.2ns and 380.7ns, respectively. Read time of
pre- and post-layout simulation is 380.7ns and 381.7ns,
respectively. Note that our SRAM has parallel input and
output ports and they work concurrently, thus write/read
delay for all ports are same.
 feedbacks of cross-coupled inverters of an SRAM bitcell (see
a 6T bitcell in Fig. 1), and then biasing bitcell ports with
appropriate voltages. Next, sweeping voltage at storage node
Q while monitoring voltage of the other storage node Q_bar.
SNM is simply the side of the largest square embedded
between the voltage transfer characteristic curves of inverters.
Simulation setup and the obtained results for SNM are
shown in Fig. 7. HSNM is 1.2V, RSNM is 0.6V, and WSNM
is 1.8V with supply voltages of ±2.5V. Because layout of
bitcell is well designed under the mismatch and symmetry
constraints, the parasitic effect to our bitcell circuit is very
small. Therefore, pre-simulation and post-layout simulation
results are totally same.
C. Summary and Analysis
(a)
Results for the maximum working frequency, area, and
power along with the performance parameters are
summarized in Table Ⅰ. They are from pre-simulation and
post-layout simulation, we also include results from an
OPenRAM report that is used to compare to simulation
results for the discussion of OPenRAM methodology.
TABLE I. SUMMARY FOR OUR SRAM CIRCUIT

Item
Specification OpenRAM Post-layout
Pre Sim.
Report Sim.
Max. Working Freq. (MHz) 357 71.4 66.7
Area (mm2 ) 0.38 n/a 0.38
Leakage Power (mW) 13.06 18.84 18.84
(b) Total Power (mW) 13.09 19.12 19.06
Write Delay (ns) n/a 5.2 5.7
Read Delay (ns) 1.4 5.7 6.7
Write Time (ns) n/a 380.2 380.7
Read Time (ns) 376.4 380.7 381.7
HSNM@±2.5V (V) n/a 1.2 1.2
RSNM@±2.5V (V) n/a 0.6 0.6
WSNM@±2.5V (V) n/a 1.8 1.8

For the maximum working frequency, we increase a

(c)
Figure 7. Simulation results for static noise margin. (a) HSNM. (b) RSNM.
(c) WSNM.
Static Noise Margin (SNM) is also a critical parameter to
evaluate the stability of an SRAM [11], it is defined as when
noise presents at the gates of cross-coupled inverters or
storage nodes, the maximum value of noise that an SRAM
bitcell can tolerate. When noise exceeds that value, the stored
data would be changed. We measure this parameter in three
states which includes Hold Static Noise margin (HSNM),
Read Static Noise Margin (RSNM), and Write Static Noise
Margin (WSNM). Butterfly-curve method is mostly
considered to measure SNM which first disconnects
clock frequency and iterate simulation until the functionality
of SRAM circuit breaks. Post-layout simulation result shows
a lower frequency compared with pre-simulation result due
to the parasitic capacitance of a control logic. As for power,
there is no significant difference for leakage power between
pre-simulation and post-layout simulation. On the one hand,
the most of leakage power is consumed by bitcell array and
the effect of parasitic resistance to bitcell is very small. On
the other hand, the memory size of our SRAM is small and
has only 96 bits, the accumulative effect of power variation
is not significant. However, dynamic power (the subtraction
of total power and leakage power) of post-layout simulation
is 0.06mW less than that of pre-simulation, this is because
the parasitic capacitance affects the actual working
frequency. For write delay/time and read delay/time, post-
layout simulation results respectively increase 0.5ns and 1ns
compared with pre-simulation results. The differences are
due to the parasitic capacitance of wordlines in a control
logic circuit. Optimizing the algorithm in OPenRAM for the
buffer insertion on wordlines can reduce the delay and
improve the speed performance. Our SRAM circuit achieves
the high stability by the SNM values measured, as compared
to 5V from VDD (+2.5) to VSS (-2.5). Besides, there shows
no difference between pre-simulation and post-layout
simulation results for SNM, and nearly no parasitic effect for
bitcell because of a fine layout structure.
As OPenRAM can support an analytical characterization
prior to a SPICE simulation, which estimates delay and
power of an SRAM by considering gate delay, unit wire
resistance and capacitance, and power parameters of base
cells, we still compare simulation results to the estimated
results from an OPenRAM report generated by an analytical
characterization. They are all same in terms of layout area.
However, OPenRAM estimates a maximum working
frequency as high as 357MHz by an analytical model,
whereas the simulation results are far smaller than that when
using a SPICE model. In terms of leakage/total power and
read delay/time, they are smaller than corresponding results
from simulation. The result differences between analytical
characterization and SPICE simulation is due to the
mismatch between analytical model and SPICE model, the
later contains more device and parasitic parameters and
therefore is more accurate. As for other performance
parameters such as write delay/time, and SNM, the
OPenRAM report does not provide the corresponding
results as they need to be measured from internal signals of
SRAM bitcells. Nevertheless, analytical characterization
provides estimate results close enough to real values for an
SRAM design which is still helpful in reducing design
iteration.
V. CONCLUSION
This paper introduces a design flow for an SRAM circuit
with OPenRAM framework. To verify the reliability to
design an SRAM circuit with the methodology used in
OPenRAM, we use a practical PDK to implement an SRAM
circuit in a 0.6m/±2.5V CMOS process. We present pre-
and post-layout simulation results with respect to the
functionality and performance of our SRAM circuit, where
results for read/write delay and SNM as well as various
performance parameters are included. The simulation results
are thoroughly analyzed, and a summary for our SRAM
circuit demonstrates the effectiveness and the reliability of
OPenRAM framework to design an SRAM in a fabricable
technology process. One of our future works is to measure
the silicon results of our SRAM circuit from a chip, the
effectiveness of the circuit designed by OPenRAM
framework can be further explored.
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