Embedded Systems and

Interfacing
EEE 315
Fahim Mahmud
Assistant Professor
Dept. of EEE
CUET
Class outline

 What is minimum mode?

 Minimum mode diagram of 8086
 Multiplexing and demultiplexing
 Latch
 Data transreceiver
 Decoder
 Clock generator
 Interrupts
 HOLD and HLDA
 Timing diagram
What is minimum mode?

 Minimum mode operation means that there is only a single processor in the
system. In our case, it’s 8086.
 A microprocessor cannot function by itself, it needs many other
components to function as a whole. That’s why we have modes (minimum
and maximum)
 The 8086 first checks its MN/MX’ pin to find out whether it should operate in
min or max mode.
 In this mode, the 8086 generates all the control signals for the system.
 This mode is suitable for small to medium-size designs with a single
processor.
 This configuration is simple and cheap.
 However, due to lack of multiple processors, it cannot perform
multiprocessing tasks.
Minimum mode diagram of 8086
Components in minimum mode

 8086 microprocessor
 8284 clock generator
 8282 latch
 8286 Data trans-receiver
 74138 3:8 decoder
Multiplexing

 Multiplexing is the process of combining multiple signals into one signal,

over a shared medium.
 We first send address on the address bus, then either send or receive data
on the data bus.
 Since we don’t send address and data simultaneously, we can send them
on the same line. This is multiplexing.
 21 lines are multiplexed. AD0-AD15, A16/S3-A19/S6, BHE’/S7
Demultiplexing of address and data

 Although address and data come out of 8086 on the same lines, we need
to differentiate or demultiplex them in order to know what is what.
 To separate the address, we use latch.
 To separate the data, we use data transreceiver.
 We enable the latch or the transreceiver at appropriate times to get what
we need.
8-bit latch (8282)

 Latch holds the address even when the address bus doesn’t send address.
For example, the processor inside an AC remote control sends the
temperature value to display. The display keeps showing, but that doesn’t
mean that the processor keeps sending the temperature value to display
continuously. The latch holds this data.
 ALE (Address Latch Enable) of 8086 is connected to STB (Strobe) of the
latch. When there is address on the data bus,
Multiplexed line latch should capture it. So,
ALE = 1. when there’s data on the multiplexed lines, ALE = 0 so that data
when ALE zero thake tokhon 8282 latch disable hoye jai.and line diye ja ase sob 8286
doesn’t go through the latch. transrecevier e pass hoye jai.although ALE is not directly connected to 8286 but when ALE is
0 ,8286 got data
 Thus, we get pure address bus out of latch.
 Address bus is 20 bits, so wee need at least 3 8-bit latches.
 OE’ (Output Enable) of 8282 is always grounded.
8-bit data transreceiver (8286)

 When the multiplexed lines carry data, DEN’ of 8086 becomes low, which is
connected to OE’ (Output Enable) of 8286, thus the data flows through it.
On the other hand, DEN’ = 1 when there is address on the multiplexed lines.
Therefore, address doesn’t come out of 8286. Thus, we have achieved a
pure data bus.
 Moreover, DT/R’ of 8086 is connected to T of 8286. If this pin is high, 8086
transmits data (write). On the contrary, if this pin is low, 8086 receives data
(read).
 Since data bus is 16 bits, we need 2 8-bit 8286.
74138 3:8 decoder

 8086 also needs to generate control signals.

 Among many control signals, the most important ones are memory read,
memory write, I/O read, I/O write.
 8086 has 3 pins for this task, M/IO’, RD’, WR’
 Based on the different combinations possible from these 3 pins, appropriate
control signals are generated by the 74138 3:8 decoder.
 The decoder produces only one output signal (active low) based on the
different input combinations.
 The 3 gate signals enable the decoder. All three must be enabled for the
decoder to operate properly.
74138 3:8 decoder

M/IO’ RD’ WR’ Operation

0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory
Read

1 1 0 Memory
Write
Clock generator (8282)

 Every processor requires a clock. Since 8086 doesn’t sense time, it needs
some sort of trigger to initiate each of its activity. For this reason, 8282 clock
generator is used.
 Standard frequency of 8086 is 6 MHz
 8282 produces this by dividing the frequency of a 18 MHz crystal oscillator
by 3. The purpose is to get a 33% duty cycle because 8086 needs a 33%
duty cycle to function properly.
 It does so by keeping the output high for 1 cycle and low for 2 cycles,
whatever may the input duty cycle be. The output is thus ensured to be
33% and 1/3 of the input frequency.
Clock generator (8282) …

 The 8282 also receives ready and reset signals from the wait state generator
and reset circuit, respectively and sends these signals too to the
components which need them.
 The ready signal is for slow devices so that the fast 8086 only sends data to
the slow devices when they are ready.
 8282 also sends a synchronized reset signal to 8086 and other devices in the
system to reset the whole system whenever necessary.
Interrupts

 Interrupts, as the name suggests, disturb the processor.

 Whenever interrupt occurs, 8086 executes an ISR (Interrupt Service Routine)
 The two pins on 8086 for interrupts are NMI (Non-Maskable Interrupt) and
INTR (Non-vectored interrupt). These two are hardware interrupts.
 NMI cannot be disabled. INTR can be disabled only by writing programs.
Software interrupts cannot be disabled because we, the programmers,
wrote them in the first place and don’t want them to be disabled.
 When 8086 receives an interrupt on INTR pin, it sends acknowledgement
signal on INTA’ pin. The device which interrupted 8086 calculates the
vector number. When 8086 sends the second INTA’, it sends the vector
number to 8086. 8086 then executes the appropriate ISR using this vector
number. (More on this later)
HOLD and HLDA

 Typically, data transfer cannot happen directly between I/O devices and
memory.
 But if for some reason, we want to do that, we can achieve it by using a
DMAC (Direct Memory Access Controller).
 DMAC sends a hold signal on the HOLD pin of 8086 asking it to hold its
operation. Then, 8086 releases the bus and gives hold acknowledgement
(HLDA) to DMAC. DMAC becomes the bus master and does its operation.
 After the operation is done, DMAC sends low signal to HOLD pin and 8086
again becomes the bus master.
Timing diagram of read cycle
Timing diagram of write cycle
Timing diagram

 1st trigger of clock pulse: 8086 gives address

 2nd trigger of clock pulse: 8086 asks for data by making RD’ low. It takes
time for data to come from memory to processor. This is known as
propagation delay.
 3rd trigger of clock pulse: Data has arrived
 4th trigger of clock pulse: 8086 stores the data in its register
 In write cycle, data immediately goes out from 8086 when it makes WR’
low. So, there is no propagation delay in write cycle.