Nama:Fr

edyGabrielPurba
Ni
m.:200402052
M.K.:Si
stem Mi
kroprosesorB

1.
(Chapter
10.
1)What
typesof
connecti
onsar
ecommont
oal
l
memor
ydev
ices?
Address,
dat
a,andcontr
olconnect
ions

2.(Chapt
er10.
2.d)
Listt
henumberofwor
dsf
oundi
neachmemor
ydev
icef
ort
hef
oll
owi
ng
numbersofaddressconnect
ions:
16Kx1
13
2 =8K

3.(Chapter10.
17)Whyarememoryaddr
essdecodersimpor
tant?
Memor yr ar
elyf
il
lst
heentir
ememor y,whichrequir
essomef orm ofdecodert
o
selectthememorydevicef
oraspeci
ficrangeofmemor yaddresses.

4.(Chapter
10.
18)Modi
fyt
heNANDgatedecoder
ofFi
gur
e10–13t
osel
ect
thememor
yfor
addressr
angeDF800H–DFFFFH.
DF800H–11011111100000000000
DFFFFH–11011111111111111111

5.(Chapter10.19)
Modif
ytheNANDgatedecoderi
nFi
gure10–13
tosel
ectthememory
foraddr
essrange40000H–407FFH.
40000H–01000000000000000000
407FFH– 01000000011111111111

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 A0-
-A10 D0-
-D7

U1NMC27C16B

8 9
7 A0 O0
10
6 A1 O1
11
5 A2 O2
13
A3 O3
R 4 14
3 4 3 A4 O415
U274ALS1331 2 A5 O516
1 A6 O617
A1 2 23A7 O7
9A 3 22A8
18 4
A1 5 19A9
5 6 6 A10
7A
16 7 20
OE
A1 10 9 18
CE
5A 11
12 21
14 VCC VPP
9 8 13
14
15

11 10

13 12

U3D74ALS04
1 2
I
O/M
9 8

3 4

5 6

6.(Chapt
er10. 20)WhentheG1inputi
shighandbot handarelow,what
happenst otheout
put
softhe74HCT1383-to-
8li
nedecoder
?
Oneoftheeightout
put
sbecomesalogi
czeroasdict
atedbytheaddr
essinput
s.

7.(Chapt
er10.
21)Modif
ythecir
cui
tofFi
gur
e10–15t
oaddr
essmemor
yrange
70000H–7FFFFH.
70000H–01110000000000000000
7FFFFH–01111111111111111111
U1

A13 1 15
A14 2 A Y0
14
A15 3 B Y1
13
C Y2
12
6 Y3
A16 11
A19 4 G1G Y4
10
5 2AG Y5
9
2B Y6
7
Y7
U2A
74HCT138
A17A1
3
8 1

74HCT00

8.(Chapt
er10.
22)Modi
fyt
heci
rcui
tofFi
gur
e10–15t
oaddr
essmemor
yrange
40000H–4FFFFH.

40000H–01000000000000000000
4FFFFH– 01001111111111111111

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 9.(Chapt
er10.
27)Modif
ytheci
rcui
tof
Figur
e10–19byr
ewri
ti
ngt
hePLDpr
ogr
amt
oaddr
e
ssmemor yatl
ocat
ionsA0000H–BFFFFHf ortheROM.
A0000H–10100000000000000000
BFFFFH–10111111111111111111

begi
n

ROM<=A19or
(not
A18)
orA17or
MIO;
R

AM<=A18andA17and(
not

MI
O);
AX19<=not
A19;

endV1;

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 10.
(Chapt
er10.
29)
Modi
fyt
heci
rcui
tof
Figur
e10–20t
osel
ect
memor
yat
locat
ion60000H
–77FFFH.
60000H–01100000000000000000
77FFFH–01110111111111111111

A19i
s0,
A18i
s1,
sot
hey
canbedi
rect
lyconnect
edG2AandG1ofdecoder‘
138

I
nFig.
10-20,A17A16A15ar
econnect
edt
oC/
B/Ai
nput
pi
nsof‘
138.A17A16A15 Y4Y5 Y6
1 0 0 0
1 0 1 0
1 1 1 0

So,
Y4U1CE,
Y5U2CE,
Y6U1CE

D0-
-D7

A0-
-A14

U1AT27256 U2AT27256 U3AT27256

10 11 10 11 10 11
9 A0 O0 12 9 A0 O0 12 9 A0 O0 12
8 A1 O1 13 8 A1 O1 13 8 A1 O1 13
7 A2 O2 15 7 A2 O2 15 7 A2 O2 15
6 A3 O3 16 6 A3 O3 16 6 A3 O3 16
5 A4 O4 17 5 A4 O4 17 5 A4 O4 17
4 A5 O5 18 4 A5 O5 18 4 A5 O5 18
3 A6 O6 19 3 A6 O6 19 3 A6 O6 19
25 A7 O7 25 A7 O7 25 A7 O7
24 A8A 24 A8A 24 A8A
21 9A1 21 9A1 21 9A1
23 0A1 23 0A1 23 0A1
2 1A1 2 1A1 2 1A1
26 2A1 26 2A1 26 2A1
27 3A1 27 3A1 27 3A1
4 4 4
22 22 22
#RD 20 OE 20 OE 20 OE
CE CE CE
U474HCT138 28 28 28
VCC VCC VCC
VPP VPP VPP

A15 2 B
A Y015 1 1 1
A16 3 C Y114
A17 6 Y213
G1 Y312
1
4
G2A Y4 110
A18 5 Y5 9
A19IO G2B Y6
/#M Y77
1

VCC

11.
(Chapt
er10.
30)Modif
ytheci
rcui
tof
Figur
e10–20t
osel
ect
eight
2725632K×8EPROMs
atmemorylocat
ions40000H–7FFFFH.

2725632Kx8EPROMhas15addr
esspi
ns(32K=215)
,8088addr
esspi
nsA0–A14got
oEP
ROM.RemainingA19-
A15needtobeconnectedtodecoder‘
138

40000H–01000000000000000000
7FFFFH– 01111111111111111111

A19i
s0,
A18i
s1,
sot
hey
canbedi
rect
lyconnect
edG2AandG1of
decoder‘
138
A17A16A15canbeconnect
edt
oC/B/Ainput
pinsof
‘138,
andout
put
pinsY0–Y7connect
tot
hechi pselectpin(CE)oft
heeight27256unit
sU1t oU8.

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 12.
(Chapt
er10.
35)Outli
nethemaj
ordi
ff
erencebet
weent
hebusesoft
he8086
and8088micr
oprocessor
s.
Themai
ndi
ff
erencesar
ethedat
abussi
zeandt
heI
/O,
memor
ycont
rol
signal
.

13.
(Chapt
er10.
36)Whati
sthepur
poseof
theBHEandA0pi
nsont
he8086mi
cropr
ocessor
?
BHEselect
stheupper
memor ybankandA0select
sthel
owermemorybank.

14.
(Chapt
er10.
37)
Whati
sthepurposeof
theBLEandA0pi
nsont
he8086mi
cropr
ocessor
?
Banklowenabl
ehasreplacedtheA0pin.

15.
(Chapter
10.39)If
BHEi
sal
ogi
c0,
thent
he memor
ybanki
s
select
ed.Uppermemor
ybank

16.
(Chapter
10.40)I
fA0i
salogi
c0,t
hent
he memor
ybanki
s
select
ed.Lowermemorybank

17.
(Chapt er10.41)Whydon’t
separatebankr
ead(RD)strobesneedtobedevel
opedwheni
nt er
facingmemor yt
othe8086?
Itdoesnot matteri
f16-
bitor
8-bit
arereadbecausethemicroprocessor
justi
gnor esanydatabusbitst
hatarenotneeded.

18.
(Chapter10.43)Devel
opa16- bi
t-
widememoryi
nter
facet
hatcont
ainsSRAM
memor yatlocati
ons200000H–21FFFFHfort
he80386SXmicropr
ocessor
.
Modifythecircui
tofFi
gure10–32.

200000H–001000000000000000000000
21FFFFH–001000011111111111111111

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 D0-
D7D8

-
D15
A1-

A1
5

10 HM62256 HM62256
A0 D0 11 10 11
A0 D0
9 12 9 12
A1 D1
8 A1 D1 13 8 13
A2 D2
7A2 D2 15 7
A3 D3
15
6A3 D3 16 6
A4 D4
16
5 A4 D4 17 5 17
A5 D5
4 A5 D5 18 4 18
A6 D6
3 A6 D6 19 3 19
D7
25 A7 D7 25 A7
A8
24 A8A 24
A9
21 9A1 21
A10
23 0 A1 23
A11
2 1 A1 2
26 2 A1 26 A12
1 3 A1 1A13
A14
4
22 22
OE
27 OE 27
WE
20 WE 20
CE
CE
28 28
VCC
VCC

#RD

U18
10 11 10 11
A0 D0 A0 D0
3 17 9 12 9 12
#W I I
/O 18 A1 D1 D1
4
I 8 13 8 A1 13
R#BH 5 I
/O 19 A2 D2 A2 D2
I I
/O 20 7 15 7 15
E 6 A3 D3 A3 D3
7 I I
/O 21 6 16 6 16
A0A D4 D4
9 I I
/O 23 5 A4 17 5 A4 17
23A D5 D5
10
I I
/O 24 4 A5 18 4 A5 18
22A D6 A6 D6
11
I I
/O 25 3 A6 19 3 19
D7 A7 D7
21A
12
I I
/O 26 25 A7 25
20A I A8 A8
24 24
19A 13 I
/O 27 A9 A9
21 21
18A 16I I
/O 23A10 23 A10
I A11
17A 2 A11 2
16 2 26A12 26A12
I
/CLK 1 A13 1 A13
28 A14 A14
VCC 22 22
27OE 27OE
GAL22LV10C/
LCC 20WE 20WE
CE CE
28 28
VCC VCC VCC

HM6225 HM6225

End

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