Report

on
Review of Electronic Interlocking (EI)
Application Data Design
 Report On Review of Electronic Interlocking (EI) Application Data Design

Outline

1. Recommendations

2. Roadmap

3. IR Scenario & Justification for Unification

4. Design Process Workflow of Approved Vendors

5. Data Design Process & Standardisation

6. Validation & Verification

7. Committee Meetings

8. Terms of Reference

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 Report On Review of Electronic Interlocking (EI) Application Data Design

1. Recommendations

To achieve uniformity in Application Data design across the vendors,

1.1 Standardisation has to be done for Signal Interlocking plan (SIP), Front Panel
Display (FPD) diagram and Route Control Chart (RCC) or Table Of Control (TOC).
Leaving any of these primary documents will not help in achieving the goal.

1.2 The nomenclature of (a) Signalling functions on Signal Interlocking Plan, (b)
Interlocking Relays have not been standardised. SIP, FPD, RCC/TOC, Interlocking
Circuits have been standardised to larger extent by earlier work groups 1

1.3 Standardisation of boolean equations using standard syntax and semantics has to
be carried out. To begin with, IR should attempt to standardise the process from
SIP till this stage.

1.4 A new workgroup has to be formed to work on standardisation of these aspects.

1.5 Electronic Interlocking vendors have to prepare pre-compilers to take

standardised boolean equations to translate them into their native style for
further compilation and generation of Application Binary.

They are at present taking the different interlocking documents as the basis for
processing Application Binary. For example,

(a) Microlok-II and MEI-633 EI systems require boolean equations for generating
the application binary for which they have to precompile and translate standard
boolean logic into their native style or type.-

(b) Westrace EI system does not require boolean equations, but requires
interlocking circuits for generating the application binary.

(c) K5BMC EI system requires only RCC/TOC for generating the interlocking
circuits and application binary.

1
(a) Working Group on Standardisation of Signalling Principles and Interlocking Practices have formulated
Directive Principles and Typical Circuits for End Cabin Motor operated points (RB 2010/Sig/WG/Interlocking
Principle dated 13/22-10-2010)

(b) RDSO Report on Standardisation of the typical circuits for Electronic Interlocking (Report no. SS/137/2013
Reference: RB 2010/Sig/WG/IP dated 02.05.2012)
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1.6 Application Data can broadly be divided into 3 categories (i) VDU Data (ii)
Application Data (iii) Configuration Data.

The precompilers also may consider configuration data required for their
systems. The configuration may include virtual I/O, physical I/O, communication
protocols etc.

1.7 Electronic Interlocking vendors have to prepare standard GUI Editor to take
standardised FPD to translate them into their native style for further compilation
and generation of VDU data and VDU binary.

1.8 Verification & Validation by Formal methods as envisaged in CENELEC standards

has to be developed for Verification & Validation of Route Control Charts or Table
of Controls and Boolean Logic as secondary process. Today, these tasks are being
carried manually. The task will be more difficult for larger yards. This will help
in elimination of manual approval process.

-Signed-
(P. Venkata Ramana)
Senior Professor Signal, IRISET
& Convener

-Signed-
(Shri G. K. Dwivedi)
Chief Signal & Telecom Engineer/Construction
South Western Railway/ Bangalore Cantonment
& Committee Member

-Signed-
(Shri Tarun Prakash)
Chief Signal Engineer
Northern Railway, New Delhi
& Committee Member

-Signed-
(Shri Anurag Goyal)
Executive Director/Signal
Research, Development & Standards Organisation, Lucknow
& Committee Member

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 Report On Review of Electronic Interlocking (EI) Application Data Design

2. Roadmap
2.1 A Working Group preferably consisting of three members with Software
Knowledge, Circuit Design knowledge and Construction Experience have to be
constituted. The work carried out by the earlier workgroups2 have to be
reviewed to define the following:

● Station Layout
○ Nomenclature of signal functions
○ Standardisation of Pictorial Symbols
○ Standardisation of Notes, Aspect Control Chart, etc.,

● Table of Control
○ Standardisation of Columns and their Labels
○ Standardisation of Column Entries
○ Standardisation of Notes

● Circuits
○ Standardisation of Circuits
○ Nomenclature of Relay contacts
○ Symbols

● Application Logic
○ Standardisation of Boolean Operators
○ Syntax and Semantics of Statements

● Typical Signalling Design

● Data Dictionary defining above standards

2.2 Precompilers have to make ready by the approved EI vendors,, after issuance of
Standardised Design Guidelines

2.3 After completion of above activities, each zonal Railway has to try out a
standardised version of plan and circuits at one station where EI system is being
installed. Precompilers are to be used to generate Application Data Design.
2
(a) Working Group on Standardisation of Signalling Principles and Interlocking Practices have formulated
Directive Principles and Typical Circuits for End Cabin Motor operated points (RB 2010/Sig/WG/Interlocking
Principle dated 13/22-10-2010)

(b) RDSO Report on Standardisation of the typical circuits for Electronic Interlocking (Report no. SS/137/2013
Reference: RB 2010/Sig/WG/IP dated 02.05.2012)
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Standard GUI Editors are to be used for generation of VDU Data. Feedback from
the railways will help in modifications and corrections to above Design
Guidelines.

2.4 After commissioning of stations on above guidelines, down the line,

standardisation has to be reviewed after gaining experience.

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3. IR Scenario & Justification for Unification

3.1 Indian Railways have 6000 block stations and out of which 1200 stations are
equipped with Electronic Interlocking systems of different makes namely
Microlok II, Westrace VLM 6 & Mark II, MEI 633, AZD-Praha, SIMIS S , VHLC,
spreading over 15 zones. Architecture varies from make to make so is Application
Data Design processes. Even Logic circuits adopted for such systems are varying
from zone to zone.

Ason May, 2017

Make Confg CR ER NR NE NF SR SC SE WR EC ECO NC NW SEC SW WC Total
Hot 2 11 2 24 15 6 9 25 2 13 44 27 11 14 3 208
Microlok II
Warm 28 20 26 44 43 53 8 1 44 83 54 32 12 12 460

Westrace Hot 2 11 69 29 2 11 8 13 18 4 14 13 6 13 213

AZD Praha Hot 11 11

VHLC Warm 13 16 4 1 9 3 46

Hot 19 3 11 33
SICAS
Warm 9 1 1 1 10 6 28

K5BMC Hot 1 7 2 12 1 6 6 35
MEI633 Hot 14 5 3 45 5 9 17 26 1 6 7 19 157
Total 31 74 47 0 124 145 68 87 81 16 122 132 110 63 57 34 1191

3.2 Earlier, Working Group on Standardisation of Signalling Principles and

Interlocking Practices have formulated Directive Principles and Typical Circuits for
End Cabin Motor operated points (RB 2010/Sig/WG/Interlocking Principle dated
13/22-10-2010). They have standardised the Signal Interlocking Plan, Front Panel
Diagram, Route Control Chart/ Table Of Control and interlocking circuits to larger
extent.

3.3 Further, RDSO has prepared Report on Standardisation of the typical circuits for
Electronic Interlocking (Report no. SS/137/2013 Reference: RB 2010/Sig/WG/IP
dated 02.05.2012).

3.4 The committee has examined above documents.

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3.5 Standardisation in Design approach and Uniformity in Application Data Design is

required to

● Expeditious Design Process - Quick Turnaround

● Expeditious Approval Process with dispensing of manual approval process
● Validation & Verification by formal methods
● Ease of Yard modifications
● Improved Understanding & Ease of Maintenance
● Conformance to RDSO Relay Logic standards
● Verification of Interlocking Logic with respect to Safety Principles
● Simulation & Visualization of Yard Working
● Test Plan Generation for Factory Acceptance Test (FAT) & Site Acceptance
Test (SAT)
● Automation of Factory Acceptance Testing

3.6 Lack of Standardisation of Application Data Design may lead to

● Railway design staff have to be familiar with all 4 vendors tools &
processes
● Significant design representation variations between and within zones -
may lead to delays and errors
● Separate training needs for each vendor specific design process
● Unable to apply Generic Tools such as Model Checkers etc., in the absence of
standardised representation
● Important steps - design & verification - are to be done fully manually or
heavily dependent on vendors

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 Report On Review of Electronic Interlocking (EI) Application Data Design

4.0 Design Process Workflow of Approved Vendors

4.1 Microlok II (Ansaldo) Design Process Flow:

Application Data Design involves two parts for any Electronic Interlocking System
(i) Application Data Design for Processor and (ii) GUI Design for VDU.

4.1.1 (i) Application Data Design Process Flow of Microlok is comprehensive and the
simplest. Designer has to deal with only one source file for generation of
application binary. The source file will have, apart from boolean equations,
declaration of vital and nonvital bits, mapping of these bits with physical I/O,
local interface declarations and communication protocol and timing declarations
etc., in well structured manner.

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4.1.2 Program Structure

Source program is comprehensive and includes boolean equations, declaration

and virtual and physical mapping of vital, non-vitals, timer, internal bits,
communication etc., which are required for generation of application binary.

-----------------------------------------------------------------
PRAGMA < compiler option string >
PROGRAM < program name >;
INTERFACE < interface definitions >
LOCAL < physical I/O>
COMM < serial I/O>
BOOLEAN BITS < bit list>;
NV.BOOLEAN BITS < bit list>;
TIMER BITS < bit list>
LOG BITS < items to log >
CONSTANTS < constant definitions >
ARRAYS < array definitions >
CONFIGURATION < configurations>
-----
LOGIC BEGIN
< boolean statements>
END LOGIC
TABLES BEGIN
< table definitions >
END TABLES
NUMERIC BEGIN
< numeric blocks >
END NUMERIC
END PROGRAM
-----------------------------------------------------------------

4.1.3 The compilation of the source file (.ml2) will generate debug symbol file (.mld)
and listing file (.mll). Listing file contains errors, warnings for missing syntax or
declarations, bits usage, unused variables, I/O jumper settings, summaries,
checksums and CRC. If no error are found, the compiler will generate application
binary (.mlp). Application binary file will be transferred to CPU flash ram of the
EI System.

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4.2 (ii) GUI Design for VDU - GUI design involves preparation of station layout using
Graphic Editor - TrakPlan, assignment of indication bit mapping and control bit
mapping, preparation of various GUI associated CSV files and preparation of an
almanac; NVP Data Checker verifies these files. On compilation of these files, a
Local Control Panel (LCP) Configuration file is generated which is deployed in
VDU PC by VDU software installer.

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4.2 Westrace II (Siemens) Design Process Flow

Circuits are prepared using Graphical Configuration Sub-system (GCSS) which in

turn generates ladder logic equations internally. On compilation, application
binary is generated which is placed in Vital Logic Module (VLM) and Network
Communication & Diagnostic Module (NCDM).

VDU GUI is prepared using PC Graphic Editor (PCGE) and this VDU data along
with mapping information is compiled by Westcad to generate VDU binary
which is placed in VDU PC.

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4.3 K5BMC (Kyosan) Design Process Flow

TOC tool generates extended Table of control (ETOC) and boolean logic directly.
Logic Data Generator (LDG) Compiler compiles the boolean logic along with
interface data into application binary. Application binary is placed in F486-4I
card of EI system.

VDU Data is prepared with GUI tool and is compiled with mapping information
into VDU binary which is placed in VDU PC.

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4.4 MEI633 (Medha) Design Process Flow

Yard Data Compiler Fitter (YDCF) compiles manually prepared boolean logic
along with interface data into application binary which is placed in Vital
Interlocking Computer (VIC) and Communication Controller (CCC) cards of EI
system.

VDU Layout is prepared on Yard Data Compiler Front End Tool (YDC-FET). After
compilation with mapping data, VDU binary is generated which is placed in VDU
PC.

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4.5 Summary - Data Design

Summarised details of tools used by approved EI vendors is listed below:

Station Logic Boolean VDU

Make TOC Remarks
Layout Circuits Logic Layout

Microlok II Manual Manual Manual Manual TrakPlan

MEI 633 Manual Manual Manual Manual YDC_FET

Manual
Validation
Westrace Manual Manual GCSS Auto PCGE
& Verification
Logic Design
K5BMC Manual Auto Auto
Generator Studio

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5. Data Design Process & Standardisation

5.1 Software development lifecycle involved in Application Data Development of

Electronic Interlocking is as:

Inception Elaboration Construction Transition

Modelling Signal Plans

Requirements Table of Control

Analysis & Design Interlocking Circuits

Implementation Boolean Logic

Verification & Validation Rev Compiler, Validators

Testing FAT

Deployment SAT
Non-Interlocking
Config & Change Mgmt

Project Management

Iterations

5.2 Various Steps involved Application Data Development of Electronic Interlocking

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5.3 Data involved in Development cycle can be categorised into 3 categories -

● Application Data required for Realisation of Interlocking, rules and regulations

● VDU Data required for Visualisation of Status of Station Yard
● Configuration Data required for Interconnectivity between Virtual I/O &
Physical I/O

5.4 Workflow involved in Development cycle

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Normal workflow involves preparation of SIP, preparation of TOC, preparation of

FPD, preparation of Logic Circuits and Equations. Generation of Station Layout and
VDU Data from FPD. Compilation Logic Equations and compilation of VDU Data
with requisite configuration data will generate Logic Binary for CPU and VDU
Binary for VDU PC.

5.5 Level of Standardisation

Standardisation can have 4 stages. Standardisation of SIP and FPD can be in Stage
1, standardisation of TOC in Stage 2, standardisation of Logic Circuits and
Equations in Stage 3 and development of pre-compiler and standard GUI Editor
in stage 4.

Indian Railways has carry out first 3 stages and Approved EI Vendors have to do
last stage.

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6. Validation & Verification

A tool suite is being developed for railways which includes a GUI-based layout
editor to capture a given yard layout and to generate the corresponding control
table. Yard specific safety properties in the form of temporal logic formulae from
the control table according to railway signalling principles are also generated as
part of this tool suite. The tool suite also contains a logic generator tool to
generate Boolean relay logic equations from the control table. Corresponding
ladder logic diagrams are also generated for visualisation. The relay logic
equations generated by the logic generator tool are used for formal modelling
the interlocking system which is then verified with respect to safety properties
using the NuSMV model checker. After verification of these auto-generated relay
logic circuits, these validated logic circuits can be used as specifications for EI
application implementation by vendors.

Till Railways will have the reliable tool, the possibility of Validation and
Verification of application data can also be explored by the industry.

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7. Committee Meetings

The committee conducted two meetings on August 29-30, 2017 at IRISET,

Secunderabad and on October 17, 2017 at CSTE/Construction Office, Bangalore
Cantt. The committee studied the practices of data preparation of all four
approved EI vendors, deliberated, discussed and debated the issues concerning
the standardization of application data design of EI systems. A draft Report has
been prepared.

Meeting I

Presentations have been given in the meeting by Dr Chittaranjan Mandal,

Professor IIT Kharagpur; Shri Sivakumar, AGM (Engineering), TSTS, Bengaluru,
;Shri Jayaraman, Manager (Engineering) Siemens; Shri Srinivasa Rao, Manager
(R&D), Medha, Hyderabad.

Dr Chittaranjan Mandal, Prof (Computer Science & Information Technology) IIT

KGP is presently working on RDSO sponsored project 'Modelling and validation of
interlocking for railway signalling systems'. He gave a presentation on 'Tools for
automatic generation and verification of yard-specific relay logic for Interlocking
Systems of Indian Railways' during the meeting.

Shri Sivakumar, TSTS has demonstrated the tool which has generated ROC and
Interlocking Circuits through Signal Layout.

Shri Jayaraman, Siemens and Shri Srinivasa Rao, Medha have presented their
design processes.

Meeting II:

The committee deliberated on the issues. At present all vendors are preparing GUI
using proprietary GUI tools with which VDU Layouts are being generated.

The committee has felt that, apart from standardisation of pre-compiler. There is
a need to standardise GUI tool

The draft report is discussed and deliberated.

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8. Terms of Reference

Railway Board Letter No. 2013/Sig/IRISET dated 09.08.2017

● To examine the present practice of Application Data preparation for our

Approved EI Vendors

● To suggest and recommend measures to be taken for standardization in

design approach

● To suggest required Roadmap for achieving uniformity in Application Data

Design

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