T 307 10 e ProManual

Programmable Controller
PROGRAMMING MANUAL
Compatible modules
PC2/L2 series
PC2J series
PC3J series
SUB-CPU
1. MAKING SEQUENCE CIRCUITS 1
2. EXECUTION OF PROGRAM 2
3. PARAMETER 3
4. USER MEMORY STRUCTURE 4
5. INSTRUCTION WORDS 5
PROGRAMMING MANUAL
FOREWORD
Thank you very much for purchasing our Programmable Controller.
This operation manual is the programming manual for TOYOPUC-PC2/3 series.
For safety use of this product, read carefully this manual and other related individual operation
manuals altogether. Further, keep these manuals in file at an easily accessible place so that
persons concerned can read them anytime as necessary.
The distributor or dealer of this product is requested to hand over the said manuals to the end
user without fail.
The specification and other relevant information included in this Manual are subject to change
due to better improvement without prior notice.
Any product applicable to the strategic goods (or services) stipulated in the Foreign Exchange
and Foreign Trade Control Act is subject to export license of the Japanese Government, where
exported to overseas.
Should this product result in trouble during the guarantee period due to somewhat cause
attributed to our responsibility, necessary device(s) or parts(s) shall be repaired or replaced at
our discretion. For any other trouble or accident out of our responsibility, our company shall be
released from the responsibility for injury which may arise from such a trouble or accident.
i
FOR SAFETY OPERATION
Before installing, operating, maintaining and checking, read carefully this Manual without fail for
proper and safety operation and work. Any operator and any maintenance man who relate to
this product (Programmable Controller) are requested to acquire the knowledge on devices,
safety information and cautions before being engaged in the operation and maintenance. This
Manual classifies the safety caution level into "WARNING" and "CAUTION" using alert symbols
as follows.
Failure to observe the instructions given in this Manual could result

in death or bodily injury of the operator.
Failure to observe the instructions given in this Manual could result in

risk of bodily injury or physical damage to equipment, etc.
Don't overhaul the module and don't touch the module internals,
with the power switch kept ON.
Failure to observe this instruction could result in electric shock.
Don't touch the terminals with the power switch kept ON.
Failure to observe this instruction could result in electric shock.
Execute write during PC run (write during run) only when cyclic
operation of main equipment/machine is in shutdown.
Failure to observe this instruction could result in breakdown of its
device(s) and bodily injury from mis-operation, if any.
In handling the lithium battery, read and observe " Lithium Battery
Handling Cautions " given in this Manual. Improper handling
would cause liquid leak, overheat, sparking, and fracture, which
could then result in breakdown of units and devices and bodily
injury.
Regarding safe-related signals and emergency stop circuit, etc.,

handle those signals in external units without through this system.
ii
Use this product under an environment which meets the
environmental general specification specified in this Manual.
Don't attach/detach each module to/from its base, with the power
switch kept ON.
Don't touch directly the electronic circuits inside the module.

Failure to observe this instruction could result in breakdown of the
module by static electricity.
iii
REVISION HISTORY OF OPERATION MANUAL
Operation manual revision No. is added as a part of Manual No. described on the cover sheet of
the manual.
Operation Manual No.
T-307 # E
N: Japanese E: English
Series No.
Revision symbol
Equivalent
Revision Japanese
Date of Revision Revision Details
No. manual
version
1 2003.06.30 1st revision

2 2004.09.02 Correction of MSET/CSET command
3 2005.01.10 Correction of CSET command
The company name “TOYODA MACHINE WORKS,LTD”
4 2006.01.01
is changed to “JTEKT CORPORATION”
Special register was corrected.
5 2006.03.20 The device that was able to use the PC3 series was corrected.
Clock adjustment instruction is added
6 2006.11.10 Correct missing description.
7 2007.03.30 Correction of I/O address allocation
8 2012.05 TOYODA brand logo added on the front cover
9 2013.04 Correction of errors T-3079N
10 2022.03 TOYODA brand logo removed
iv
Composition of Related Operation Manuals
Operation Title Outline
manual No.
This manual describes the basic
T- 8 22 # E PC2 series operating procedure, functions, and
specifications of PC2 series.
This manual describes the basic
T- 8 33 # E PC2J series operating procedure, functions, and
specifications of PC2J series.
This manual describes the basic operating
T-845#E PC2J SUB-CPU procedure, functions, and specifications of
SUB-CPU.
T-862#E PC2JN procedure, functions, and specifications of
PC2JN.
PC2JNM This manual describes the basic operating
T-873#E PC2JNF procedure, functions, and specifications of
PC2JNM/PC2JNF.
T-880#E PC2S1 series procedure, functions, and specifications of
PC2S1 series.
T-300#E PC3J series procedure, functions, and specifications of
PC3J series.
T-303#E PC3JNF/PC3JNM procedure, functions, and specifications of
PC3JNF/PC3JNM.
T-304#E PC3JM procedure, functions, and specifications of
PC3JM.
T-310#E PC3JD procedure, functions, and specifications of
PC3JD.
T-320#E PC3JB series procedure, functions, and specifications of
PC3JB series.
T-311#E PC3JG procedure, functions, and specifications of
PC3JG.
v
This manual describes programming with the TOYOPUC-PC2/3 series.
Although the basic programming method is common to all the PC2/3 series, there are differences
in the application instructions and the external I/O devices which can be used and in the program
capacities, etc. Model-specific functions are marked as shown below. Common functions are not
marked.
Along with this manual, it is recommended that you read the operation manuals for TOUOPUC.
PC/L2-specific functions------------------PC2/L2
PC2J series-specific function------------PC2J
The PC2J series controllers are classified into two types according to the program capacity.
PC2J
PC2JS
8KW PC2JR PC2J-8KW
PC2JF
PC2F
PC2FS
PC2JC
16KW PC2J16 PC2J-16KW
SUB-CPU
PC2JN
32KW PC2JNM PC2J-32KW

PC2JNF
PC3J-specific functions---------------PC3J
PC3JG-specific functions-------------PC3JG
Ver.---------This is usable for the specific version or later.

PC2/L2, PC2J : Ver 3.50 or later
PC2JS/JR : Ver2.30 or later
PC2JC : Ver 3.20 or later
PC2J16 : Ver2.10 or later
SUB-CPU : Ver2.50 or later
PC2JNM/PC2JNF : Ver2.00 or later
This is not usable for PC2JN.
vi
Contents
FOREWORD
FOR SAFETY OPERATION
REVISION HISTORY OF OPERATION MANUAL
Composition of Related Operation Manuals
Contents 1
1. MAKINK SEQUENCE CIRCUITS......................................................................................................................... 1-1
1.1. Usage of TOYOPUC ...................................................................................................................................... 1-1
1.1.1. Connection between I/O devices and TOYOPUC ................................................................................... 1-1
1.1.2. I/O address .............................................................................................................................................. 1-1
1.2. Circuit diagram configuration ......................................................................................................................... 1-4
1.3. I/O circuit ........................................................................................................................................................ 1-5
1.3.1. Input section ............................................................................................................................................ 1-5
1.3.2. Output section.......................................................................................................................................... 1-6
1.4. Logic section .................................................................................................................................................. 1-7
1.4.1. Internal relay (dummy output).................................................................................................................. 1-7
1.4.2. Timer........................................................................................................................................................ 1-8
1.4.3. Counter .................................................................................................................................................... 1-9
1.4.4. Keep relay.............................................................................................................................................. 1-10
1.4.5. Edge detection....................................................................................................................................... 1-11
1.4.6. Special relay .......................................................................................................................................... 1-12
1.4.7 Link relay ................................................................................................................................................ 1-37
1.4.8. Designation of Register Bit PC3J........................................................................................................ 1-38
1.5. Application instruction................................................................................................................................... 1-39
1.5.1. Application instruction............................................................................................................................ 1-39
1.5.2. Data register .......................................................................................................................................... 1-39
1.5.3. File register ............................................................................................................................................ 1-40
1.5.4. Link register ........................................................................................................................................... 1-40
1.5.5. Current value register ............................................................................................................................ 1-40
1.5.6. Buffer register PC3JG............................................................................................................................ 1-40
1.5.7. Special register ...................................................................................................................................... 1-41
2. EXECUTION OF PROGRAM ............................................................................................................................... 2-1
2.1. Processing operation...................................................................................................................................... 2-1
2.2. Subroutine ...................................................................................................................................................... 2-4
2.3. Interrupt program PC2/L2............................................................................................................................ 2-5
2.3.1. Periodic interrupt...................................................................................................................................... 2-5
2.3.2. External interrupt ..................................................................................................................................... 2-6
2.3.3. Interrupt program considerations............................................................................................................. 2-7
2.4. Scan time ....................................................................................................................................................... 2-8
3. PARAMETER ........................................................................................................................................................ 3-1
3.1. Contents of parameters.................................................................................................................................. 3-1
3.2. Setting the parameters ................................................................................................................................... 3-4
3.2.1. Auto setting by CPU module.................................................................................................................... 3-4
3.2.1.1. In case of PC2/L2, PC2J.............................................................................................................. 3-4
3.2.1.2. In case of PC3J series ................................................................................................................. 3-8
3.2.2. Setting with a peripheral device............................................................................................................... 3-9
4. USER MEMORY STRUCTURE............................................................................................................................ 4-1
4.1. Program memory structure ............................................................................................................................ 4-1
4.1.1. In case of PC2/L, PC2J ........................................................................................................................... 4-1
4.1.2. In case of PC3J series............................................................................................................................. 4-2
4.2. Data memory structure................................................................................................................................. 4-11
4.2.1. In case of PC2/L, PC2J ......................................................................................................................... 4-11
4.2.1.1. Data memory map........................................................................................................................... 4-11
4.2.1.2. Data memory address..................................................................................................................... 4-12
4.2.2. In case of PC3J series........................................................................................................................... 4-15
4.2.2.1. Data memory map........................................................................................................................... 4-15
4.2.2.2. I/O address table ........................................................................................................................ 4-18
5. INSTRUCTION WORDS....................................................................................................................................... 5-1
5.1. Basic instructions ........................................................................................................................................... 5-1
5.1.1. Extension on the PC3J series ................................................................................................................. 5-2
1.STR, STR NOT............................................................................................................................................ 5-6
2.AND, AND NOT ........................................................................................................................................... 5-7
3.OR, OR NOT ............................................................................................................................................... 5-8
4.AND STR ..................................................................................................................................................... 5-9
5.OR STR ..................................................................................................................................................... 5-10
6. ... OUT....................................................................................................................................................... 5-11
7. .... SET....................................................................................................................................................... 5-12
8. ... RST....................................................................................................................................................... 5-13
9.PTS, NTS................................................................................................................................................... 5-14
10.FPS, FRD, FPP ....................................................................................................................................... 5-16
11. ... FST....................................................................................................................................................... 5-17
12. . NOT....................................................................................................................................................... 5-18
13. . NOP....................................................................................................................................................... 5-19
5.2. Timer and counter instructions ..................................................................................................................... 5-20
1.TMRH (Direct mode 10ms timer) .......................................................................................................... 5-25
2.TMRH (Indirect mode 10ms timer)........................................................................................................ 5-26
3.TMR (Direct mode 100ms timer)........................................................................................................... 5-27
4.TMR (Indirect mode 100ms timer) ........................................................................................................ 5-28
5.TMRSH (Direct mode 10ms integrating timer)...................................................................................... 5-29
6.TMRSH (Indirect mode 10ms integrating timer) ................................................................................... 5-30
7.TMRS (Direct mode 100 ms integrating timer) ..................................................................................... 5-31
8.TMRS (Indirect mode 100 ms integrating timer) ................................................................................... 5-32
9.CNT (Direct mode up counter) .............................................................................................................. 5-33
10.CNT (Indirect mode up counter).......................................................................................................... 5-34
11.CNTD (Direct mode down counter) ..................................................................................................... 5-35
12.CNTD (Indirect mode down counter) .................................................................................................. 5-36
13.CNTH (Direct mode up/down counter)................................................................................................ 5-37
14.CNTH (Indirect up/down counter) ....................................................................................................... 5-39
15.ETMRH Extended 10ms Timer ........................................................................................................... 5-41
16.ETMR Extended 100ms Timer ............................................................................................................ 5-42
17.ETMRSH Extended 10ms Integrating Timer....................................................................................... 5-43
18.ETMRS Extended 100ms Integrating Timer ....................................................................................... 5-44
19.ECNT Extended Counter (UP) ............................................................................................................ 5-45
20.ECNTD Extended Counter (Down) ..................................................................................................... 5-46
21.ECNTH Extended Counter (Up-Down) ............................................................................................... 5-47
5.3. Contact type application instructions............................................................................................................ 5-48
1.=H 2-digit hexadecimal constant comparison (=).................................................................................. 5-50
2.=D 3-digit decimal constant comparison (=).......................................................................................... 5-51
3.=N Byte data comparison (=) ................................................................................................................ 5-52
4.W=H 4-digit hexadecimal constant comparison (=) .............................................................................. 5-53
5.W=D 5-digit decimal constant comparison (=) ...................................................................................... 5-54
6.W=N Word data comparison (=)............................................................................................................ 5-55
7.D=H 8-digit hexadecimal constant comparison (=) *............................................................................. 5-56
8.D=D 10-digit decimal constant comparison (=) * .................................................................................. 5-57
9.D=N 32-bit data comparison (=) * ......................................................................................................... 5-58
10.<>H 2-digit hexadecimal constant comparison (<>) ........................................................................... 5-59
11.<>D 3-digit decimal constant comparison (<>).................................................................................... 5-60
12.<>N Byte data comparison (<>) .......................................................................................................... 5-61
13.W<>H 4-digit hexadecimal constant comparison (<>) ........................................................................ 5-62
14.W<>D 5-digit decimal constant comparison (<>)................................................................................ 5-63
15.W<>N Word data comparison (<>) ..................................................................................................... 5-64
16.D<>H 8-digit hexadecimal constant comparison (<>) * ...................................................................... 5-65
17.D<>D 10-digit decimal constant comparison (<>) * ............................................................................ 5-66
18.D<>N 32-bit data comparison (<>) * ................................................................................................... 5-67
19.>H 2-digithexadecimal constant comparison (>)................................................................................. 5-68
20.>D 3-digit decimal constant comparison (>)........................................................................................ 5-69
21.>N Byte data comparison (>) .............................................................................................................. 5-70
22.W>H 4-digit hexadecimal constant comparison (>) ............................................................................ 5-71
23.W>D 5-digit decimal constant comparison (>) .................................................................................... 5-72
24.W>N Word data comparison (>).......................................................................................................... 5-73
25.D>H 8-digit hexadecimal constant comparison (>) *........................................................................... 5-74
26.D>D 10-digit decimal constant comparison (>) * ................................................................................ 5-75
27.D>N 32-bit data comparison (>) * ....................................................................................................... 5-76
28.>=H 2-digit hexadecimal constant comparison (>=) ........................................................................... 5-77
29.>=D 3-digit decimal constant comparison (>=) ................................................................................... 5-78
30.>=N Byte data comparison (>=) .......................................................................................................... 5-79
31.W>=H 4-digit hexadecimal constant comparison (>=) ........................................................................ 5-80
32.W>=D 5-digit decimal constant comparison (>=)................................................................................ 5-81
33.W>=N Word data comparison (>=) ..................................................................................................... 5-82
34.D>=H 8-digit hexadecimal constant comparison (>=) * ...................................................................... 5-83
35.D>=D 10-digit decimal constant comparison (>=) * ............................................................................ 5-84
36.D>=N 32-bit data comparison (>=) * ................................................................................................... 5-85
37.<H 2-digit hexadecimal constant comparison (<)................................................................................ 5-86
38.<D 3-digit decimal constant comparison (<)........................................................................................ 5-87
39.<N Byte data comparison (<) *............................................................................................................ 5-88
40.W<H 4-digit hexadecimal constant comparison (<) ............................................................................ 5-89
41.W<D 5-digit decimal constant comparison (<) .................................................................................... 5-90
42.W<N Word data comparison (<) * ....................................................................................................... 5-91
43.D<H 8-digit hexadecimal constant comparison (<) *........................................................................... 5-92
44.D<D 10-digit decimal constant comparison (<) * ................................................................................ 5-93
45.D<N 32-bit data comparison (<) * ....................................................................................................... 5-94
46.<=H 2-digit hexadecimal constant comparison (<=) ........................................................................... 5-95
47.<=D 3-digit decimal constant comparison (<=) ................................................................................... 5-96
48.<=N Byte data comparison (<=) *........................................................................................................ 5-97
49.W<=H 4-digit hexadecimal constant comparison (<=) ........................................................................ 5-98
50.W<=D 5-digit decimal constant comparison (<=)................................................................................ 5-99
51.W<=N Word data comparison (<=) *................................................................................................. 5-100
52.D<=H 8-digit hexadecimal constant comparison (<=) * .................................................................... 5-101
53.D<=D 10-digit decimal constant comparison (<=) * .......................................................................... 5-102
54.D<=N 32-bit data comparison (<=) * ................................................................................................. 5-103
5.4. Output type application instructions Note)............................................................................................... 5-104
5.4.1. Transfer instructions ............................................................................................................................ 5-122
1.MOV 2-digit Hex constant transfer (FUN100) ..................................................................................... 5-123
2.WMOV 4-digit Hex constant transfer (FUN101).................................................................................. 5-124
3.DMOV 8-digit Hex constant transfer (FUN102) .................................................................................. 5-125
4.MOVP 2-digit BCD constant transfer (FUN103).................................................................................. 5-126
5.WMOVP 4-digit BCD constant transfer (FUN1) .................................................................................. 5-127
6.DMOVP 8-digit BCD constant transfer (FUN104) ............................................................................... 5-128
7.MOVR 3-digit decimal constant transfer (FUN105) ............................................................................ 5-129
8.WMOVR 5-digit decimal constant transfer (FUN7) ............................................................................. 5-130
9.DMOVR 10-digit decimal constant transfer (FUN106)........................................................................ 5-131
10.MOVQ 3-digit octal transfer (FUN107).............................................................................................. 5-132
11.WMOVQ 6-digit octal transfer (FUN8)............................................................................................... 5-133
12.DMOVQ 11-digit octal transfer (FUN108) ......................................................................................... 5-134
13.MOVT 2-digit Hex constant transfer to two places (FUN62)............................................................. 5-135
14.WMOVT 4-digit Hex constant transfer to two places (FUN 110)....................................................... 5-136
15.MOVE 1-byte data direct transfer (FUN90)....................................................................................... 5-137
16.WMOVE 2-byte data direct transfer (FUN0) ..................................................................................... 5-138
17.DMOVE 4-byte data direct transfer (FUN111)................................................................................... 5-139
18.MOVF 1-byte data indirect transfer 1 (FUN74) ................................................................................. 5-140
19.WMOVF 2-byte data indirect transfer 1 (FUN112) ............................................................................ 5-141
20.DMOVF 4-byte data indirect transfer 1 (FUN113) * .......................................................................... 5-142
21.MOVG 1-byte data indirect transfer 2 (FUN75) ................................................................................ 5-143
22.WMOVG 2-byte data indirect transfer 2 (FUN114) ........................................................................... 5-144
23.DMOVG 4-byte data indirect transfer 2 (FUN115) *.......................................................................... 5-145
24.MOVH 1-byte data indirect transfer 3 (FUN76)................................................................................. 5-146
25.WMOVH 2-byte data indirect transfer 3 (FUN116) ........................................................................... 5-147
26.DMOVH 4-byte data indirect transfer 3 (FUN117) *.......................................................................... 5-148
27.BMOV1 Byte data block transfer 1 (FUN70)..................................................................................... 5-149
28.BMOV2 Byte data block transfer 2 (FUN118) *................................................................................. 5-150
29.WBMOV Word data block transfer (FUN119) * ................................................................................. 5-151
30.BMVI Byte data indirect block transfer (FUN71) ............................................................................... 5-152
31.WBMVI Word data indirect block transfer (FUN120) *...................................................................... 5-153
32.DIV Byte data delivery (FUN5).......................................................................................................... 5-154
33.WDIV Word data delivery (FUN122) ................................................................................................. 5-155
34.DDIV 32-bit data delivery (FUN123) * ............................................................................................... 5-156
35.BDIV Byte data block delivery(FUN72) ............................................................................................. 5-157
36.WBDIV Word data block delivery(FUN126) ...................................................................................... 5-158
37.PUP Byte data extraction (FUN6) ..................................................................................................... 5-159
38.WPUP Word data extraction (FUN124) ............................................................................................ 5-160
39.DPUP 32-bit data extraction (FUN125) * .......................................................................................... 5-161
40.BPUP Byte data block extraction(FUN73) ........................................................................................ 5-162
41.WBPUP Word data block extraction(FUN127).................................................................................. 5-163
42.SXCH 4-bit data exchange(FUN53).................................................................................................. 5-164
43.XCH 8-bit data exchange(FUNl32) ................................................................................................... 5-165
44.WXCH 16-bit data exchange(FUN2)................................................................................................. 5-166
45.DXCH 32-bit data exchange(FUN133) * ........................................................................................... 5-167
46.BXCH Byte data block exchange(FUN134) ...................................................................................... 5-168
47.WBXCH Word data block exchange (FUN 135) ............................................................................... 5-169
48.JIS Storage in JIS code (FUN 109)................................................................................................... 5-170
49.FIL1 Byte data fill 1 (FUN 77)............................................................................................................ 5-171
50.FIL2 Byte data fill 2 (FUN 128) * ....................................................................................................... 5-172
51.WFIL Word data fill (FUN 129) *........................................................................................................ 5-173
52.FILI1 Byte data indirect fill 1 (FUN 78) .............................................................................................. 5-174
53.FILI2 Byte data indirect fill 2 (FUN 130) * ......................................................................................... 5-175
54.WFILI Word data indirect fill (FUN 131) *.......................................................................................... 5-176
55.CMOV Byte data transfer on clearance confirmation (FUN 20)........................................................ 5-177
56.WCMOV Word data transfer on clearance confirmation (FUN 166)................................................. 5-178
57.CLR Matching data clearance (byte) (FUN 21)................................................................................. 5-179
58.WCLR Matching data clearance (Word) (FUN 167) ......................................................................... 5-180
59.REF External input transfer (FUN 283) !# .......................................................................................... 5-181
60.REFO External output transfer (FUN 284) !# ..................................................................................... 5-182
61.MOVJ 1-byte transfer from register to file register (FUN 144) %& ..................................................... 5-183
62.WMOVJ 2-byte transfer from register to file register (FUN 145) %& .................................................. 5-184
63.DMOVJ 4-byte transfer from register to file register (FUN 146) %& ................................................... 5-185
64.MOVK 1-byte transfer from file register to register (FUN 147) %& ..................................................... 5-186
65.WMOVK 2-byte transfer from file register to register (FUN 148) %& ................................................. 5-187
66.DMOVK 4-byte transfer from file register to register (FUN 149) %& .................................................. 5-188
5.4.2. Arithmetic operations ........................................................................................................................... 5-189
67.+ Byte data binary addition (FUN 168).............................................................................................. 5-190
68.W+ Word data binary addition (FUN 92)........................................................................................... 5-191
69.D+ 32-bit data binary addition (FUN 169) ......................................................................................... 5-192
70.+P 2-digit BCD addition (FUN 177)................................................................................................... 5-193
71.W+P 4-digit BCD addition (FUN 10) ................................................................................................. 5-194
72.D+P 8-digit BCD addition (FUN 178) ................................................................................................ 5-195
73.- Byte data binary subtraction (FUN 170) ......................................................................................... 5-196
74.W- Word data binary subtraction (FUN 93)....................................................................................... 5-197
75.D- 32-bit data binary subtraction (FUN 171) ..................................................................................... 5-198
76.-P 2-digit BCD subtraction (FUN 179)............................................................................................... 5-199
77.W-P 4-digit BCD subtraction (FUN 11).............................................................................................. 5-200
78.D-P 8-digit BCD subtraction (FUN 180) ............................................................................................ 5-201
79.* Byte data binary multiplication (FUN 172) ...................................................................................... 5-202
80.W* Word data binary multiplication (FUN 94) ................................................................................... 5-203
81.D* 32-bit data binary multiplication (FUN 173).................................................................................. 5-204
82.*P 2-digit BCD multiplication (FUN 181) ........................................................................................... 5-205
83.W*P 4-digit BCD multiplication (FUN 182) ........................................................................................ 5-206
84.D*P 8-digit BCD multiplication (FUN 183)......................................................................................... 5-207
85.W/B Word data binary division 1 (FUN 95) ....................................................................................... 5-208
86./ Byte data binary division (FUN 174) # ............................................................................................. 5-209
87.W/ Word data binary division 2 (FUN 175) # ..................................................................................... 5-210
88.D/ 32-bit data binary division (FUN 176) #......................................................................................... 5-211
89./P 2-digit BCD division (FUN 184)..................................................................................................... 5-212
90.W/P 4-digit BCD division (FUN 185) ................................................................................................. 5-213
91.D/P 8-digit BCD division (FUN 186) .................................................................................................. 5-214
5.4.3 Logical operation instructions............................................................................................................... 5-215
92.AND Byte data logical product(AND) (FUN 13) ................................................................................ 5-216
93.WAND Word data logical product(AND) (FUN 187).......................................................................... 5-217
94.DAND 32-bit data logical product(AND) (FUN 188).......................................................................... 5-218
95.OR Byte data logical sum(OR) (FUN 14) .......................................................................................... 5-219
96.WOR Word data logical sum(OR) (FUN 189) ................................................................................... 5-220
97.DOR 32-bit data logical sum(OR) (FUN 190) ................................................................................... 5-221
98.NOT Byte data inversion (FUN 9) ..................................................................................................... 5-222
99.WNOT Word data inversion (FUN 191) ............................................................................................ 5-223
100.DNOT 32-bit data inversion (FUN 192)........................................................................................... 5-224
101.XOR Byte data exclusive logical sum(XOR) (FUN 18) ................................................................... 5-225
102.WXOR Word data exclusive logical sum(XOR) (FUN 193) ............................................................ 5-226
103.DXOR 32-bit data exclusive logical sum(XOR) (FUN 194)............................................................. 5-227
5.4.4 Increment and decrement .................................................................................................................... 5-228
104.INC Byte data binary increment (FUN 195) .................................................................................... 5-229
105.WINC Word data binary increment (FUN 63).................................................................................. 5-230
106.DINC 32-bit data binary increment (FUN 196)................................................................................ 5-231
107.INCP 2-digit BCD increment (FUN 199).......................................................................................... 5-232
108.WINCP 4-digit BCD increment (FUN 200) ...................................................................................... 5-233
109.DINCP 8-digit BCD increment (FUN 201) ....................................................................................... 5-234
110.DEC Byte data binary decrement (FUN 197) .................................................................................. 5-235
111.WDEC Word data binary decrement (FUN 64) ............................................................................... 5-236
112.DDEC 32-bit data binary decrement (FUN 198) ............................................................................. 5-237
113.DECP 2-digit BCD decrement (FUN 202) ....................................................................................... 5-238
114.WDECP 4-digit BCD decrement (FUN 203).................................................................................... 5-239
115.DDECP 8-digit BCD decrement (FUN 204)..................................................................................... 5-240
5.4.5. Search ................................................................................................................................................. 5-241
116.SRH1 Byte data search 1 (FUN 88) ................................................................................................ 5-242
117.WSRH1 Word data search 1 (FUN 89) ........................................................................................... 5-244
118.SRH2 Byte data search 2 (FUN 212) .............................................................................................. 5-246
119.WSRH2 Word data search 2 (FUN 213) ......................................................................................... 5-248
120.DSRH 32-bit data Search (FUN 214).............................................................................................. 5-250
5.4.6 Parity .................................................................................................................................................... 5-252
121.MKP1 Odd parity composition (FUN 83)......................................................................................... 5-253
122.MKP2 Even parity composition (FUN 81) ....................................................................................... 5-254
123.PCH1 Odd parity check (FUN 84)................................................................................................... 5-255
124.PCH2 Even Parity check (FUN 82) ................................................................................................. 5-256
5.4.7. Data conversion................................................................................................................................... 5-257
125.BIN 2-digit BCD to 8-bit binary (FUN 152) ...................................................................................... 5-258
126.WBIN 4-digit BCD to 16-bit binary (FUN 3)..................................................................................... 5-259
127.DBIN 8-bit BCD to 32-bit binary (FUN 153) .................................................................................... 5-260
128.BCD 8-bit binary to 2-digit BCD (FUN 154) .................................................................................... 5-261
129.WBCD 16-bit binary to 4-bit BCD (FUN 4)...................................................................................... 5-262
130.DBCD 32-bit binary to 8-digit BCD (FUN 155)................................................................................ 5-263
131.JBIN JIS code to binary (FUN 156)................................................................................................. 5-264
132.BJIS Binary to JIS code (FUN 157) ................................................................................................ 5-266
133.DECO 4 to 16 decoder (FUN 50) .................................................................................................... 5-268
134.ENCO 16 to 4 encoder (FUN 51) .................................................................................................... 5-270
135.SEG 7-segment decode (FUN 52) .................................................................................................. 5-272
136.WTIM1 Hours, minutes, and seconds to seconds (FUN 158) ........................................................ 5-274
137.WTIM2 Seconds to hours, minutes and seconds (FUN 159) ......................................................... 5-276
138.CDSET Code conversion set (FUN 85) .......................................................................................... 5-278
139.CDO1 Code conversion output 1 (FUN 86) .................................................................................... 5-279
140.CDO2 Code conversion output 2 (FUN 87) .................................................................................... 5-280
5.4.8 Comparison .......................................................................................................................................... 5-281
141.CP Byte data comparison (FUN 17)................................................................................................ 5-282
142.WCP Word data comparison (FUN 12) ........................................................................................... 5-283
143.DCP 32-bit data comparison (FUN 211) ......................................................................................... 5-284
5.4.9. Bit operation......................................................................................................................................... 5-285
144.BSET Byte data bit set (FUN 136) *................................................................................................ 5-286
145.WBSET Word data set (FUN 137) .................................................................................................. 5-287
146.DBSET 32-bit data bit set (FUN 138) * ........................................................................................... 5-288
147.BRST Byte data bit reset (FUN 139) * ............................................................................................ 5-289
148.WBRST Word data bit reset (FUN 140) .......................................................................................... 5-290
149.DBRST 32-bit data bit reset (FUN 141) * ........................................................................................ 5-291
150.BPU Bit extraction (FUN 54) *......................................................................................................... 5-292
151.WBPU Word data bit extraction (FUN 142)..................................................................................... 5-293
152.DBPU 32-bit data extraction (FUN 143) * ....................................................................................... 5-294
153.SUM Byte data ON-bit count (FUN 208) ......................................................................................... 5-295
154.WSUM Word data ON-bit count (FUN 209) .................................................................................... 5-296
155.DSUM 32-bit data ON-bit count (FUN 210) .................................................................................... 5-297
5.4.10 Shift .................................................................................................................................................... 5-298
156.SFR Byte data 1 bit right shift (FUN 217) * ..................................................................................... 5-299
157.WSFR Word data 1 bit right shift (FUN 36) * .................................................................................. 5-300
158.DSFR 32-bit data 1 bit right shift (FUN 218) *................................................................................. 5-301
159.BSFR Byte data n bits right shift (FUN 224) * ................................................................................. 5-302
160.WBSFR Word data n bits right shift (FUN 225) * ............................................................................ 5-303
161.DBSFR 32-bit data n bits right shift (FUN 226) *............................................................................. 5-304
162.SFL Byte data 1 bit left shift (FUN 219) * ........................................................................................ 5-305
163.WSFL Word data 1 bit left shift (FUN 37) * ..................................................................................... 5-306
164.DSFL 32-bit data 1 bit left shift (FUN 220) *.................................................................................... 5-307
165.BSFL Byte data n bits left shift (FUN 227) * .................................................................................... 5-308
166.WBSFL Word data n bits left shift (FUN 228) * ............................................................................... 5-309
167.DBSFL 32-bit data n bits left shift (FUN 229) *................................................................................ 5-310
168.SRL Byte data 1 bit right-left shift (FUN 221) * ............................................................................... 5-311
169.WSRL Word data 1 bit right-left shift (FUN 222) *........................................................................... 5-312
170.DSRL 32-bit data 1 bit right-left shift (FUN 223) * ........................................................................... 5-313
171.BSRL Byte data n bits right-left shift (FUN 230).............................................................................. 5-314
172.WBSRL Word data n bits right-left shift (FUN 231) ......................................................................... 5-315
173.DBSRL 32-bit data n bits right-left shift (FUN 232) ......................................................................... 5-316
174.SUP 4 bit data upper-digit direction shift (FUN 251)....................................................................... 5-317
175.UP1 Byte data upper-digit direction shift 1 (FUN 91)...................................................................... 5-318
176.UP2 Byte data upper-digit direction shift 2 (FUN 252).................................................................... 5-319
177.WUP Word data upper-digit direction shift (FUN 253) .................................................................... 5-320
178.DUP 32-bit data upper-digit direction shift (FUN 254) .................................................................... 5-321
179.SDOWN 4 bit data lower-digit direction shift (FUN 255) ................................................................. 5-323
180.DOWN Byte data lower-digit direction shift (FUN 256) ................................................................... 5-324
181.WDOWN Word data lower-digit direction shift (FUN 257) .............................................................. 5-325
182.DDOWN 32-bit data lower-digit direction shift (FUN 258)............................................................... 5-326
183.FIFW Byte data FIFO write (FUN 160)............................................................................................ 5-328
184.WFIFW Word data FIFO write (FUN 161)....................................................................................... 5-329
185.DFIFW 32-bit data FIFO write (FUN 162) ....................................................................................... 5-330
186.FIFR Byte data FIFO read (FUN 163)............................................................................................. 5-332
187.WFIFR Word data FIFO read (FUN 164) ........................................................................................ 5-334
188.DFIFR 32-bit data FIFO read (FUN 165) ........................................................................................ 5-336
189.SFIN Accumulation shift input (FUN 68) ......................................................................................... 5-338
190.SFOUT Accumulation shift output (FUN 69) ................................................................................... 5-340
5.4.11. Rotate................................................................................................................................................. 5-342
191.RRC Byte data right rotate with carry (FUN 233) * ......................................................................... 5-343
192.WRRC Word data right rotate with carry (FUN 234) * .................................................................... 5-344
193.DRRC 32-bit data right rotate with carry (FUN 235) *..................................................................... 5-345
194.RR Byte data right rotate without carry (FUN 242) *....................................................................... 5-346
195.WRR Word data right rotate without carry (FUN 243) * .................................................................. 5-347
196.DRR 32-bit data right rotate without carry (FUN 244) * .................................................................. 5-348
197.RLC Byte data left rotate with carry (FUN 236) * ............................................................................ 5-349
198.WRLC Word data left rotate with carry (FUN 237) * ....................................................................... 5-350
199.DRLC 32-bit data left rotate with carry (FUN 238) *........................................................................ 5-351
200.RL Byte data left rotate without carry (FUN 245) *.......................................................................... 5-352
201.WRL Word data left rotate without carry (FUN 246) * ..................................................................... 5-353
202.DRL 32-bit data left rotate without carry (FUN 247) * ..................................................................... 5-354
203.RLRC Byte data right-left rotate with carry (FUN 239).................................................................... 5-355
204.WRLRC Word data right-left rotate with carry (FUN 240) ............................................................... 5-356
205.DRLRC 32-bit data right-left rotate with carry (FUN 241) ............................................................... 5-357
206.RLR Byte data right-left rotate without carry (FUN 248) ................................................................. 5-358
207.WRLR Word data right-left rotate without carry (FUN 249) ............................................................ 5-359
208.DRLR 32-bit data right-left rotate without carry (FUN 250)............................................................. 5-360
5.4.12. Programmed branch .......................................................................................................................... 5-361
209.JMP JUMP (FUN 272)..................................................................................................................... 5-362
210.CALL Subroutine call (FUN 273)..................................................................................................... 5-363
211.RET Return from subroutine (FUN 464).......................................................................................... 5-364
212.FOR Start repetition (FUN 472) # .................................................................................................... 5-365
213.FORN Start repetition (indirect) (FUN 476) #................................................................................... 5-366
214.NEXT End of repetition (FUN 480) # ............................................................................................... 5-367
5.4.13 Master control .................................................................................................................................... 5-368
215.MC Master control set (FUN 440) ................................................................................................... 5-369
216.MCR Master control reset (FUN 444) ............................................................................................. 5-370
5.4.14. Input/output control............................................................................................................................ 5-371
217.RIO Input/output refresh (FUN 280) ! .............................................................................................. 5-372
218.RI Input refresh (FUN 281).............................................................................................................. 5-373
219.RO Output refresh (FUN 282) ......................................................................................................... 5-374
5.4.15. Sequential interrupt ........................................................................................................................... 5-375
220.DI Interrupt inhibit (FUN 276) % ....................................................................................................... 5-376
221.PDI Partial interrupt inhibit (FUN 278) % ......................................................................................... 5-377
222.EI Interrupt enable (FUN 277) % ...................................................................................................... 5-378
223.PEI Partial interrupt enable (FUN 279) % ........................................................................................ 5-379
224.RETI Return from interrupt routine (FUN 468) % ............................................................................. 5-380
5.4.16. Label .................................................................................................................................................. 5-381
225.START Main program start (FUN 448)............................................................................................ 5-382
226.END Main program end (FUN 452)................................................................................................. 5-383
227.PEND End of program (FUN 456)................................................................................................... 5-384
228.LABEL Label (FUN 460).................................................................................................................. 5-385
5.4.17 Special module data transfer ............................................................................................................. 5-386
229.SPR Special module byte-data readout (for readout of file for the SIO module) (FUN 304)........ 5-387
230.SPW Special module byte-data write (for writing of file for the SIO module) (FUN 306) ............. 5-389
231.HCR High-speed counter data readout (FUN 316) ! ....................................................................... 5-391
232.HCW High-speed counter data write (FUN 317) ! ........................................................................... 5-392
233.IOR Shared I/O unit data readout (for A/D module) (FUN 318) ! .................................................... 5-393
234.IOW Shared I/O unit data write (for A/D module) (FUN 319) ! ........................................................ 5-394
5.4.18. Sequential debug............................................................................................................................... 5-395
235.ENB Trace enable (FUN 274) ......................................................................................................... 5-396
236.TRG Trace trigger (FUN 275).......................................................................................................... 5-397
5.4.19. I/O monitor control ............................................................................................................................. 5-398
237.KEY I/O monitor key input (FUN 294) %#......................................................................................... 5-401
238.LEDD I/O monitor display (FUN 289) %# ......................................................................................... 5-402
239.LEDC I/O monitor display clear (FUN 290) %# ................................................................................ 5-404
5.4.20. Application instruction for memory card PC2/L2 ............................................................................... 5-405
240.CDR Memory card data read (FUN 296) $ ...................................................................................... 5-406
241.CDW Memory card data write (FUN 297) $ ..................................................................................... 5-407
242.CDIR Indirect memory card data read (FUN 298) $ ........................................................................ 5-408
243.CDIW Indirect memory card write (FUN 299) $ ............................................................................... 5-409
5.4.21. Other application instruction .............................................................................................................. 5-410
244.SYS Setting/resetting of I/O monitor error automatic indication ..................................................... 5-411
245.ANN Annunciator (FUN 291)........................................................................................................... 5-412
246.USC User defined clock (FUN 293) ................................................................................................ 5-413
247.ADJ Built-in clock 30-second adjustment (FUN 292) ! .................................................................... 5-414
248.BAUD Peripheral device communication speed setting (FUN 288) # ............................................. 5-415
249.STOP Program stop (FUN 287) ...................................................................................................... 5-416
250.WDR Scan timer reset (FUN 46)..................................................................................................... 5-417
5.4.22. Extension of applied instruction for PC3J series PC3J ..................................................................... 5-418
251.BBMOV Bit Block Transfer (move) (FUN 121) PC3J ...................................................................... 5-422
252.STURN 4bits inversion (FUN 259) PC3J ........................................................................................ 5-423
253.TURN 8bits inversion (FUN 260) PC3J........................................................................................... 5-423
254.WTURN 16bits inversion (FUN 261) PC3J ..................................................................................... 5-423
255.MOVAD Address Constant Transfer (Move) (FUN 320) PC3J ....................................................... 5-425
256.+H Addition of hexadecimal 2-digit constant (FUN 323) PC3J ....................................................... 5-426
257.W+H Addition of hexadecimal 4-digit constant (FUN 324) PC3J.................................................... 5-427
258.D+H Addition of hexadecimal 8-digit constant (FUN 325) PC3J .................................................... 5-428
259.+HP Addition of BCD 2-digit constant (FUN 326) PC3J ................................................................. 5-429
260.W+HP Addition of BCD 4-digit constant (FUN 327) PC3J .............................................................. 5-430
261.D+HP Addition of BCD 8-digit constant (FUN 328) PC3J............................................................... 5-431
262.-H Deduction of hexadecimal 2-digit constant (FUN 329) PC3J .................................................... 5-432
263.W-H Deduction of hexadecimal 4-digit constant (FUN 330) PC3J ................................................. 5-433
264.D-H Deduction of hexadecimal 8-digit constant (FUN 331) PC3J .................................................. 5-434
265.-HP Addition of BCD 2-digit constant (FUN 332) PC3J .................................................................. 5-435
266.W-HP Addition of BCD 4-digit constant (FUN 333) PC3J............................................................... 5-436
267.D-HP Addition of BCD 8-digit constant (FUN 334) PC3J................................................................ 5-437
268.*H Multiplication of hexadecimal 2-digit constant (FUN 335) PC3J................................................ 5-438
269.W*H Multiplication of hexadecimal 4-digit constant (FUN 336) PC3J ............................................ 5-439
270.D*H Multiplication of hexadecimal 8-digit constant (FUN 337) PC3J ............................................. 5-440
271.*HP Multiplication of BCD 2-digit constant (FUN 338) PC3J .......................................................... 5-441
272.W*HP Multiplication of BCD 4-digit constant (FUN 339) PC3J....................................................... 5-442
273.D*HP Multiplication of BCD 8-digit constant (FUN 340) PC3J........................................................ 5-443
274./H Divide of hexadecimal 2-digit constant (FUN 341) PC3J ........................................................... 5-444
275.W/H Divide of hexadecimal 4-digit constant (FUN 342) PC3J........................................................ 5-445
276.D/H Divide of hexadecimal 8-digit constant (FUN 343) PC3J ........................................................ 5-446
277./HP Divide of BCD 2-digit constant (FUN 344) PC3J ..................................................................... 5-447
278.W/HP Divide of BCD 4-digit constant (FUN 345) PC3J .................................................................. 5-448
279.D/HP Divide of BCD 8-digit constant (FUN 346) PC3J................................................................... 5-449
280.ANDH Logical product (AND) of hexadecimal 2-digit constant (FUN 347) PC3J ........................... 5-450
281.WANDH Logical product (AND) of hexadecimal 4-digit constant (FUN 348) PC3J........................ 5-451
282.DANDH Logical product (AND) of hexadecimal 8-digit constant (FUN 349) PC3J ........................ 5-452
283.ORH Logical sum (OR) of hexadecimal 2-digit constant (FUN 350) PC3J..................................... 5-453
284.WORH Logical sum (OR) of hexadecimal 4-digit constant (FUN 351) PC3J ................................. 5-454
285.DORH Logical sum (OR) of hexadecimal 8-digit constant (FUN 352) PC3J .................................. 5-455
286.XORH Exclusive logical sum (XOR) of hexadecimal 2-digit constant (FUN 353) PC3J................. 5-456
287.WXORH Exclusive logical sum (XOR) of hexadecimal 4-digit constant (FUN 354) PC3J ............. 5-457
288.DXORH Exclusive logical sum (XOR) of hexadecimal 8-digit constant (FUN 355) PC3J .............. 5-458
289.STI1 Byte data sum (FUN 362) PC3J ............................................................................................. 5-459
290.WSTI1 Word data sum (FUN 363) PC3J ........................................................................................ 5-459
291.DSTI1 32-bit data sum (FUN 364) PC3J......................................................................................... 5-459
292.MAX Byte data maximum value retrieve (FUN 374) PC3J ............................................................. 5-461
293.WMAX Word data maximum value retrieve (FUN 375) PC3J ........................................................ 5-461
294.DMAX 32-bit data maximum value retrieve (FUN 376) PC3J......................................................... 5-461
295.MIN Byte data minimum value retrieve (FUN 377) PC3J ............................................................... 5-462
296.WMIN Word data minimum value retrieve (FUN 378) PC3J........................................................... 5-462
297.DMIN 32-bit data minimum value retrieve (FUN 379) PC3J ........................................................... 5-462
298.AVE Byte data average (FUN 380) PC3J ....................................................................................... 5-463
299.WAVE Word data average (FUN 381) PC3J................................................................................... 5-463
300.DAVE 32-bit data average (FUN 382) PC3J ................................................................................... 5-463
301.CRET Return from subroutine (FUN 285) PC3J............................................................................. 5-463
302.ARIO Area-designated I/O refresh (FUN 295) PC3J ...................................................................... 5-464
303.SYS Applied command flag clear mode setting (FUN 300) PC3J .................................................. 5-465
304.BRSET Buffer register(EB) address set (FUN 371) PC3JG......................................................... 5-466
305.WBR Data loading from the buffer register(EB) (FUN 372) PC3JG............................................. 5-467
306.WBW Data saving to the buffer register(EB) (FUN 373) PC3JG ................................................. 5-468
307.MSET Output of the message for DLNK-M2 (FUN 302) PC3JG ................................................. 5-469
308.CSET I/O Register read-out instruction issue to TOYOPUC-PCS (FUN 370) PC3JG..................... 5-470
309.SYS Clock adjustment instruction (FUN 300) PC3J ......................................................................... 5-479
Note) The instructions marked with # can be used by the L2 but not by the PC2 of the version before
SCPU-3.01.
The instructions marked with * can not be use by the PC2 of the some versions.
The available versions are the following as.
CPU Version
PC2J Ver3.50 or later
PC2JS/JR Ver2.30 or later
PC2JF Ver3.50 or later
PC2F Ver4.30 or later
PC2FS Ver2.10 or later
PC2JC Ver3.20 or later
PC2J16 Ver2.10 or later
SUB-CPU Ver2.50 or later
PC2JNM/PC2JNF Ver2.00 or later
PC2JN Ver2.10 or later
The instructions marked with ! can not be used by the SUB-CPU.
The instructions marked with % can be used by the PC2/L2.
The instructions marked with $ can be used by the PC2/L2 of the Ver SCPU-4.10 or later.
The instructions marked with & can be used by the PC3J series.
Index of instruction words
- Byte data binary subtraction (FUN 170) 5-196

* Byte data binary multiplication (FUN 172) 5-202
*H Multiplication of hexadecimal 2-digit constant (FUN 335) PC3J 5-438
*HP Multiplication of BCD 2-digit constant (FUN 338) PC3J 5-441
*P 2-digit BCD multiplication (FUN 181) 5-205
/ Byte data binary division (FUN 174) # 5-209
/H Divide of hexadecimal 2-digit constant (FUN 341) PC3J 5-444
/HP Divide of BCD 2-digit constant (FUN 344) PC3J 5-447
/P 2-digit BCD division (FUN 184) 5-212
+ Byte data binary addition (FUN 168) 5-190
+H Addition of hexadecimal 2-digit constant (FUN 323) PC3J 5-426
+HP Addition of BCD 2-digit constant (FUN 326) PC3J 5-429
+P 2-digit BCD addition (FUN 177) 5-193
<=D 3-digit decimal constant comparison (<=) 5-96
<=H 2-digit hexadecimal constant comparison (<=) 5-95
<=N Byte data comparison (<=) * 5-97
<>D 3-digit decimal constant comparison (<>) 5-60
<>H 2-digit hexadecimal constant comparison (<>) 5-59
<>N Byte data comparison (<>) 5-61
<D 3-digit decimal constant comparison (<) 5-87
<H 2-digit hexadecimal constant comparison (<) 5-86
<N Byte data comparison (<) * 5-88
=D 3-digit decimal constant comparison (=) 5-51
=H 2-digit hexadecimal constant comparison (=) 5-50
=N Byte data comparison (=) 5-52
>=D 3-digit decimal constant comparison (>=) 5-78
>=H 2-digit hexadecimal constant comparison (>=) 5-77
>=N Byte data comparison (>=) 5-79
>D 3-digit decimal constant comparison (>) 5-69
>H 2-digithexadecimal constant comparison (>) 5-68
>N Byte data comparison (>) 5-70
ADJ Built-in clock 30-second adjustment (FUN 292) ! 5-414

AND Byte data logical product(AND) (FUN 13) 5-216
AND STR 5-9
AND, AND NOT 5-7
ANDH Logical product (AND) of hexadecimal 2-digit constant (FUN 347) PC3J 5-450
ANN Annunciator (FUN 291) 5-412
ARIO Area-designated I/O refresh (FUN 295) PC3J 5-464
AVE Byte data average (FUN 380) PC3J 5-463
BAUD Peripheral device communication speed setting (FUN 288) # 5-415

BBMOV Bit Block Transfer (move) (FUN 121) PC3J 5-422
BCD 8-bit binary to 2-digit BCD (FUN 154) 5-261
BDIV Byte data block delivery(FUN72) 5-157
BIN 2-digit BCD to 8-bit binary (FUN 152) 5-258
BJIS Binary to JIS code (FUN 157) 5-266
BMOV1 Byte data block transfer 1 (FUN70) 5-149
BMOV2 Byte data block transfer 2 (FUN118) * 5-150
BMVI Byte data indirect block transfer (FUN71) 5-152
BPU Bit extraction (FUN 54) * 5-292
BPUP Byte data block extraction(FUN73) 5-162
BRSET Buffer register(EB) address set (FUN 371) PC3JG 5-466
BRST Byte data bit reset (FUN 139) * 5-289
BSET Byte data bit set (FUN 136) * 5-286
BSFL Byte data n bits left shift (FUN 227) * 5-308
BSFR Byte data n bits right shift (FUN 224) * 5-302
BSRL Byte data n bits right-left shift (FUN 230) 5-314
BXCH Byte data block exchange(FUN134) 5-168
CALL Subroutine call (FUN 273) 5-363

CDIR Indirect memory card data read (FUN 298) $ 5-408
CDIW Indirect memory card write (FUN 299) $ 5-409
CDO1 Code conversion output 1 (FUN 86) 5-279
CDO2 Code conversion output 2 (FUN 87) 5-280
CDR Memory card data read (FUN 296) $ 5-406
CDSET Code conversion set (FUN 85) 5-278
CDW Memory card data write (FUN 297) $ 5-407
CLR Matching data clearance (byte) (FUN 21) 5-179
CMOV Byte data transfer on clearance confirmation (FUN 20) 5-177
CNT (Direct mode up counter) 5-33
CNT (Indirect mode up counter) 5-34
CNTD (Direct mode down counter) 5-35
CNTD (Indirect mode down counter) 5-36
CNTH (Direct mode up/down counter) 5-37
CNTH (Indirect up/down counter) 5-39
CP Byte data comparison (FUN 17) 5-282
CRET Return from subroutine (FUN 285) PC3J 5-463
CSET I/O Register read-out instruction issue to TOYOPUC-PCS (FUN 370) PC3JG 5-470
D- 32-bit data binary subtraction (FUN 171) 5-198

D* 32-bit data binary multiplication (FUN 173) 5-204
D*H Multiplication of hexadecimal 8-digit constant (FUN 337) PC3J 5-440
D*HP Multiplication of BCD 8-digit constant (FUN 340) PC3J 5-443
D*P 8-digit BCD multiplication (FUN 183) 5-207
D/ 32-bit data binary division (FUN 176) # 5-211
D/H Divide of hexadecimal 8-digit constant (FUN 343) PC3J 5-446
D/HP Divide of BCD 8-digit constant (FUN 346) PC3J 5-449
D/P 8-digit BCD division (FUN 186) 5-214
D+ 32-bit data binary addition (FUN 169) 5-192
D+H Addition of hexadecimal 8-digit constant (FUN 325) PC3J 5-428
D+HP Addition of BCD 8-digit constant (FUN 328) PC3J 5-431
D+P 8-digit BCD addition (FUN 178) 5-195
D<=D 10-digit decimal constant comparison (<=) * 5-102
D<=H 8-digit hexadecimal constant comparison (<=) * 5-101
D<=N 32-bit data comparison (<=) * 5-103
D<>D 10-digit decimal constant comparison (<>) * 5-66
D<>H 8-digit hexadecimal constant comparison (<>) * 5-65
D<>N 32-bit data comparison (<>) * 5-67
D<D 10-digit decimal constant comparison (<) * 5-93
D<H 8-digit hexadecimal constant comparison (<) * 5-92
D<N 32-bit data comparison (<) * 5-94
D=D 10-digit decimal constant comparison (=) * 5-57
D=H 8-digit hexadecimal constant comparison (=) * 5-56
D=N 32-bit data comparison (=) * 5-58
D>=D 10-digit decimal constant comparison (>=) * 5-84
D>=H 8-digit hexadecimal constant comparison (>=) * 5-83
D>=N 32-bit data comparison (>=) * 5-85
D>D 10-digit decimal constant comparison (>) * 5-75
D>H 8-digit hexadecimal constant comparison (>) * 5-74
D>N 32-bit data comparison (>) * 5-76
DAND 32-bit data logical product(AND) (FUN 188) 5-218
DANDH Logical product (AND) of hexadecimal 8-digit constant (FUN 349) PC3J 5-452
DAVE 32-bit data average (FUN 382) PC3J 5-463
DBCD 32-bit binary to 8-digit BCD (FUN 155) 5-263
DBIN 8-bit BCD to 32-bit binary (FUN 153) 5-260
DBPU 32-bit data extraction (FUN 143) * 5-294
DBRST 32-bit data bit reset (FUN 141) * 5-291
DBSET 32-bit data bit set (FUN 138) * 5-288
DBSFL 32-bit data n bits left shift (FUN 229) * 5-310
DBSFR 32-bit data n bits right shift (FUN 226) * 5-304
DBSRL 32-bit data n bits right-left shift (FUN 232) 5-316
DCP 32-bit data comparison (FUN 211) 5-284
DDEC 32-bit data binary decrement (FUN 198) 5-237
DDECP 8-digit BCD decrement (FUN 204) 5-240
DDIV 32-bit data delivery (FUN123) * 5-156
DDOWN 32-bit data lower-digit direction shift (FUN 258) 5-326
DEC Byte data binary decrement (FUN 197) 5-235
DECO 4 to 16 decoder (FUN 50) 5-268
DECP 2-digit BCD decrement (FUN 202) 5-238
Deduction of hexadecimal 2-digit constant (FUN 329) PC3J 5-432
DFIFR 32-bit data FIFO read (FUN 165) 5-336
DFIFW 32-bit data FIFO write (FUN 162) 5-330
D-H Deduction of hexadecimal 8-digit constant (FUN 331) PC3J 5-434
D-HP Addition of BCD 8-digit constant (FUN 334) PC3J 5-437
DI Interrupt inhibit (FUN 276) % 5-376
DINC 32-bit data binary increment (FUN 196) 5-231
DINCP 8-digit BCD increment (FUN 201) 5-234
DIV Byte data delivery (FUN5) 5-154
DMAX 32-bit data maximum value retrieve (FUN 376) PC3J 5-461
DMIN 32-bit data minimum value retrieve (FUN 379) PC3J 5-462
DMOV 8-digit Hex constant transfer (FUN102) 5-125
DMOVE 4-byte data direct transfer (FUN111) 5-139
DMOVF 4-byte data indirect transfer 1 (FUN113) * 5-142
DMOVG 4-byte data indirect transfer 2 (FUN115) * 5-145
DMOVH 4-byte data indirect transfer 3 (FUN117) * 5-148
DMOVJ 4-byte transfer from register to file register (FUN 146) %& 5-185
DMOVK 4-byte transfer from file register to register (FUN 149) %& 5-188
DMOVP 8-digit BCD constant transfer (FUN104) 5-128
DMOVQ 11-digit octal transfer (FUN108) 5-134
DMOVR 10-digit decimal constant transfer (FUN106) 5-131
DNOT 32-bit data inversion (FUN 192) 5-224
DOR 32-bit data logical sum(OR) (FUN 190) 5-221
DORH Logical sum (OR) of hexadecimal 8-digit constant (FUN 352) PC3J 5-455
DOWN Byte data lower-digit direction shift (FUN 256) 5-324
D-P 8-digit BCD subtraction (FUN 180) 5-201
DPUP 32-bit data extraction (FUN125) * 5-161
DRL 32-bit data left rotate without carry (FUN 247) * 5-354
DRLC 32-bit data left rotate with carry (FUN 238) * 5-351
DRLR 32-bit data right-left rotate without carry (FUN 250) 5-360
DRLRC 32-bit data right-left rotate with carry (FUN 241) 5-357
DRR 32-bit data right rotate without carry (FUN 244) * 5-348
DRRC 32-bit data right rotate with carry (FUN 235) * 5-345
DSFL 32-bit data 1 bit left shift (FUN 220) * 5-307
DSFR 32-bit data 1 bit right shift (FUN 218) * 5-301
DSRH 32-bit data Search (FUN 214) 5-250
DSRL 32-bit data 1 bit right-left shift (FUN 223) * 5-313
DSTI1 32-bit data sum (FUN 364) PC3J 5-459
DSUM 32-bit data ON-bit count (FUN 210) 5-297
DUP 32-bit data upper-digit direction shift (FUN 254) 5-321
DXCH 32-bit data exchange(FUN133) * 5-167
DXOR 32-bit data exclusive logical sum(XOR) (FUN 194) 5-227
DXORH Exclusive logical sum (XOR) of hexadecimal 8-digit constant (FUN 355) PC3J 5-458
ECNT Extended Counter (UP) 5-45

ECNTD Extended Counter (Down) 5-46
ECNTH Extended Counter (Up-Down) 5-47
EI Interrupt enable (FUN 277) % 5-378
ENB Trace enable (FUN 274) 5-396
ENCO 16 to 4 encoder (FUN 51) 5-270
END Main program end (FUN 452) 5-383
ETMR Extended 100ms Timer 5-42
ETMRH Extended 10ms Timer 5-41
ETMRS Extended 100ms Integrating Timer 5-44
ETMRSH Extended 10ms Integrating Timer 5-43
FIFR Byte data FIFO read (FUN 163) 5-332

FIFW Byte data FIFO write (FUN 160) 5-328
FIL1 Byte data fill 1 (FUN 77) 5-171
FIL2 Byte data fill 2 (FUN 128) * 5-172
FILI1 Byte data indirect fill 1 (FUN 78) 5-174
FILI2 Byte data indirect fill 2 (FUN 130) * 5-175
FOR Start repetition (FUN 472) # 5-365
FORN Start repetition (indirect) (FUN 476) # 5-366
FPS, FRD, FPP 5-16
FST 5-17
HCR High-speed counter data readout (FUN 316) ! 5-391

HCW High-speed counter data write (FUN 317) ! 5-392
-HP Addition of BCD 2-digit constant (FUN 332) PC3J 5-435
INC Byte data binary increment (FUN 195) 5-229

INCP 2-digit BCD increment (FUN 199) 5-232
IOR Shared I/O unit data readout (for A/D module) (FUN 318) ! 5-393
IOW Shared I/O unit data write (for A/D module) (FUN 319) ! 5-394
JBIN JIS code to binary (FUN 156) 5-264

JIS Storage in JIS code (FUN 109) 5-170
JMP JUMP (FUN 272) 5-362
KEY I/O monitor key input (FUN 294) %# 5-401
LABEL Label (FUN 460) 5-385

LEDC I/O monitor display clear (FUN 290) %# 5-404
LEDD I/O monitor display (FUN 289) %# 5-402
MAX Byte data maximum value retrieve (FUN 374) PC3J 5-461
MC Master control set (FUN 440) 5-369
MCR Master control reset (FUN 444) 5-370
MIN Byte data minimum value retrieve (FUN 377) PC3J 5-462
MKP1 Odd parity composition (FUN 83) 5-253
MKP2 Even parity composition (FUN 81) 5-254
MOV 2-digit Hex constant transfer (FUN100) 5-123
MOVAD Address Constant Transfer (Move) (FUN 320) PC3J 5-425
MOVE 1-byte data direct transfer (FUN90) 5-137
MOVF 1-byte data indirect transfer 1 (FUN74) 5-140
MOVG 1-byte data indirect transfer 2 (FUN75) 5-143
MOVH 1-byte data indirect transfer 3 (FUN76) 5-146
MOVJ 1-byte transfer from register to file register (FUN 144) %& 5-183
MOVK 1-byte transfer from file register to register (FUN 147) %& 5-186
MOVP 2-digit BCD constant transfer (FUN103) 5-126
MOVQ 3-digit octal transfer (FUN107) 5-132
MOVR 3-digit decimal constant transfer (FUN105) 5-129
MOVT 2-digit Hex constant transfer to two places (FUN62) 5-135
MSET Output of the message for DLNK-M2 (FUN 302) PC3JG 5-469
NEXT End of repetition (FUN 480) # 5-367

NOP 5-19
NOT 5-18
NOT Byte data inversion (FUN 9) 5-222
OR Byte data logical sum(OR) (FUN 14) 5-219

OR STR 5-10
OR, OR NOT 5-8
ORH Logical sum (OR) of hexadecimal 2-digit constant (FUN 350) PC3J 5-453
OUT 5-11
-P 2-digit BCD subtraction (FUN 179) 5-199

PCH1 Odd parity check (FUN 84) 5-255
PCH2 Even Parity check (FUN 82) 5-256
PDI Partial interrupt inhibit (FUN 278) % 5-377
PEI Partial interrupt enable (FUN 279) % 5-379
PEND End of program (FUN 456) 5-384
PTS, NTS 5-14
PUP Byte data extraction (FUN6) 5-159
REF External input transfer (FUN 283) !# 5-181

REFO External output transfer (FUN 284) !# 5-182
RET Return from subroutine (FUN 464) 5-364
RETI Return from interrupt routine (FUN 468) % 5-380
RI Input refresh (FUN 281) 5-373
RIO Input/output refresh (FUN 280) ! 5-372
RL Byte data left rotate without carry (FUN 245) * 5-352
RLC Byte data left rotate with carry (FUN 236) * 5-349
RLR Byte data right-left rotate without carry (FUN 248) 5-358
RLRC Byte data right-left rotate with carry (FUN 239) 5-355
RO Output refresh (FUN 282) 5-374
RR Byte data right rotate without carry (FUN 242) * 5-346
RRC Byte data right rotate with carry (FUN 233) * 5-343
RST 5-13
SDOWN 4 bit data lower-digit direction shift (FUN 255) 5-323

SEG 7-segment decode (FUN 52) 5-272
SET 5-12
SFIN Accumulation shift input (FUN 68) 5-338
SFL Byte data 1 bit left shift (FUN 219) * 5-305
SFOUT Accumulation shift output (FUN 69) 5-340
SFR Byte data 1 bit right shift (FUN 217) * 5-299
SPR Special module byte-data readout (for readout of file for the SIO module) (FUN 304) 5-387
SPW Special module byte-data write (for writing of file for the SIO module) (FUN 306) 5-389
SRH1 Byte data search 1 (FUN 88) 5-242
SRH2 Byte data search 2 (FUN 212) 5-246
SRL Byte data 1 bit right-left shift (FUN 221) * 5-311
START Main program start (FUN 448) 5-382
STI1 Byte data sum (FUN 362) PC3J 5-459
STOP Program stop (FUN 287) 5-416
STR, STR NOT 5-6
STURN 4bits inversion (FUN 259) PC3J 5-423
SUM Byte data ON-bit count (FUN 208) 5-295
SUP 4 bit data upper-digit direction shift (FUN 251) 5-317
SXCH 4-bit data exchange(FUN53) 5-164
SYS Applied command flag clear mode setting (FUN 300) PC3J 5-465
SYS Setting/resetting of I/O monitor error automatic indication 5-411
SYS Clock adjustment instruction (FUN 300) PC3J 5-479
TMR (Direct mode 100ms timer) 5-27

TMR (Indirect mode 100ms timer) 5-28
TMRH (Direct mode 10ms timer) 5-25
TMRH (Indirect mode 10ms timer) 5-26
TMRS (Direct mode 100 ms integrating timer) 5-31
TMRS (Indirect mode 100 ms integrating timer) 5-32
TMRSH (Direct mode 10ms integrating timer) 5-29
TMRSH (Indirect mode 10ms integrating timer) 5-30
TRG Trace trigger (FUN 275) 5-397
TURN 8bits inversion (FUN 260) PC3J 5-423
UP1 Byte data upper-digit direction shift 1 (FUN 91) 5-318

UP2 Byte data upper-digit direction shift 2 (FUN 252) 5-319
USC User defined clock (FUN 293) 5-413
W- Word data binary subtraction (FUN 93) 5-197

W* Word data binary multiplication (FUN 94) 5-203
W*H Multiplication of hexadecimal 4-digit constant (FUN 336) PC3J 5-439
W*HP Multiplication of BCD 4-digit constant (FUN 339) PC3J 5-442
W*P 4-digit BCD multiplication (FUN 182) 5-206
W/ Word data binary division 2 (FUN 175) # 5-210
W/B Word data binary division 1 (FUN 95) 5-208
W/H Divide of hexadecimal 4-digit constant (FUN 342) PC3J 5-445
W/HP Divide of BCD 4-digit constant (FUN 345) PC3J 5-448
W/P 4-digit BCD division (FUN 185) 5-213
W+ Word data binary addition (FUN 92) 5-191
W+H Addition of hexadecimal 4-digit constant (FUN 324) PC3J 5-427
W+HP Addition of BCD 4-digit constant (FUN 327) PC3J 5-430
W+P 4-digit BCD addition (FUN 10) 5-194
W<=D 5-digit decimal constant comparison (<=) 5-99
W<=H 4-digit hexadecimal constant comparison (<=) 5-98
W<=N Word data comparison (<=) * 5-100
W<>D 5-digit decimal constant comparison (<>) 5-63
W<>H 4-digit hexadecimal constant comparison (<>) 5-62
W<>N Word data comparison (<>) 5-64
W<D 5-digit decimal constant comparison (<) 5-90
W<H 4-digit hexadecimal constant comparison (<) 5-89
W<N Word data comparison (<) * 5-91
W=D 5-digit decimal constant comparison (=) 5-54
W=H 4-digit hexadecimal constant comparison (=) 5-53
W=N Word data comparison (=) 5-55
W>=D 5-digit decimal constant comparison (>=) 5-81
W>=H 4-digit hexadecimal constant comparison (>=) 5-80
W>=N Word data comparison (>=) 5-82
W>D 5-digit decimal constant comparison (>) 5-72
W>H 4-digit hexadecimal constant comparison (>) 5-71
W>N Word data comparison (>) 5-73
WAND Word data logical product(AND) (FUN 187) 5-217
WANDH Logical product (AND) of hexadecimal 4-digit constant (FUN 348) PC3J 5-451
WAVE Word data average (FUN 381) PC3J 5-463
WBCD 16-bit binary to 4-bit BCD (FUN 4) 5-262
WBDIV Word data block delivery(FUN126) 5-158
WBIN 4-digit BCD to 16-bit binary (FUN 3) 5-259
WBMOV Word data block transfer (FUN119) * 5-151
WBMVI Word data indirect block transfer (FUN120) * 5-153
WBPU Word data bit extraction (FUN 142) 5-293
WBPUP Word data block extraction(FUN127) 5-163
WBR Data loading from the buffer register(EB) (FUN 372) PC3JG 5-467
WBRST Word data bit reset (FUN 140) 5-290
WBSET Word data set (FUN 137) 5-287
WBSFL Word data n bits left shift (FUN 228) * 5-309
WBSFR Word data n bits right shift (FUN 225) * 5-303
WBSRL Word data n bits right-left shift (FUN 231) 5-315
WBW Data saving to the buffer register(EB) (FUN 373) PC3JG 5-468
WBXCH Word data block exchange (FUN 135) 5-169
WCLR Matching data clearance (Word) (FUN 167) 5-180
WCMOV Word data transfer on clearance confirmation (FUN 166) 5-178
WCP Word data comparison (FUN 12) 5-283
WDEC Word data binary decrement (FUN 64) 5-236
WDECP 4-digit BCD decrement (FUN 203) 5-239
WDIV Word data delivery (FUN122) 5-155
WDOWN Word data lower-digit direction shift (FUN 257) 5-325
WDR Scan timer reset (FUN 46) 5-417
WFIFR Word data FIFO read (FUN 164) 5-334
WFIFW Word data FIFO write (FUN 161) 5-329
WFIL Word data fill (FUN 129) * 5-173
WFILI Word data indirect fill (FUN 131) * 5-176
W-H Deduction of hexadecimal 4-digit constant (FUN 330) PC3J 5-433
W-HP Addition of BCD 4-digit constant (FUN 333) PC3J 5-436
WINC Word data binary increment (FUN 63) 5-230
WINCP 4-digit BCD increment (FUN 200) 5-233
WMAX Word data maximum value retrieve (FUN 375) PC3J 5-461
WMIN Word data minimum value retrieve (FUN 378) PC3J 5-462
WMOV 4-digit Hex constant transfer (FUN101) 5-124
WMOVE 2-byte data direct transfer (FUN0) 5-138
WMOVF 2-byte data indirect transfer 1 (FUN112) 5-141
WMOVG 2-byte data indirect transfer 2 (FUN114) 5-144
WMOVH 2-byte data indirect transfer 3 (FUN116) 5-147
WMOVJ 2-byte transfer from register to file register (FUN 145) %& 5-184
WMOVK 2-byte transfer from file register to register (FUN 148) %& 5-187
WMOVP 4-digit BCD constant transfer (FUN1) 5-127
WMOVQ 6-digit octal transfer (FUN8) 5-133
WMOVR 5-digit decimal constant transfer (FUN7) 5-130
WMOVT 4-digit Hex constant transfer to two places (FUN 110) 5-136
WNOT Word data inversion (FUN 191) 5-223
WOR Word data logical sum(OR) (FUN 189) 5-220
WORH Logical sum (OR) of hexadecimal 4-digit constant (FUN 351) PC3J 5-454
W-P 4-digit BCD subtraction (FUN 11) 5-200
WPUP Word data extraction (FUN124) 5-160
WRL Word data left rotate without carry (FUN 246) * 5-353
WRLC Word data left rotate with carry (FUN 237) * 5-350
WRLR Word data right-left rotate without carry (FUN 249) 5-359
WRLRC Word data right-left rotate with carry (FUN 240) 5-356
WRR Word data right rotate without carry (FUN 243) * 5-347
WRRC Word data right rotate with carry (FUN 234) * 5-344
WSFL Word data 1 bit left shift (FUN 37) * 5-306
WSFR Word data 1 bit right shift (FUN 36) * 5-300
WSRH1 Word data search 1 (FUN 89) 5-244
WSRH2 Word data search 2 (FUN 213) 5-248
WSRL Word data 1 bit right-left shift (FUN 222) * 5-312
WSTI1 Word data sum (FUN 363) PC3J 5-459
WSUM Word data ON-bit count (FUN 209) 5-296
WTIM1 Hours, minutes, and seconds to seconds (FUN 158) 5-274
WTIM2 Seconds to hours, minutes and seconds (FUN 159) 5-276
WTURN 16bits inversion (FUN 261) PC3J 5-423
WUP Word data upper-digit direction shift (FUN 253) 5-320
WXCH 16-bit data exchange(FUN2) 5-166
WXOR Word data exclusive logical sum(XOR) (FUN 193) 5-226
WXORH Exclusive logical sum (XOR) of hexadecimal 4-digit constant (FUN 354) PC3J 5-457
XCH 8-bit data exchange(FUNl32) 5-165

XOR Byte data exclusive logical sum(XOR) (FUN 18) 5-225
XORH Exclusive logical sum (XOR) of hexadecimal 2-digit constant (FUN 353) PC3J 5-456
Note) The instructions marked with # can be used by the L2 but not by the PC2 of the version before
SCPU-3.01.
CPU Version
1. MAKINK SEQUENCE CIRCUITS
1.1. Usage of TOYOPUC
1.1.1. Connection between I/O devices and TOYOPUC
The equipment is provided with limit switches (LS) which provide information on the location of
machine components and with pushbutton switches (PB) which give instructions to the machine.
The devices defining the conditions of action, generically called I/O devices, should be connected
to the input module on the TOYOPUC.
The equipment is also provide with solenoid valves (SOL) which drive and control, by hydraulic
medium, the cylinders used as actuator and with magnetic switches (MS) which turn on or off the
motors. These devices, generically called output devices, should be connected to the output
module on the TOYOPUC.
1.1.2. I/O address
First specify a terminal to which an input or output device is to be connected. Each terminal has its
proper number and this is called I/O address. In a sequence program, the I/O address specifies
the I/O device.
(1) I/O coding
I/O addresses are expressed by 3-digit hexadecimal numeral and are determined as follows:
1) Stating address of each base is specified. The starting address of the CPU base is “000”.
The upper 2 digits of starting address of an added I/O base are the value set by the I/O
address selector switch on the I/O power module for PC2/L2 and on the selector module for
PC2J/3J, and the lowest digit is “0”. (For example, setting the I/O address selector to “12”
results in the starting address of “120” for the added I/O base. )
When setting the I/O addresses for racks, take care not to use the same addresses for bases.
2) The allocation of addresses for each base starts from the leftmost slot with respect to the
starting address for that base.
1-1
3) The number of points assigned to a base is basically the number of input/output points on the
I/O module being installed in that slot and can be changed from the programmer. I/O
addresses equivalent of 32 points for PC2/L2 and 16 points for PC2J/3J are usually allocated
to a slot with no I/O module mounted.
The communication modules and special modules have a different number of allocation points.
(Refer to the instruction manual of each module.)
Note 1) Available I/O addresses for PC2/L2 range from 000 to 7FF.
Allocation of address 800 and higher will result in an address setting error and
display of message “RACK ADDR ERROR” on the I/O monitor. If this happens,
correct the address allocation.
Available I/O addresses for PC2J range from 000 to 1FF.
Available I/O addresses for PC3J range from 000 to 3FF.
Allocation of address exceeded the maximum address will result in an address
setting error and the PC2J/3J-CPU displays the error code “49”.
If this happens, correct the address allocation.
Note 2) Sharing the same address with more than base causes address overlapping and the
error message “I/O ADDRESS ERR” will appear on the I/O monitor of the PC2/L2 and
“46” for PC2J/3J.If this appears, correct the address allocation.
Note 3) If the total consumption memory capacity is 60K bytes or less, up to 8communication
modules can be installed. Each communication module has its own consumption
memory capacity. (Refer to the instruction manual of each module.)The
consumption memory capacity refers to the capacity of the memory used in data
exchange between the CPU and communication modules. It has no relation with the
user memory (Program, data memory, comment), that is, the user memory will not be
reduced.
(2) Specifying rack number

Specifying rack number is to distinguish a particular rack from the others. Set the rack number
in a hexadecimal number, using 1 to E (F must not be used.) , from the “R.NO.” switch on the
I/O power module of the PC2/L2 and the selector module of the PC2J/3J. The rack number of
CPU base is regarded as “0”.
Note 1) Sharing a rack with more than one base results in an I/O rack number overlap error,
displaying the error message “RACK NO.ERROR” on the I/O monitor. Correct the
duplicated rack number.
PC2J do not have the function detecting the overlap error. In case of the overlap
error for PC3J, the error message is displayed.
Note 2) Specifying “F” for a rack number results in an I/O rack No. specification error. The
error message “RACK NO F USED” is displayed on the I/O monitor of the PC2/L2
and “41” for PC2J/3J. Correct the rack No.
1-2
(3) I/O address allocation
Example 1 : For PC2/L2
0 1 2 3 4 5 6 7
IN-22 IN-22 A/D D/A vacancy SIO IN-22 OUT-28
I/O 32 32 64 32 32 0 32 32
power points points points points points point points points
1E0 200 220 260 280 2A0 2C0
| | | | | | |
1FF 21F 25F 27F 29F 2BF 2DF
0 1 2 3 4 5 6 7
IN-22 IN-22 IN-22 OUT-25 OUT-25 IN-22 OUT-28 OUT-29
I/O 32 32 32 32 32 32 32 32
power points points points points points points points points
0E0 100 120 140 160 180 1A0 1C0
| | | | | | | |
0FF 11F 13F 15F 17F 19F 1BF 1DF
0 1 2 3 4 5 6 7
PC-
PC2/L2 IN-21 IN-21 IN-21 IN-21 OUT-21 OUT-21 OUT-21 Module name
LINK
CPU
0 32 32 32 32 32 32 32 Occupied points
point points points points points points points points
000 020 040 060 080 0A0 0C0 Address
| | | | | | | allocation
01F 03F 05F 07F 09F 0BF 0DF
Example2 : For PC2J/3J

0 1 2 3 4 5 6 7
HPC-
IN-12 IN-12 OUT-15 OUT-15 OUT-15 IN-12 OUT-18
LINK
Selector
0 16 16 16 16 16 16 16
point points points points points points points points
080 090 0A0 0B0 0C0 0D0 0E0
| | | | | | |
08F 09F 0AF 0BF 0CF 0DF 0EF
0 1 2 3 4 5 6 7
PC2J IN-22 IN-22 A/D D/A vacancy SIO IN-22 OUT-28 Module name
pow CPU
16 16 16 16 16 16 16 16 Occupied
er points points points points points points points points points
000 010 020 030 040 050 060 070 Address

| | | | | | | | allocation
00F 01F 02F 03F 04F 05F 06F 07F
1-3
1.2. Circuit diagram configuration
Usually, a circuit diagram representing sequence circuit including TOYOPUC is drawn in a form of
relay circuit (ladder diagram). The figures below show recommendable expression of circuit
configuration which make the design and maintenance of control board easier.
Machine unit (A) Machine unit(B)
Input Logic Output Input Logic Output

section section section section section section
Circuits and components of the same function in a machine should be represented in a respective
block, such as input, logic and output section on a machine basis.
1-4
1.3. I/O circuit
1.3.1. Input section
Devices to which TOYOPUC sends input signals (such as pushbutton switch and limit switch) are
written in the input section.
Example of circuit
Input(21)
Start
Original
Advanced end
Address Example of Example of symbol

Type
identifier address (Contact)
X
Input EX PC3J X150
GX PC3JG
1-5
1.3.2. Output section
Devices to which TOYOPUC sends outputs (such as solenoid-operated

directional control valve, electro-magnetic vale and magnetic switch) are
written in output section.
Example of circuit
Output(21)
Advance
Retract
Spindle start

Type
identifier address (Coil) (Contact)
Y
Output EY PC3J Y260
GY PC3JG
1-6
1.4. Logic section
1.4.1. Internal relay (dummy output)
Internal relay (dummy output) for temporary storage which does not drive external devices such as
solenoid-operated valve or magnetic switch is written in logic section.
Example of circuit
Advance memorized

Type
M
Internal
EM PC3J M000
relay
GM PC3JG
1-7
1.4.2. Timer
The timers used are divided into the following categories and are to be expressed in the logic
section.
Mnemonic
Function
Extended PC3J
Unit in 10ms TMRH ETMRH
Direct setup Unit in
TMR ETMR
100ms
Timer
Unit in 10ms TMRH ETMRH
Indirect
Unit in
setup TMR ETMR
100ms
Unit in 10ms TMRSH ETMRSH
Direct setup Unit in
TMRS ETMRS
Integrating 100ms
timer Unit in 10ms TMRSH ETMRSH
Indirect
Unit in
setup TMRS ETMRS
100ms
Example of circuit
End of advance timer

0.2sec

Type
T012
T
Timer T012
ET PC3J
T012
1-8
1.4.3. Counter
The counters used are divided into the following categories and are to be expressed in the logic
section.
Mnemonic
Function
Extended PC3J
Direct setup CNT ECNT
Up counter
Indirect setup CNT ECNT
Direct setup CNTD ECNTD
Down counter
Indirect setup CNTD ECNTD
Up/Down Direct setup CNTH ECNTH
counter Indirect setup CNTH ECNTH
Example of circuit

Type
C
Counter C051
EC PC3J
1-9
1.4.4. Keep relay
Relays used to hold the current condition when power is removed.

They are to be represented in the logic section.
Example of circuit
Work finish setting
Work finish
tti

Type
identifier address (Set coil) (Reset coil) (Contact)
Keep K
K00A
relay EK PC3J
1-10
1.4.5. Edge detection
Turns on for a period equal to one scan of sequence when conditions are met( )or not
met ( ). This part should be expressed in logic section.
Example of circuit
Store set value
Setting switch
OFF pulse

Type
identifier address (Rise contact) (Fall contact)
Edge P
P001
detection EP PC3J
(Note) The address must not be used duplication.

512 edge detection, P000 to P1FF, are possible.
4096 edge detection, EP000 to EPFFF, are possible.
1-11
1.4.6. Special relay
Special relays are internal relays whose application and function are predetermined by the TOYOPUC, the
primary applications being to indicate operation status of this machine and result of arithmetic operation
made through application instruction.
Example of circuit
TOYOPUC
Battery error (flicker 1sec)
Data comparison
D1000<D1001
D1000=D1001
D1000>D1001

Type
V
Special relay V51
EV PC3J
(1) In case of PC2/L2,PC2J

Of these relays, communication resets (V80-V87) are used as output (coil) and the remainders input
(contact).
Remember that the application of an out instruction to special relays other than V89-V87 results in
uncertain operation.
It is all reservation area for the address that doesn't exist in the list. Therefore, the user cannot use its
address.
1-12
Address Name Outline Description
0: No ERR0 ON against occurrence of major error
V01 MAJOR ERROR
1: ERR0 in occurring OFF after ERROR is reset
0: No ERR1 ON against occurrence of minor error.
V02 MINOR ERROR
1: ERR1 in occurring OFF after ERROR is reset.
0: No ALM ON against ALARM
V03 ALARM
1: ALM in outputting OFF after ERROR is reset.
V04 NORMALLY ON Normally 1 Normally ON irrespective of run status.
V05 NORMALLY OFF Normally 0 Normally OFF irrespective of run status.
END command
ON ON by resetting and OFF by END
V06 1ST SCAN
Reset processing.
OFF
Turns ON if there is key input when the I/O
User mode key input 0:Key input not contained monitor is in the user mode and OFF when
V07
PC2/L2 1:Key input contained the key input of the application instruction
is executed.
V08 Memory card mounting 0:Memory card is not mounted Turns ON when the memory card is
# PC2/L2 1:Memory card is mounted mounted
0:Other than program card Turns ON by program card mode setting
V20 Program card mode
mode and OFF by CPU RAM or data card mode
# PC2/L2
1:In program card mode setting.
Turns ON by data card mode setting and
V21 Data card mode 0:Other than data card mode
OFF by CPU RAM or program card mode
# PC2/L2 1:In data card mode
setting.
Turns ON when the I/O monitor is in the
I/O monitor user mode 0:I/O monitor mode
V22 user mode and OFF when in the I/O
PC2/L2 1:User mode
monitor mode
0:Not debug mode Turns ON by the debug mode setting and
V23 Debug mode
1:In debug mode OFF when error reset
0:Not during dummy stop Turns ON when the dummy scan stop is
V24 During dummy stop
1:During dummy stop executed and OFF when error reset
Request for stop 0:Request for stop not issued Turn ON by a request for scan stop and OF
V25
continued 1:Request for stop issued when error request
0:Scanning OFF during sequence scan and ON during
V26 Stopped
1:Stopped stepping
0:Sequence instruction not
executed
V27 RUN ON during sequence scan
1:Sequence instruction
executed
0:1-instruction step not in
V30 1-instruction step progress ON while 1-instruction step is in progress
1:1-instruction step in progress
0:1-block step not in progress
V31 1-block step ON while 1-block step is in progress
1:1-block step in progress
0:1-scan step not in progress
V32 1-scan step ON while 1-scan step is in progress
1:1-scan step in progress
Turn ON when the trace starts and OFF
0:Trigger not detected
V33 Trigger detection when the trigger instruction is executed
1:Trigger detected
after an enable is detected.
0:Enable not detected Turns OFF when the trace starts and ON
V34 Enable detection
1:Enable detected when the enable instruction is executed
# : Can be used with SCPU-4.10 or later version CPU.

(WCPU version is irrelevant)
1-13
0:Not tracing Turn ON when the time trace starts and
V35 Time trace
1:Tracing when it ends.
0:Not tracing Turns ON when the scan trace starts and
V36 Scan trace
1:Tracing OFF it ends
0:Not tracing Turns ON when the instruction trace starts
V37 Instruction trace
1;Tracing and OFF when it ends
0:Not set Turns On when the status latch execution
V3D Status latch setting
1:Set is specified.
0:Not off-line
V3F I/O off-line ON during I/O off-line processing.
1:Off-line processing
ON if applied command error occurs and
APPLIED COMMAND 0: No error
V50 OFF if not, but limited to only command
ERROR 1 (ER) 1: Error
with confinement .
0: Comparative result not small Result of comparison with applied
V51 <
1: Comparative result small command
0: Comparative result unequal Result of comparison with applied
V52 =
1: Comparative result equal command
0: Comparative result not large Result of comparison with applied
V53 >
1: Comparative result large command
0: Result not 0 ON when computation result of applied
V54 ZERO (Z)
1: Result 0 command is 0.
0: No digit down The computation result of applied
V55 BORROW (BO)
1: Digit down command is smaller than 0.
The computation result of applied
0: No digit up
V56 CARRY (CY) command exceeded the specific digit
1: Digit up
number.
0.05 sec
V70 0.1 SEC CLOCK Clock of cycle 0.1 sec and duty 50%
0.05 sec
0.1 sec
0.1 sec
0.5 sec
V72 1-SEC CLOCK Clock of cycle 1 sec and duty 50%
0.5 sec
1 sec
1 sec
30 sec
30 sec
1 scan
V78 SCAN CLOCK Clock to turn ON/ OFF SCAN every 1 scan.
1 scan
n scan Clock to turn ON/OFF scan at scanning
V79 USER DEFINED CLOCK 1
m scan interval preset by applied command.
n scan Clock to turn ON/OFF scan at scanning
V7A USER DEFINED CLOCK 2
m scan interval preset by applied command.
COMMUNICATION RESET 0: RESET OFF
V80 No.1 1: RESET ON
1-14
LINK1 COMMAND USE PERMIT
V90 FLAG
V91 LINK1 COMMAND ERROR FLAG
V92 LINK2 COMMAND USE PERMIT

FLAG
FLAG
FLAG

FLAG
V9A LINK6 COMMAND USE PERMIT

FLAG
V9B LINK6 COMMAND ERROR FLAG
V9C LINK7 COMMAND USE PERMIT

FLAG
V9D LINK7 COMMAND ERROR FLAG
V9E LINK8 COMMAND USE PERMIT

FLAG
V9F LINK8 COMMAND ERROR FLAG
VA0 ALL ST IN COMMUNICATING
VA1 LINK PARAMETER ERROR 0: No error

No.1
VA2 COMMUNICATION ERROR 1: Error
VA3

No.2
VA6 COMMUNICATION ERROR 1: Error
VA7

No.3
VAA COMMUNICATION ERROR 1: Error
VAB
VAC ALL ST IN COMMUNICATING
VAD LINK PARAMETER ERROR 0: No error

No.4
VAE COMMUNICATION ERROR 1: Error
VAF
VB0 ALL ST IN COMMUNICATING
VB1 LINK PARAMETER ERROR 0: No error

No.5
VB2 COMMUNICATION ERROR 1: Error
VB3

No.6
VB6 COMMUNICATION ERROR 1: Error
VB7

No.7
VBA COMMUNICATION ERROR 1: Error
VBB
VBC ALL ST IN COMMUNICATING
VBD LINK PARAMETER ERROR 0: No error

No.8
VBE COMMUNICATION ERROR 1: Error
VBF
0: No error
VC0 CPU ERROR ON upon detection of CPU module error.
1: Error
0: No error ON upon detection of POWER DOWN .
VC1 POWER DOWN
1: Error OFF after reset or power on
0: No error ON detection of program or parameter data
VC2 MEMORY DATA ERROR
1: Error error.
0: No error
VC3 I/O BUS ERROR ON upon detection of I/O bus error.
1: Error
ON upon detection of special module error
SPECIAL MODULE 0: No error OFF after ERROR reset
VC4
ERROR 1: Error
1-15
MODULE PARAMETER 0: No error ON when CPU can not recognize correctly
VC5
ERROR 1: Error I/O module.
0: No error
VC6 PARAMETER ERROR ON upon detection of parameter error.
1: Error
I/O MODULE ERROR 0: No error ON upon detection of I/O module error
VC7
( Fuse blown, etc.) 1: Error OFF after ERROR reset
ON upon detection of I/O module composition
I/O COMPOSITION 0: No error error/
VC8 ( Allocation of special card number and I/O
ERROR 1: Error
addresses )
USER PROGRAM 0: No error ON upon detection of error related to user
VC9
ERROR 1: Error program. OFF after ERROR reset.
Turns ON when an error related to the
MEMORY CARD ERROR 0: No error
VCA memory card is detected and OFF when
PC2/L2 1: Error
reset or power is supplied.
ON when I/O identification codes of
I/O VERIFICATION 0: No error
VE0 parameter differ from actually mounted I/O
ERROR 1: Error
modules.
0: No error ON upon detection of SCAN TIME OVER .
VE1 SCAN TIME-OVER
Turns ON when an application instruction
Arithmetic operation 0: No error
VE2 error is detected and OFF when error reset
instruction error 1: Error
or 0 is set.
0: No error ON upon error detection
VF0 BATTERY ERROR
1: Error OFF after ERROR reset
Memory card battery error 0: No error ON upon error detection
VF1
PC2/L2 1: Error OFF after ERROR reset
SPECIAL MODULE 0: No error ON against allocation error of
VF2
ALLOCATION ERROR 1: Error communication (link) module.
1-16
(2) In case of PC3J
Special relays are used for special applications such as CPU status, applied commands,
link module, etc. And these relays exist in the basic area and the extended area.
For the data memory separate mode the special relays are provided in the basic area
every each program. In this case, applied-command related special relays which are used
in each sequence program are configured in special-relay area corresponding to the
program. Other relays are all configured in the special relay area for " PRG.1".
Don't handle a user because "V58~V5D" "EV800~EVBFF" is used for the one for the
executive control of SFC when you do programming by SFC.
It is all reservation area for the address that doesn't exist in the list. Therefore, the user
cannot use its address.
(2-1) Data memory separate mode PRG.1

V01 MAJOR ERROR
V02 MINOR ERROR
V03 ALARM
END command
V06 1ST SCAN
Reset processing.
OFF
IN DUMMY 0: Not in dummy stopping ON by executing dummy scan stop
V24
STOPPING 1: In dummy stopping OFF by resetting
STOP REQ IN 0: No stop request ON by dummy scan stop request.
V25
CONTINUING 1: Stop requested OFF by resetting
0: In scanning OFF during sequence scan
V26 IN STOPPING
1: In stopping But ON during step-operation
0: Sequence command
ON while sequence command is in
V27 RUN non-execution
1: Sequence command in executing executing.
DATA MEMORY 0: Single mode
V38 ON under data area division mode
MODE 1: Division mode
0: Not FUN FLAG CLEAR
PRG.1 FUN FLAG ON when program-1 is FUN FLAG CLEAR
V39 MODE
CLEAR MODE 1: FUN FLAG CLEAR MODE
mode.
0: Not in data backing up
V3A IN DATA BACK-UP ON while user data is being backed up
1: In data backing-up
0: Sequence command
ON while program-1 is executing sequence
V40 PRG.1 RUN non-execution
command.
1: Sequence command in executing
0: Sequence command
command.
0: Sequence command
command.
1-17
PRG.1 APPLIED ON if applied command error occurs in
0: No error
V50 COMMAND ERROR 1 program-1 and OFF if not, but limited to only
(ER) 1: Error
command with confinement .
0: Comparative result not
Result of comparison with applied command in
V51 PRG.1 < small
1: Comparative result small program-1
0: Comparative result
unequal Result of comparison with applied command in
V52 PRG.1 = 1: Comparative result program-1
equal
0: Comparative result not
Result of comparison with applied command in
V53 PRG.1 > large
1: Comparative result large program-1
V54 PRG.1 ZERO (Z)
1: Result 0 command in program-1 is 0.
0: No digit down The computation result of applied command in
V55 PRG.1 BORROW (BO)
1: Digit down program-1 is smaller than 0.
0: No digit up The computation result of applied command in
V56 PRG.1 CARRY (CY)
1: Digit up program-1 exceeded the specific digit number.
DATA ERROR UNCHECK ALM is cleared by
V5E DATA ERROR CLEAR 1: Data error cleared
turning ON this special relay (V5E).
Back-up start USER DATA BACK-UP is started by ON->OFF
V5F DATA BACKUP START with fall of this special relay (V5F). V3A keeps ON
while the back-up is being executed.
0.05 sec
0.05 sec
0.1 sec
0.1 sec
0.5 sec
0.5 sec
1 sec
1 sec
30 sec
30 sec
1 scan
1 scan
n scan Clock to turn ON/OFF scan at scanning interval
m scan preset by applied command.
Prg.1-Link1 0: RESET OFF
V80 COMMUNICATION RESET 1: RESET ON
Note) For the communication (link) modules, see the respective Instruction Manuals.
1-18
LINK COMMAND USE ü
V90 PERMIT FLAG Prg.1-
ý
V91
LINK COMMAND
þ
Link 1
ERROR FLAG
LINK COMMAND USE ü
ý
þ Link 2
LINK COMMAND
V93 ERROR FLAG
LINK COMMAND USE ü
ý
þ Link 3
LINK COMMAND
V95 ERROR FLAG
LINK COMMAND USE ü Prg.1-
V96 PERMIT FLAG
ý
þ Link 4
LINK COMMAND
V97 ERROR FLAG
LINK COMMAND USE ü
ý
þ Link 5
LINK COMMAND
V99 ERROR FLAG
LINK COMMAND USE ü
V9A PERMIT FLAG Prg.1-
ý
þ Link 6
LINK COMMAND
V9B ERROR FLAG
V9C PERMIT FLAG
ý
þ Link 7
LINK COMMAND
V9D ERROR FLAG
V9E PERMIT FLAG
ý
þ Link 8
LINK COMMAND
V9F ERROR FLAG
ALL ST IN
VA0 COMMUNICATING ü
LINK PARAMETER ï
VA1 ERROR Prg.1- 0: No error
ý
COMMUNICATION
ï
Link1 1: Error
VA2 ERROR
þ
VA3
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link2 1: Error
VA6 ERROR
þ
VA7
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link3 1: Error
VAA ERROR
þ
VAB
ALL ST IN
VAC COMMUNICATING ü
LINK PARAMETER ï
VAD ERROR Prg.1- 0: No error
ý
COMMUNICATION
ï
Link4 1: Error
VAE ERROR
þ
VAF
ALL ST IN
VB0 COMMUNICATING ü
LINK PARAMETER ï
VB1 ERROR Prg.1- 0: No error
ý
COMMUNICATION
ï
Link5 1: Error
VB2 ERROR
þ
VB3
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link6 1: Error
VB6 ERROR
þ
VB7
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link7 1: Error
VBA ERROR
þ
VBB
ALL ST IN
VBC COMMUNICATING ü
LINK PARAMETER ï
VBD ERROR Prg.1- 0: No error
ý
COMMUNICATION
ï
Link8 1: Error
VBE ERROR
þ
VBF
1-19
0: No error
1: Error
VC1 POWER DOWN
MEMORY DATA 0: No error ON detection of program or parameter data
VC2
ERROR 1: Error error.
0: No error
1: Error
ON upon detection of special module error
SPECIAL MODULE 0: No error OFF after ERROR reset
VC4
ERROR 1: Error
MODULE PARAMETER 0: No error ON when CPU can not recognize correctly I/O
VC5
ERROR 1: Error module.
0: No error
1: Error
VC7
ON upon detection of I/O module composition error/
I/O COMPOSITION 0: No error
VC8 ( Allocation of special card number and I/O
ERROR 1: Error addresses )
VC9
BACK UP MEMORY 0: No error
VCA ON upon detection of back-up memory error
ERROR 1: Error
ON upon detection of memory data error (VC2).
DATA ERROR 0: checked
VCB OFF with V5E ON or use of peripheral
UNCHECK 1: uncheck
equipment.
PRG.1 0: No error ON upon errors related to user program as
VD0
USER PROGRAM ERROR 1: Error program-1
VD1
VD2
PRG.1 PARAMETER 0: No error ON upon detection of program-1 parameter
VD8
ERROR 1: Error error
VD9
VDA
I/O VERIFICATION 0: No error ON when I/O identification codes of parameter
VE0
ERROR 1: Error differ from actually mounted I/O modules.
VE1 SCAN TIME-OVER
PRG.1 APPLIED ON against occurrence of error of applied
0: No error
VE2 COMMAND ERROR command (V50) in program-1. It is held until
LATCH
1: Error
reset or 0 write.
PRG.1 SCAN TIME 0: No error ON upon detection of scan time-over in
VE8
OVER 1: Error program-1. OFF after reset or power on
VE9
VEA
VF0 BATTERY ERROR
SPECIAL MODULE 0: No error ON against allocation error of communication
VF2
ALLOCATION ERROR 1: Error (link) module.
DIAGNOSIS MODULE 0: No error
VF3 ON against diagnosis module error.
ERROR 1: Error
0: No error
VF5 BATTERY ERROR ON upon detection of built-in clock error.
1: Error
1-20
V04 NORMALLY ON NORMALLY 1 ON irrespective operation status
V05 NORMALLY OFF NORMALLY 0 OFF irrespective of operation status
END command
ON
V06 1ST SCAN ON by resetting and OFF by END processing.
Reset
OFF
0: Not in dummy stopping ON by executing dummy scan stop
V24 IN DUMMY STOPPING
1: In dummy stopping OFF by resetting
IN STOP REQUEST 0: No stop request ON by dummy scan stop request.
V25
V26 IN STOPPING
PRG.2 FUN FLAG 0: Not FUN FLAG CLEAR MODE ON when program-2 is FUN FLAG CLEAR
V39 1: FUN FLAG CLEAR MODE
CLEAR MODE mode.
0: No error
1: Error
(ER) command with confinement .
0: Comparative result not small Result of comparison with applied command in
V51 PRG.2 < 1: Comparative result small program-2
0: Comparative result unequal Result of comparison with applied command in
V52 PRG.2 = 1: Comparative result equal program-2
0: Comparative result not large Result of comparison with applied command in
V53 PRG.2 > 1: Comparative result large program-2
V54 PRG.2 ZERO (Z)
0.05 sec
0.05 sec
0.1 sec
0.1 sec
0.5 sec
0.5 sec
1 sec
1 sec
30 sec
30 sec
1 scan
1 scan
USER DEFINED CLOCK n scan Clock to turn ON/OFF scan at scanning interval
V79
1 m scan preset by applied command.
V7A
1-21
Prg2-Link1 0: RESET OFF
LINK COMMAND
V90 ü
USE PERMIT FLAG Prg2-
ý
V91
LINK COMMAND
þ Link 1
ERROR FLAG
LINK COMMAND
V92 ü
ý
V93
LINK COMMAND
þ Link 2
ERROR FLAG
LINK COMMAND
V94 ü
ý
V95
LINK COMMAND
þ Link 3
ERROR FLAG
LINK COMMAND
V96 ü
ý
V97
LINK COMMAND
þ Link 4
ERROR FLAG
LINK COMMAND
V98 ü
ý
V99
LINK COMMAND
þ Link 5
ERROR FLAG
LINK COMMAND
V9A ü
ý
V9B
LINK COMMAND
þ Link 6
ERROR FLAG
LINK COMMAND
V9C ü
ý
LINK COMMAND Link 7
V9D ERROR FLAG
þ
LINK COMMAND
V9E ü
ý
LINK COMMAND Link 8
V9F ERROR FLAG
þ
ALL ST IN
VA1
LINK PARAMETER ï
ERROR Prg2- 0: No error
ý
COMMUNICATION ï Link1 1: Error
VA2 ERROR þ
VA3
ALL ST IN
VA5
LINK PARAMETER ï
ý
COMMUNICATION ï Link 2 1: Error
VA6 ERROR þ
VA7
ALL ST IN
VA9
LINK PARAMETER ï
ý
VAA ERROR þ
VAB
ALL ST IN
VAD
LINK PARAMETER ï
ý
VAE ERROR þ
VAF
1-22
ALL ST IN
VB1
LINK PARAMETER ï
ý
VB2 ERROR
þ
VB3
ALL ST IN
VB5
LINK PARAMETER ï
ý
VB6 ERROR
þ
VB7
ALL ST IN
VB9
LINK PARAMETER ï
ý
VBA ERROR
þ
VBB
ALL ST IN
VBD
LINK PARAMETER ï
ý
VBE ERROR
þ
VBF
PRG.2 APPLIED ON against occurrence of applied command
0: No error
VE2 COMMAND LATCH error (V50) in program-2 and it is held until reset
ERROR
1: Error
or 0 write.
(Note) For the communication (link) modules, see the respective Instruction Manuals.
1-23
V04 NORMALLY ON NORMALLY 1 ON irrespective operation status
V05 NORMALLY OFF NORMALLY 0 OFF irrespective of operation status
END command
ON
V06 1ST SCAN ON by resetting and OFF by END processing.
Reset
OFF
IN STOP REQUEST 0: No stop request ON by dummy scan stop request.
V25
V26 IN STOPPING
PRG.3 FUN FLAG 0: Not FUN FLAG CLEAR MODE ON when program-3 is FUN FLAG CLEAR
V39 1: FUN FLAG CLEAR MODE
CLEAR MODE mode.
0: No error
1: Error
(ER) command with confinement .
0: Comparative result not small Result of comparison with applied command in
V51 PRG.3 < 1: Comparative result small program-3
0: Comparative result unequal Result of comparison with applied command in
V52 PRG.3 = 1: Comparative result equal program-3
0: Comparative result not large Result of comparison with applied command in
V53 PRG.3 > 1: Comparative result large program-3
V54 PRG.3 ZERO (Z)
0.05 sec
0.05 sec
0.1 sec
0.1 sec
0.5 sec
0.5 sec
1 sec
1 sec
30 sec
30 sec
1 scan
1 scan
V79
V7A
1-24
LINK COMMAND
V90 ü
ý
V91
LINK COMMAND
þ Link 1
ERROR FLAG
LINK COMMAND
V92 ü
ý
V93
LINK COMMAND
þ Link 2
ERROR FLAG
LINK COMMAND
V94 ü
ý
V95
LINK COMMAND
þ Link 3
ERROR FLAG
LINK COMMAND
V96 ü
ý
V97
LINK COMMAND
þ Link 4
ERROR FLAG
LINK COMMAND
V98 ü
ý
V99
LINK COMMAND
þ Link 5
ERROR FLAG
LINK COMMAND
V9A ü
ý
V9B
LINK COMMAND
þ Link 6
ERROR FLAG
LINK COMMAND
V9C ü
ý
LINK COMMAND Link 7
V9D ERROR FLAG
þ
LINK COMMAND
V9E ü
ý
LINK COMMAND Link 8
V9F ERROR FLAG
þ
ALL ST IN
VA1
LINK PARAMETER ï
ý
VA2 ERROR þ
VA3
ALL ST IN
VA5
LINK PARAMETER ï
ý
VA6 ERROR þ
VA7
ALL ST IN
VA9
LINK PARAMETER ï
ý
VAA ERROR þ
VAB
ALL ST IN
VAD
LINK PARAMETER ï
ý
VAE ERROR þ
VAF
1-25
ALL ST IN
VB1
LINK PARAMETER ï
ý
VB2 ERROR
þ
VB3
ALL ST IN
VB5
LINK PARAMETER ï
ý
VB6 ERROR
þ
VB7
ALL ST IN
VB9
LINK PARAMETER ï
ý
VBA ERROR
þ
VBB
ALL ST IN
VBD
LINK PARAMETER ï
ý
VBE ERROR
þ
VBF
PRG.3 APPLIED ON against occurrence of applied command
0: No error
VE2 COMMAND LATCH error (V50) in program-3 and it is held until reset
ERROR
1: Error
or 0 write.
(Note) For the communication (link) modules, see the respective Instruction Manuals.
1-26
(2-4) Data memory single mode, basic area
V01 MAJOR ERROR
V02 MINOR ERROR
V03 ALARM
END command
V06 1ST SCAN
Reset processing.
OFF
V25
V26 IN STOPPING
0: Sequence command non-execution ON while sequence command is in
V27 RUN 1: Sequence command in executing executing.
0: Single mode
V38 DATA MEMORY MODE
1: Division mode
ON under data area division mode
FUN FLAG CLEAR 0: Not FUN FLAG CLEAR MODE
V39
MODE 1: FUN FLAG CLEAR MODE ON under FUN FLAG CLEAR mode.
V3A IN DATA BACK-UP
ON while user data is being backed up
0: Sequence command non-execution ON while program-1 is executing
V40 PRG.1 RUN 1: Sequence command in executing sequence command.
ON if applied command error occurs and OFF if
V50 not, but limited to only command with
confinement .
0: Comparative result not small Result of comparative command of applied
V51 < 1: Comparative result small commands
0: Comparative result unequal Result of comparative command of applied
V52 = 1: Comparative result equal commands
0: Comparative result not large Result of comparative command of applied
V53 > 1: Comparative result large commands
0: Result not 0 ON when computation result of applied command
V54 ZERO (Z)
1: Result 0 is 0
0: No digit down The computation result of applied command is
V55 BORROW (BO)
1: Digit down smaller than 0.
0: No digit up The computation result of applied command is
V56 CARRY (CY)
1: Digit up over the digit number.
Back-up start USER DATA BACK-UP is started by ON->OFF of
V5F DATA BACKUP START with fall this special relay (V5F). V3A keeps ON while
the back-up is being executed.
1-27
0.05 sec
0.05 sec
0.1 sec
0.1 sec
0.5 sec
0.5 sec
1 sec
1 sec
30 sec
30 sec
1 scan
1 scan
V80 COMMUNICATION
RESET 1: RESET ON
V81 COMMUNICATION
RESET 1: RESET ON
V82 COMMUNICATION
RESET 1: RESET ON
V83 COMMUNICATION
RESET 1: RESET ON
V84 COMMUNICATION
RESET 1: RESET ON
V85 COMMUNICATION
RESET 1: RESET ON
V86 COMMUNICATION
RESET 1: RESET ON
V87 COMMUNICATION
RESET 1: RESET ON
LINK COMMAND USE
V90 ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link1
V91 ERROR FLAG
LINK COMMAND USE
V92 ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link2
V93 ERROR FLAG
LINK COMMAND USE
V94 ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link3
V95 ERROR FLAG
LINK COMMAND USE
V96 ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link4
V97 ERROR FLAG
LINK COMMAND USE
V98 ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link5
V99 ERROR FLAG
LINK COMMAND USE
V9A ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link6
V9B ERROR FLAG
LINK COMMAND USE
V9C ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link7
V9D ERROR FLAG
LINK COMMAND USE
V9E ü
PERMIT FLAG Prg1-
ý
LINK COMMAND
þ
Link8
V9F ERROR FLAG
1-28
ALL ST IN
LINK PARAMETER ï
VA1 Prg1- 0: No error
ERROR ý
COMMUNICATION ï
Link1 1: Error
VA2 ERROR þ
VA3
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link2 1: Error
VA6 ERROR þ
VA7
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link3 1: Error
VAA ERROR þ
VAB
ALL ST IN
LINK PARAMETER ï
VAD Prg1- 0: No error
ERROR ý
COMMUNICATION ï
Link4 1: Error
VAE ERROR þ
VAF
ALL ST IN
LINK PARAMETER ï
VB1 Prg1- 0: No error
ERROR ý
COMMUNICATION ï
Link5 1: Error
VB2 ERROR þ
VB3
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link6 1: Error
VB6 ERROR þ
VB7
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link7 1: Error
VBA ERROR þ
VBB
ALL ST IN
LINK PARAMETER ï
VBD Prg1- 0: No error
ERROR ý
COMMUNICATION ï
Link8 1: Error
VBE ERROR þ
VBF
0: No error
1: Error
VC1 POWER DOWN
1: Error OFF after reset or power rethrow-in
0: No error
VC2 MEMORY DATA ERROR ON detection of program or parameter data error.
1: Error
0: No error
1: Error
SPECIAL MODULE 0: No error ON upon detection of special module error
VC4
ERROR 1: Error ON after ERROR reset
MODULE PARAMETER 0: No error
VC5 ON when CPU can not recognize correctly I/O module.
ERROR 1: Error
0: No error
1: Error
VC7
1-29
Addres
Name Outline Description
s
VC8
ERROR 1: Error ( Allocation of special card number and I/O
addresses )
VC9
ERROR 1: Error
DATA ERROR 0: checked ON upon detection of memory data error (VC2) .
VCB
UNCHECK 1: uncheck OFF with V5E ON or use of peripheral equipment.
VD0
VD1
VD2
PRG.1 PARAMETER 0: No error
VD8 ON upon detection of program-1 parameter error
ERROR 1: Error
VD9 ON upon detection of program-2 parameter error
ERROR 1: Error
VDA ON upon detection of program-3 parameter error
ERROR 1: Error
I/O VERIFICATION 0: No error ON upon detection of SCAN TIME OVER .
VE0
ERROR 1: Error OFF after reset or power rethrow-in
VE1 SCAN TIME-OVER
ON against occurrence of error of applied
PRG.1 APPLIED 0: No error
VE2 command (V50) in program-1. It is held until reset
COMMAND ERROR LATCH 1: Error
or 0 write.
PRG.1 SCAN TIME 0: No error ON upon detection of scan time-over in program-1.
VE8
OVER 1: Error OFF after reset or power rethrow-in
VE9
VEA
VF0 BATTERY ERROR
SPECIAL MODULE 0: No error ON against allocation error of communication (link)
VF2
ALLOCATION ERROR 1: Error module.
ERROR 1: Error
0: No error
1: Error
1-30
(2-5) Data memory single mode, extended area
EV00 COMMUNICATION RESET 1: RESET ON
LINK COMMAND USE
EV10 ü
PERMIT FLAG Prg2-
ý
EV11
LINK COMMAND
þ
Link1
ERROR FLAG
LINK COMMAND USE
EV12 ü
PERMIT FLAG Prg2-
ý
EV13
LINK COMMAND
þ
Link2
ERROR FLAG
LINK COMMAND USE
EV14 ü
PERMIT FLAG Prg2-
ý
EV15
LINK COMMAND
þ
Link3
ERROR FLAG
LINK COMMAND USE
EV16 ü
PERMIT FLAG Prg2-
ý
LINK COMMAND
þ
Link4
EV17 ERROR FLAG
LINK COMMAND USE
EV18 ü
PERMIT FLAG Prg2-
ý
LINK COMMAND
þ
Link5
EV19 ERROR FLAG
LINK COMMAND USE
EV1A ü
PERMIT FLAG Prg2-
ý
LINK COMMAND
þ
Link6
EV1B ERROR FLAG
LINK COMMAND USE
EV1C ü
PERMIT FLAG Prg2-
ý
LINK COMMAND
þ
Link7
EV1D ERROR FLAG
LINK COMMAND USE
EV1E ü
PERMIT FLAG Prg2-
ý
LINK COMMAND
þ
Link8
EV1F ERROR FLAG
ALL ST IN
EV20 COMMUNICATING ü
LINK PARAMETER ï
EV21 Prg2- 0: No error
ERROR ý
COMMUNICATION ï
Link1 1: Error
EV22 ERROR þ
EV23
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link2 1: Error
EV26 ERROR þ
EV27
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link3 1: Error
EV2A ERROR þ
EV2B
ALL ST IN
EV2C COMMUNICATING ü
LINK PARAMETER ï
EV2D Prg2- 0: No error
ERROR ý
COMMUNICATION ï
Link4 1: Error
EV2E ERROR þ
EV2F
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link5 1: Error
EV32 ERROR þ
EV33
1-31
ALL ST IN
LINK PARAMETER ï
EV35 ERROR Prg2- 0: No error
ý
COMMUNICATION ï
Link6 1: Error
EV36 ERROR
þ
EV37
ALL ST IN
EV39
LINK PARAMETER ï
ý
COMMUNICATION ï
Link7 1: Error
EV3A ERROR
þ
EV3B
ALL ST IN
EV3D
LINK PARAMETER ï
ý
COMMUNICATION ï
Link8 1: Error
EV3E ERROR
þ
EV3F
Prg3-Link1
0: RESET OFF
EV40 COMMUNICATION
1: RESET ON
RESET
Prg3-Link2
0: RESET OFF
EV41 COMMUNICATION
1: RESET ON
RESET
Prg3-Link3
0: RESET OFF
EV42 COMMUNICATION
1: RESET ON
RESET
Prg3-Link4
0: RESET OFF
EV43 COMMUNICATION
1: RESET ON
RESET
Prg3-Link5
0: RESET OFF
EV44 COMMUNICATION
1: RESET ON
RESET
Prg3-Link6
0: RESET OFF
EV45 COMMUNICATION
1: RESET ON
RESET
Prg3-Link7
0: RESET OFF
EV46 COMMUNICATION
1: RESET ON
RESET
Prg3-Link8
0: RESET OFF
EV47 COMMUNICATION
1: RESET ON
RESET
LINK COMMAND USE
EV50 ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link1
EV51 ERROR FLAG
LINK COMMAND USE
EV52 ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link2
EV53 ERROR FLAG
LINK COMMAND USE
EV54 ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link3
EV55 ERROR FLAG
LINK COMMAND USE
EV56 ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link4
EV57 ERROR FLAG
LINK COMMAND USE
EV58 ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link5
EV59 ERROR FLAG
LINK COMMAND USE
EV5A ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link6
EV5B ERROR FLAG
LINK COMMAND USE
EV5C ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link7
EV5D ERROR FLAG
LINK COMMAND USE
EV5E ü
PERMIT FLAG Prg3-
ý
LINK COMMAND
þ
Link8
EV5F ERROR FLAG
1-32
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link1 1: Error
EV62 ERROR þ
EV63
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link2 1: Error
EV66 ERROR þ
EV67
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link3 1: Error
EV6A ERROR þ
EV6B
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link4 1: Error
EV6E ERROR þ
EV6F
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link5 1: Error
EV72 ERROR þ
EV73
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link6 1: Error
EV76 ERROR þ
EV77
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link7 1: Error
EV7A ERROR þ
EV7B
ALL ST IN
LINK PARAMETER ï
ERROR ý
COMMUNICATION ï
Link8 1: Error
EV7E ERROR þ
EV7F
1-33
(2-6) PC2 compatible mode
V01 MAJOR ERROR
V02 MINOR ERROR
V03 ALARM
END command
V06 1ST SCAN
Reset processing.
OFF
V25
V26 IN STOPPING
0: Sequence command
non-execution ON while sequence command is in
V27 RUN 1: Sequence command in executing.
executing
FUN FLAG CLEAR 0: Not FUN FLAG CLEAR MODE
V39
MODE 1: FUN FLAG CLEAR MODE ON under FUN FLAG CLEAR mode.
V3A IN DATA BACK-UP
ON while user data is being backed up
ON if applied command error occurs and OFF if
V50 not, but limited to only command with
confinement .
0: Comparative result not small Result of comparative command of applied
V51 < 1: Comparative result small commands
0: Comparative result unequal Result of comparative command of applied
V52 = 1: Comparative result equal commands
0: Comparative result not large Result of comparative command of applied
V53 > 1: Comparative result large commands
0: Result not 0 ON when computation result of applied command
V54 ZERO (Z)
1: Result 0 is 0
0: No digit down The computation result of applied command is
V55 BORROW (BO)
1: Digit down smaller than 0.
0: No digit up The computation result of applied command is
V56 CARRY (CY)
1: Digit up over the digit number.
Back-up start USER DATA BACK-UP is started by ON->OFF of
V5F DATA BACKUP START with fall this special relay (V5F). V3A keeps ON while the
back-up is being executed.
0.05 sec
0.05 sec
0.1 sec
0.1 sec
0.5 sec
0.5 sec
1 sec
1 sec
30 sec
30 sec
1-34
1 scan
1 scan
n scan Clock to turn ON/OFF scan at scanning interval preset by
applied command.
m scan
n scan Clock to turn ON/OFF scan at scanning interval preset by
applied command.
m scan
LINK COMMAND USE ü
V90 PERMIT FLAG Prg1-
ý
V91
LINK COMMAND
þ
Link1
ERROR FLAG
LINK COMMAND USE ü
ý
V93
LINK COMMAND
þ
Link2
ERROR FLAG
LINK COMMAND USE ü
ý
V95
LINK COMMAND
þ
Link3
ERROR FLAG
LINK COMMAND USE ü
ý
V97
LINK COMMAND
þ
Link4
ERROR FLAG
LINK COMMAND USE ü
ý
V99
LINK COMMAND
þ
Link5
ERROR FLAG
LINK COMMAND USE ü
V9A PERMIT FLAG Prg1-
ý
V9B
LINK COMMAND
þ
Link6
ERROR FLAG
LINK COMMAND USE ü
V9C PERMIT FLAG Prg1-
ý
V9D
LINK COMMAND
þ
Link7
ERROR FLAG
LINK COMMAND USE ü
V9E PERMIT FLAG Prg1-
ý
V9F
LINK COMMAND
þ
Link8
ERROR FLAG
ALL ST IN
LINK PARAMETER ï
VA1 ERROR Prg1- 0: No error
ý
COMMUNICATION
ï
Link1 1: Error
VA2 ERROR
þ
VA3
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link2 1: Error
VA6 ERROR
þ
VA7
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION
ï
Link3 1: Error
VAA ERROR
þ
VAB
ALL ST IN
LINK PARAMETER ï
VAD ERROR Prg1- 0: No error
ý
COMMUNICATION
ï
Link4 1: Error
VAE ERROR
þ
VAF
1-35
ALL ST IN
LINK PARAMETER ï
VB1 ERROR Prg1- 0: No error
ý
COMMUNICATION ï
Link5 1: Error
VB2 ERROR
þ
VB3
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION ï
Link6 1: Error
VB6 ERROR
þ
VB7
ALL ST IN
LINK PARAMETER ï
ý
COMMUNICATION ï
Link7 1: Error
VBA ERROR
þ
VBB
ALL ST IN
LINK PARAMETER ï
VBD ERROR Prg1- 0: No error
ý
COMMUNICATION ï
Link8 1: Error
VBE ERROR
þ
VBF
0: No error
1: Error
VC1 POWER DOWN
0: No error
VC2 MEMORY DATA ERROR ON detection of program or parameter data error.
1: Error
0: No error
1: Error
SPECIAL MODULE 0: No error ON upon detection of special module error
VC4
ERROR 1: Error ON after ERROR reset
MODULE PARAMETER 0: No error ON when CPU can not recognize correctly I/O
VC5
ERROR 1: Error module.
0: No error
1: Error
VC7
VC8
ERROR 1: Error ( Allocation of special card number and I/O
addresses )
VC9
ERROR 1: Error
DATA ERROR 0: Checked ON upon detection of memory data error (VC2) .
VCB
UNCHECK 1: Uncheck OFF with V5E ON or use of peripheral equipment.
I/O VERIFICATION 0: No error ON upon detection of SCAN TIME OVER .
VE0
ERROR 1: Error OFF after reset or power rethrow-in
VE1 SCAN TIME-OVER
VF0 BATTERY ERROR
SPECIAL MODULE 0: No error ON against allocation error of communication (link)
VF2
ALLOCATION ERROR 1: Error module.
ERROR 1: Error
0: No error
1: Error
1-36
1.
1.4.7 Link relay
Link relays are internal relays used foe data linking between PLCs and communication between
remote I/Os.
These relays can also be used for applications basically made for the general purpose internal relay
(M***), when they are not used as communication relays.
Example of circuit
Operation ready
Original position
Continuous

Type
L
Link relay L102
EL PC3J
1-37
1.
1.4.8. Designation of Register Bit PC3J
Register bit addresses(16 bits) can be used for coil address and contact address.
Register bit addresses can be used for contact commands and output commands (OUT, SET, RST).
The sequence programs are expressed as ever. Register address is followed by bit position.
Identifier Name Bit address Points Data

hold
area at
power
cut-off
D Data register D0000-0 ~ 2FFF-F 196608 O
R Link register R0000-0 ~ 07FF-F 32768 O
N Present value register N0000-0 ~ 01FF-F 8192 O
S Special register S0000-0 ~ 03FF-F 16384 O
B File register B0000-0 ~ 1FFF-F 131072 O
U
Extended data register U0000-0 ~ 7FFF-F 524288 O
Extended present value
EN EN0000-0 ~ 07FF-F 32768 O
register
Extended setup value
H H0000-0 ~ 07FF-F 32768 O
register
Extended special
ES ES0000-0 ~ 07FF-F 32768 O
register
D0000 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
F E D C B A 9 8 7 6 5 4 3 2 1 0
D0000- D0000- D0000- D0000-1 D0000-0
1-38
1.5. Application instruction
1.5.1. Application instruction
TOYOPUC can store data and process numerical data through arithmetic operations, in addition to
operation of sequential processing. To enable the controller to handle this numerical data, special
instructions called application instructions (or function instructions) are available.
Application instructions are roughly classified as follows:
(1) Contact type application instruction

Compares values of 2 pieces of data and when the conditions are met, closes the specified
contact.
Example of circuit diagram
(2) Output type application instruction
Used to transfer data, process arithmetic and logical operations and to handle other data
process oriented functions. The instruction will be executed when the previous operation
resulted in ON. (The instruction will be executed every scan as long as the operation result
is ON. To execute only once at the start, use .)
1.5.2. Data register
Used to store data when application instruction is executed.

One data register consists of 16 bits.
1-39
1.5.3. File register
Reserved for extension of data register and used when the data register area becomes short.
Note that the file register can store data resulting from execution of limited application instructions
regarding data transfer and some other similar function only.
1.5.4. Link register
Used to link data of PLCs. Can also be used as data register when not used for data linking.
1.5.5. Current value register
Stores the current value of a timer or counter. The current contents of a this register from an
application instruction. For this reason, one can read and change the current values and existing
settings of a timer and counter by specifying the appropriate current value register in an
application command.
However, the set value register only exists in the extended timer/extended counter.
1.5.6. Buffer register PC3JG
Data in the buffer register area can be loaded and saved by the applied commands.
1-40
1.5.7. Special register
The special registers listed in the table below are available for special applications such as CPU
status, built-in clock, link modules, etc. These special registers are in Basic area and extended
area.
It is all reservation area for the address that doesn't exist in the list. Therefore, the user cannot use
its address.
Address Name Description

S000 Initial scan time Initial sequence program execution time (ms)
S001 SCAN TIME max value Maximum scan time in sequence program (ms) Binary
S002 SCAN TIME min value Minimum scan time in sequence program (ms) Binary
S003 SCAN TIME Present value Updated scan time in sequence program (ms) Binary
S004 Time (Sec) Present time of the built-in clock is stored.
S005 Time (Minutes) For data display, 1 digit is displayed by 1Byte in BCD
code.
S006 Time (Hours) (Ex. "0102" represents "12".)
S007 Time (Day) Year data is displayed with lower two digits of AD year. BCD
S008 Time (Month) "day of week" data is represented by 0 ~ 6, which (1 digit/byte)
S009 Time (Year) correspond to Sun. ~ Sat.
Even if the register is rewritten directly, time change is
S00A Day of week impossible. Please perform a setup of time from <Setup
data/time> of Pcwin.
User mode key code Stores the code of a key pressed when I/O monitor is in the user
S00B
PC2/L2 mode.
S00C Cumulative value of CPU module make (current feed) Binary, lower
Integrated make time
S00D time (h) Binary, upper
S00E Binary, lower
Integrated run time Cumulative value of sequence program run time (h)
S00F Binary, upper
S019
&
Time (Minute/sec) Present time of the built-in clock is stored.
For data display, 2 digits are represented by 1Byte in
S01A BCD
&
Time (Day/Hour) BCD code. (2 digit/byte)
(Ex. "1234" in S019 represents "12 (min).34(sec).)
S01B Year data represents last two digits of the year A.D. .
&
Time (Year/month)
When using the optional E2PROM and writing to sequential
E2PROM write-in
programs in E2PROM, “9999” written in this register cancels the
S020 interlock
ROM write-in interlock. Usually the values are those which were
PC2J
cleared upon power supply.
S200
Error information (Note 1)
∼
S24F
S250
Annunciator information (Note 2)
∼
S2CF
S300
Communication (link) See the individual instruction manual for each communication(link)
∼
module status information module.

S3FF
& : In case of PC2/L2. this is available for SCPU-4.70 or later.

This is available for PC2J Ver 3.50 or later, PC2JC Ver 3.20 or later, SUB-CPU Ver 2.50 or later,
PC2JNM/PC2JNF Ver 2.00 or later.
For PC2JS/JR/S1, S004-S01B is not available.
1-41
(Note 1) Error information
Locations S200-S24F, equivalent of 80 words, of special registers are used to store up to 8
error codes and error code associated data. When an error message comes to the register
as the CPU detects fault, it causes data shift in the register to delete the oldest data and
enters in place. Thus error data stored are always the last 8 events.
Address
New S200 HOST SLAVE
S20A Error 0 information S200 Error codes
S214 Error-related Error-related
Error 1 information S201 information 2 information 1
S21E Error-related Error-related
S228 Error 3 information S203 Error detection time (sec)
S232 Error 4 information S204 Error detection time (min)
S23C Error 5 information S205 Error detection time (hour)
S246 Error 6 information S206 Error detection time (day)
Former S24F Error 7 information S207 Error detection time (month)
S208 Error detection time (year)
Error detection time Error detection time
Cancel S209
(day of week) (day of week)
Error-related information are stored with hexadecimal number.
The current time of the built-in clock is stored.
The data represents 1bit at 1 digit in BCD code. (EX. "0102"
represents "12". )
Year data is represented by lower two digits of AD year and the
"day of week" data is represented by 0 ~ 6, which then
correspond to Sunday ~ Saturday.
1-42
(Note 2) Annunciator information
Locations S250-S2CF, equivalent of 128 words, of the special register are exclusively used
to store annunciator messages and times at which the message are issued. These locations
are user accessible and can be programmed to store up to 8 messages concerning device
diagnosis.
Address
S250 Annunciator 0 code
S251 Annunciator 0 message
S259 Annunciator 0 detected time(sec)
S25A Annunciator 0 detected time(minute)
S25B Annunciator 0 detected time(hour)
S25C Annunciator 0 detected time(day)
S25D Annunciator 0 detected time(month)
25E Annunciator 0 detected time(year)
S25F Annunciator 0 detected time(W day)
S2CE Annunciator 0 detected time(year)

S2CF Annunciator 0 detected time(W day)
1-43
(2) In case of PC3J
Under data memory separate mode the special registers in basic area are available
individually for each program. In this case, the special registers for built-in clock time,
annunciator, link modules, etc. used in each sequence program are in special register area
corresponding to the program. Other special registers are all in the special register area for
"PRG.1".It is all reservation area for the address that doesn't exist in the list. Therefore, the
user cannot use its address.
SCAN TIME min
S002 Minimum scan time in sequence program (ms) Binary
value
SCAN TIME Present
S003 Updated scan time in sequence program (ms) Binary
value
S004 Time (Sec) Present time of the built-in clock is stored.
S005 Time (Minutes) For data display, 1 digit is displayed by 1Byte in
S006 Time (Hours) BCD code.
BCD
S007 Time (Day) (Ex. "0102" represents "12".) (1 digit/byte)
S008 Time (Month) Year data is displayed with lower two digits of AD
S009 Time (Year) year. "day of week" data is represented by 0 ~ 6,
S00A Day of week which correspond to Sun. ~ Sat. (Note 4)
Binary,
S00C
Cumulative value of CPU module make (current feed) lower
Integrated make time
time (h) Binary,
S00D
upper
Binary,
S00E
lower
Binary,
S00F
upper
S010 End processing time max value Maximum end processing time in sequence program (ms) Binary
Minimum end processing time in sequence program
S011 End processing time Min value Binary
(ms)
Updated end processing time in sequence program
S012 End processing time Present value Binary
(ms)
S019 Time (Minute·sec) Present time of the built-in clock is stored.
BCD
S01A Time (Day·Hour) For data display, 2 digits are represented by 1Byte in
(2 digit/byte)
S01B Time (Year·month) BCD code.(Ex. "1234" represents "12 (min).34(sec).)
This timer works by 1ms as 0 seconds when the power
S022 1ms timer supply is turned on. This special register can be used Binary
3JG series/3J series since Ver3.3.
This timer works by 10ms as 0 seconds when the
S023 10ms timer power supply is turned on. This special register can be Binary
used 3JG series/3J series since Ver3.3.
S0A8
Link module code Code of the mounted link modules (Note 3 )
~
S0AF
Initial scan
S0C0 Initial sequence program execution time in program-1 (ms) Binary
time
SCAN TIME Maximum scan time in sequence program of program-1
S0C1 Binary
max value (ms)
PRG.1
SCAN TIME
S0C2 Minimum scan time in sequence program of program-1 Binary
min value
SCAN TIME
S0C3 Present value
Updated scan time in sequence program of program-1 Binary
Initial scan
S0C4 Initial sequence execution time in program-2 (ms) Binary
time
S0C5 Binary
max value (ms)
PRG.2
SCAN TIME Minimum scan time in sequence program of program-2
S0C6 Binary
min value (ms)
SCAN TIME Updated scan time in sequence program of program-2
S0C7 Present value
Binary
(ms)
1-44
S0C8 Initial scan time Initial sequence execution time in program-3 (ms) Binary
SCAN TIME max Maximum scan time in sequence program of program-3
S0C9 (ms)
Binary
value
PRG.3 SCAN TIME min
S0CA Minimum scan time in sequence program of program-3 (ms) Binary
value
SCAN TIME Present
S0CB Updated scan time in sequence program of program-3 (ms) Binary
value
S0E0 Changed portion Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8: parameter Bit
Program
S0E1 Ti m e ( M i n u t e · s e c ) Present time of the built-in clock is stored.
change BCD
S0E2 history 1 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0E3 Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
Program
change BCD
S0E6 history 2 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0E7 Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
Program
change BCD
S0EA history 3 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0EB Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
S0EC Changed portion Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8: parameter Bit
Program
S0ED Ti m e ( M i n u t e · s e c ) Present time of the built-in clock is stored.
change BCD
S0EE history 4 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0EF Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
S0F0 Changed portion Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8: parameter Bit
Program
S0F1 Ti m e ( M i n u t e · s e c ) Present time of the built-in clock is stored.
change BCD
S0F2 history 5 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0F3 Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
Program
change BCD
S0F6 history 6 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0F7 Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
Program
change BCD
S0FA history 7 T i m e ( D a y · H o u r ) For data display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0FB Ti m e ( Ye a r · m o n t h ) (Ex. "1234" represents "12 (min).34(sec).)
Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8:
S0FC Changed portion Bit
Program parameter
S0FD change Ti m e ( M i n u t e · s e c ) Present time of the built-in clock is stored.
history 8 T i m e ( D a y · H o u r ) BCD
S0FE For data display, 2 digits are represented by 1Byte in BCD code.
(Ex. "1234" represents "12 (min).34(sec).) (2 digit/byte)
S0FF Ti m e ( Ye a r · m o n t h )
S200
~
S24F
S250
PRG.1 Annunciator
(Note 2)
~
information
S2CF
S2D1 CPU Version CPU Version is stored.
S300 Prg1-Link1 Communication
(link) module See the individual instruction manual for each communication(link)
~
status module.
S3FF Prg1-Link8 information
1-45
S004 Time (Sec)
S005 Time (Minutes) Present time of the built-in clock is stored.
S006 Time (Hours) For data display, 1 digit is displayed by 1Byte in BCD code.
(Ex. "0102" represents "12".) BCD
S007 Time (Day) Year data is displayed with lower two digits of AD year. "day of (1 digit/byte)
S008 Time (Month) week" data is represented by 0 - 6, which correspond to Sun. -
S009 Time (Year) Sat.(Note 4)
S00A Day of week
S019 Time (Minute·sec) Present time of the built-in clock is stored. For data display, 2
BCD
S01A Time (Day·Hour) digits are represented by 1Byte in BCD code. (2 digit/byte)
S01B Time (Year·month) (Ex. "1234" represents "12 (min).34(sec).)
S0A8
Link module code Code of the mounted link modules(Note 3 )
~
S0AF
S250
PRG.2 Annunciator
(Note 2)
~
information
S2CF
(link) module
~
See the individual instruction manual for each communication(link) module.

status
S004 Time (Sec)
S005 Time (Minutes) Present time of the built-in clock is stored.
S006 Time (Hours) For data display, 1 digit is displayed by 1Byte in BCD code.
(Ex. "0102" represents "12".) BCD
S007 Time (Day) Year data is displayed with lower two digits of AD year. "day of (1 digit/byte)
S008 Time (Month) week" data is represented by 0 - 6, which correspond to Sun. -
S009 Time (Year) Sat.(Note4)
S00A Day of week
S019 Time (Minute·sec) Present time of the built-in clock is stored. For data display, 2
BCD
S01A Time (Day·Hour) digits are represented by 1Byte in BCD code. (2 digit/byte)
S0A8
~
S0AF
S250
PRG.3 Annunciator
(Note 2)
~
information
S2CF
(link) module
~

status
1-46
(2-4)Data memory single mode, Basic area
SCAN TIME min
S002 Minimum scan time in sequence program (ms) Binary
value
SCAN TIME Present
S003 value
Updated scan time in sequence program (ms) Binary
S004 Time (sec) Present time of the built-in clock is stored.
S005 Time (minutes) For data display, 1 digit is displayed by 1Byte in
S006 Time (Hours) BCD code.
BCD
S007 Time (day) (Ex. "0102" represents "12".) (1 digit/byte)
S008 Time (Month) Year data is displayed with lower two digits of AD
S009 Time (year) year. "day of week" data is represented by 0 ~ 6,
S00A Day of week which correspond to Sun. ~ Sat.(Note 4)
Binary,
S00C
lower
Integrated make time Cumulative value of CPU module make (current feed) time (h)
Binary,
S00D
upper
Binary,
S00E
lower
Binary,
S00F
upper
End processing time max Maximum end processing time in sequence program
S010 value Binary
(ms)
Minimum end processing time in sequence program
S011 End processing time Min value Binary
(ms)
End processing time Present Updated end processing time in sequence program
S012 value Binary
(ms)
S019 Time (Minute·sec) Present time of the built-in clock is stored. For data display,
BCD
S01A Time (Day·Hour) 2 digits are represented by 1Byte in BCD code.
(2 digit/byte)
S0A8
~
S0AF
Initial sequence program execution time in program-1
S0C0 Binary
(ms)
S0C1 Binary
PRG.1
max value (ms)
SCAN TIME
S0C2 Minimum scan time in sequence program of program-1 Binary
min value
SCAN TIME
S0C3 Present value
Updated scan time in sequence program of program-1 Binary
Initial scan
time
SCAN TIME
S0C5 Maximum scan time in sequence program of program-2 (ms) Binary
PRG.2
max value
SCAN TIME
S0C6 Minimum scan time in sequence program of program-2 (ms) Binary
min value
SCAN TIME
S0C7 Present value
Updated scan time in sequence program of program-2 (ms) Binary
Initial scan
time
SCAN TIME
S0C9 Maximum scan time in sequence program of program-3 (ms) Binary
PRG.3
max value
SCAN TIME
S0CA Minimum scan time in sequence program of program-3 (ms) Binary
min value
SCAN TIME
S0CB Present value
Updated scan time in sequence program of program-3 (ms) Binary
1-47
S0E1 Program Time (Minute · sec) Present time of the built-in clock is stored.
change For data display, 2 digits are represented by 1Byte in BCD BCD
S0E2 Time (Day· Hour)
history 1 code. (2 digit/byte)
S0E3 Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S0E6 change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0EA change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0EB Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S0ED Program Time (Minute · sec) Present time of the built-in clock is stored.
S0EE change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0EF Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S0F1 Program Time (Minute · sec) Present time of the built-in clock is stored.
S0F2 change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0F3 Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S0F6 change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0FA change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0FB Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S0FC Changed portion Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8: parameter Bit
S0FD Program Time (Minute · sec) Present time of the built-in clock is stored.
S0FE change Time (Day· Hour) For data display, 2 digits are represented by 1Byte in BCD BCD
S0FF Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
S200
~
S24F
S250
~
S2CF
(link) module
~

status
1-48
(2-5)Data memory single mode, extended area
ES000 Prg2-Link1 Communication See the individual instruction manual for each communication
(link) module
~
~
status
(link) module.
ES0FF Prg2-Link8 information (Corresponding to S300 - S3FF).
ES100 Prg3-Link1 Communication See the individual instruction manual for each communication
(link) module
~
status
(link) module.
ES1FF Prg3-Link8 information (Corresponding to S300 - S3FF).
1-49
(2-6) PC2 Compatible Mode
S000 Initial scan time Initial sequence program execution time (ms) Binary
S002 SCAN TIME min value Minimum scan time in sequence program (ms) Binary
S003 SCAN TIME Present value Updated scan time in sequence program (ms) Binary
S004 Time (sec)
Present time of the built-in clock is stored.
S005 Time (minutes) For data display, 1 digit is displayed by 1Byte in BCD
S006 Time (Hours) code.
BCD
S007 Time (day) (Ex. "0102" represents "12".)
(1 digit/byte)
S008 Time (Month) Year data is displayed with lower two digits of AD year.
S009 Time (year) "day of week" data is represented by 0 - 6, which
correspond to Sun. - Sat.(Note4)
S00A Day of week
S00C Binary, lower
Integrated make time Cumulative value of CPU module make (current feed) time (h) Binary,
S00D upper
S00E Binary, lower
Integrated run time Cumulative value of sequence program run time (h) Binary,
S00F upper
Maximum end processing time in sequence program
S010 End processing time max value
(ms)
Binary
S011 End processing time Min value Minimum end processing time in sequence program (ms) Binary
End processing time Present
S012 value
Updated end processing time in sequence program (ms) Binary
S019 Time (Minute· sec) Present time of the built-in clock is stored.
BCD
S01A Time (Day· Hour) For data display, 2 digits are represented by 1Byte in
(2 digit/byte)
S01B Time (Year· month) BCD code. (Ex. "1234" represents "12 (min).34(sec).)
S022 1ms timer power supply is turned on. This special register Binary
can be used 3JG series/3J series since Ver3.3.
S0A8
~
S0AF
S0E1 Program Time (Minute · sec)
change
Present time of the built-in clock is stored. For data
BCD
S0E2 history 1 Time (Day· Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
Program
S0E5 change
Time (Minute · sec) Present time of the built-in clock is stored. For data
BCD
S0E6 history 2 Time (Day· Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
Program
S0E9 change
BCD
S0EA history 3 Time (Day· Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0EB Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
Program
S0ED change
BCD
S0EE history 4 Time (Day· Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0EF Time (Year· month) (Ex. "1234" represents "12 (min).34(sec).)
Program
S0F1 change
BCD
S0F2 history 5 Time (Day·Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0F3 Time (Year·month) (Ex. "1234" represents "12 (min).34(sec).)
Program
S0F5 change
BCD
S0F6 history 6 Time (Day· Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
Program
S0F9 change
Time (Minute · sec) Present time of the built-in clock is stored.
BCD
S0FA history 7 Time (Day· Hour) For data display, 2 digits are represented by 1Byte in (2 digit/byte)
S0FB Time (Year· month) BCD code. (Ex. "1234" represents "12 (min).34(sec).)
S0FC Changed portion Bit B:PRG.3 Bit A: PRG.2, Bit 9 : PRG.1 ,Bit 8: parameter Bit
Program
S0FD change
BCD
S0FE history 8 Time (Day·Hour) display, 2 digits are represented by 1Byte in BCD code. (2 digit/byte)
S0FF Time (Year·month) (Ex. "1234" represents "12 (min).34(sec).)
1-50
S200
~
S24F
S250
~
S2CF
(link) module See the individual instruction manual for each communication(link)
~
status module.
(Note 1) Error information

Locations S200-S24F, equivalent of 80 words, of special registers are used to store up to 8
error codes and error code associated data. When an error message comes to the register
as the CPU detects fault, it causes data shift in the register to delete the oldest data and
enters in place. Thus error data stored are always the last 8 events.
Address
New S200 HOST SLAVE
S20A Error 0 information S200 Error codes
S214 Error-related Error-related
S21E Error-related Error-related
S228 Error 3 information S203 Error detection time (sec)
S232 Error 4 information S204 Error detection time (min)
S23C Error 5 information S205 Error detection time (hour)
S246 Error 6 information S206 Error detection time (day)
Former S24F Error 7 information S207 Error detection time (month)
S208 Error detection time (year)
Error detection time Error detection time
Cancel S209
(day of week) (day of week)
Error-related information are stored with hexadecimal number.
The current time of the built-in clock is stored.
The data represents 1bit at 1 digit in BCD code. (EX. "0102"
represents "12". )
Year data is represented by lower two digits of AD year and the
"day of week" data is represented by 0 ~ 6, which then
correspond to Sunday ~ Saturday.
(Note 2) Annunciator information
Locations S250-S2CF, equivalent of 128 words, of the special register are exclusively used
to store annunciator messages and times at which the message are issued. These locations
are user accessible and can be programmed to store up to 8 messages concerning device
diagnosis.
Address
S250 Annunciator 0 code
S259 Annunciator 0 detected time(sec)
S25A Annunciator 0 detected time(minute)
S25B Annunciator 0 detected time(hour)
S25C Annunciator 0 detected time(day)
1-51
S25D Annunciator 0 detected time(month)
25E Annunciator 0 detected time(year)
S25F Annunciator 0 detected time(W day)
S2CE Annunciator 0 detected time(year)

S2CF Annunciator 0 detected time(W day)
(Note 3) Code of the mounted link modules

module name code
PC link master 0102

PC1-I/F output 0102
PC link slave 0002
PC1-I/F input 0002
Computer link 0003
ME-NET master 0104
ME-NET slave 0004
SIO module 0005
Memory card I/F 0005
High speed remote I/O 0008
AS-I 0008
HPC link master 4009
SUB-CPU master 4009
HPC link slave **09 ** : Slave number
SUB-CPU slave **09 ** : Slave number
2-port M-NET 0002

Pulse output module 0100
DLNK-M 8008
DLNK-S2 8008
DLNK-M2 8208
Ethernet 8203
AF1K 800E
MA1K 810E
Motion controller 820E
FL-net(8KB) 8009
FL-net(16KB) 8109
FL-net(32KB) 8209
PROFI-S2 8309
(Note 4)
Even if the register is rewritten directly, time change is impossible. Please perform a setup of
time from <Setup data/time> of Pcwin or use an exclusive use of an application instruction.
(Please refer to "309 SYS Clock adjustment instruction(FUN300)" in "5.4.22 Extension of
applied instructions for PC3J series( ver 2.6~)" about an application instruction.)
1-52
2. EXECUTION OF PROGRAM
2.1. Processing operation

Sequential program starts at the first location in the sequential program area and stops on an END
instruction followed by internal post-processings such as updating of external I/O data and self
diagnosis. And then the program returns back to the step in which START instruction resides and
repeats steps through the END instruction. The portion of whole program starting from the beginning
of the program to START instruction is called the initial sequential program (initial program) and a
program from START to END instructions is called main sequential program (main program). A
START instruction can be stored at the beginning of whole program to have the main program only.
The processing for external I/O data starts by reading the external I/O data onto the image memory
before the initial sequence program. Then, the initial sequence program and main sequence
program are executed for the data on the image memory.
After executing the END instruction, the data on the image memory is output to the external output
module. That is the end of one scan.
After that, the current external I/O data is read onto the image memory before the START instruction
and the processing shown above is executed as(2), (3), and so on.
2-1
(2) In case of PC3J
The PC3JG can execute two or more programs, that is, three sequence programs maximum. In
detail, these programs are executed in the order of program-1, program-2, program-3 and end
processing.
The number of programs and execution/ non-execution ( *1) of program-2 and -3 are set up using
the CPU operation mode parameters.
Furthermore, link/non-link ( *2) of program-2 and -3 with RUN signal is also set using the CPU
operation mode parameters.
*1 Execution of program-2 /-3 can be selected from the CPU operation mode parameters. If
INEFFECTIVE(Non-execution) is selected, the applicable program (program-2 or 3) is not
executed.
*2 Link of program-2/-3 can be selected from the CPU operation mode parameters. If "LINK"
is selected and the applicable program stops, RUN signal turns OFF linked with the
program stop and all other programs stop simultaneously.
(2-1) Program execution sequence

Power ON or Reset/Start
Update I/O data

1st scan only*3
PRG.1 PRG.1 PRG.1
Initial 1st Initial 1st Initial

program*3 program*3 scan program*3
scan
only*3 only*3
START START START
Main Main Main

program program program
CALL
END END END
LABEL *4 LABEL *4 LABEL *4

Subroutine Subroutine Subroutine
RET program program program
RET RET RET
· ·
· ·
· ·
PEND PEND PEND
*3 Initial program is a sequence program being executed only once whenever the power
switch is turned ON or RESET/START is pressed.
*4 :showing label No. of subroutine program. 128 subroutines of S000 ~ S127 per
program and 1024 subroutines of EL0000~EL1023 commonly available for jump and
subroutine can be created respectively.
2-2
(2-2) Execution/non-execution of program
Execution/non-execution of program 2 and program 3 is set using the CPU operation mode
parameters. Program for which non-execution was selected is not executed.
Execution of program -1,to -3 Execution of program -1,-3 Execution of program -1,-2 Execution of program –1 only
PRG.1 PRG.1 PRG.1 PRG.1

Execution (fixed) Execution (fixed) Execution (fixed) Execution (fixed)

Execution Non-execute Execution Non-execute

Execution Execution Non-execute Non-execute
End processing End processing End processing End processing

(Update I/O data) (Update I/O data) (Update I/O data) (Update I/O data)
(2-3) Link of program with RUN signal
Link of program-2 and -3 with RUN signal can be selected from the CPU operation mode
parameters. If "LINK" is selected and applicable program stops, RUN signal turns OFF linked
with the program and all other programs stop simultaneously.
Link with RUN signal (by parameter setting) RUN signal status at program stopping
Program-1 Program-2 Program-3 Program-1 Program-2 Program-3
Link (fixed) Link Link OFF OFF OFF

Link (fixed) Non-link Link OFF Continued OFF
Link (fixed) Link Non-link OFF OFF Continued
Link (fixed) Non-link Non-link OFF Continued Continued
(2-4) Execution of SFC program
The SFC program is executed after the main program of each program.
START
Main program SFC program
END
2-3
2.2. Subroutine
A part of program which is repeatedly used in different parts of the program is called subroutine and
stored in an area together with other subroutines. When a CALL instruction in a program is
encountered, a subroutine having the label in which the subroutine number denoted by the CALL
instruction is executed. A RET instruction causes the program to return to the step where
processing was made before issuing of the CALL.
Processing order
START (1)
(6)
CALL S***
(3) Followed by repetition of
steps (2) to (6)
CALL S***
(5)
END
LABEL S***
(2) (4)
Subroutine
RET
Available number of subroutines are 128, S000 to Sl27. These subroutines can be nested as shown
below.
For PC3J series, 1024 labels (EL0000 – EL1023) is added.
Processing order
START (1)
(6)
CALL S***
Followed by repetition of
(5) steps (2) to (6)
END
LABEL S***
(2)
CALL S###
(4)
RET
LABEL S###
(3)
RET
2-4
2.3. Interrupt program PC2/L2
The PC2/L2 can handle interruption in two ways: processing of interrupt by executing a special
sequence at the predetermined interval and processing of a special sequence as external interrupt
event occurs. The PC2J has no interrupt function.
2.3.1. Periodic interrupt
A function to start an interrupt program at an interval. Up to 4 interrupt programs can be provided for
the controller. The interval of interruption can be set from the programmer as a premeter, in a range
from 0 to 655350 ms(in units of 10 ms). Setting parameter to 0 denotes no interruption. When the
periodic interruption is programmed, the interrupt programs having an interrupt number, I0-I3, in the
label are executed at individually set intervals. The program returns to the main routine on a RETI
instruction.
Processing order
START (1) (6)

EI
Periodic interrupt0 (3)
Periodic interrupt1 (5)
END
LABEL I0
(2)
RETI
LABEL I1
(4)
RETI
2-5
2.3.2. External interrupt
An interrupt program can be started by external interrupt source through an external interrupt
module(optional). The interrupt module includes l6 input points. Up to 4 modules can be installed to
accommodate maximum 64(16x 4)external interrupt signals.
When an external interrupt is applied, the controller executes the interrupt program having the label
whose interrupt number(E0-E63) corresponds to the input point, and returns to the main program as
the RETI instruction is fed.
Processing order
START (1) (6)

EI
External interrupt0 (3)
External interrupt1 (5)
END
LABEL E0
(2)
RETI
LABEL E1
(4)
RETI
2-6
2.3.3. Interrupt program considerations
(1) Interrupt program can be enabled and prohibited by application instructions EI and DI,
respectively.
(2) Default setting upon power-up and reset start is an interrupt program prohibited state(DI
state).EI instruction must be executed beforehand to execute the interrupt program.
(3) When an interruption occurs during execution of basic or application instruction, the interrupt
program is started upon completion of the current execution. This means that an interruption
during execution of an application program requiring a long processing period such as the block
transfer will have a long interrupt latency.
(4) Occurring of an interrupt(in EI status)having higher interrupt priority to the currently processed
interrupt program can make interruptible state and will be processed before the current
program. An interrupt(even in EI status) of lower level than the currently processed interrupt
program is suspended until the RETI instruction is executed.
High Priority Low
External interrupt Periodic interrupt

0 1 2 3 4 62 63 0 1 2 3
(5) When an interrupt is accepted, the controller is in interrupt inhibit(DI)status during

execution of the interrupt program. To enable the controller for multi interruption(nesting),EI
instruction must be executed by the interrupt program. Execution of the RETI instruction
automatically enters into interrupt enable(EI)status.
(6) The interrupt program is executed for the data on the image program. Therefore, the output
data calculated during the interrupt processing is not output to the external output module until
one scan is finished, that is, until the END instruction is finished. In order to output the result of
the interrupt processing to the external output module immediately, use the I/O control
instruction, RIO, RI, or RO(refer to 5-4-14),in front of the RETI instruction.
2-7
2.4. Scan time
The timer interval between the start of the program and the execution of START instruction, i.e. the
execution period of initial program is called the scan time of initial program; and the interval
between the end of execution of START instruction and the starting of the next execution of START
instruction, i.e. the cycle time of main program, is the scan time of main program.
These scan times are continuously compared with the contents of the scan timer set by parameter
and cause a scan timer over error when one or both of them exceed the preset value. For obtaining
correct comparison result, these parameters should be set to match the scan time of corresponding
program.
The scan time value of program being executed is stored in special register, S000-S003, and can be
read out on the I/O monitor or by an appropriate application instruction.
Address Contents
S000 Scan time in the initial program (Binary : ms)
S001 Maximum scan time in the sequence program (Binary : ms)
S002 Minimum scan time in the sequence program (Binary : ms)
S003 Current scan time in the sequence program (Binary : ms)
(2) In case of PC3J
Address Contents
S001 Maximum scan time in the sequence program (Binary : ms)
S002 Minimum scan time in the sequence program (Binary : ms)
S003 Updated scan time in the sequence program (Binary : ms)
S010 Maximum end processing time in the sequence program (Binary : ms)
S011 Minimum end processing time in the sequence program (Binary : ms)
S012 Updated end processing time in the sequence program (Binary : ms)
Initial sequence program execution time in
S0C0 (Binary : ms)
program-1
Maximum scan time in sequence program of
S0C1 (Binary : ms)
program-1
PRG1
Minimum scan time in sequence program of
S0C2 (Binary : ms)
program-1
Updated scan time in sequence program of
S0C3 (Binary : ms)
program-1
S0C4 (Binary : ms)
program-2
S0C5 (Binary : ms)
program-2
PRG2
S0C6 (Binary : ms)
program-2
S0C7 (Binary : ms)
program-2
S0C8 (Binary : ms)
program-3
S0C9 (Binary : ms)
program-3
PRG3
S0CA (Binary : ms)
program-3
S0CB (Binary : ms)
program-3
2-8
3. PARAMETER
Some functions of the TOYOPUC, such as processing upon occurrence of error and setting of
interrupt interval are user settable and are called parameters.
3.1. Contents of parameters

The table below lists these parameters which are set from the peripheral device. For setting
procedures, refer to the instruction manual for the peripheral device.
Items Settable range

PC2/L2 PC2J-16KW PC2J-8KW
PC2/L,PC2J
Program capacity 32KW(Fixed) 16KW(Fixed) 8KW(Fixed)

CPU operation mode
File register capacity 8KW(Fixed) None(0KW) None(0KW)

Comment capacity 24KW(Fixed) None(0KW) None(0KW)
Data area separate mode 1 - 5 / PC3JG mode
User memory Data area single mode 1 - 6
PC3J series
PC2 compatible mode

Program1 Effective [Execute] (fixed)
Program execution Effective [Execute]
Program2,3
/Ineffective [Non-execute]
Program1 Link (Fixed)
Link with RUN signal
Program2,3 Link /Non-link
Overall PC3J
Scan time timer value Initial program 1 - 65535ms
Basic performance
Main program
Scan time over
Running status against I/O table verification error
Stop/continue
error Applied command error
Data error PC3J
I/O module allocation *1 Type identification code Module identification code
(0 - E rack, 0 - 7 slots ) Allocation points 0 - 64points/slot
Link
Link parameters*2 Depending on type of link module
module
Other Program name 64characters (half size)
*1 The CPU has the function to recognize the installation status of I/O module, whereby I/O
configuration preset in parameters is compared with the real installation status of same
module when the power switch is turned ON or RESET is pressed.
Therefore, incorrect configuration of I/O module or use of incorrect module type and missing
parameter setting would result in " I/O TABLE VERIFICATION ERROR".
In addition to the above function, allocation of I/O address occupied points to each slot is can
be set and this data is prior to the real points in I/O module.
*2 Fourteen (15) link modules (communication) maximum can be installed.
However, the number of modules per program is up to 8 maximum.
Also, the memory consumption capacity can not be installed in excess to 60Kbyte. This
capacity differs depending on each communication module.
The memory consumption capacity means "memory capacity" which is used for data change
between CPU and communication module. It does not relate to user memory ( program data
memory, equipment information memory).
Use of link (communication) modules never results in reduction of user memory capacity. At
initial stage the CPU allocates the memory capacity to each link (communication) module by
equally distributing 60Kbyte space thereto.
3-1
(1) Program capacity
Set the memory capacity for a sequential program.

PC2/L2 32K words PC2J-16KW words
PC2J/8KW 8K words
PC3J series This is decided according to CPU operation mode.
(2) File register capacity
Set the capacity of file register area.

PC2/L2 8K words PC2J OK word
PC3J series This is decided according to CPU operation mode.
(3) Comment capacity
Set the data capacity of comment area.

PC2/L2 24K words PC2J OK word
PC3J series Comment is made to the binary and preserved. So, the capacity is
changeable.
(4) Time length of scan time
Set the time length of scan timer for initial program and main program in unit of milliseconds.
The time length should be within 1 to 65535 ms. If the scan exceeds the time set by this
parameter, the scan time over error will occur.
(5) Operating status in error condition
Select stop or continue of the current program upon occurring of the following error, “Scan time
over”, “I/O table verifying error” or “Application instruction error”.
(6) Program name
Store the program name as a parameter, and the contents of program are easily recognizable.
(7) Type discriminating code of I/O modules
Set the type of I/O module for each slot. When the power is turned on or upon a reset start,
the CPU compares the set type with the actual module used. If they do not agree, the CPU
reports an “I/O TABLE VERIFYING ERROR”. There are two methods for setup procedures:
Manual setup for each slot and reading the actual module type to use it as a parameter. (Refer
to the instruction manual for each module for type discriminating codes.)
3-2
(8) Number of allocation points of I/O module
Set the number of I/O points each I/O slot occupies.

Setting can be made either by 1) setting each slot by manual input or 2) reading the actual
installation status of I/O modules and using the readings as parameters. This data takes
priority over the actual points of I/O module.
(9) Interval of periodic interruptions PC2/L2
Set the periods of 4 periodic intervals, respectively, to the value between 0 and 655350 ms (in
units of 10 milliseconds). Setting the time to 0 means no interruption.
(10) External interrupt mask flag PC2/L2
Classify the inputs from optional external interrupt module, if any into ones to be processed as
interrupt input or ones to be handled as normal input.
(11) Link parameter
Set the parameter of communication module to be used, such as PC link module and computer
link module. Details of parameters differ from model to model and should be set by referring to
the instructions of the module to be used.
3-3
3.2. Setting the parameters
There are two ways to set the parameters: auto setting by the CPU module and individual setting by
a peripheral device. While setting the parameters individually using a peripheral device, it is
convenient to use the function which reads the actual installation status of the modules and sets
those reading in “Type discriminating code of I/O module” and “Number of allocation points of I/O
module”.
3.2.1. Auto setting by CPU module

3.2.1.1. In case of PC2/L2, PC2J
In auto setting by the CPU module, the parameters are set as shown in the chart below. If you want
to set the parameters otherwise, use a peripheral device to set them individually.
If a communication module is installed, note that the number of points for the communication data
cannot be set by auto setting; set the parameter using a peripheral device.
Items PC2/L2 PC2J-32KW PC2J-16KW PC2J-8KW

Program capacity 32KW 32KW 16KW 8KW
File register capacity 8KW 0KW 0KW 0KW
Comment capacity 24KW 0KW 0KW 0KW
I/O table verification error Stop
Runnin
Scan time over Stop
g status
against Applied command error Run
error
Initial scan time over detection 10ms
Scan time over detection 100ms
External interrupt mask All points masked
Periodic interrupt All points 0 (No interrupt))
I/O module discrimination Actual installation
Number of I/O allocation points
Actual installation
(Note 1)
Actual installation
Link parameters are allocated starting from the one closest
Link parameter
to the CPU. I/O points are not allocated. PC link is
allocated to a slave station.
3-4
(Note 1) The number of I/O points allocated to an empty slot are different in the PC2/L2 and
PC2J.
PC2/L2 : Since 32-point modules are standard, 32 points are

(Up to SCPU-3**) allocated to all empty slots.
PC2/L2 : 32 points are allocated to an empty slot which is found in

(SCPU-4.00 or later) between I/O modules. However, 0 point is allocated
to the last empty slot of each rack.
PC2J : Since 16-point modules are standard 16 points are

allocated to an empty slot which is found between I/O
modules. However, 0 point is allocated to the last
empty slot of each rack.
Example
0 1 2 3 0 1 2 3
PC2/L2
CPU vacancy IN-22 OUT-21 vacancy PC2J vacancy IN-22 OUT-21 vacancy
(Up to 32 32 32 32 16 16 16 0
SCPU - points points points points CPU points points points point Allocated
3**)
points
000 020 040 060 000 010 020
| | | | | | | I/O address
01F 03F 05F 07F 00F 01F 02F

0 point to the
last vacant slot
32 points to all vacant slots 16 points to a vacant slot found between

I/O modules
0 1 2 3
PC2/L2
CPU vacancy IN-21 OUT-21 vacancy
(SCPU- 32 32 32 0
4.00 or points points points point
later) Allocated points
000 020 040
| | |
I/O address
01F 03F 05F
0 point to the last vacant slot
32points to a vacant slot found between I/O modules
3-5
(1) Setting with Pc2/L2
Setting is done with the I/O monitor.

(When the version is SCPU-4.60 or higher, the reset-start switch can be used as with the
PC2J.)
Operation procedure:
(a) Press the CLEAR key to display the version.
(b) Pressing and P sets the PC2/L2 in the waiting state for parameter auto
setting. * 0
(c) The parameters are set by pressing SHIFT + MODE , ,and SET .
*
Note:
This operation is effective only when the program is paused. If these keys are pressed when a
program is being executed, “CPU RUNNING!” is displayed.
Input key Display

CLEAR
TOYOPUC-PC2V2.01
*
P
0 PARAM.AUTO_SET_?
SHIFT MODE
PARAM.AUTO_SET_?
* PARAM.AUTO_SET_ *
SET
PLEASE_RESET_ _ _ _
(RUN) CPU_RUNNING_ ! _ _ _
3-6
(2) Setting with PC2J/PC2JC
Setting is done with the reset-start switch.
Operation procedure:
(a) Move reset-start switch to “START” when the power is turned off and hold it there with your
finger so that the switch will not return to “RESET”.
(b) Supply the power
(c) Now auto setting for parameters has been finished. If an error is detected, the error code
is displayed and if not, “00” blinks on the display.
(The PC2JC is not provided with a 7-segment display.)
Blinking
(d) Reset and start again; the sequential program will start.
(3) Setting with PC2JS/PC2JR/PC2J16
Setting is done with the dedicated switch.
Operating procedure:
(a) Press the switch located just above the peripheral device connector.
(b) Now auto setting for parameters has finished.
(c) Re-supply the power or start from the peripheral device; the sequential program will start.
Switch
3-7
3.2.1.2. In case of PC3J series
In auto setting by the CPU module, the parameters are set as shown in the chart below. If you want
to set the parameters otherwise, use a peripheral device to set them individually.
If a communication module is installed, note that the number of points for the communication data
cannot be set by auto setting; set the parameter using a peripheral device.
Item Set value

Identification of I/O
as actually installed
Allocation of I/O module module
(0~E rack and 0~7 slot) Allocation
as actually installed
of I/O point
*1
Link parameter as actually installed *2
*1 Only such name setting as lack No., slot No. and link module is implemented.
*2 DLNK is allocated as high-speed remote I/O. Set DLNK using peripheral equipment.
Lack No. and slot No. are allocated from link 1-1 in program 1 in the order of their smaller
number. They are also allocated to link 2- # in program 2 when actual installed link
number exceeds 8.
However they are allocated to link 3- # in program 3 when CPU operation mode having
no program 2 is selected.
No allocation is made for the link that is exceeded link number 8 when CPU operation
mode having neither program 2 nor program 3 is selected.
(1) Setting
(a)With the power switch kept
OFF, shift "RESET/START"
switch to " START" and press
the same switch with finger
so as not to return.
START
RESET
RESET/START switch
(b)Turn ON the power switch.
(c)This completes automatic setting of I/O modules and link parameters. If error is
detected at this stage, ERR lamp lights.
(d)If no error, the sequence is put in RUN by RESET/START switch.
3-8
3.2.2. Setting with a peripheral device
Setting with PCwin (For other peripheral devices, refer to their instruction manuals).
(1) Parameter setting

For parameter setting, if the Folder of parameter on the Project Screen is double clicked,
following parameter setting items will be displayed.
Next by double clicking the items to be set, setting dialog will be displayed.
Double-click
the item to be
set
3-9
(2) CPU operation mode
Please determine the data area (program capacity, file register capacity, comment capacity)
matching to the system.
(a) PC3J series

In case target PLC is PC3JG, [PC3JG separate] , [Separate 1-5] or [Single 1-6] is selected.
In case of other PC3 series, [Separate 1-5] or [Single 1-6] is selected.
Note) When the set mode is ' separate ', it is not possible to change it to single mode.
Similarly, when the set mode is 'single', it is not possible to change it to the split mode. If
the circuit under editing is of PC compatibility mode, the separate mode can be changed
to single mode.
(b) PC2/PC2J series

[PC2 mode] should be selected when the object PLC is of PC2/PC2J series.
Input of "program capacity", "file register" and "comment capacity" will be possible when
PC2 mode is selected.
Complete the setting by clicking[OK]. For canceling the setting, click [cancel].
3-10
(3) CPU operation state
Setting whether execution is to be made against allocated Program Number or not is

made (Setting of Program 2,3 cannot be made in case of PC2 compatible mode).
(4) I/O module
Select all the modules mounted on the Rack.

As for method of setting, there are “Automatic Setting” and “Manual Setting”. (Usually
“automatic setting” is carried out.)
(a) Setting
Select the Rack No. and the Slot No. that are to be set and press [Set (S)]. Following screen
will be displayed. Set the Allocated point, Identification code, Module Type and Module
Name.
3-11
(b) Current value
Current state can be easily set by reading the Program from the CPU.
(i)Read the Program from the CPU.
(ii)After displaying the setting of I/O module, “Current Value” is pressed.
(iii)Following message will be displayed and select [Yes].
(iv)Since setting will be changed, click [OK] and end the process.
(5) Run state during error
Run state when error is detected in CPU can be set. Insert the check in the item “Stop the
CPU” when error occurs.
(6) Scan time timer
Scan Time Value of overall Program of the System, Initial Program of Programs 1 ~ 3 and
each Scan Time value of Main Program are set. At the time of Program execution, if set scan
time is executed, CPU error will occur.
3-12
(7) Program name
Program name can be respectively set in the system and Program 1~3. Input Range is
maximum 64 half size characters.
Program Name set here will be displayed in the Program Folder of the Project Screen.
(8) Interruption
Interruption is of 2 types namely “Fixed Cycle Interruption” and “External Interruption”.

Select the appropriate item and set .
(a) Setting of fixed cycle interruption timer.
Selecting Interruption No., if [Details] is pressed, Details Setting Screen will be displayed.
After all the settings are complete, press [OK].
3-13
(b) Setting of external interruption timer
Selecting Interruption No., if [Details] is pressed, Detailed setting screen will be displayed.
Set the Mask and the used program.

After the setting is complete, click [OK].
Cautions when setting parameters
(1) If you have made a program using only a peripheral device and tried to write “program
+parameter” or “program” to the CPU, a parameter error will be developed. In that case,
perform parameter auto setting by the CPU. If you want to set the parameters differently from
the auto setting, set the parameters using a peripheral device before writing “program +
parameter”.
(2) If you had set the parameters by auto setting, read out “program + parameter” from the CPU
before changing programs or storing it to a floppy disk. If this is neglected, the parameter data
in the peripheral device does not agree with the parameter data in the CPU which may cause
damage to the CPU’s parameters later during the write-in operation.
3-14
4. USER MEMORY STRUCTURE
4.1. Program memory structure
4.1.1. In case of PC2/L, PC2J
The program memory location of TOYOPUC is divided into three areas: program area, parameter area
and comment data area and is backed up by a lithium battery to protect memory during power loss.
Upon entering memory card operation, the data is transferred from the card to these memory locations.
8Kwords(16Kbytes) PC2J-8KW
Max. 32K words
Program area Program area 16Kwords(32Kbytes) PC2J-16KW
(64Kbytes)
32Kwords(64Kbytes) PC2J-32KW
Parameter Parameter
16Kbytes 16Kbytes
area area
Comment data PC2J

48Kbytes
are
PC2/L2
(1) Program area
The memory space to store the sequential program.
(2) Parameter memory area
Some of the CPU functions such as processing upon occurrence of error and intervals periodic
interrupts are user settable.
These setting values area called parameters and stored in this area.
(3) Comment data memory area
The CRT programmer and GP1 have function to add comment to a sequential program. These
additional comments are stored in this area.
A comment can be made to an I/O address (bit address, byte address, or word address) or to a
serial No. of an application instruction. Comment data up to 28 half-size characters, or 14 full-size
characters can be stored in this area.
PC2/L2 Up to 1536 comments can be stored in the comment data area in the CPU. For more
than 1536 comments, store them on a floppy disk using the GP1 (GL1).
PC2J The PC2J does not have comment data area in its CPU.
Store all comments on a floppy disk.
For details, refer to the instruction manual for GP1 (GL1).
4-1
4.1.2. In case of PC3J series
(1) Program capacity and data capacity

Program capacity and data capacity depend on CPU operation mode.
" Data area separate mode", " Data area single mode", and "PC2 compatible mode" are available as
CPU operation mode. And program capacity and data capacity can be selected as necessary.
Data area separate mode : has independent data area every each program.
Data area single mode : data area in each program is common to other programs.
PC2 compatible mode : Use of PC2 Series peripheral devices is allowed. However, the number
of available programs is limited to one 32K words program (Program-1).
Any function extended in PC3J is unable to be used under this mode.
The PC3 Series peripheral equipment (Hellowin) is available for CPU operation modes except PC3JG
mode.
The PC3 Series peripheral equipment (Pcwin before Ver4.* ) is available for CPU operation modes
except PC3JG mode.
The PC3 Series peripheral equipment (Pcwin Ver5.* or later) are available for all modes.
Relationship of CPU operation mode to program capacity and data capacity :

Program capacity KW Basic area data capacity KW Extended area data capacity KW
Mode relay
PRG.1 PRG.2 PRG.3 PRG.1 PRG.2 PRG.3 data buffer
register
Separate
mode 1 16 16 16 8 8 8 8 - -
Separate
mode 2 32 - 16 16 - 8 8 - -
Separate
mode 3 16 32 - 8 16 - 8 - -
Separate
mode 4 16 16 - 8 16 - 8 16 -
Separate
mode 5 16 - 16 16 - 8 8 16 -
PC3JG 60 60 60 8 8 8 16 32 128
PC3 Single 16 16 16 24*
1
8
mode 1
Single 1
mode 2 32 - 16 24* 8
Single 1
mode 3 16 32 - 24* 8
Single 1
mode 4 32 - - 24* 8
Single 1
mode 5 16 - - 24* 8
Single 1
mode 6 16 16 - 24* 8
PC2 compatible 32 - - 24 - - - -
*1 The basic area data in single mode is common to each program.
Note: Change of operation mode would cause sequence programs and data hitherto to be canceled.
Caution it !
4-2
In addition to the above, as CPU operation mode parameter execution/non-execution of program-2,-
3 and its link with RUN signal can be selected.
Item Selection value

Program1 Effective [EXECUTE] (fixed)
*1
Program execution Program2 Effective /ineffective ( Execute/non-execute)
Program3 Effective /ineffective ( Execute/non-execute)
Program1 Link (fixed)
*2
RUN signal link Program2 Link /Non-link
Program3 Link /Non-link
*1 Execution of Program-2 and-3 can be selected from the parameters.
If "INEFFECTIVE" is selected, the applicable program (program-2 or -3) is not
executed.
*2 Link of program-2 and -3 with RUN signal is selected from the parameters. If "LINK" is
selected and the applicable program stops, RUN signal turns OFF, linked with the
program , then allowing stop of all the programs.
4-3
(2) Separate patterns of program data
(2-1)Data area separate mode
Separate pattern 1
PRG.1 PRG.2 PRG.3
Program 1 Program 2 Program 3

(16KW) (16KW) (16KW)
I/O
Basic area Basic area Basic area

data data data
Extended area
data
Separate pattern 2
PRG.1 PRG.3
Program 1 Program 3
(16KW)
(32KW)
I/O
Basic area
Basic area data
data
Extended area
data
4-4
Separate pattern 3
PRG.1 PRG.2
Program 1 Program 2
(16KW)
(32KW)
I/O
Basic area
data Basic area
data
Extended area
data
Separate pattern 4
PRG.1 PRG.2
Program 1 Program 2
(16KW) (16KW)
I/O
Basic area
data Basic area
data
Extended area
data
4-5
Separate pattern 5
PRG.1 PRG.3
Program 1 Program 3
(16KW) (16KW)
I/O
Basic area
Basic area data
data
Extended area
data
PC3JG mode
PRG.1 PRG.2 PRG.3

(60KW) (60KW) (60KW)
I/O
Basic area Basic area Basic area

data data data
Extended area
data
4-6
(2-2)Data area single mode
Single pattern 1
PRG.1 PRG.2 PRG.3

(16KW) (16KW) (16KW)
I/O
Basic area
data
Extended area
data
Single pattern 2
PRG.1 PRG.3
Program 1 Program 3
(16KW)
(32KW)
I/O
Basic area
data
Extended area
data
4-7
Single pattern 3
PRG.1 PRG.2
Program 1 Program 2
(16KW)
(32KW)
I/O
Basic area
data
Extended area
data
Single pattern 4
PRG.1
Program 1
(32KW)
I/O
Basic area
data
Extended
area
data
4-8
Single pattern 5
PRG.1
Program 1
(16KW)
I/O
Basic area
data
Extended
area
data
Single pattern 6
PRG.1 PRG.2
Program 1 Program 2
(16KW) (16KW)
I/O
Basic area
data
Extended area
data
4-9
(2-3)PC2 compatible mode
PRG.1
Program 1
(32KW)
I/O
Basic area
data
4-10
4.2. Data memory structure
4.2.1. In case of PC2/L, PC2J
4.2.1.1. Data memory map
Indirect address (Hexadecimal) PC2/L2 Indirect address (Hexadecimal) PC2J

0000 0000
Edge detection (P000 ~ 1FFF) Edge detection (P000 ~ 1FFF)
0040 0040
Keep relay (K000 ~ 2FF) Keep relay (K000 ~ 2FF)
00A0 00A0
Special relay (V000 ~ 0FF) Special relay (V000 ~ 0FF)
00C0 00C0
Timer, counter (T,C000 ~ 1FF) Timer, counter (T,C000 ~ 1FF)
0100 0100
Link relay (L000 ~ 7FF) Link relay (L000 ~ 7FF)
0200 0200
I/O (X,Y000 ~ 7FF) I/O (X,Y000 ~ 7FF)
0300 0300
Internal relay (M000 ~ 07FF) Internal relay (M000 ~ 07FF)
0400 0400
Special register (S0000 ~ 03FF) Special register (S0000 ~ 03FF)
0C00 0C00
Current value register (N0000 ~ 01FF) Current value register (N0000 ~ 01FF)
1000 1000
Link register (R0000 ~ 07FF) Link register (R0000 ~ 07FF)
2000 2000 PC2J-8KW Data register

(D0000 ~ 0FFF)
Data register (D0000 ~ 2FFF)
PC2J-16KW Data register
PC2J-32KW (D0000 ~ 2FFF)
8000
C000
File register (B0000 ~ 1FFF)
FFFF
4-11
4.2.1.2. Data memory address
Data
Indirect PC2/L2 PC2J holding
byte
No. Identifier Name address
area at
Bit Word Bit Word power cut
offset Points addres Points
address address address off
1 X Input X,Y000 X,Y00 X,Y00W
X,Y00W~
0200 2048 0 512 -
2 Y Output ~7FF 7FW ~1FW
~1FF
M000 M00W M000 M00W
3 M Internal relay 0300 2048 2048 -
~7FF ~7FW ~7FF ~7FW
K000 K00W K000 K00W
4 K keep-relay 0040 768 768 O
~2FF ~2FW ~2FF ~2FW
V000 V00W V000 V00W
5 V Special relay 00A0 256 256 -
~0FF ~0FW ~0FF ~0FW
6 T Timer T,C000 T,C00W T,C000 T,C00W
00C0 512 512 -
7 C Counter ~1FF ~1FW ~1FF ~1FW
L000 L00W L000 L00W~
8 L Link relay 0100 2048 2048 -
~7FF ~7FW ~7FF 7FW
Edge P000 P000
9 P 0000 - 512 - 512 -
detection ~1FF ~1FF
PC2J-8KW 4096
D0000
~0FFF
D0000 PC2J-16KW
10 D Data register 2000 - 12288 - 12288 O
~2FFF PC2J-32KW
D0000
~2FFF
R0000 R0000
11 R Link register 1000 - 2048 - 2048 O
~07FF ~07FF
Present value N0000 N0000
12 N register
0C00 - 512 - 512 O
~01FF ~01FF
Special S0000 S0000
13 S 0400 - 1024 - 1024 O
register ~03FF ~03FF
B0000
14 B File register C000 - 8192 - - - O
~1FFF
(1) Bit devices area external I/O, internal relay, etc. which are usually set or reset by 1 bit and designated
by the bit address.
Word devices are devices such as the data register handled by a unit of 16 bits and are designated
by the word address.
(2) A bit device can be handled by a unit of 16 bits as if it is a word device. This can be done by using an
application instruction and replacing the lowest bit of a bit address with the character W (as it
implies).
Example 1 : X10W…..Represents 16 points, X100-X10F
Example 2 : M03W…..Represents 16 points, M030-M03f
(Note) When handling the data in a unit of 16 bits or 2 bits, use word address. Designation cannot
be made using bit or byte address (refer to the following). Therefore, for example, 16-point
data from X108 to X117 or from D0H to D1L cannot be handled as 1-word data.
4-12
(3) When data is divided into two 8 bits, it should be distinguished from the other in addressing by
suffixing H (upper byte) and L (lower byte). For bit devices, W in a word address is replaced by H or
L.
Example 1 : D1000L…..Represents the lower 8 bits of D1000.
Example 2 : X10H……..Represents upper 8 bits of X10W (X100-X10F),

i.e. X108-X10F.
(Note) When handling the data in a unit of 16bits (word) or 32bits, designation starting with the upper
byte of the register cannot be made.
Example: H L
D0 D0H and D1L cannot be designated as one word.
D1
(EX.)
Bit address Word address Byte address
X000 (LSB) (LSB)
X001
X002
X003
X00L Lower byte
X004
X005
Bit X006
address X007 (MSB)
X00W
area X008 (LSB)
X009
X00A
X00B
X00H Upper byte
X00C
X00D
X00E
X00F (MSB) (MSB)
D0000-0 (LSB) (LSB)
D0000-1
D0000-2
D0000-3
D0000L Lower byte
D0000-4
D0000-5
Word D0000-6
address D0000-7 (MSB)
D0000
area D0000-8 (LSB)
(Example) D0000-9
D0000-A
D0000-B
D000H Upper byte
D0000-C
D0000-D
D0000-E
D0000-F (MSB) (MSB)
4-13
Bit address Bit data Byte data Word data
0 0
1 0
2 1
3 0
34h
4 1
5 1
6 0
7 0
1234h
8 0
9 1
A 0
B 0
12h
C 1
D 0
E 0
F 0
h:Indicated with hexadecimal number.
(4) When addressing indirect, use the following formula.

1) Changing a word address or lower byte address to indirect address.
Indirect address = Hex. Value of address x 2 + indirect address offset
Example 1 : Obtain the indirect address of D1000 or D1000L.

1000 x 2 + 2000 = 4000 (hex.)
Example 2 : Obtain the indirect address of M03W.
3 x 2 + 0300 = 0306 (hex.)
2) Changing an upper byte address to indirect address.

Indirect address = Hex. Value of address x 2 + indirect offset + 1
Example 1 : Obtain the indirect address of N1ffH.

1FF x 2 + 0C00 + 1 = FFF (hex.)
Example 2 : Obtain the indirect address of X 10H.
10 x 2 + 0200 + 1 = 221 (hex.)
(Note) Indirect address must be within the data memory area which exists in the CPU.
PC2/L2 : 000-7FFF, C000-FFF
PC2J-8KW : 0000-3FFF
PC2J-16KW : 0000-7FFF
3) Indirect addressing examples

Use the indirect addressing method when indirectly designating the address specified in the
operand used in function instructions such as MOVF (FUN 74).
[Example]
With the MOVF instruction, the transfer destination address (D1) specified in the second address
is indirectly designated.
For example, in the case of D1 = (hexadecimal), the transfer destination is the indirect 0306
(hexadecimal). As shown in [Example 2] in 1 ), the transfer destination is “M03W”.
(Note) Indirect address are assigned in units of bytes. Therefore, with function instruction which
handle data in units of 16 bits (words) and 32 bits, make sure the address is an even number
(lowest bit is 0).
As well as the direct addressing method, designation that starts with an upper byte is not
allowed. (Refer to (3).)
4-14
(5) The address cannot be shared between the identifiers X and Y or T and C.
1) X, Y area
Example
IN-12 OUT-18 OUT-18 IN-12
CPU
(Input) (Output) (Output) (Input)
X000 Y010 Y020 X030
I/O address
~
~
X00F Y01F Y02F X03F
When X000 exists, Y000 cannot.
2) T, C area
A total of 512 points (000 to 1FF) can be used between T and C. However, the address cannot
be shared by timer and counter.
Example
When T000 is used for the timer, C000 cannot be used.

When C001 used for the counter, T001 cannot be used.
4.2.2. In case of PC3J series

4.2.2.1. Data memory map
By presetting CPU operation mode, the PC3J series can select program capacity and data capacity
as necessary from the combinations listed below. Data area separate mode, data area single mode
and PC2 compatible mode are respectively available as the CPU operation modes.
Data area separate mode: The data area in each program is independent from others.
Data area single mode: The data area in each program is common to other program.
PC2 compatible mode: Use of the peripheral devices for PC2 Series is allowed.
But the number of programs is limited to one 32K words (one program).
Use of the functions extended in PC3J is not allowed.
4-15
Program capacity and data capacity under data area separate mode
Timer/
Program Keep- Link Rise/fall Data Link File Buffer
*1 Internal relay counter
CPU relay relay detection register register register register
Data M0-7FF T,C0-1FF
operation I/O K0-2FF L0-7FF P0-1FF *2 R0-7FF
mode area EM0-1FFF ET,C0-
Capacity
No. EK0-FFF EL0-1FFF EP0-FFF
K words GM0-FFFF 7FF W/16bit
Points Points Points Points W/16bit W/16bit W/16bit
Points
16 1 2048 768 512 2048 512 4K 2K - -
16 2 Basic 1024 2048 768 512 2048 512 4K 2K - -
Data area
16 3 2048 768 512 2048 512 4K 2K - -
separate 1
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 14336 6400 3584 14336 5632 12K 6K - -
32 1 2048 768 512 2048 512 12K 2K - -
- 2 Basic 1024 - - - - - - - - -
Data area
16 3 2048 768 512 2048 512 4K 2K - -
separate 2
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 12288 5632 3072 12288 5120 16K 4K - -
16 1 2048 768 512 2048 512 4K 2K - -
32 2 Basic 1024 2048 768 512 2048 512 12K 2K - -
Data area
- 3 - - - - - - - - -
separate 3
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 12288 5632 3072 12288 5120 16K 4K - -
16 1 2048 768 512 2048 512 4K 2K - -
16 2 Basic 1024 2048 768 512 2048 512 12K 2K - -
Data area
- 3 - - - - - - - - -
separate 4
Common Extended (2048) 8192 4096 2048 8192 4096 16K - - -
to program
-1,-2 -3 Total 1024 12288 5632 3072 12288 5120 32K 4K - -
16 1 2048 768 512 2048 512 12K 2K - -
- 2 Basic 1024 - - - - - - - - -
Data area
16 3 2048 768 512 2048 512 4K 2K - -
separate 5
to program
-1,-2 -3 Total 1024 12288 5632 3072 12288 5120 32K 4K - -
60 1 2048 768 512 2048 512 4K 2K - -
60 2 Basic 2048 2048 768 512 2048 512 4K 2K - -
Data area
PC3JG 60 3 2048 768 512 2048 512 4K 2K - -
mode
Common Extended (67584) 73726 4096 2048 8192 4096 32K - - 128K
to program
-1,-2 -3 Total 1024 73726 6400 3584 14336 5632 44K 6K - 128K
*1 Inputs/outputs are all common to all the programs.

Basic-1024points(X,Y0-3FF), Basic-2048 points(X,Y0-7FF)
Extended-2048points(EX,EY0-7FF), Extended-67584 points(EX,EY0-7FF/GX,GY0-FFFF)
*2 Register address: Basic-4K (D0-FFF), Extended-32K (U0-7FFF)
4-16
Program capacity and data capacity under data area single mode
*2 Timer/
Program Keep- Link Rise/fall Data Link File Buffer
*1 Internal relay counter
CPU I/O relay relay detection register register register register
M0-7FF T,C0-1FF
operation Data X,Y0-3FF K0-2FF L0-7FF P0-1FF *3 R0-7FF B0-1FFF
mode EM0-1FFF ET,C0-
Capacity
No. area (EX,Y0-7FF) EK0-FFF EL0-1FFF EP0-FFF
K words Points 7FF W/16bit
Points Points Points Points W/16bit W/16bit W/16bit
Points
16 1 512
16 2 Basic 1024 2048 768 512 2048 512 12K 2K 8K -
Data area
single 16 3 512
mode 1
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 5632 12K 2K 8K -
32 1 512
- 2 Basic 1024 2048 768 512 2048 - 12K 2K 8K -
Data area
single 16 3 512
mode 2
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 5120 12K 2K 8K -
16 1 512
32 2 Basic 1024 2048 768 512 2048 512 12K 2K 8K -
Data area
single - 3 -
mode 3
Common Extended (2048) 8192 4096 2048 8192 4096 - - - -
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 5120 12K 2K 8K -
32 1 512
- 2 Basic 1024 2048 768 512 2048 - 12K 2K 8K -
Data area
single - 3 -
mode 4
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 4608 28K 2K 8K -
16 1 512
- 2 Basic 1024 2048 768 512 2048 - 12K 2K 8K -
Data area
single - 3 -
mode 5
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 4608 44K 2K 8K -
16 1 512
16 2 Basic 1024 2048 768 512 2048 512 12K 2K 8K -
Data area
single - 3 -
mode 6
to program
-1,-2 -3 Total 1024 10240 4864 2560 10240 5120 28K 2K 8K -
*1 Data area is common to all programs.

*2 Extended I/O can not be used as real I/O.
*3 Register address: Basic-4K (D0-FFF), Basic-12K (D0-2FFF), Extended-16K (U0-3FFF)
*4
Program capacity and data capacity under PC2 compatible mode
Keep- Timer/ Link Rise/fall Data Link File Buffer
Program Internal relay
CPU relay counter relay detection register register register register
Data I/O M0-7FF
operation K0-2FF T,C0-1FF L0-7FF P0-1FF D0-2FFF R0-7FF B0-1FFF
mode Capacity
area X,Y0-3FF
K words No. Points Points
Points Points Points Points W/16bit W/16bit W/16bit W/16bit
32 1 1024 2048 768 512 2048 512 12K 2K 8K -

- - Basic - - - - - - - - - -
PC2
interchage - - - - - - - - - - - -
mode
Common Extended - - - - - - - - - -
to program
-1,-2 –3 Total 1024 2048 768 512 2048 512 12K 2K 8K -
*4 The peripheral devices can not be used under PC2 compatible mode.
4-17
4.2.2.2. I/O address table
Data
Numbe
Address area
Identifier
*2 holdin
Bit Word r Indirect g area
No.
Name Points byte at

address address of
address power
words cut off
*1 1 X Input
X,Y000 – 7FF 2048 X,Y00W – 7FW 128 200 – 2FF -
*1 2 Y Output
3 M Internal relay M000 - 7FF 2048 M00W - 7FW 128 300 - 3FF -
Bit address area

4 K keep-relay K000 - 2FF 768 K00W - 2FW 48 40 - 9F
5 V Special relay V000 - 0FF 256 V00W - 0FW 16 A0 - BF -
*1 6 T Timer
T,C000 - 1FF 512 T,C00W - 1FW 32 C0 - FF -
Basic area
*1 7 C Counter
8 L Link relay L000 - 7FF 2048 L00W - 7FW 128 100 - 1FF -
9 P Edge detection P000 - 1FF 512 - - - -
*3 1 2000-7FF
D Data register D0000-0 - 2FFF-F 196608 D0000 - 2FFF 12288
0 F
1000-1FF
Word address area
11 R Link register R0000-0 - 07FF-F 32768 R0000 - 07FF 2048

F
1 Present value
N N0000-0 - 01FF-F 8192 N0000 - 01FF 512 C00 - FFF
2 register
1
S Special register S0000-0 - 03FF-F 16384 S0000 - 03FF 1024 400 - BFF
3
*3 1 B File register B0000-0 - 1FFF-F 131072 B0000 - 1FFF 8192
C000-FFF
4 F
1
EX Extended input
*1 5 EX,EY000 - 7FF 2048 EX,EY00 - 7FW 128 B00 - BFF -
1
EY Extended output
*1 6
1 Extended internal
EM EM000 - 1FFF 8192 EM00W - 1FFW 512 C00 - FFF -
7 relay
Bit address area
1
EK Extended keep-relay EK000 - FFF 4096 EK00W - FFW 256 200 - 3FF
8
1 Extended special
EV EV000 - FFF 4096 EV00W - FFW 256 400 - 5FF -
Extended area 1
9 relay
2
1 ET Extended timer
* 0 ET,EC000 - 7FF 2048 ET,EC00 - 7FW 128 600 - 6FF -
2
EC Extended counter
*1 1
2
EL Extended link relay EL000 - 1FFF 8192 EL00W - 1FFW 512 700 - AFF -
2
2 Extended edge
EP EP000 - FFF 4096 - - - -
3 detection
2 Extended present EN0000-0 - 2000-2FF
EN 32768 EN0000 - 07FF 2048
4 value register 07FF-F F
Word address
2 Extended setup 3000-3FF

area
H H0000-0 - 07FF-F 32768 H0000 - 07FF 2048

5 value register F
2 Extended special ES0000-0 - 1000-1FF
ES register
32768 ES0000 - 07FF 2048
6 07FF-F F
12
* GX Extended input
7 GX,GY0000 - GX,GY000W - C000 -
65536 4096 -
Extended
Bit address area
12 FFFF FFFW DFFF

area 2
* 8 GY Extended output
2 Extended internal GM000W - E000 -

GM GM0000 - FFFF 65536 4096 -
9 relay FFFW FFFF
*3
3
Word address
0000-FFF
U Extended data register U0000-0 - 7FFF-F 524288 U0000 - 7FFF 32768
0 F
*3 3 EB Extended buffer register Not use -

EB00000-1FFF
131072 -
1 F
4-18
*1 Address can not be allocated in overlap to X and Y (EX,EY,GX,GY) and T and C ( ET, EC).
It is incorrect to allocate like (X000/Y000, EX000/EY000, T000/C000, ET000/EC000. )
*2 Used to indirectly designate address using applied command. For indirectly designating address to
extended area and data area of other program, follow the sequence given below.
Use the register of area designated with indirect address as the applied command operand register.
Designate indirect address with offset+ indirect byte address. The offset value is 0000h in the extended
area, 4000h in Program 1, 8000h in Program 2, and C000h in Program 3.
EX. 8 points (1 byte) of EX000 to EX007 in the extended area are transferred to the lower byte of Program
2 D0000.
MOVH (EM00W) -> (P2-D0100)
The register (EM00W) of extended The register P2-D0100) of Program 2 is

area is used to designate the used to designate the area of Program
extended area with indirect 2 with indirect address.
Herein, set in advance indirect byte address 0B00h ( 0000h + 0B00h) in the extended area EX000
- EX007 in the extended internal relays (EM00W( EM000 - EM00F) and indirect byte address A000h
(8000h + 2000h) of D0000 lower byte in the data register P2-D0100 of Program 2 respectively.
*3 An address changes by the mode of CPU of operation.
4-19
(a)Indirect addressing
The address space of relay/register has three kinds of the following.
Basic register of own program (_****)
Own program register area
File register (B****)
Basic register of other programs (P*-_****)
Other programs register area
Enhancing register (E_****,H****)
Enhancing data register area Enhancing data register (U****)
When CPU operation mode is "data separate 1 mode", the execution of the sequence program and the
referred register are shown as follows.
Execution of program
P1 executing P2 executing P3 executing
P1 P2 P3
: M0 P2-M0 : M0 P3-M0 : M0 P1-MO

|-||-----------( )-| |-||-----------( )-| |-||-----------( )-|
: EX0 P3-LO : EX2 P1-L0 : EX1 P2-LO
|-||-----------( )-| |-||-----------( )-| |-||-----------( )-|
: : :
|---------[ U0]-| |---------[ U0]-| |---------[ U0]-|
: : :
Referred register
Own program register Other programs register Enhancing data register
Address area Address area Address area
0000 P1 P2 P3 0000 Enhancing 0000Enhancing data register
3FFF (_****) (_****) (_****) (E_****,H****) (U****)
4000 P1
(P1-_****)
Because of the change of the 8000 P2
execution of the program, the
register of the area changes too. (P2-_****)
C000 P3
FFFF (P3-_****) FFFF
Note) It is an example of one data separate mode 1. Refer since of the following page for the address map
of other modes.
The distinction of three above-mentioned address spaces is never considered at the direct address
specification. When "_****" and the address are specified, the register of the basic area of the program
executing now is accessed. The basic area of another program when specifying, "P*-_****", the
Enhancing arear when specifying, "E_**** and H****", the enhancing data register area is accessed when
specifying, "U****".
4-20
The register which stores indirect addressing should use the register of the area specified by indirect
addressing to distinguish three above-mentioned address spaces at the indirect addressing specification.
Address indirectly specified Register of storage destination
1 Indirect addressing in own area _**** Register of own area (_****)
->
B**** (B****)
2 Indirect addressing in other P*-_**** Register of other areas 1 (P*-_****)
areas 1 E_**** -> (E_****)
H**** (H****)
3 Indirect addressing in other areas G_**** Register of other areas 2 (G_****)
->
2
4 Indirect addressing of enhancing U**** Enhancing data register (U****)
->
data register
1.When you do addressing indirectly compared with the oun area

lTo the register of the operand by which indirect addressing is stored, the register of the own area
is used.
lIndirect addressing is specified in the indirect byte address.
2.When you do addressing indirectly compared with other areas (data area of the extended partition
and another program)
lTo the register of the operand by which indirect addressing is stored, the register of the area
specified by indirect addressing is used.
lIndirect addressing is specified in offset + indirect byte address.
The offset value is 0000h in the extended area, 4000h in Program 1, 8000h in Program 2, and
C000h in Program 3.
EX. 8 points (1 byte) of EX000 to EX007 in the extended area are transferred to the lower byte of
Program 2 D0000.
MOVH (EM00W) ® (P2-D0100)
The register (EM00W) of extended The register P2-D0100) of Program 2 is

area is used to designate the extended used to designate the area of Program 2
area with indirect address. with indirect address.
Herein, set in advance indirect byte address 0B00h ( 0000h+0B00h) in the extended area EX000 -
EX007 in the extended internal relays (EM00W( EM000 - EM00F) and indirect byte address A000h
(8000h +2000h) of D0000 lower byte in the data register P2-D0100 of Program 2 respectively.
3.When you do addressing indirectly compared with other areas 2 (data area of the extended partition)
To the register of the operand by which indirect addressing is stored, the register of G_**** is used.
4.When you do addressing indirectly compared with the enhancing data register area
lTo the register of the operand by which indirect addressing is stored, the enhancing data register is
used.
lIndirect addressing is specified in the indirect byte address.
The offset value of the indirect addressing of the register by the operation mode of CPU is indicated in
the next table.
4-21
Offset value of indirect addressing of registe(data separate mode)
Data separate mode
Separate Separate Separate Separate Separate
1 2 3 4 5
Program area
P1 P1 P1 P1 P1 16KW
P2 P2 P2 16KW
P3 P3 P3 16KW
Data area address
0000 0000 0000 0000 0000

Own program area P1 P2 P3 P1 P3 P1 P2 P1 P2 P1 P3 16KB
3FFF 3FFF 3FFF 3FFF 3FFF
32KB
7FFF 7FFF 7FFF 7FFF
address
0000 0000 0000 0000 0000

Other program areas Enhancing Enhancing Enhancing Enhancing Enhancing
4000 4000 4000 4000 4000

P1 P1 P1 P1 P1
64KB
8000 8000 8000

P2 P2 P2
C000 C000 C000

P3 P3 P3
FFFF FFFF FFFF FFFF FFFF
address
Enhancing data 0000 Enhancing 0000 Enhancing

data data
register area register register 32KB
7FFF 7FFF
4-22
Offset value of indirect addressing of registe(data separate mode)
Data separate mode
PC3JG
Program area
P1 60KW
P2 60KW
P3 60KW
Data area
0000
Own program area P1 P2 P3 16KB
3FFF
0000
Other program areas Enhancing
4000
P1
64KB
8000
P2
C000
P3
FFFF
C000 GX/Y
Other program areas2 16KB
FFFF GM
Enhancing data 0000 Enhancing

data
register area register 32KB
7FFF
4-23
Offset value of indirect addressing of registe(data Single mode and PC2 compatible mode)
Data single mode
Single1 Single2 Single3 Single4 Single5 Single6
/ PC2
Program area compatible
P1 P1 P1 P1 P1 P1 16KW
P2 P2 P2 16KW
P3 P3 16KW
Data area address
0000 P1,P2,P3 0000 P1,P2,P3 0000 P1,P2,P3 0000 P1,P2,P3 0000 P1,P2,P3 0000 P1,P2,P3
Own program area
common common common common common common
32KB
7FFF 7FFF 7FFF 7FFF 7FFF 7FFF
C000 File C000 File C000 File C000 File C000 File C000 File
64KB
FFFF register FFFF register FFFF register FFFF register FFFF register FFFF register
address
0000 0000 0000 0000 Enhancing 0000 0000

Other program areas Enhancing Enhancing Enhancing Enhancing Enhancing 16KB
3FFF 3FFF 3FFF 3FFF *1 3FFF 3FFF
address
Enhancing data 0000 Enhancing 0000 Enhancing 0000 Enhancing

data data data
register register register
register area 32KB
7FFF *1 7FFF
64KB
FFFF
*1) There is no area of "Enhance" and "Enhancing data register" in PC2 compatible mode.
4-24
(b) Method of expressing byte address
Where address is expressed with byte address, word address is followed by H, L, being then
expressed with upper byte or lower byte within word data . The addresses in the pit address area
are followed by W for word address, but they are followed by H, L for byte address.
Addresses in the word address area can be used as bit address by adding bit to right end of
word address.
(EX.)
Bit address Word address Byte address
X000 (LSB) (LSB)
X001
X002
X003
X00L Lower byte
X004
X005
Bit X006
address X007 (MSB)
X00W
area X008 (LSB)
(Example) X009
X00A
X00B
X00H Upper byte
X00C
X00D
X00E
X00F (MSB) (MSB)
D0000-0 (LSB) (LSB)
D0000-1
D0000-2
D0000-3
D0000L Lower byte
D0000-4
D0000-5
Word D0000-6
address D0000-7 (MSB)
D0000
area D0000-8 (LSB)
(Example) D0000-9
D0000-A
D0000-B
D000H Upper byte
D0000-C
D0000-D
D0000-E
D0000-F (MSB) (MSB)
Bit address Bit data Byte data Word data
0 0
1 0
2 1
3 0
34h
4 1
5 1
6 0
7 0
1234h
8 0
9 1
A 0
B 0
12h
C 1
D 0
E 0
F 0
h : Indicated with hexadecimal number.

4-25
5. INSTRUCTION WORDS
5.1. Basic instructions
Processing time ms
Step
No. Symbol Language number Function
PC2/L2 PC2J *1 PC2JS/JR PC3J
Computing start
1 STR 1(2) 0.25 0.75 1.5 0.08~0.28
(normally ON)
Computing start
2 STR NOT 1(2) 0.25 0.75 1.5 0.08~0.28
(normally OFF)
Series connection
3 AND 1(2) 0.25 0.75 1.5 0.08~0.28
(normally ON)
AND NOT Series connection
4 1(2) 0.25 0.75 1.5 0.08~0.28
(normally OFF)
Parallel connection
5 OR 1(2) 0.25 0.75 1.5 0.08~0.28
(normally ON)
Parallel connection
6 OR NOT 1(2) 0.25 0.75 1.5 0.08~0.28
(normally OFF)
Logic block series
7 AND STR 1 0.25 0.5 1.0 0.08
connection
Logic block parallel
8 OR STR 1 0.25 0.5 1.0 0.08
connection
9 OUT 1(2) Coil output 0.5 1.0 2.0 0.12~0.4
10 SET 1(2) Keep-relay setting 0.5 1.0 2.0 0.32~0.4
11 RST 1(2) Keep-relay resetting 0.5 1.0 2.0 0.32~0.4
12 PTS 1(2) Rise differentiation 0.5 1.0 2.0 0.32~0.4
13 NTS 1(2) Fall differentiation 0.5 1.0 2.0 0.32~0.4
14 FPS 1 Multi-coil branching start 0.25 0.5 1.0 0.08
15 FRD 1 Multi-coil branching 0.25 0.5 1.0 0.08
16 FPP 1 Multi-coil branching end 0.25 0.5 1.0 0.08
17 FST 1 Unconditional output 0.25 0.5 1.0 0.08
18 NOT 1 Condition reversing 0.25 0.5 1.0 0.08
19 NOP 1 Non-processing 0.25 0.5 1.0 0.08
The parenthesized step number is subject to designation of the data in other program area or an
extended area for PC3J series.
*1 : PC2J series except PC2JS/JR
5-1
5.1.1. Extension on the PC3J series
(1) Extended relays
The sequence programs are expressed as ever. "E" representing an extended area is
prefixed to the head of an identifier.
Extended relays are common to each program.
Data
Identifier hold
Name Bit address Points area at
power
cut-off
EX Extended input
EX,EY000 ~ 7FF 2048 -
EY Extended output
Extended internal
EM EM0000 ~ 1FFF 8192 -
relay
EK Extended keep-relay EK000 ~ FFF 4096 O
ET Extended timer
ET,EC000 ~ 7FF 128 -
EC Extended counter
EL Extended link relay EL000 ~ 1FFF 8192 -
Extended special
EV EV000 ~ FFF 4096 -
relay
PC3JG GX Extended input GX,GY0000 ~
65536 -
PC3JG GY Extended output FFFF
Extended internal
PC3JG GM GM0000 ~ FFFF 65536 -
relay
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
P2-M100 M100 M100 Y200 M100

=H P3-D0000L=12h
Sequence EM0000
X000 EM0000 Y200 X000 P2-M110
program
·····
·····
·····
END END END

PEND PEND PEND
I/O area X000

Y200
M100 M100 M100
Basic
M110
area data
D0000
Extended
EM0000
area data
5-2
(2) Extended edge detection
4096 extended edge detection command points are added to the PC3J Series. The
sequence programs are expressed as ever. "E" representing an extended area is
prefixed to the head of an identifier.
Extended edge detection command is common to each program.
Overlap use of same address is not allowed. For example, where EP000 is used in
program-1, it can not be used in program-2 and -3. Of course, overlap use of EP000 in
program-1 is not allowed.
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
M000 P000 M100 M000 P000 M100 Y200 P000 M100
Sequence L000
X000 EP000 M200 EP500 Y200 X000 EPA00 P2-M110
program
·····
·····
·····
END END END
PEND PEND PEND
Edge
P000 ~ 1FF P000 ~ 1FF P000 ~ 1FF
detection
Extended
edge EP000 ~ FFF
detection
5-3
(3) Designation of Register Bit
Designation of register bit by basic command is added to the PC3J Series. Register bit
addresses can be used for contact commands and output commands (OUT, SET, RST).
The sequence programs are expressed as ever. Register address is followed by bit
position.
Data
Identifier hold
area
Name Bit address Points at
power
cut-off
D Data register D0000-0 ~ 2FFF-F 196608 O
R Link register R0000-0 ~ 07FF-F 32768 O
N Present value register N0000-0 ~ 01FF-F 8192 O
S Special register S0000-0 ~ 03FF-F 16384 O
B File register B0000-0 ~ 1FFF-F 131072 O
U Extended data register U0000-0 ~ 7FFF-F 524288 O
Extended present value
EN EN0000-0 ~ 07FF-F 32768 O
register
Extended setup value
H H0000-0 ~ 07FF-F 32768 O
register
Extended special
ES ES0000-0 ~ 07FF-F 32768 O
register
D000 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
F E D C B A 9 8 7 6 5 4 3 2 1 0
0
D0000-F D0000-E D0000-D D0000-1 D0000-0
(4) SET/RST commands

Usable devices are added. Usable device for SET/RST is only K device (keep relay) in
PC2 Series. The following devices is usable in PC3J Series.
division device
relay M,K,V,L
basic area
register D,R,N,S,B
relay EM,EK,EV,EL,GM
extended area
register U,EN,H,ES
M000 EL0000 D0000-2
The areas other than K(keep relay) can be used in PC3J.
5-4
(5) Designation of inter-program relays
The PC3J Series can execute two or more programs , that is, three different sequence
programs maximum. Any program data can be mutually utilized among these programs
without special setting. Sequence program is expressed as ever.
When the CPU operation mode is "Data area division mode", inter-program data can be
mutually utilized each other by adding Program No. to the address head.
However, inter-program relays can not be designated under "Data area single mode"
and "PC2 interchange mode" because the data area in each program is common to
other programs under these modes.
Data area division mode : Basic area data are independent every each program.
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
P2-M100 M100 M100 Y200 M100
=H P3-D0000L=12h
Sequence EM0000
X000 P3-M100 Y200 P1-M100 P2-M110
program
·····
·····
·····
END END END
PEND PEND PEND
I/O area X000

Y200
M100 M100 M100
Basic M110
area data D0000
Extended EM0000
area data
Data area single mode: The data area in each program are common to other programs.
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
M100 M100 M200 Y200 M300

=H D0000L=12h
Sequence
X000 EM0000 Y200 M310
program EM000 X000
·····
·····
·····
END END END

PEND PEND PEND
I/O area X000

Y200
M100
Basic
area data D0000
Extended EM0000
area data
5-5
1. STR, STR NOT
(1) Usable devices
X Y M K V T C L P D R N S B Constant
PC3 / PC2
OP1 O O O O O O O O
PC3 EX EY EM EK EV ET EC EL EP U H EN ES GX GY GM EB
extended OP1 O O O O O O O O O O O
(2) Number of steps 1(2)
(3) Symbol
STR
STR NOT
(4) Function
STR is the instruction to start operation at normally ON and STR NOT at normally OFF, each
storing ON/OFF information of the designated device in the accumulator as the operation result.
(5) Example
5-6
2. AND, AND NOT
(1) Usable devices
PC3 / PC2
OP1 O O O O O O O O
(3) Symbol
AND
AND NOT
(4) Function
AND is the instruction to make serial connection at normally ON and AND NOT instruction at
normally OFF. AND operation(logical product) is carried out between ON/OFF information of
the specified device and the operation result stored in the accumulator. The logical product is
stored into the accumulator, replacing the current content.
(5) Example of program
5-7
3. OR, OR NOT
(1) Usable devices
PC3 / PC2
OP1 O O O O O O O O
(3) Symbol
OR
OR NOT
(4) Function
OR is the instruction to make parallel connection at normally ON and OR NOT instruction at
normally OFF. OR operation(logical sum) is carried out between ON/OFF information of the
specified device and the operation result stored in the accumulator. The logical sum is stored in
the accumulator, replacing the current content.
5-8
4. AND STR
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(2) Number of steps 1
(3) Symbol
(4) Function
Carries out AND operation between two logical blocks and makes the logical product as the
new operation result.
(6) Notes
Available instructions are up to 24 when using AND STR consecutively. Use of more than 24
instructions will have unexpected result.
5-9
5. OR STR
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(3) Symbol
(4) Function
Carries out OR operation between two logical blocks and makes the logical sum as the new
operation result.
(6) Notes
Available instructions are up to 24 when using OR STR consecutively. Use of more than 24
instructions will have unexpected result.
5-10
6. OUT
(1) Usable devices
PC3 / PC2
OP1 O O O O O
extended OP1 O O O O O O O
(3) Symbol
(4) Function
Outputs the operation result stored in the accumulator to the specified device.
5-11
7. SET
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1 O
(3) Symbol
(4) Function
Turns on specified keep relay if the operation result before SET instruction is ON("1").
5-12
8. RST
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1 O
(3) Symbol
(4) Function
Turns off the specified keep relay if the operation result before RST instruction is ON("1").
5-13
9. PTS, NTS
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1 O
(3) Symbol
(4) Function
PTS turns on("1")the previous operation result for 1 scan period when the previous result
changes from OFF to ON.
NTS turns on("1")the previous operation result for 1 scan period when the previous result
changes from ON to OFF.
Time chart
5-14
(6) Notes
The address of device "P" available for instructions PTS and NTS is 512 points. Use only one
address for one device and avoid address overlapping.
Refer to the following page restrictions upon use.
Notes on use in a subroutine or interrupt

When used in a subroutine or interrupt, the PTS or NTS instruction may not be detected in
some cases.
Example
As shown in the time chart, if X20 is ON when X10 turns OFF from ON, Y100 does not turn
ON for one scan even when X10 and X20 turn ON next.
If X20 turns OFF when X10 is ON, Y100 functions normally (that is, when X20 functions as
shown by the dotted line, Y100 and P000 function as shown by the dotted line, as well)
Program example
Time chart
Since is not executed during

the period indicated by *, turning OFF
of X20 cannot be detected.
5-15
10. FPS, FRD, FPP
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(3) Symbol
(4) Function
These instructions are used at the point where the circuit is branched into several outputs. FPS
is used at the beginning of the branch to store the current operation result into the stack, FRD is
used after branching to read the current operation result. EPP is used at the end of branching
and returns stack contents to the value when it was before execution of FPS instruction.
5-16
11. FST
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(3) Symbol
(4) Function
Turns on ("1")the operation result.
5-17
12. NOT
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(3) Symbol
(4) Function
Inverts the operation result stored in accumulator (ON to OFF or OFF to ON).
5-18
13. NOP
(1) Usable devices
PC3 / PC2
OP1
extended OP1
(3) Symbol
None
(4) Function
No-operation instruction and has no effect on the operation.
Used to delete an instruction word and the like.
5-19
5.2. Timer and counter instructions
(1) Timer and counter commands
Processing time ms
Classifi Step Content of
cation
Function Mnemonic
number
Symbol (example) computation PC2/L2 PC2J PC3J
T000 10ms timer of 655.35
Direct-
sec at setup value
designated TMRH 4 20 54.1 3.7
TMRH K=655.35
10ms timer
T001 10ms timer on which
Indirect-
D0100 content is set
designated TMRH 4 21 53.8 3.8
TMRH S=D0100 up (as a setup value)
10ms timer
Timer
T002 100ms timer of 6553.5
Direct-
sec at setup value
designated TMR 4 21 53.8 3.7
TMR K=6553.5
100ms timer
T003 100ms timer on which
Indirect-
D0101 content is set
designated TMR 4 21 53.9 3.8
TMR S=D0100 up (as a setup value)
100ms timer
Direct-
T004 10ms integrating timer
designated
T of 123.45 sec at setup
10ms TMRSH 4 28 55.0 3.7
TMRSH K=123.45 value
integrating
R
timer
Indirect-
T005 10ms integrating time
designated
T on which D0102
10ms TMRSH 4 27 55.1 3.8
TMRSH S=D0102 content is set up (as a
integrating
Integr R setup value).
timer
ating
Direct-
timer T006 100ms integrating
designated
T timer of 1234.5 sec at
100ms TMRS 4 26 55.0 3.7
TMRS K=1234.5 setup value
integrating
R
timer
Indirect-
T007 100ms integrating time
designated
T on which D0103
100ms TMRS 4 26 55.4 3.8
TMRS S=D0103 content is set up (as a
integrating
R setup value).
timer
C008 UP-counter of 65535
Direct-
CK at a setup value
designated CNT 4 22 54.1 3.8
CNT K=65535
UP counter R
UP
counter C009 UP-counter on which
Indirect-
CK D0104 content is set
designated CNT 4 22 54.9 3.9
CNT S=D0104 (as a setup value).
UP counter R
Direct- C00A DOWN-counter of
designated CK 12345 at setup value
CNTD 4 23 56.8 3.6
DOWN CNTD K=12345
counter R
DOWN
DOWN-counter on
counter Indirect- C00B which D0105 content
designated CK
CNTD 4 is set up (as a setup 23 59.3 3.7
DOWN CNTD S=D0105
R value)
counter
C00C UP-DOWN counter of
Direct- CK
65535 at setup value
designated
CNTH 4 U/D CNTH K=65535 28 64.0 3.5
UP-DOWN
counter R
UP-
DOWN C00D UP-DOWN counter on
counter
Indirect- CK which D0106 content
designated is set up (as a setup
CNTH 4 U/D CNTH S=D0106 28 64.3 3.6
UP-DOWN value)
counter R
K,S : Value set to counter or timer
5-20
T : Timer input for integration
R : Clear
CK : Count input
U/D : Input command defining mode-Up count if the condition is met; Down if the
condition is not met.
(Note) The address used for timer cannot be used for the counter. As well, the address used
for the counter cannot be used for the timer.
5-21
(2) Exclusive extended timer and counter commands for PC3J
Processing time ms
Classifi Step Content of
Function Mnemonic Symbol (example)
cation number computation PC2/L2 PC2J PC3J
10ms timer on which
ET000 content of extended
Extended
ETMRH 3 ETMRH S=H0000 setup value register - - 5.6
10ms timer
H0000 is set as a
Time setup value
r 100ms timer on which
ET001 content of extended
Extended
ETMR 3 ETMR S=H0001 setup value register - - 5.6
100ms timer
H0001 is set as a
setup value
10ms integrating timer
Extended ET002 on which the content
10ms T of extended setup
ETMRSH 3 ETMRSH S=H0002 - - 5.6
integrating value register H0002
timer R is set up as a setup
Integr
value
ating
100ms integrating
timer
Extended ET003 timer on which the
100ms T content of extended
ETMRS 3 ETMRS S=H0003 - - 5.6
integrating setup value register
timer R H0003 is set up as a
setup value
UP-counter on which
EC004 the content of
UP Extended CK
counter ECNT 3 ECNT S=H0004 extended setup value - - 5.7
UP-counter
R register H0004 is set
up as a setup value
DOWN-counter on
Extended EC005 which the content of
DOWN CK
counter DOWN- ECNTD 3 ECNTD S=H0005 extended setup value - - 5.5
counter R register H0005 is set
up as a setup value
EC006 UP-DOWN counter on
CK which the content of
UP- Extended
ECNTH S=H0006 extended setup value
DOWN UP-DOWN ECNTH 3 U/D - - 5.4
counter register H0006 is set
counter
up as a setup value
R
Extended setup value register: Fixed setup value register corresponding to coil address
K,S : Value set to counter or timer
T : Timer input for integration
R : Clear
CK : Count input
U/D : Input command defining mode-Up count if the condition is met; Down if the
condition is not met.
(Note) The address used for timer cannot be used for the counter. As well, the address used
for the counter cannot be used for the timer.
5-22
Notes on use of the timer instruction
(1) When “1” is set (0.1S for 100ms timer and 0.01S for 10ms timer),the timer may expire
instantaneously. Timer accuracy is 0 to -1 or –(scan time). Thus, when the increment of the
timer (100ms or 10ms) is smaller than the scan time, the timer may expire instantaneously with
a setting other than “1”.
(2) In a subroutine or interrupt :
When the timer instruction is used in a subroutine or interrupt, it may turn ON immediately in
some cases.
If X20 is OFF when X10 turns ON and the timer instruction is executed when X10 and X20 turns
ON next, the timer adds the time lapsed in the section indicated by the arrow in the time chart
and thus, does not function normally.
If the subroutine is such that it is executed every scan, use of the timer in the subroutine causes
no problem.
Program example
Time chart
Since the instruction is executed during the period indicated by T, the timer
cannot determine when X20 has turned ON. Therefore, the timer assumes that the condition
has been satisfied (X20=ON) immediately after the previous instruction was executed and thus
adds the lapsed time T to the current value. Therefore, when the timer set value is less than
or equal to T, the timer turns ON immediately after the timer instruction is executed.
5-23
(3) Clearing the timer current value of the direct/indirect timer
When the condition is failure, The timer current value of the direct/indirect timer is cleared.
It is not cleared at turning off or reset. So, if the condition is success at restarting, the timer
runs continuously. (If turning off or reset on time-up, the timer is soon time-up at restarting.)
If the timer current value must be cleared at the sequence running, it is cleared by the
following method.
(i) The timer condition is the normally OFF of V06(scan1 is ON).

(Example 1) The timer current value of T000 is cleared at the scan 1.
condition
(ii) The timer current register is set 0000 on the initial sequence.
(Example 2) The timer current register(N001) of T001 is cleared on the initial sequence.
N001
(4) Current value register (N****)

The current value register (N****) corresponding to each timer and counter is stored in the
from of 4-digit hexadecimal value.
Current values can be monitored or changed using function instructions.
[Example 1 ]
Current values of T123 is stored in N0123.

Current Value of C156 is stored in N0156.
[Example 2 ]
Outputting the current value of counter C100 into output Y100-Y10F(Y10W) after converting it
into BCD :
(It is assumed that the current value is 9999 or less and will not overflow after being converted
into BCD.)
For the extended timer and extended counter, the current values are stored to EN registers and the
setting values are stored to H registers.
Coil Setup value Present value
address register register
ET000
ET/EC000 H000 EN000
ETMRH S=H0000
ET/EC001 H001 EN001
ET/EC002 H002 EN002
The content of fixed The content of fixed
...
extended setup value extended present value

register, which corresponds register , which ET/EC7FF H7FF EN7FF
to coil address, is the setup corresponds to coil
5-24
1. TMRH (Direct mode 10ms timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value (0.01-655.35)
(4) Function
The count value of this timer is directly set by a constant in 10ms units. If the operation done
before the issue of TMRH instruction has resulted in ON, the timer counting the time end when
the terminal time is reached, turns on the specified device (T000-T1FF).

Turns on Y012 when 50ms elapsed after turning on of X000.
5-25
2. TMRH (Indirect mode 10ms timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
The contents of register is the setting value
(4) Function
The timer loads the count value(1-65535)stored in the specified register. If the operation before
the issue of TMRH instruction has resulted in ON, the timer counts out time in 10 ms units and
when the terminal count is reached, turns on the specified device (T000-T1FF).

Sets the count value with a binary input data(X100-X00F). Turns on Y011 when the specified
time elapsed after turning on of Y010.
5-26
3. TMR (Direct mode 100ms timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value (0.01-6553.5)
(4) Function
The count value of this timer is directly set by a constant in 100ms units. If the operation done
before the issue of THR instruction has resulted in ON, the timer counting the timer end when
the terminal time is reached, turns on the specified device (T000-T1FF).

Turns on Y012 when 10 sec. elapsed after turning on of X000.
5-27
4. TMR (Indirect mode 100ms timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
(4) Function
The timer loads the count value(1-65535)stored in the specified register. If the operation before
the issue of TMR instruction has resulted in ON, the timer counts out time in 100 ms units and
when the terminal count is reached, turns on the specified device (T000-T1FF).

Sets the count value with the contents of D001. Turns on Y011 when the specified time elapsed
after turning on of Y010.
5-28
5. TMRSH (Direct mode 10ms integrating timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value
(4) Function
The count value of this integrating timer is directly set by a constant in 10ms units. If the
operation done on the T input has resulted in ON, the timer starts counting the time and when
the terminal time is reached, turns on the specified device (T000-T1FF). The contents(current
value)is kept unclear until the next R input becomes ON.

Turns on Y012 when the accumulated ON-time of X000 is 50 ms. Turns off Y012 when X001
is ON.
5-29
6. TMRSH (Indirect mode 10ms integrating timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
(4) Function
The integrating timer loads the count value(1-65535)stored in the specified register. If the
operation done on T input has resulted in ON, the timer counts out time in 10 ms units and
when the terminal count is reached, turns on the specified device (T000-T1FF).The
contents(current value)is kept unclear until the next R input becomes ON.

Turns on Y012 when the accumulated ON-time of X000 is the value specified by the contents of
D1002.Turns off Y012 when X001 is ON.
5-30
7. TMRS (Direct mode 100 ms integrating timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value
(4) Function
The count value of this integrating timer is directly set by a constant in 100 ms units. If the
operation done on the T input has resulted in ON, the timer starts counting the time and when
the terminal time is reached, turns on the specified device (T000-T1FF).The contents(current
value)is kept unclear until the next R input becomes ON.

Turns on Y012 when the accumulated ON-time of X000 is 10 sec.
Turns off Y012 when X001 is ON.
5-31
8. TMRS (Indirect mode 100 ms integrating timer)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
(4) Function
The integrating timer loads the count value(1-65535)stored in the specified register. If the
operation done on T input has resulted in ON, the timer counts out time in 100 ms units and
when the terminal count is reached, turns on the specified device (T000-T1FF).The
contents(current value)is kept unclear until the next R input becomes ON.

Turns on Y012 when the accumulated ON-time of X000 is the value specified by the contents of
D1003.Turns off Y012 when X001 is ON.
5-32
9. CNT (Direct mode up counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value
(4) Function
An up counter whose quantity is directly set with a constant. If the R input is OFF, the counter
increments the current value by 1 upon turning on of the CK input and turns on the specified
device (C000-C1FF)when the terminal count is reached. The counter clears the current value
upon ON of R input, turning off the specified device.

Turns on Y013 on the 5th ON of X000 and turns off Y013 on the ON of X001.
5-33
10. CNT (Indirect mode up counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
(4) Function
The up counter loads the count value(1-65535)stored in the specified register. If the R input is
OFF, the counter increments the current value by 1 upon turning on of the CK input and turns
on the specified device(C000-C1FF)when the terminal count is reached. The counter clears the
current value upon ON of R input, turning off the specified device.

Turns on Y013 when the number of ON of X000 is the set value specified by the contents of
D1004.Turns off Y013 when the X001is ON.
5-34
11. CNTD (Direct mode down counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value
(4) Function
A down counter whose quantity is directly set with a constant.
If the R input is OFF, the counter decrements the current value by 1 upon turning on of the CK
input and turns on the specified device (C000-C1FF) when the terminal count is reached. The
current value equals the set value upon ON of R input and the specified device is turned off.

Turns on Y013 on the 5th ON of X000 and turns off Y013 on the ON of X001.
5-35
12. CNTD (Indirect mode down counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
(4) Function
The down counter loads the count value(1-65535)stored in the specified register. If the R input
is OFF, the counter decrements the current value by 1 upon turning on of the CK input and turns
on the specified device(C000-C1FF)when the terminal count is reached. The counter clears the
current value upon ON of R input, turning off the specified device.

Turns on Y013 when the number of ONs of X000 is the set value specified by the contents of
D1004.Turns off Y013 when the X001 is ON.
5-36
13. CNTH (Direct mode up/down counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O
value
extended Device
Setting
value
(3) Symbol
Set value
(4) Function
An up/down counter whose count quantity is directly set with a constant. If the R input is OFF
and the U/D input is ON, the counter increments the current value by 1 on the ON of CK input. If
R and U/D inputs are OFF, the counter decrements the value by 1 on the ON of CK input. When
the contents reach the set value, the counter turns on the specified device(C000-C1FF).
The current value is forced to match the set value when the R input goes ON, turning off the
specified device.

Turns on Y013 when the number of ON of X000 when X002 is ON equals the number of ON of
X000 when X002 is OFF. Turns off Y013 when X001 is ON.
5-37
Time chart
5-38
14. CNTH (Indirect up/down counter)
(1) Usable devices
PC3 / PC2
Device O
Setting
O O O O O O O
value
extended Device
Setting
O O O O O O O O O O
value
(3) Symbol
The contents of register is

the setting value
(4) Function
The up/down counter loads the count value(1-65535)stored in the specified register. If the R
input is OFF and the U/D input is ON, the counter increments the current value by 1 on the ON
of CK input. If R and U/D inputs are OFF, the counter decrements the value by 1 on the ON of
CK input. When the contents reach the set value, the counter turns on the specified
device(C000-C1FF).The current value is forced to match the set value when the R input goes
ON, turning off the specified device.

Turns on Y013 when the number of ON of X000 when X002 is ON equals the number of ONs of
X000 when X002 is OFF. Turns off Y013 when X001 is ON.
5-39
Time chart
* The initial value of the register D1006 is "3".
5-40
5.
15. ETMRH Extended 10ms Timer
(1) Usable devices

PC3 / PC2
Device
Setting
value
EX EY EM EK EV ET EC EL EP U H EN ES GX GY GM EB
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
This is a 10ms unit timer using the contents (1 ~ 65535) of register (H) as the setup value.
When the calculated results up to ETMRH command are ON, this timer counts the time and
turns ON the designated devices (ET000 ~ ET7FF) when the setup value is reached.
(5) Program
Program to turn ON Y012 10 seconds after X000 turned ON.
5-41
16. ETMR Extended 100ms Timer
(2) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
When the calculated results up to ETMR command are ON, this timer counts the time and
(5) Program
Program to turn ON Y012 10 seconds after X000 turned ON.
5-42
17. ETMRSH Extended 10ms Integrating Timer
(1) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
When the calculated results up to ETMRSH command are ON, this timer counts the time and
The counted value (present value) is not cleared until R input turns ON.
(5) Program (EX.)

Program to turn ON Y012 when the cumulative ON time of X000 has reached the setup
value shown with the content of H005 and to turn OFF Y012 if X001 is ON.
5-43
18. ETMRS Extended 100ms Integrating Timer
(1) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
When the calculated results up to ETMRS command are ON, this timer counts the time and
The counted value (present value) is not cleared until R input turns ON.
(5) Program (EX.)

Program to turn ON Y012 when the cumulative ON time of X000 has reached the setup value
shown with the content of H005 and to turn OFF Y012 if X001 is ON.
5-44
19. ECNT Extended Counter (UP)
(1) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
This is a UP counter using the contents(1 ~ 65535)of the setup value register (H) as its setup
value. This counter adds +1 to the counted value (present value) whenever CK input turns
ON, if R input is OFF, and, when the setup value is reached, turn ON the designated devices
( EC000 ~ EC7FF). When R input turns ON, the present value comes to 0 and the
designated devices turn OFF.
(5) Program (Ex.)

Program to turn ON Y013 when X000 turns ON 5 times and to turn OFF Y013 when X001
turns ON.
5-45
20. ECNTD Extended Counter (Down)
(1) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
This is a DOWN counter using the contents (1 ~ 65535) of the setup value register (H) as its
setup value. This counter deducts -1 from the counted value (present value) whenever CK
input turns ON, if R input is OFF, and, when the counted down value comes to 0, turn ON the
designated devices ( EC000 ~ EC7FF).
When R input turns ON, the present value reaches the same as the setup value and the
designated devices turn OFF.
(5) Program (Ex.)
Program to turn ON Y013 when X000 turns ON 5 times and to turn OFF Y013 when X001
turns ON.
5-46
21. ECNTH Extended Counter (Up-Down)
(1) Usable devices

PC3 / PC2
Device
Setting
value
PC3
Device O
extended Setting
O
value
(3) Symbol
(4) Function
This is a UP-DOWN counter using the contents(1 ~ 65535)of the setup value register (H) as
its setup value. This counter adds +1 to the counted value (present value) whenever CK input
turns ON, if R input is OFF and U/D input is ON, and deducts -1 from the counted value
(present value) whenever CK input turns ON, if R input is OFF and U/D input is OFF. When
the present value and the setup value match one another, the designated devices (EC000 ~
EC7FF) turn ON. Furthermore, when R input turns ON, the present value reaches the same
as the setup value and the designated devices turn OFF.
(5) Program (EX.)

Program to turn ON Y013 when the ON frequency of X000 with X002 kept ON matches the
ON frequency of X000 with X002 kept OFF and to turn OFF Y013 when X001 turns ON.
5-47
5.3. Contact type application instructions
These are applied instructions and function as contact, i. e. they compare the values of two data,
and when the result meets the predetermined condition, turn ON. The instructions are roughly
classified into STR, AND OR, as appropriate to use in the sequence circuit.
(1) STR format
This type of instruction is used at the beginning of an operation as the basic STR instruction is.
The result of the comparison or operation is stored in the accumulator as ON/OFF information.
(2) AND format
Used for serial connection as the basic AND instruction is. The result of the previous
operation and the one obtained from the comparison done by this instruction are ANDed and
the logical product is stored in the accumulator.
(3) OR format
Used for parallel connection as the basic OR instruction is.

The result of the previous operation and the one obtained from the comparison done by this
instruction are ORed and the logical sum is stored in the accumulator.
(Note) The instructions marked with * can not be use by the PC2 of the some versions.
CPU Version
5-48
Contact type applied commands
No. Comman STR AND OR
Classification d word
Symbol Function
STR AND OR PC2 PC2J PC3J PC2 PC2J PC3J PC2 PC2J PC 3J
2digits 640 576 664 =H 33.0 54.2 1.08 18.0 52.8 1.08 18.1 53.8 1.08
Hexa =H
decim 4digits 648 579 672 W=H W=H S H 30.0 54.2 1.08 15.0 53.9 1.08 15.0 54.2 1.08
Constant
D=H
al
8digits *656 *582 *680 D=H The current flows 32.0 66.8 1.92 17.0 56.4 2.08 17.6 49.6 1.92
across the contact if
3digits 641 577 665 =D
=D
33.0 54.0 1.08 18.0 52.9 1.08 18.1 52.8 1.08
S=H, S=K, S 1 =S 2
= Deci 5digits 649 580 673 W=D W=D S K upon comparison of 30.0 54.2 1.08 15.0 53.7 1.08 15.0 54.0 1.08
mal D=D
register to constant
10digits *657 *583 *681 D=D 32.0 66.8 1.92 17.0 56.6 2.08 17.6 49.4 1.92
or register to
8bits 34.0 54.0 1.20 19.0 53.3 1.20 19.1 53.6 1.20
Register
644 587 668 =N register.

=N
16bits 652 581 676 W=N W=N S1 S2 30.0 54.3 1.20 15.0 54.3 1.20 15.0 53.8 1.20
D=N
32bits *660 *584 *684 D=N 33.0 66.2 2.16 18.6 51.8 2.24 19.2 59.8 2.16
2digits 688 585 712 <>H 32.4 54.1 1.16 18.0 53.6 1.16 18.0 53.5 1.16
Hexa <>H
decim 4digits 696 588 720 W<>H W<> S H 29.4 54.3 1.16 15.0 53.7 1.16 15.0 53.9 1.16
Constant
H
al The current flows
8digits *704 *591 *728 D<>H 32.0 66.8 2.08 17.0 59.4 2.08 17.6 45.4 2.08
3digits 689 586 713 <>D <>D S¹H, S¹K, 32.4 53.9 1.16 18.0 53.7 1.16 18.0 53.5 1.16
≠ Deci 5digits 697 589 721 W<>D W<> S K S 1 ¹S 2 upon
29.4 54.3 1.16 15.0 53.8 1.16 15.0 54.1 1.16
mal D comparison of
10digits *705 *592 *729 D<>D register to constant 32.0 66.8 2.08 17.0 59.4 2.08 17.6 45.4 2.08
or register to
8bits 33.5 53.9 1.28 19.0 53.4 1.28 18.9 53.5 1.28
Register
692 587 716 <>N

<>N register.
16bits 700 590 724 W<>N W<> S1 S2 30.0 53.8 1.28 15.0 53.7 1.28 15.0 53.9 1.28
N
32bits *708 *593 *732 D<>N 33.0 66.0 2.32 18.6 54.4 2.32 19.2 48.2 2.32
2digits 736 594 760 >H 33.0 53.5 1.16 18.0 52.9 1.16 18.0 53.4 1.16
Hexa >H
decim 4digits 744 597 768 W>H W>H S H 29.4 54.3 1.16 15.0 53.9 1.16 15.0 53.7 1.16
Constant
al D>H
8digits *752 *600 *776 D>H The current flows 31.4 65.8 2.16 17.0 58.6 2.16 18.4 48.0 2.16
3digits 737 595 761 >D 33.0 53.8 1.16 18.0 52.5 1.16 18.0 53.4 1.16
>D S>H, S> K, S 1 >S 2
> Deci 5digits 745 598 769 W>D W>D S K upon comparison of 30.0 54.9 1.16 15.0 54.3 1.16 15.0 54.2 1.16
mal D>D
Comparison (contact type)
10digits *753 *601 *777 D>D 31.4 65.6 2.16 17.0 58.6 2.16 18.4 48.0 2.16
or register to
8bits 34.0 53.4 1.28 19.0 52.8 1.28 19.0 53.4 1.28
Register
740 596 764 >N register.

>N
16bits 748 599 772 W>N W>N S1 S2 30.0 53.6 1.28 15.0 54.1 1.28 15.0 54.3 1.28
D>N
32bits *756 *602 *780 D>N 33.8 65.2 2.52 18.6 53.2 2.48 20.0 50.2 2.48
2digits 784 603 808 >=H 33.0 53.2 1.08 18.0 52.9 1.08 18.6 52.9 1.08
Hexa >=H
decim 4digits 792 606 816 W>=H W>=H S H 30.0 53.3 1.08 15.0 53.9 1.08 15.6 54.2 1.08
Constant
D>=H
al
8digits *800 *609 *824 D>=H The current flows 31.4 66.4 2.08 17.0 58.6 20.8 17.0 48.4 2.08
3digits 785 604 809 >=D 33.0 52.5 1.08 18.0 52.5 1.08 18.6 53.7 1.08
>=D S³H, S³K, S 1 ³S 2
≥ Deci 5digits 793 607 817 W>=D W>=D S K upon comparison of 30.0 53.2 1.08 15.0 53.6 1.08 15.6 53.9 1.08
mal D>=D
10digits *801 *610 *825 D>=D 31.4 66.4 2.08 17.0 58.6 2.08 17.0 48.4 2.08
or register to
8bits 34.0 53.0 1.20 19.0 53.0 1.20 18.6 53.0 1.20
Register
788 605 812 >=N register.

>=N
16bits 796 608 820 W>=N W>=N S1 S2 29.4 53.6 1.20 15.0 54.1 1.20 15.6 53.8 1.20
D>=N
32bits *804 *611 *828 D>=N 34.4 65.6 2.40 18.6 53.2 2.40 18.6 50.4 2.40
2digits 832 612 856 <H 33.0 53.5 1.16 18.0 53.7 1.16 18.6 53.7 1.16
Hexa <H
decim 4digits 840 615 864 W<H W<H S H 30.0 54.2 1.16 15.0 53.6 1.16 15.6 54.2 1.16
Constant
al D<H
8digits *848 *618 *872 D<H The current flows 32.0 66.6 2.16 17.0 59.0 2.16 18.4 49.0 2.16
3digits 833 613 857 <D 33.0 53.4 1.16 18.0 53.5 1.16 18.6 53.8 1.16
<D S<H, S< K, S 1 <S 2
< Deci 5digits 841 616 865 W<D W<D S K upon comparison of 30.0 54.1 1.16 15.0 54.0 1.16 15.6 53.9 1.16
mal D<D
10digits *849 *619 *873 D<D 32.0 66.6 2.16 17.0 59.0 2.16 18.4 49.0 2.16
or register to
8bits 34.0 55.8 1.28 19.0 43.4 1.28 19.6 41.0 1.28
Register
*836 *614 *860 <N register.

<N
16bits *844 *617 *868 W<N W<N S1 S2 15.0 44.4 1.28 15.0 44.4 1.28 15.6 42.2 1.28
D<N
32bits *852 *620 *876 D<N 33.0 65.4 2.48 18.6 53.4 2.48 20.0 51.0 2.48
2digits 880 621 904 <=H 33.0 53.2 1.08 18.0 53.0 1.08 18.6 53.6 1.08
Hexa <=H
decim 4digits 888 624 912 W<=H W<=H S H 30.0 54.2 1.08 15.0 54.6 1.08 15.6 54.0 1.08
Constant
al D<=H
8digits *896 *627 *920 D<=H The current flows 31.4 65.6 2.08 18.4 58.2 2.08 17.8 48.4 2.08
3digits 881 622 905 <=D 33.0 53.6 1.08 18.0 53.1 1.08 18.6 53.3 1.08
<=D S£H, S£K, S 1 £S 2
≤ Deci 5digits 889 625 913 W<=D W<=D S K upon comparison of 30.0 54.0 1.08 15.0 53.8 1.08 15.6 54.5 1.08
mal D<=D
10digits *897 *628 *921 D<=D 31.4 65.6 2.08 18.4 58.2 2.08 17.8 48.4 2.08
or register to
8bits 34.0 55.2 1.20 19.0 43.6 1.20 19.6 41.6 1.20
Register
*884 *623 *908 <=N register.

<=N
16bits *892 *626 *916 W<=N W<=N S1 S2 30.0 56.8 1.20 15.0 44.6 1.20 15.6 42.0 1.20
D<=N
32bits *900 *629 *924 D<=N 33.8 65.4 2.40 20.0 53.0 2.40 19.4 50.8 2.40
S, D : Register H : Hexadecimal constant K : Decimal constant
5-49
1. =H 2-digit hexadecimal constant comparison (=)
(1) Usable devices
PC3 / PC2 OP1 O O O O O O O O O O O O
OP2 O
PC3
OP1 O O O O O O O O O O O O O O O
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 2-digit hexadecimal constant. If they are equal,
provides ON state.
1) Turns on Y00F if the data in X000-X007 is 23 in BCD number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is FF in hexadecimal number and
X000 is ON.
3) Turns on Y00F if the upper 8bits of the data register D1000 is AA in hexadecimal number or if
X000 is ON.
5-50
2. =D 3-digit decimal constant comparison (=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 3-digit decimal constant. If they are equa1,
provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is 15 in decimal number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is 250 in decimal number and X000
is ON.
3) Turns on Y010 if the upper 8bits of the data register D1000 is 123 in decimal number or if X000
is ON.
5-51
3. =N Byte data comparison (=)
(1) Usable devices
OP2 O O O O O O O O O O O O
PC3
extended OP2 O O O O O O O O O O O O O O O
(3) Symbol
(4) Function
Compares two 8-bit data and provides ON state if they are equal.
1) Turns on Y011 if the upper 8bits of the data register D0001 and the lower 8bits of the data
register D0002 are equal.
2) Turns on Y011 if the lower 8bits of the data register D1000 and the value represented by
X010-X017 are equal and X000 is ON.
3) Turns on Y011 if the lower 8bits of the data register D1000 and the upper 8bits of D1000 are
equal or if X000 is ON.
5-52
4. W=H 4-digit hexadecimal constant comparison (=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with hexadecimal 4-digit constant. If they are equal,
provides ON state.
1) Turns on Y00F if the data in X000-X00F is 1234 in hexadecimal number.
2) Turns on Y00F if the data register D1000 is FFFF in hexadecimal number and X000 is ON.
3) Turns on Y00F if the data register D1000 is AAAA in hexadecimal number or if X000 is ON.
5-53
5. W=D 5-digit decimal constant comparison (=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with decimal 5-digit constant. If they are equal,
provides ON state.
1) Turns on Y123 if the current count of C000(contents of the current value register N000)is 15.
2) Turns on Y123 if the data register D0004 is 1234 in decimal number and X000 is ON.
3) Turns on Y123 if the data register D0004 is 12345 in decima1 number or if X000 is ON.
5-54
6. W=N Word data comparison (=)
(1) Usable devices
PC3
(3) Symbol
(4) Function
1) Turns on Y123 if the current count of C000(contents of the current value register N000)and that
of C001(current value counter N001)are equal.
2) Turns on Y123 if the contents of X010-X01F and D1000are equal and X000 is ON.
3) Turns on Y123 if the contents of the data registers D1000 and D1001 are equal or if X000 is
ON.
5-55
7. D=H 8-digit hexadecimal constant comparison (=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 32-bit data from the register with hexadecimal 8-digit constant. If they are equal,
provides ON state.
1) Turns on Y00F if the data in X000-X01F is 12343678 in hexadecimal number.
2) Turns on Y00F if the data register D1001 and D1000is FFFFFFFF in hexadecimal number and
X000 is ON.
3) Turns on Y00F if the data register D1001 and D1000 is AAAAAAAA in hexadecimal number or if
X000 is ON.
5-56
8. D=D 10-digit decimal constant comparison (=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 32-bit data from the register with decimal l0-digit constant. If they are equal,
provides ON state.

1) Turns on Y123 if the register D000A and D0009 is 1234567890 in decimal number.
2) Turns on Y123 if the data register D000A and D0009 is 4000000000 in decimal number and
X000 is ON.
3) Turns on Y123 if the data register D000A and D0009 is 100000 in decimal number or if X000 is
ON.
5-57
9. D=N 32-bit data comparison (=) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
1) Turns on Y123 if the contents of the data register D000C and D000B, and D000E and D000D
are equal.
2) Turns on Y123 if the contents of X010-X02F and D1001 and D1000 are equal and X000 is ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000, and D1003 and D1002 are
5-58
10. <>H 2-digit hexadecimal constant comparison (<>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 2-digit hexadecimal constant. If they are not
equal, provides ON state.
1) Turns on Y00F if the data in X000-X007 is not 23 in hexadecimal number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is not FF in hexadecimal number
and X000 is ON.
3) Turns on Y00F if the upper 8bits of the data register D1000 is not AA in hexadecimal number or
if X000 is ON.
5-59
11. <>D 3-digit decimal constant comparison (<>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 3-digit decimal constant. If they are not equal,
provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is not 15 in decimal number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is not 250 in decimal number and
X000 is ON.
3) Turns on Y010 if the upper 8bits of the data register D1000 is not 123 in decimal number or if
X000 is ON.
5-60
12. <>N Byte data comparison (<>)
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 8-bit data and provides ON state if they are not equal.
1) Turns on Y011 if the upper 8bits of the data register D0001 and the lower 8bits of the data
register D0002 are not equal.
2) Turns on Y011 if the lower 8bits of the data register D1000 and the value represented by
X010-X017 are not equal and X000 is ON.
3) Turns on Y011 if the lower 8bits of the data register D1000 and the upper 8bits of D1000 are not
5-61
13. W<>H 4-digit hexadecimal constant comparison (<>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digit hexadecimal constant. If they are not
1) Turns on Y00F if the data in X000-X00F is not 1234 in BCD number.
2) Turns on Y00F if the data register D1000 is not FFFF in hexadecimal number and X000 is ON.
3) Turns on Y00F if the data register D1000 is not AAAA in hexadecimal number or if X000 is ON.
5-62
14. W<>D 5-digit decimal constant comparison (<>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 5-digit decima1 constant. If they are not equal,
provides ON state.
1) Turns on Y123 if the current count of C000(contents of the current value register N000)is not
15.
2) Turns on Y123 if the data register D0004 is not 1234 in decimal number and X000 is ON.
3) Turns on Y123 if the data register D0004 is not 12345 in decimal number or if X000 is ON.
5-63
15. W<>N Word data comparison (<>)
(1) Usable devices
PC3
(3) Symbol
(4) Function
1) Turns on Y123 if the current count of C000(contents of the current value register N000)and that
of C001(current value counter N001)are not equal.
2) Turns on Y123 if the contents of X010-X01F and D1000 are not equal and X000 is ON.
3) Turns on Y123 if the contents of the data registers D1000 and D1001 are not equal or if X000 is
ON.
5-64
16. D<>H 8-digit hexadecimal constant comparison (<>) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 32-bit data from the register with 8-digit hexadecimal constant. If they are not
1) Turns on Y00F if the data in X000-X01F is not 12345678 in BCD number.
2) Turns on Y00F if the data register D1001 and D1000 is not FFFFFFFF in hexadecimal number
and X000 is ON.
3) Turns on Y00F if the data register D1001 and D1000 is not AAAAAAAA in hexadecimal number
or if X000 is ON.
5-65
17. D<>D 10-digit decimal constant comparison (<>) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 32-bit data from the register with l0-digit decimal constant. If they are not equal,
provides ON state.
1) Turns on Y123 if the register D000A and D0009 is not 1234567890 in decimal number.
2) Turns on Y123 if the data register D000A and D0009 is not 4000000000 in decimal number and
X000 is ON.
3) Turns on Y123 if the data register D000A and D0009 is not 100000 in decimal number or if
X000 is ON.
5-66
18. D<>N 32-bit data comparison (<>) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
1) Turns on Y123 if the contents of the data registers D000C and D000B, and D000E and D000D
are not equal.
2) Turns on Y123 if the contents of X010-X02F, and D1001 and D1000 are not equal and X000 is
ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000 and D1003 and D1002 are
not equal or if X000 is ON.
5-67
19. >H 2-digithexadecimal constant comparison (>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 2-digit hexadecimal constant, and if the register
data is larger, provides ON state.
1) Turns on Y00F if the data in X000-X007 is larger than 23 in BCD number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is larger than 12 in hexadecimal
number and X000 is ON.
3) Turns on Y00F if the upper 8bits of the data register D1000 is larger than AA in hexadecimal
number or if X000 is ON.
5-68
20. >D 3-digit decimal constant comparison (>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares an 8-bit data from the register with 3-digit decimal constant, and if the register data
is larger, provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is larger than 15 in decimal number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is larger than 250 in decimal number
and X000 is ON.
3) Turns on Y010 if the upper 8bits of the data register D1000 is larger than 123 in decimal
5-69
21. >N Byte data comparison (>)
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 8-bit data and if the first 8-bit data is larger than the second, provides ON state.
1) Turns on Y011 if the upper 8bits of the data register D0001 is larger than the lower 8bits of the
data register D0002.
2) Turns on Y011 if the lower 8bits of the data register D1000 is larger than the value represented
by X010-X018 and X000 is ON.
3) Turns on Y011 if the lower 8bits of the data register D1000 is larger than the upper 8bits of
D1000 or if X000 is ON.
5-70
22. W>H 4-digit hexadecimal constant comparison (>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digit hexadecimal constant, and if the register
1) Turns on Y00F if the data in X000-X00F is larger than 1234 in BCD number.
2) Turns on Y00F if the data register D1000 is larger than 5555 in hexadecimal number and X000
is ON.
3) Turns on Y00F if the data register D1000 is larger than AAAA in hexadecimal number or if X000
is ON.
5-71
23. W>D 5-digit decimal constant comparison (>)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 5-digit decimal constant, and if the register data
1) Turns on Y123 if the current count of C000(contents of the current value register N000)is larger
than 15 in decimal number.
2) Turns on Y123 if the data register D0004 is larger than 1234 in decimal number and X000 is
ON.
3) Turns on Y123 if the data register D0004 is larger than 12345 in decimal number or if X000 is
ON.
5-72
24. W>N Word data comparison (>)
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 16-bit data and if the first data is larger than the second, provides ON state.
than that of C001 (current value counter N001).
2) Turns on Y123 if the value represented by X010-X01F is larger than the contents of D1000 and
X000 is ON.
3) Turns on Y123 if the contents of the data register D1000 is larger than that of D1001 or if X000
is ON.
5-73
25. D>H 8-digit hexadecimal constant comparison (>) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X01F is larger than 12345678 in Hex number.
2) Turns on Y00F if the data register D1000 and D1000 is larger than 55555555 in hexadecimal
3) Turns on Y00F if the data register D1001 and D1000 is larger than AAAAAAAA in hexadecimal
5-74
26. D>D 10-digit decimal constant comparison (>) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 32-bit data from the register with 10-digit decima1 constant, and if the register data
1) Turns on Y123 if the register D000A and D0009 is larger than 1234567890 in decimal number.
2) Turns on Y123 if the data register D000A and D0009 larger than 4000000000 in decimal
3) Turns on Y123 if the data register D000A and D0009 is larger than 100000 in decimal number
or if X000 is ON.
5-75
27. D>N 32-bit data comparison (>) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 32-bit data and if the first data is larger than the second, provides ON state.
1) Turns on Y123 if the contents of the data register D000C and D000B is larger than that of the
data register D000E and D000D.
2) Turns on Y123 if the value represented by X010-X02F is larger than the contents of D1001 and
D1000, and X000 is ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000 is larger than that of the
data register D1003 and D1002 or if X000 is ON.
5-76
28. >=H 2-digit hexadecimal constant comparison (>=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
data is larger than or equal to the constant, provides ON state.
1) Turns on Y00F if the data in X000-X007 is larger than or equal to 23 in BCD number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is larger than or equal to 12 in
hexadecimal number and X000 is ON.
3) Turns on Y00F if the upper 8bits of the data register D1000 is larger than or equal to AA in
hexadecimal number or if X000 is ON.
5-77
29. >=D 3-digit decimal constant comparison (>=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
>=D
(4) Function
is larger than or equal to the constant, provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is larger than or equal to 15 in
decimal number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is larger than or equal to 250 in
decimal number and X000 is ON.
3) Turns on Y010 if the upper 8bits of the data register D1000 is larger than or equal to 123 in
decimal number or if X000 is ON.
5-78
30. >=N Byte data comparison (>=)
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 8-bit data and if the first data is larger than or equal to the second, provides ON
state.

1) Turns on Y011 if the upper 8bits of the data register D0001 is larger than or equal to the lower
8bits of the data register D0002.
2) Turns on Y011 if the lower 8bits of the data register D1000 is larger than or equal to the value
represented by X010-X018 and X000 is ON.
3) Turns on Y011 if the 1ower 8bits of the data register D1000 is larger than or equal to the upper
8bits of D1000 or if X000 is ON.
5-79
31. W>=H 4-digit hexadecimal constant comparison (>=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
Compares a 16-bit data from the register with 4-digithexadecimal constant, and if the register
1) Turns on Y00F if the data in X000-X00F is larger than or equal to 1234 in BCD number.
2) Turns on Y00F if the data register D1000 is larger than or equal to 5555 in hexadecimal number
and X000 is ON.
3) Turns on Y00F if the data register D1000 is larger than or equal to AAAA in hexadecimal
5-80
32. W>=D 5-digit decimal constant comparison (>=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
than or equal to 15.
2) Turns on Y123 if the data register D0004 is larger than or equal to 1234 in decimal number and
X000 is ON.
3) Turns on Y123 if the data register D0004 is larger than or equal to 12345 in decimal number or
if X000 is ON.
5-81
33. W>=N Word data comparison (>=)
(1) Usable devices
PC3
(3) Symbol
(4) Function
state.
than or equal to that of C001(current value counter N001).
2) Turns on Y123 if the value represented by X010-X01F is larger than or equal to the contents of
D1000 and X000 is ON.
3) Turns on Y123 if the contents of the data register D100 is larger than or equal to that of D1001
or if X000 is ON.
5-82
34. D>=H 8-digit hexadecimal constant comparison (>=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X01F is larger than or equal to 12345678 in BCD number.
2) Turns on Y00F if the data register D1001 and D1000 is larger than or equal to 55555555 in
3) Turns on Y00F if the data register D1001 and D1000 is larger than or equal to AAAAAAAA in
5-83
35. D>=D 10-digit decimal constant comparison (>=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y123 if the register D000A and D0009 is larger than or equal to 1234567890 in
decimal number.
2) Turns on Y123 if the data register D000A and D0009 is larger than or equal to 4000000000 in
3) Turns on Y123 if the data register D000A and D0009 is larger than or equal to 100000 in
5-84
36. D>=N 32-bit data comparison (>=) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
state.
1) Turns on Y123 if the contents of the data register D000C and D000B is larger than or equal to
that of the data register D000E and D000D.
2) Turns on Y123 if the value represented by X010-X02F is larger than or equal to the contents of
D1001 and D1000, and X000 is ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000 is larger than or equal to
that of the data register D1003 and D1002 or if X000 is ON.
5-85
37. <H 2-digit hexadecimal constant comparison (<)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
data is smaller than the constant, provides ON state.
1) Turns on Y00F if the data in X000-X007 is smaller than 23 in BCD number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is smaller than 12 in hexadecimal
3) Turns on Y00F if the upper 8bits of the data register D100C is smaller than AA in hexadecimal
5-86
38. <D 3-digit decimal constant comparison (<)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
is smaller than the constant, provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is smaller than 15 in decimal
number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is smaller than 250 in decimal
3) Turns on Y010 if the upper 8bits of the data register D100Cis smaller than 123 in decimal
5-87
39. <N Byte data comparison (<) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 8-bit data and if the first data is smaller than the second, provides ON state.
1) Turns on Y011 if the lower 8bits of the data register D0002 is smaller than the upper 8bits of the
data register D0001.
2) Turns on Y011 if the lower 8bits of the data register D1000 is smaller than the value
3) Turns on Y011 if the lower 8bits of the data register D1000 is smaller than the upper 8bits of
5-88
40. W<H 4-digit hexadecimal constant comparison (<)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X00F is smaller than 1234 in BCD number.
2) Turns on Y00F if the data register D1000 is smaller than 5555 in hexadecimal number and
X000 is ON.
3) Turns on Y00F if the data register D1000 is smaller than AAAA in hexadecimal number or if
X000 is ON.
5-89
41. W<D 5-digit decimal constant comparison (<)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
is smaller than the constant, provides ON state.
1) Turns on Y123 if the current count of C000(contents of the current value register N000)is
smaller than 15.
2) Turns on Y123 if the data register D0004 is smaller than 1234 in decimal number and X000 is
ON.
3) Turns on Y123 if the data register D0004 is smaller than 12345 in decimal number or if X000 is
ON.
5-90
42. W<N Word data comparison (<) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
smaller than that of C001 (current value counter N001).
2) Turns on Y123 if the value represented by X010-X01F is smaller than the contents of D1000
and X001 is ON.
3) Turns on Y123 if the contents of the data register D1000 is smaller than that of D1001 or if X001
is ON.
5-91
43. D<H 8-digit hexadecimal constant comparison (<) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X01F is smaller than 12345678 in BCD number.
2) Turns on Y00F if the data register D1001 and D1000 is smaller than 55555555 in hexadecimal
3) Turns on Y00F if the data register D1001 and D1000 is smaller than AAAAAAAA in hexadecimal
5-92
44. D<D 10-digit decimal constant comparison (<) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
is smaller than the constant.
1) Turns on Y123 if the register D000A and D0009 is smaller than 1234567890 in decimal number.
2) Turns on Y123 if the data register D000A and D0009 is smaller than 4000000000 in decimal
3) Turns on Y123 if the data register D000A and D0009 is smaller than 100000 in decimal number
or if X000 is ON.
5-93
45. D<N 32-bit data comparison (<) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
1) Turns on Y123 if the contents of the data register D000C and D000B is smaller than that of the
data register D000E and D000D.
2) Turns on Y123 if the value represented by X010-X02F is smaller than the contents of D1001and
D1000, and X000 is ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000 is smaller than that of the
data register D1003 and D1002 or if X000 is ON.
5-94
46. <=H 2-digit hexadecimal constant comparison (<=)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
data is smaller than or equal to the constant, provides ON state.
1) Turns on Y00F if the data in X000-X007 is smaller than or equal to 23 in BCD number.
2) Turns on Y00F if the lower 8bits of the data register D1000 is smaller than or equal to 55 in
3) Turns on Y00F if the upper 8bits of the data register D100C is smaller than or equal to AA in
5-95
47. <=D 3-digit decimal constant comparison (<=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
is smaller than or equal to the constant, provides ON state.
1) Turns on Y010 if the lower 8bits of the data register D0000 is smaller than or equal to 15 in
decimal number.
2) Turns on Y010 if the lower 8bits of the data register D1000 is smaller than or equal to 250 in
3) Turns on Y010 if the upper 8bits of the data register D1000 is smaller than or equal to 123 in
5-96
48. <=N Byte data comparison (<=) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
Compares two 8-bit data and if the first data is smaller than or equal to the second, provides
ON state.
1) Turns on Y011 if the upper 8bits of the data register D0001 is smaller than or equal to the lower
8bits of the data register D0002.
2) Turns on Y011 if the lower 8bits of the data register D0001 is smaller than or equal to the value
3) Turns on Y011 if the lower 8bits of the data register D1000 is smaller than or equal to the upper
8bits of D1000 or if X000 is ON.
5-97
49. W<=H 4-digit hexadecimal constant comparison (<=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X00F is smaller than or equal to 1234 in BCD number.
2) Turns on Y00F if the data register D1000 is smaller than or equal to 5555 in hexadecimal
3) Turns on Y00F if the data register D1000 is smaller than or equal to AAAA in hexadecimal
5-98
50. W<=D 5-digit decimal constant comparison (<=)
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
smaller than or equal to 15.
2) Turns on Y123 if the data register D0004 is smaller than or equal to 1234 in decimal number
and X000 is ON.
3) Turns on Y123 if the data register D0004 is smaller than or equal to 12345 in decimal number or
if X000 is ON.
5-99
51. W<=N Word data comparison (<=) *
(1) Usable devices
PC3
(3) Symbol
(4) Function
ON state.
smaller than or equal to that of C001(current value counter N001).
2) Turns on Y123 if the value represented by X010-X01F is smaller than or equal to the contents
of D1000 and X001 is ON.
3) Turns on Y123 if the contents of the data register D1000 is smaller than or equal to that of
5-100
52. D<=H 8-digit hexadecimal constant comparison (<=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y00F if the data in X000-X01F is smaller than or equal to 12345678 in BCD number.
2) Turns on Y00F if the data register D1001 and D1000 is smaller than or equal to 55555555 in
3) Turns on Y00F if the data register D1001 and D1000 is smaller than or equal to AAAAAAAA in
5-101
53. D<=D 10-digit decimal constant comparison (<=) *
(1) Usable devices
OP2 O
PC3
extended OP2
(3) Symbol
(4) Function
1) Turns on Y123 if the register D000A and D0009 is smaller than or equal to 1234567890 in
decimal number.
2) Turns on Y123 if the data register D000A and D0009 is smaller than or equal to 4000000000 in
3) Turns on Y123 if the data register D000A and D0009 is smaller than or equal to 100000 in
5-102
54. D<=N 32-bit data comparison (<=) *
(1) Usable devices
PC3
(3) Sumbol
(4) Function
ON state.
1) Turns on Y123 if the contents of the data register D000C and D000B is smaller than or equal to
that of the data register D000E and D000D.
2) Turns on Y123 if the value represented by X010-X02F is smaller than or equal to the contents
of D1001 and D1000, and X000 is ON.
3) Turns on Y123 if the contents of the data register D1001 and D1000 is smaller than or equal to
that of the data register D1003 and D1002 or if X000 is ON.
5-103
5.
5.4. Output type application instructions Note)
Output type application instructions are used to process numeric data and are executed if the previous
operation resulted in ON.
The output type application instructions are classified as follows :
Transfer
Arithmetic operation
Logical operation
Increment/decrement
Search
Parity operation
Data exchange
Comparison
Bit operation
Shift
Rotate
Programmed branch
Master control
Input/output control
Sequential interrupt
Label
Special unit data transfer
Sequential debug
I/O monitor control
Others
Note) The instructions marked with # can be used by the L2 but not by the PC2 of the version
before SCPU-3.01.
CPU Version
5-104
Note1 : Some output type application instructions alter the resulting flag prepared in the special relay
in accordance with the result of operation made by these instructions. The altered flag can
be used as one of the conditions for the next operation. The table below shows the available
resulting flags.
Symbol Name Address

CY Carry flag V56
BO Borrow flag V55
Z Zero flag V54
> Greater-than flag V53
= Equal flag V52
< Less-than flag V51
ER Error flag V50
How to use resulting flag
(1) Application instructions which are always executed
The resulting flags are updated every scan. Therefore, they can be used as contacts until an
application instruction whose output includes these flags is next executed.
5-105
(2) Application instructions executed only when conditions are met
When the application instruction is not executed (when conditions are not met), the resulting flags are
not updated. In such a case, use the flags in the AND operation with these conditions.
(3) Application instructions executed in rise or fall
Note that the flags are only output once. To always use the resulting flags as contacts, they must be
connected to a keep relay.
5-106
(4) Output-type application instructions
Flag Execution time (µs)
Command
Classification No. Symbol Function V56 V55 V54 V53 V52 V51 V50 PC2/L2 PC2J PC3J
word
Not Not Not
(CY) (BO) (Z) (>) (=) (<) (ER) Execution Execution Execution
execution execution execution
2 digits 100 MOV MOV 6.8 1.0 34.5 2.0 0.72 0.32
Hexadecimal constant Hexadecimal constant H (2,4, 8
transfer
4 digits 101 WMOV WMOV
DMOV
H D
digits ) ...transferred to D.
- - - - - - - 6.4 1.0 35.7 2.0 0.72 0.32
8 digits 102 DMOV 8.0 1.25 43.8 2.5 1.12 0.4
2 digits 103 MOVP MOVP 6.8 1.0 34.5 2.0 0.72 0.32
BCD constant H (2, 4, 8 digits)..transferred to
BCD constant transfer 4 digits 1 WMOVP WMOVP
DMOVP
H D
D.
- - - - - - - 6.4 1.0 35.1 2.0 0.72 0.32
8 digits 104 DMOVP 8.0 1.25 43.3 2.5 1.12 0.4
3 digits 105 MOVR MOVR
6.8 1.0 34.7 2.0 0.72 0.32
Decimal constant Decimal constant K ( 3, 5, 10
transfer
5 digits 7 WMOVR WMOVR K D
digits) ...transferred to D.
- - - - - - - 6.4 1.0 35.1 2.0 0.72 0.32
DMOVR
10 digits 106 DMOVR 8.0 1.25 43.6 2.5 1.12 0.4
3 digits 107 MOVQ MOVQ 6.8 1.0 34.2 2.0 0.72 0.32
Octal constant Q (3, 6, 11 digits) ..transferred
Octal constant transfer 6 digits 8 WMOVQ WMOVQ
DMOVQ
Q D
to D.
- - - - - - - 6.4 1.0 35.4 2.0 0.72 0.32
11 digits 108 DMOVQ 8.0 1.25 42.6 2.5 1.12 0.4
Hexadecimal constant 2 digits 62 MOVT MOVT Hexadecimal constant H (2, 4 9.8 1.25 36.2 2.5 1.04 0.4
WMOT H D1 D2
digits) ..transferred to D1, D2.
- - - - - - -
transfer to two destinations 4 digits 110 WMOVT 9.0 1.25 37.2 2.5 1.04 0.4
8bits 90 MOVE MOVE
6.8 1.0 34.8 2.0 0.92 0.32
Direct transfer 16bits 0 WMOVE WMOVE S D S data transferred to D - - - - - - - 6.4 1.0 35.5 2.0 0.92 0.32
DMOVE
32bits 111 DMOVE 8.2 1.0 45.2 2.0 1.52 0.32
Register to register transfer
8bits 74 MOVF MOVF

22.8 1.0 46.8 2.0 4.16 0.32
Indirect transfer S data is transferred to register which of
- - - - - - ↑ 15.6 1.0 47.4 2.0 4.16 0.32
5-107
16bits 112 WMOVF WMOVF S D

address is D content.
(1) DMOVF
32bits *113 DMOVF 21.2 1.0 54.2 2.0 4.76 0.32
Transfer
8bits 75 MOVG MOVG

23.2 1.0 45.8 2.0 4.16 0.32
Indirect transfer Data in register which of address is S content
(2)
16bits 114 WMOVG WMOVG S D
is transferred to D.
- - - - - - ↑ 15.6 1.0 46.6 2.0 4.16 0.32
DMOVG
32bits *115 DMOVG 21.0 1.0 54.4 2.0 4.76 0.32
8bits 76 MOVH MOVH Data in register which of address is S content 26.8 1.0 50.5 2.0 5.76 0.32
Indirect transfer
(3)
16bits 116 WMOVH WMOVH S D is transferred to register which of address is D - - - - - - ↑ 19.6 1.0 51.6 2.0 5.76 0.32
DMOVH content.
32bits *117 DMOVH 26.8 1.0 57.0 2.0 6.36 0.32
Direct transfer Data in the area which of head address is S is
(1)
8bits 70 BMOV1 BMOV S D1 D2
transferred to the area from D1 up to D2.
- - - - - - ↑ 38.8+7.3n 1.25 67.7+3.3n 2.5 8.46+0.92n 0.4
Direct transfer 8bits *118 BMOV2 Data of the number indicated with K which of 43.1+7.3n 1.25 73.2+1.87n 2.5 7.80+0.92n 0.4
BMOV2 head address is S are transferred to the area - - - - - -
Block transfer
(2) 16bits *119 WBMOV WBMOV

S D K
which of head address is D. ↑ 40.0+4.0n 1.25 66.5+2.69n 2.5 8.04+0.92n 0.4
8bits 71 BMV1 Data in the area which of head address is S1 is 42.4+7.3n 1.25 70.5+2.5n 2.5 8.88+0.92n 0.4
BMV1 transferred to the area which of head address
Indirect transfer WBMV S1 D S2 - - - - - -
16bits *120 WBMV1 is D content. The content of S2 is the number ↑ 42.6+4.0n 1.25 68.7+2.68n 2.5 8.04+0.92n 0.4
of transferred.
8bits 5 DIV DIV S1 data is transferred to address shown with 28.2 1.25 49.2 2.5 4.88 0.4
Data distribution 16bits 122 WDIV
WDIV
DDIV
S1 D S2 ( address shown with D + offset value shown - - - - - - ↑ 20.6 1.25 51.8 2.5 5.20 0.4
with S2 content).
32bits *123 DDIV 24.2 1.25 59.6 2.5 6.12 0.4
Transfers the data of the area wherein the
8bits 72 BDIV BDIV number of data is S2 content and which of head 48.1+7.3n 1.25 74.6+1.8n 2.5 9.72+0.92n 0.4
S1 D S2
Block distribution WBDIV address is (S1 address + offset value shown - - - - - -
with S1 content) to the locations starting at the ↑
16bits 126 WBDIV address specified by the content of D.
41.6+4.0n 1.25 76.7+2.7n 2.5 9.76+0.92n 0.4
8bits 6 PUP PUP The content of address shown with (S1 address 25.5 1.25 50.2 2.5 4.88 0.4
Data extract 16bits 124 WPUP WPUP S1
DPUP
S2 D + offset value shown with content of S2) is - - - - - - ↑ 20.6 1.25 59.2 2.5 5.20 0.4
transferred to the address shown with D.
32bits *125 DPUP 24.2 1.25 59.6 2.5 6.12 0.4
S,D : register H : hexadecimal constant K : Decimal constant Q : Octal constant C : Character constant
Flag Execution time (ms)
Command PC2/L2 PC2J PC3J
Classification No. word
Symbol Function V56 V55 V54 V53 V52 V51 V50
Not Not Not
8bits 73 BPUP Data in the area which of head address is S1 46.9+7.3n 1.25 79.7+1.9n 2.5 9.72+0.92n 0.4
BPUP content and wherein the number of data is the
S1 D S2
Block extract WBPUP content of S2 is transferred to the area which of - - - - - - ↑ 45.2+4.0n 1.25 79.0+2.6n 2.5 9.76+0.92n 0.4
16bits 127 WBPUP head address is the offset value shown with (D
address + content of D).
4bits 53 SXCH SXCH 13.2 1.0 43.2 2.0 1.80 0.32
8bits 132 XCH XCH For 4bit change, upper 4bit and lower 4bit of D1 10.4 1.0 45.0 2.0 1.36 0.32
D1 D2
Data change WXCH are changed and stored in D2. For 8 and 16bit - - - - - - - 9.6 1.0 46.7 2.0 1.36 0.32
16bits 2 WXCH DXCH change, the contents of D1 and D2 are changed.
32bits *133 DXCH 14.3 1.0 55.8 2.0 2.64 0.32
8bits 134 BXCH BXCH Data in the areas which of respective head 29.1+12.1n 1.25 55.8+10.3n 2.5 7.24+1.36n 0.4
Block change WBXCH
D1 D2 K addresses are D1 and D2 addresses and which - - - - - - ↑ 28.6+7.8n 1.25 57.2+12.2n 2.5 8.48+1.36n 0.4
16bits 135 WBXCH are shown with constant K are changed.
Character addresses C1,C2 (JIS code address)
JIS C1 C2 D
JIS Code store 109 JIS are stored in area of 4byte portion from D - - - - - - ↑ 21.7 1.25 58.4 2.5 4.80 0.4
address.
Hexadecimal 2-digit constant H is stored in the
Data fill 1 8bits 77 FIL1 FIL1 H D1 D2 area from address shown with D1 up to address - - - - - - ↑ 25.8+5.3n 1.25 55.8+1.0n 2.5 5.20+0.64n 0.4
shown with D2.
Transfer
8bits *128 FIL2 FIL2

H S K H is transferred to an area wherein head 24.2+5.3n 1.25 45.2+1.01n 2.5 5.44+0.64n 0.4
Data fill 2 WFIL address is S and the number of data is K. - - - - - - ↑ 21.5+3.6n 1.25 46.0+1.40n 2.5 5.84+0.62n 0.4
16bits *129 WFIL
The content of S is stored in an area wherein
Indirect data fill 1 8bits 78 FILI1 FILI1 S D1 D2 the head address is D1 content and the number - - - - - - ↑ 31.4+5.3n 1.25 54.6+1.0n 2.5 6.28+0.64n 0.4
of data is the content of D2.
5-108
8bits *130 FILI2 FILI2

S1 D S2
The content of S1 is stored in an area wherein 31.7+5.3n 1.25 55.4+0.87n 2.5 5.80+0.64n 0.4
Indirect data fill 2 WFILI the head address is the content of D and the - - - - - - ↑ 24.2+3.6n 1.25 58.7+1.24n 2.5 6.20+0.64n 0.4
16bits *131 WFILI number of data is the content of S2.
8bits 20 CMOV CMOV Data portion from S address is transferred to 40.8+11.9n 1.25 82.6+3.4n 2.5 8.68+1.76n 0.4
Clear check transfer WCMOV
S D K the data area from D, if data of K portion from D ↑ - - - - - ↑ 41.8+8.0n 1.25 84.0+5.0n 2.5 8.68+1.76n 0.4
16bits 166 WCMOV address are all 0.
8bits 21 CLR CLR
If data of K portion commencing from S address 40.5+12.2n 1.25 76.6+2.8n 2.5 7.80+1.76n 0.4
S D K and data of K portion commencing from S
Matched data clear WCLR
address match one another, the data of K ↑ - - - - - ↑ 41.7+9.2n 1.25 81.5+4.1n 2.5 8.44+1.76n 0.4
16bits 167 WCLR
portion commencing from D is cleared.
REF S D K External input data of K byte portion is
External I/O transfer !#283 REF transferred to an area which of head address is - - - - - - ↑ 146+4.25n 1.25 117.7+26.8n 2.5 13.92+2.16n 0.4
D, from S address.
Data of K byte portion is transferred to external
REFO S D K
External output transfer !#284 REFO output which of head address is D , from S - - - - - - ↑ 156+4.25n 1.25 133.0+24.5n 2.5 12.28+1.88n 0.4
address.
Classification No. Command
PC2/L2 PC2J PC3J
word Not Not Not
Register 8bits %&144 MOVJ MOVJ 21.6 1.0 4.52 0.32
↓ The content of S is transferred to File Register
16bits %&145 WMOVJ WMOVJ S D - - - - - - ↑ 16.0 1.0 4.52 0.32
Transfer
File DMOVJ D.
File register register 32bits %&146 DMOVJ 21.2 1.0 5.12 0.32
transfer File 8bits %&147 MOVK MOVK 15.3 1.0 0.92 0.32
register The content of File Register S is transferred to
↓ 16bits %&148 WMOVK WMOVK
DMOVK
S D
D. - - - - - - - 11.6 1.0 0.92 0.32
Register 32bits %&149 DMOVK 14.4 1.0 1.52 0.32
8bits 168 + + The respective contents of S1 and S2 are added 30.2 1.25 54.4 2.5 2.52 0.4
Binary 16bits 92 W+ W+ S1 S2 D and the result is stored in D. Data are all ↑ - ↑ - - - - 23.8 1.25 56.0 2.5 2.52 0.4
D+
handled as binary number.
32bits 169 D+ 29.6 1.25 70.8 2.5 4.60 0.4
Add
2digits 177 +P +P The respective contents of S1 and S2 are 63.5 1.25 68.6 2.5 7.92 0.4
BCD 4digits 10 W+P W+P
D+P
S1 S2 D added and the result is stored in D. The data ↑ - ↑ - - - ↑ 95.2 1.25 126.5 2.5 22~25 0.4
are all handled as BCD.
8digits 178 D+P 201~464 1.25 161.0 2.5 55~59 0.4
8bits 170 - - The content of S2 from that of S1 and the result 28.2 1.25 48.0 2.5 3.32 0.4
Binary 16bits 93 W- W-
D-
S1 S2 D is stored in D. The data are all handled as - ↑ ↑ - - - - 22.6 1.25 49.2 2.5 3.32 0.4
binary number.
32bits 171 D- 30.0 1.25 68.0 2.5 5.16 0.4
Deduct
2digits 179 -P -P The content of S2 is deducted from that of S1 61.7 1.25 68.6 2.5 8.36 0.4
BCD 4digits 11 W-P W-P
D-P
S1 S2 D and the result is stored in D. The data are all - ↑ ↑ - - - ↑ 92.0 1.25 125.8 2.5 21~23 0.4
handled as BCD.
8digits 180 D-P 200~463 1.25 157.8 2.5 56~67 0.4
8bits 172 * * 14.6 1.25 41.4 2.5 1.36 0.4
5-109
The content of S1 is multiplied by the content of

Binary 16bits 94 W* W* S1 S2 D S2. The result is stored in D. The data are - - - - - - - 12.6 1.25 47.8 2.5 4.72 0.4
D*
all handled as binary number.
32bits 173 D* 24.6 1.25 105.6 2.5 23.76 0.4
Arithmetic calculation
Multiply
2digits 181 *P *P The content of S1 is multiplied by the content of 58.0 1.25 92.2 2.5 14.80 0.4
BCD 4digits 182 W*P W*P S1 S2 D S2. The result is stored in D. The data are - - - - - - ↑ 103~359 1.25 177.0 2.5 39~50 0.4
D*P
all handled as BCD.
8digits 183 D*P 250~1034 1.25 1846.0 2.5 160~180 0.4
8bits #174 / / The content of S1 is divided by that of S2. The
27.2 1.25 54.4 2.5 16~19 0.4
16bits 95 W/B W/B S1 S2 D quotient is stored in D and the remainder 24.0 1.25 57.4 2.5 28~30 0.4
Binary W/ - - - - - - ↑
16bits #175 W/ D/
stored in D+1. The data are all handled as 19.2 1.25 58.2 2.5 28~30 0.4
binary number.
Divide 32bits #176 D/ 554.0 1.25 742.0 2.5 76~83 0.4
2digits 184 /P /P The content of S1 is divided by that of S2. The 65.6 1.25 84.8 2.5 21.32 0.4
quotient is stored in D and the remainder
BCD 4digits 185 W/P W/P
D/P
S1 S2 D
stored in D+1. The data are all handled as - - - - - - ↑ 104.0 1.25 170.5 2.5 54~57 0.4
8digits 186 D/P BCD. 694~1038 1.25 573~1762 2.5 150~164 0.4
8bits 195 INC INC After +1 to the content of D, it is compared with 34.4 1.0 51.6 2.0 3.56 0.32
Binary 16bits 63 WINC WINC
DINC
S D the content of S1. The data are handled as ↑ - ↑ - ↑ - - 29.4 1.0 51.8 2.0 3.56 0.32
binary number.
32bits 196 DINC 39.4 1.0 61.6 2.0 5.08 0.32
Increment
2digits 199 INCP INCP After +1 to the content of D, it is compared with 61.0 1.0 68.6 2.0 8.16 0.32
BCD 4digits 200 WINCP WINCP
DINCP
S D the content of S1. The data are handled as ↑ - ↑ - ↑ - ↑ 84.6 1.0 112.8 2.0 22~24 0.32
BCD.
8digits 201 DINCP 212~480 1.0 171.0 2.0 55~67 0.32
8bits 197 DEC DEC 24.2 0.75 47.3 1.5 2.96 0.24
WDEC -1 is deducted from the content of D. The
Binary 16bits 64 WDEC DDEC
D
data are all handled as binary number. - ↑ ↑ - - - - 20.5 0.75 45.6 1.5 2.96 0.24
32bits 198 DDEC 29.6 0.75 57.4 1.5 4.04 0.24
Decrement
2digits 202 DECP DECP 45.8 0.75 61.4 1.5 5.12 0.24
-1 is deducted from the content of D. The
BCD 4digits 203 WDEC WDECP
DDECP
D
data are all handled as BCD. - ↑ ↑ - - - ↑ 65.4 0.75 88.0 1.5 15~18 0.24
8digits 204 DDEC 135~402 0.75 121.8 1.5 40~51 0.24
PC2/L2 PC2J PC3J
word Not Not Not
8bits 13 AND AND Logical product(AND) of S1 content and S2 18.2 1.25 43.4 2.5 2.52 0.4
Logical product (AND) 16bits 187 WAND WAND S1 S2 D content is determined. The result is stored in - - ↑ - - - - 16.2 1.25 43.2 2.5 2.52 0.4
DAND D.
32bits 188 DAND 23.0 1.25 62.0 2.5 4.12 0.4
Logic calculation
8bits 14 OR OR 18.2 1.25 43.2 2.5 2.52 0.4

Logical sum (OR) of S1 content and S2 content
Logical sum (OR) 16bits 189 WOR WOR S1 S2 D
is determined. The result is stored in D. - - ↑ - - - - 16.2 1.25 43.2 2.5 2.52 0.4
DOR
32bits 190 DOR 23.0 1.25 61.3 2.5 4.12 0.4
8bits 9 NOT NOT
17.2 1.0 38.5 2.0 2.64 0.32
The content of S is reversed (to 0 if each bit is
Reverse (NOT) 16bits 191 WNOT WNOT S D
1 and to 1 if it is 0.). The result is stored in D. - - ↑ - - - - 15.6 1.0 40.4 2.0 2.64 0.32
DNOT
32bits 192 DNOT 20.4 1.0 53.6 2.0 4.28 0.32
8bits 18 XOR Exclusive logical sum (XOR) of S1 content and 18.6 1.25 42.9 2.5 2.84 0.4
Exclusive logical sum XOR
16bits 193 WXOR WXOR S1 S2 D S2 content is determined. The result is stored - - ↑ - - - - 16.6 1.25 43.5 2.5 2.64 0.4
(XOR) DXOR in D.
32bits 194 DXOR 23.8 1.25 61.2 2.5 3.56 0.4
If a data matching the content of S1 exists
8bits 88 SRH1 SRH1 between S2 address and S3 address, CARRY 39.2+5.7n 1.25 63.1+1.5n 2.5 4.48+0.92n 0.4
Data search 1 WSRH1
S1 S2 S3
FLAG is turned ON and the position data is ↑ - - - - - ↑
89 33.6+5.0n 1.25 68.7+1.9n 2.5 4.32+0.92n 0.4
Search
16bits WSRH1 stored in S1+1.

8bits 212 SRH2 If an data matching S1 content exists in the 35.1+5.8n 1.25 87.4+1.4n 2.5 3.92+1.48n 0.4
SRH2 area of data number designated with K from
Data search 2 16bits 213 WSRH2
WSRH2
DSRH
S1 S2 K the address of S2, CARRY FLAG is turned and ↑ - - - - - ↑ 28.3+5.0n 1.25 89.5+1.9n 2.5 3.92+1.48n 0.4
the position data is stored in S1+1 and the
32bits 214 DSRH matched data stored in S2 respectively. 28.0+6.0n 1.25 86.7+4.3n 2.5 4.20+2.24n 0.4
5-110
PC2/L2 PC2J PC3J
word Not Not Not
Odd 83 MKP1 Most significant bit is set/reset so that the bit 21.2 1.0 46.7 2.0 3.96 0.32
Parity calculation
MKP1 number of "1" becomes odd (MKP1) [Even

Parity bit create MKP2 S D
(MKP2)], using the lower 7bits in the content of - - - - - - -
Even 81 MKP2 21.2 1.0 46.1 2.0 3.96 0.32
S as "source data". The result is stored in D.
Odd 84 PCH1 PCH1 CARRY FLAG is turned ON unless the bit 23.0 0.75 50.2 1.5 5.52 0.24
Parity check PCH2 S number of "1" is odd (PCH1) [even (PCH2)] ↑ - - - - - -
Even 82 PCH2 upon parity check of S content. 23.0 0.75 51.8 1.5 5.52 0.24
BCD -> 2 digits -> 8bits 152 BIN BIN 25.2 1.0 52.5 2.0 3.56 0.32
WBIN S D BCD data stored in S is converted to binary
Conversion to 4 digits -> 16bits 3 WBIN DBIN data and, thereafter, stored in D. - - - - - - ↑ 34.8 1.0 70.4 2.0 7.12 0.32
binary data 8 digits -> 32bits 153 DBIN 77.0 1.0 123.2 2.0 15.88 0.32
Binary -> 8bits -> 2 digits 154 BCD BCD 21.8 1.0 48.6 2.0 3.64 0.32
Binary data stored in S is converted to BCD
Conversion to 16bits -> 4 digits 4 WBCD WBCD
DBCD
S D
data and, thereafter, stored in D.
- - - - - - ↑ 30.2 1.0 68.6 2.0 10~13 0.32
BCD data 32bits -> 8 digits 155 DBCD 55.4~318.2 1.0 117.6 2.0 27~38 0.32
Character and numeral data shown with K from
the address of S are deemed as JIS code and
JIS ->Conversion to binary data 156 JBIN JBIN S D K then stored in the area having D as its head - - - - - - ↑ 29.7+14.4n 1.25 36.2+37.0n 2.5 3.08+3.92n 0.4
address, after converted to binary number.
The digit number shown with K from the
BJIS S D K address of S is deemed as hexadecimal
Binary data -> Conversion to JIS 157 BJIS number and the stored in the area having D as - - - - - - ↑ 25.0+10.0n 1.25 33.7+22.0n 2.5 2.84+3.00n 0.4
its head address, after converted to JIS code.
The content of S is stored in D, after its lower
4 ->16 DECODER 50 DECO DECO S D
4bit was decoded to hexadecimal data. - - ↑ - - - - 13.2 1.0 38.1 2.0 1.24 0.32
ON bit position, of 16 bits in the S content, is
converted to binary data (two or more ON bits;
5-111
16 ->4 DECODER 51 ENCO ENCO S D - - - - - - - 18.5 1.0 78.6 2.0 5.80 0.32
Conversion
Priority is given to the lower bit.) and the

converted data is stored in lower 4 bits of D.
Binary 4bit data is converted to 7-segment
data, but limited to the digit number shown with
SEG S D K
7-SEGMENT DECODER 52 SEG K from the address of S, and the converted - - - - - - ↑ 36.4+9.6n 1.25 67.9+12.1n 2.5 8.88+2.26n 0.4
data is stored in the area which of head
address is D.
The BCD type data of hour, minute and second
Hour, minute, second -> which is stored in 4 bytes with S on its head is
Convert to sec
158 WTIM1 WTIM1 S D
converted to binary data of 0.1 sec unit and the - - - - - - ↑ 77.8 1.0 105.4 2.0 11.20 0.32
converted data is stored in D.
The content of S is deemed as binary data of
Sec -> 0.1 sec unit and converted to BCD type data of
159 WTIM2 WTIM2 S D hour, minute and second. The converted data - - - - - - - 64.6 1.0 79.4 2.0 47.83 0.32
Convert to hour, minute, sec
is stored in 4 bytes with D on its head.
The content of S1 is transferred to register
Code conversion Setting 85 CDSET CDSE S1 S2 D shown with (D address +S2 content). The - - - - - - ↑ 44.4 1.25 61.6 2.5 6.04 0.4
content of S1 is handled as BCD.
The content of register shown with (S2 address
CDO1 S1 S2 D
Code conversion Output 1 86 CDO1 +S content ) is transferred to D. The content of - - - - - - ↑ 49.0 1.25 60.2 2.5 6.04 0.4
S1 is handled as BCD.
BCD data stored in the register shown with (S2
address +S1 content) is transferred to D+1 and
Code conversion Output 2 87 CDO2 CDO2 S1 S2 D
furthermore transferred to D after converted to - - - - - - ↑ 64.0 1.25 75.8 2.5 8.20 0.4
binary data.
PC2/L2 PC2J PC3J
word Not Not Not
8bits 17 CP 30.1 1.0 48.6 2.0 2.84 0.32
Conversion
CP Upon comparison of S1 content with S2 content,

Comparison 16bits 12 WCP WCP S1 S2 either one of >, =, < FLAGS is turned ON - - - ↑ ↑ ↑ - 25.9 1.0 48.7 2.0 2.84 0.32
DCP from the size relation between the two.
32bits 211 DCP 31.5 1.0 64.0 2.0 4.36 0.32
8bits *136 BSET BSET 13.9 1.0 37.0 2.0 2.00 0.32
Bit set 16bits 137 WBSET WBSET
DBSET
S D D bit is set as designated in S content. - - - - - - - 13.9 1.0 39.0 2.0 2.00 0.32
32bits *138 DBSET 17.5 1.0 42.4 2.0 2.80 0.32
8bits *139 BRST BRST 13.9 1.0 37.4 2.0 2.00 0.32
Bit operation
Bit reset 16bits 140 WBRST WBRST

DBRST
S D D bit is reset as designated in S content. - - - - - - - 13.9 1.0 38.6 2.0 2.00 0.32
32bits *141 DBRST 17.6 1.0 42.2 2.0 2.80 0.32
8bits *54 BPU BUP 20.3 1.0 42.6 2.0 3.16 0.32
Bit content of S2 which is designated in S1
Bit extract 16bits 142 WBUP WBUP
DBUP
S1 S2
content is transferred to CARRY FLAG. ↑ - - - - - - 18.7 1.0 43.8 2.0 4.16 0.32
32bits *143 DBUP 22.3 1.0 47.2 2.0 3.96 0.32
8bits 208 SUM SUM 17.2 1.0 103.0 2.0 3~9 0.32
The sum of bits under ON, of bits in S content,
On bit counter 16bits 209 WSUM WSUM S D
is counted and the result is stored in D. - - - - - - - 26.0 1.0 168.0 2.0 3~16 0.32
DSUM
32bits 210 DSUM 45.2 1.0 303.0 2.0 3~30 0.32
8bits *217 SFR D SFR
S content is shifted by 1 bit to the right. The 20.8 0.75 44.8 1.5 2.76 0.24
content entered in D is shifted to most
1 bit right shift 16bits *36 WSFR T WSFR S
significant bit and the content of least ↑ - - - - - - 17.8 0.75 45.8 1.5 2.64 0.24
DSFR
32bits *218 DSFR significant bit is shifted to CARRY FLAG. 26.4 0.75 57.2 1.5 3.52 0.24
8bits *224 BSFR BSFR
22.9 1.0 48.3+0.27n 2.0 3.36+0.56n 0.32
S content is shifted by designated bit number
↑ - - - - - -
5-112
n-bit right shift 16bits *225 WBSFR WBSFR S K

(K) to the right. 21.1 1.0 48.9+0.27n 2.0 3.36+0.56n 0.32
DBSFR
32bits *226 DBSFR 33.4 1.0 55.1+6.63n 2.0 3.80+0.96n 0.32
8bits *219 SFL D SFL
S content is shifted by 1 bit to the left. the 21.3 0.75 45.4 1.5 2.76 0.24
content entered in D is shifted to most
1 bit left shift 16bits *37 WSFL T WSFL S significant bit and the content of least ↑ - - - - - - 18.52 0.75 45.8 1.5 2.64 0.24
DSFL
32bits *220 DSFL significant bit is shifted to CARRY FLAG 26.32 0.75 57.8 1.5 3.28 0.24
S.ft
8bits *227 BSFL BSFL 23.6 1.0 48.5+0.21n 2.0 3.36+0.56n 0.32
S content is shifted by designated bit number
n bit left shift 16bits *228 WBSFL WBSFL S K
(K) to the left. ↑ - - - - - - 22.0 1.0 49.2+0.23n 2.0 3.36+0.56n 0.32
DBSFL
32bits *229 DBSFL 33.7 1.0 55.0+6.63n 2.0 3.88+0.96n 0.32
8bits *221 SRL D
SRL 21.4 0.75 58.0 1.5 3.76 0.24
S content is shifted by 1 bit to the left (L/R=ON)
1 bit right/left shift 16bits *222 WSRL L/R
T
WSRL
DSRL
S
[right (L/R=OFF). ↑ - - - - - - 18.6 0.75 59.2 1.5 3.76 0.24
32bits *223 DSRL 28.7 0.75 70.0 1.5 4.28 0.24
8bits 230 BSRL L/R BSRL S content is shifted 1 bit by designated bit 26.4 1.0 54.8+0.4n 2.0 4.52+0.48n 0.32
n bit right/left shift 16bits 231 WBSRL T
WBSRL
DBSRL
S number (K) to the left (L/R=ON) ↑ - - - - - - 25.6 1.0 56.9+0.3n 2.0 4.52+0.48n 0.32
[right )L/R=OFF)].
32bits 232 DBSRL 36.8 1.0 63.4+7.0n 2.0 4.68+0.80n 0.32
PC2/L2 PC2J PC3J
word Not Not Not
4bits 251 SUP 24.4+7.0n 1.0 66.7+4.1n 2.0 6.34+1.10n 0.32

Data in area with S on its head address and
8bits 252 UP2 SUP
with data number designated with K are shifted
17.1+7.7n 1.0 52.5+1.9n 2.0 5.20+0.92n 0.32
UP2 S K
WUP to upper significant direction. The least
Upper significant shift
16bits 253 WUP DUP significant data is 0. - - - - - - ↑ 19.6+4.8n 1.0 56.8+2.4n 2.0 5.52+0.92n 0.32
32bits 254 DUP 17.0+9.6n 1.0 59.6+4.8n 2.0 5.76+1.68n 0.32

Data in areas from S1 up to S2 are shifted at
Shift
8bits 91 UP1 UP1 S1 S2 unit of 1 byte. Least significant data remains 25.1+7.7n 1.0 49.6+2.0n 2.0 4.52+0.92n 0.32
unchanged.
4bits 255 SDOWN 22.5+8.1n 1.0 66.1+4.1n 2.0 6.62+0.94n 0.32

Data in area with S on its head address and
8bits 256 DOWN SDOWN
with data number designated with K are shifted
18.0+7.3n 1.0 55.1+1.7n 2.0 5.28+0.92n 0.32
Lower significant shift DOWN
WDOWN
S K
to lower significant direction. Most significant - - - - - - ↑
16bits 257 WDOWN DDOWN data is 0. 17.0+4.8n 1.0 57.0+2.4n 2.0 5.76+0.92n 0.32
32bits 258 DDOWN 13.6+9.6n 1.0 60.5+4.9n 2.0 5.88+1.68n 0.32
8bits 160 FIFW 36.4 1.25 55.7 2.5 5.84 0.4

FIFW S content is transferred to the address shown
WFIFW S D1 D2 with ( offset value shown with D1 address + D2
FIFO write 16bits 161 WFIFW - - - - - - ↑ 24.6 1.25 58.3 2.5 6.36 0.4
5-113
DFIFW content). Furthermore, +1 is added to D2

content.
32bits 162 DFIFW 29.0 1.25 66.5 2.5 7.12 0.4
8bits 163 FIFR S content is transferred to D2. Data in the 21.5+7.3n 1.25 42.5+1.9n 2.5 5.88+1.00n 0.4
FIFO
FIFR area with S as its head address and with D1

FIFO read 16bits 164 WFIFR WFIFR
DFIFR
S D1 D2 content as its data number are shifted to lower - - - - - - ↑ 21.8+4.8n 1.25 40.4+3.0n 2.5 6.08+1.00n 0.4
significant direction. Furthermore, +1 is
added to D1 content.
32bits 165 DFIFR 21.4+9.6n 1.25 38.0+5.7n 2.5 6.40+1.84n 0.4
The areas from S address up to D address are
Stack shift input 68 SFIN SFIN S D deemed as STACK and the content of S is all - - - - - - ↑ 29.3+6.0n 1.0 71.0+1.8n 2.0 6.68+0.84n 0.32
stacked. However, 0 is deemed as "no data".
S content is transferred to D2. The data from
Stack shift output 69 SFOUT SFOUT D1 S D2 D1 address up to S-1 are shifted to upper - - - - - - ↑ 32.4+7.6n 1.25 59.4+1.8n 2.5 9.94+0.96n 0.4
significant direction. D1 content is made to 0.
Symbol Function PC2/L2 PC2J PC3J
word V56 V55 V54 V53 V52 V51 V50
Not Not Not
8bits *233 RRC 12.4+20.6n 1.0 56.7+0.19n 2.0 3.72+0.48n 0.32
RRC S content and CARRY FLAG are rotated to the
With carry 16bits *234 WRRC WRRC S K right, by the bit number designated with K. ↑ - - - - - ↑ 11.6+19.0n 1.0 57.2+0.24n 2.0 3.72+0.48n 0.32
DRRC
Rotate to 32bits *235 DRRC 16.4+22.6n 1.0 63.0+6.64n 2.0 4.48+0.88n 0.32
right 8bits *242 RR 12.4+15.2n 1.0 52.1+0.27n 2.0 3.72+0.48n 0.32
Without RR S content is rotated to the right, by the bit
carry
16bits *243 WRR WRR S K number designated with K. ↑ - - - - - ↑ 11.6+13.6n 1.0 53.1+0.22n 2.0 3.72+0.48n 0.32
DRR
32bits *244 DRR 16.4+17.2n 1.0 59.1+8.59n 2.0 4.52+0.88n 0.32
8bits *236 RLC RLC
12.4+21.0n 1.0 56.5+0.26n 2.0 3.72+0.48n 0.32
With WRLC S content and CARRY FLAG is rotated to the
carry
16bits *237 WRLC DRLC
S K
left, by the bit number designated with K. ↑ - - - - - ↑ 11.6+19.8n 1.0 57.2+0.23n 2.0 3.72+0.48n 0.32
Rotate
Rotate to 32bits *238 DRLC 16.4+22.7n 1.0 63.3+6.62n 2.0 4.48+0.88n 0.32
left 8bits *245 RL 12.4+15.6n 1.0 52.3+0.23n 2.0 3.72+0.48n 0.32
RL
Without S content is rotated to the left, by the bit
carry
16bits *246 WRL WRL
DRL
S K
number designated with K. ↑ - - - - - ↑ 11.6+14.4n 1.0 53.0+0.24n 2.0 3.72+0.48n 0.32
32bits *247 DRL 16.4+17.2n 1.0 58.7+8.65n 2.0 4.52+0.88n 0.32
8bits 239 RLRC L/R RLRC 16.0+20.3n 1.0 67.2+0.6n 2.0 4.52+0.48n 0.32
With S S content and CARRY FLAG are rotated to the
T WRLRC
carry
16bits 240 WRLRC DRLRC left (L/R =ON) [right (L/R=OFF), by the bit ↑ - - - - - ↑ 15.5+18.8n 1.0 66.5+0.3n 2.0 4.52+0.48n 0.32
number designated with K.
Rotate to 32bits 241 DRLRC 20.2+22.8n 1.0 76.7+7.1n 2.0 5.60+0.88n 0.32
5-114
right/left 8bits 248 RLR L/R RLR 16.4+14.8n 1.0 62.8+0.6n 2.0 4.52+0.48n 0.24
S content is rotated to the left (L/R=ON) [right
Without T WRLR S
carry
16bits 249 WRLR DRLR (L/R =OFF)], by the bit number designated with ↑ - - - - - ↑ 14.2+13.8n 1.0 64.0+0.2n 2.0 4.52+0.48n 0.24
K.
32bits 250 DRLR 19.8+17.2n 1.0 70.0+9.0n 2.0 5.60+0.88n 0.24
Jumped into label No. Ln.
Jump 272 JMP JMP Ln - - - - - - - 112 0.75 75.4 1.5 8.00 0.24
Sub routine of label No. Sn is executed and
Sub-routine call 273 CALL CALL Sn steps following this command example are - - - - - - - 139 0.75 107.5 1.5 14.20 0.24
executed.
Program branching
After termination of subroutine, the steps

Return from sub routine 464 RET RET following the CALL command which called - - - - - - - 104 78.5 5.40
applicable subroutine are executed.
This command - NEXT command are repeated
Repeating start #472 FOR FOR K K times. - - - - - - - 95 54.8 4.56
Always Always Always
This command - NEXT command are repeated executed executed executed
Repeating start (indirect) #476 FORN FORN S by the frequency shown with S content. -1 is - - - - - - - 100 61.2 5.96
deducted from S content whenever executed.
Program from FOR and FORN commands up 4.04(FOR)
Repeating end #480 NEXT NEXT to this command is repeated by the frequency - - - - - - - 88 58.4
designated with FOR, FORN commands. 4.24(FORN)
word V56 V55 V54 V53 V52 V51 V50
Not Not Not
Output command of the master control range
Set 440 MC MC from SET up to RESET is controlled . 102 63.5 5.96
K Always Always Always
Master control MCR Normally controlled if MO command input is - - - - - - - executed executed executed
Reset 444 MCR ON and all OFF if the same command input is 98 58.0 3.86
OFF.
External input ON/OFF information is
RIO transferred to Device X and the ON/OFF
I/O refresh !280 RIO information of Device Y is transferred to the - - - - - - - 510~960 0.5 247.5 1.0 23.28+0.18n 0.16
I/O control
external output unit.

External input data of K byte portion is
Input refresh 281 RI RI D K
transferred to Device X from the address of D. - - - - - - ↑ 132+3.0n 1.0 90.7+25.3n 2.0 8.84+1.32n 0.32
ON/OFF information on Device Y of K byte
Output refresh 282 RO RO D K portion is transferred to external output unit - - - - - - ↑ 132+3.0n 1.0 106+22.9n 2.0 9.64+1.08n 0.32
from D address,
Interrupt inhibit %276 DI DI Inhibits sequence interrupt - - - - - - - 80 0.5
Inhibits interrupt of some(K2) external interrupt

Sequential interrupt
Partial interrupt inhibit %278 PDI PDI K1 K2

levels from level K1
- - - - - - ↑ 250+7.2n 1.0
Interrupt enable %277 EI EI Permits sequence interrupt - - - - - - - 115 0.5

5-115
Permits interrupt of some(K2) external interrupt

Partial interrupt enable %279 PEI PEI K1 K2
levels from level K1
- - - - - - ↑ 254+7.1n 1.0
Return from interrupt

processing routine
%468 RETI RETI Indicating end of the interrupt program ↑ ↑ ↑ ↑ ↑ ↑ ↑ 334
Main program start 448 START START Indicating start-up of main sequence program. - - - - - - - 154 68.2 -
Always
Main program end 452 END END Indicating end of main sequence program. - - - - - - - 414
executed
528.0 -
Label
Always Always
executed executed
Indicating end of sequence program including
Program end 456 PEND PEND
subroutine. - - - - - - - - - -
Indicating division and jump of sequence

Label 460 LABEL LABEL Ln
program . - - - - - - - 68.5 30.3 1.48
S,D : register H : hexadecimal constant K : Decimal constant Q : Octal constant C : Character constant n: Label No.
word V56 V55 V54 V53 V52 V51 V50
Not Not Not
Directly reads internal memory of high speed
High speed counter data read 316 HCR HCR S1 S2
counter module. - - - - - - ↑ 208 1.0 171.0 2.0 151 0.32
Directly writes data in internal memory of high
317 HCW - - - - - - ↑
Special module
High speed counter data write HCW S1 S2 H 153+115n 1.25 120.2+119.4n 2.5 3+115n 0.4
speed counter module.
Directly reads internal memory of analog
Common I/O data read 318 IOR IOR S1 S2 H
module. - - - - - - ↑ 69+205n 1.25 98.1+129.4n 2.5 3+120n 0.4
Directly writes data in internal memory of
Common I/O data write 319 IOW IOW S1 S2 H
analog module. - - - - - - ↑ 87+143n 1.25 79.4+184.1n 2.5 15+78.5n 0.4
Directly reads internal memory of serial I/O
Special module byte data read 304 SPR SPR S1 S2 S3
module. - - - - - - ↑ 1135+3.8n 1.25 580.8+7.2n 2.5 633+25n 0.4
Directly write data in internal memory of serial
Special module byte data write 306 SPW SPW S1 S2 S3
I/O module.
- - - - - - ↑ 926+6.4n 1.25 708.8+6.2n 2.5 371+38n 0.4
Satisfies the enable condition of the
Enable 274 ENB ENB - - - - - - - 77 0.5 33.9 1.0
Sequence
debug mode
debug
Satisfies the trigger condition of the

Trigger 275 TRG TRG
debug mode
- - - - - - - 83 0.5 40.4 1.0
Stores the input key code to D when the

Key input %#294 KEY KEY D
I/O monitor is in the user mode.
- - - - - - ↑ 77 0.75
I/O monitor
Displays the data of K bytes from S on

LEDD S H K
Display %#289 LEDD the position H on the monitor display - - - - - - ↑ 120+6.3n 1.25
when the I/O monitor is in the user mode
5-116
Turns off the monitor display when the

Display clear %#290 LEDC LEDC
I/O monitor is in the user mode.
- - - - - - - 97 0.5
Transfers the data from the memory card

Memory card data read $296 CDR CDR H D K
word address H (K words) to D.
- - - - - - ↑ 266.5+36.3n 1.25
Memory card data trnsfer
Transfers the data from S (K words) to

Memory card data write $297 CDW CDW S H K
the memory card word address H.
- - - - - - ↑ 287.4+35.8n 1.25
Transfers the S2 amount of data from

Indirect memory card data the memory card word address S1 to the
read $298 CDIR CDIR S1 D S2
data memory address D up to the S2
- - - - - - ↑ 286.1+36.3n 1.25
amount from it
Transfers the S2 amount of data from
Indirect memory card data $299 CDIW CDIW S1 D S2 the data memory address S1 to the
- - - - - - ↑ 273.7+35.9n 1.25
read memory card word address D up to the
S2 amount from it
Command
PC2/L2 PC2J PC3J
(CY) (BO) (Z) (>) (=) (<) (ER) Execution Not Not Not
Execution Execution
Message data and time in the 16Byte
ANN H S area with code H and S on its head
Annunciator 291 ANN
address are transferred to the
- - - - - - ↑ 281 1.0 391.0 2.0 141.88 0.32
annunciator area of special register.
User defined clock 1, 2 in special relay
User defined clock 293 USC USC K1 K2 K3
are set up.
- - - - - - ↑ 103 1.25 60.8 2.5 75.42 0.4
30 sec correction is made to the built-in

clock. Less than 30 sec is rounded off.
Built-in clock 30 sec correction !292 ADJ ADJ
More than 30 sec is counted up as 1
- - - - - - - 376 0.5 468.0 1.0 188 0.16
minute.
The communication speed for
Communication speed setting
for peripheral equipment
#288 BAUD BAUD K peripheral equipment is changed into - - - - - - ↑ 107 0.75 72.4 1.5 57.06 0.24
Others
the speed designated with K.
Program stop 287 STOP STOP Run of sequence program is stopped. - - - - - - - 140 0.5 78.2 1.0 - 0.16
Scan time reset 46 WDR WDR The scan time monitor timer is reset. - - - - - - - 77 0.5 33.4 1.0 52 0.16
Cancels the I/O monitor error automatic

I/O monitor SYS 0h 0h 0h
display.
- - - - - - - 265.8
Error automatic 1.25
System call
Sets the I/O monitor error automatic

set/cancel SYS 0h 1h 0h - - - - - - - 265.7
5-117
display.
$300 SYS
SYS 1h 0h 0h Cancels the I/O monitor user mode. - - - - - - - 584.0
II/O monitor
1.25
User mode set/cancel SYS 1h 1h 0h Sets the I/O monitor user mode. - - - - - - - 624.7
(5) Exclusive applied commands for PC3J
Execution time
Flag
Command (ms)
Symbol Function PC3J
V56 V55 V54 V53 V52 V51 V50
Not
(CY) (BO) (Z) (>) (=) (<) (ER) Execution
execution
Bit data with bit position represented by h1

Transfer commands
of S at its head and with points represented 27~39

Bit block transfer 121 BBMOV BBMOV Sh1 Dh2 K
by K is transferred to an area with bit
- - - - - - ↑ +0.34n(Bit)
0.4
position represented by h2 of D at its head.
4bit 259 STURN Transfer to area with D as its head address 8.76+2.36n 0.4
STURN
8bit 260 in inverse sequence from last data in data 8.76+1.72n 0.4
Inversion TURN TURN
WTURN
S D K
area with S as its head address and with
- - - - - - ↑
16bit 261 WTURN points represented by K. 8.76+1.72n 0.4
S is stored in D after changed into
Address constant transfer 320 MOVAD MOVAD S D
indirect address.
- - - - - - - 0.72 0.32
8bit 323 +H After S content and constant H were 2.40 0.4

+H S H D added, the result is stored in D. Data are all
16bit 324 W+H W+H handled as binary value. 2.40 0.4
Binary ↑ - ↑ - - - -
S content and constant H are added and the result
32bit 325 D+H D+H S H is stored in the address next to S. The data are all 4.04 0.4
Constant handled as binary number.
addition 2 digits 326 +HP After S content and constant K were 7.80 0.4
+HP S K D added, the result is stored in D.
4 digits 327 W+HP W+HP
The data are all handled as BCD. 23.80 0.4
BCD ↑ - ↑ - - - ↑
S content and constant K are added and
8 digits 328 D+HP D+HP S K the result is stored in the address next to S. 58~64 0.4
The data are all handled as BCD.
8bit 329 -H -H S H D After S content and constant H were 3.20 0.4
W-H deducted, the result is stored in D. The
16bit 330 0.4
Arithmetic computation
W-H 3.20
data are all handled as binary value.
Binary - ↑ ↑ - - - -
S content and constant H are deducted
32bit 331 D-H D-H S H and the result is stored in D. The data are 4.52 0.4
all handled as binary number.
Constant
deduction 2 digits 332 -HP -HP S K D
After S content and constant K were 6.92 0.4
W-HP deducted, the result is stored in D. The
4 digits 333 W-HP data are all handled as BCD.
22.76 0.4
- ↑ ↑ - - - ↑
BCD S content and constant K are deducted and the
8 digits 334 D-HP D-HP S K result is stored in the address next to S. The data 55~67 0.4
are all handled as binary number.
8bit 335 *H
*H
After S content and constant H were 1.24 0.4
S H D
W*H multiplied, the result is stored in D. The
16bit 336 W*H data are all handled as binary value.
4.60 0.4
Binary - - - - - - -
After S content and constant H were multiplied,
32bit 337 D*H D*H S H the result is stored in the address next to S. 23.04 0.4
Constant The data are all handled as binary value.
multiplica-
tion 2 digits 338 *HP *HP S K D
After S content and constant K were 13~15 0.4
W*HP multiplied, the result is stored in D. The
4 digits 339 W*HP data are all handled as BCD. 39~50 0.4
BCD - - - - - - ↑
After S content and constant K were multiplied, the
D*HP S K
8 digits 340 D*HP result is stored in the address next to S. The data 160~180 0.4
8bit 341 /H After S content and constant H were 17~19 0.4

/H H D divided, the result is stored in D and
W/H
S
16bit 342 W/H remainder stored in next address. The 28~30 0.4
data are all handled as binary value.
Arithmetic computation
Binary - - - - - - ↑
After S content and constant H were
D/H S H divided, the result is stored in address next
32bit 343 D/H
to S and remainder stored in next address .
77~82 0.4
Constant The data are all handled as binary value.
dividing 2 digits 344 /HP After S content and constant K were 21.26 0.4
/HP S K D divided, the result is stored in D and
W/HP
4 digits 345 W/HP remainder stored in next address. The data 56.92 0.4
BCD - - - - - - ↑
After S content and constant K were
D/HP S K divided, the result is stored in address next
8 digits 346 D/HP 149~164 0.4
to S and remainder stored in next address.
The data are all handled as BCD.
S,D : Register , H : Hexadecimal constant K : decimal constant
- 5-118 -
Execution time
Flag
Command (ms)
V56 V55 V54 V53 V52 V51 V50
Not
execution
8bit 347 ANDH After logic product (AND) of S content and 2.40 0.4
ANDH H D constant H was computed, the result is
Constant logic 16bit 348 WANDH WANDH
stored in D. 2.40 0.4
- - ↑ - - - -
product After logic product(AND) of S content and
32bit 349 DANDH DANDH S H constant H was computed, the result is 3.96 0.4
stored in address next to S.
Logic computation
8bit 350 ORH After logic sum (OR) of S content and 2.40 0.4
ORH S H D constant H was computed, the result is
16bit 351 WORH WORH 0.4
Constant logic stored in D. 2.40
- - ↑ - - - -
sum After logic sum (OR) of S content and
32bit 352 DORH constant H was computed, the result is 3.96 0.4
DORH S H
stored in address next to S.
8bit 353 XORH After exclusive logic sum (XOR) of S 2.72 0.4
XORH S H D content and constant H was computed, the
Constant 16bit 354 WXORH WXORH result is stored in D. 2.72 0.4
exclusive logic - - ↑ - - - -
After exclusive logic sum (XOR) of S
sum 0.4
32bit 355 DXORH DXORH S H content and constant H was computed, the 3.96
result is stored in address next to S.
- 5-119 -
Execution time
Flag
Command
(µs)
V56 V55 V54 V53 V52 V51 V50
(CY) (BO) (Z) (>) (=) (<) (ER) Not
Execution execution
8bit 362 STI1 6.12+0.84n 0.4
STI1 S1 D S2 The sum in data area with S1 as head address and
Sum 16bit 363 WSTI1 WSTI1
DSTI1
with number represented by S2 content is stored in D. - - ↑ - - - ↑ 7.00+1.08n 0.4
The data are all handled as binary value.
32bit 364 DSTI1 7.80+1.52n 0.4
Statistic processing
8bit 374 MAX 5.56+1.00n 0.4

Maximum value in data area with S1 as head address
Max value MAX S1 D S2
retrieval 16bit 375 WMAX WMAX and with number represented by S2 content is stored - - - - - - ↑ 5.72+1.00n 0.4
DMAX
in D.
32bit 376 DMAX 6.20+1.60n 0.4
8bit 377 MIN 5.72+1.00n 0.4

MIN S1 D S2 Minimum value in data area with S1 as head address
Min value
retrieval 16bit 378 WMIN WMIN
DMIN
and with number represented by S2 content is stored - - - - - - ↑ 5.72+1.00n 0.4
in D.
32bit 379 DMIN 6.20+1.60n 0.4
8bit 380 AVE Mean value in data area with S1 as head address and with 33.24+1.08n 0.4
AVE S1 D S2 number represented by S2 content is stored in D. The data are
Mean 16bit 381 WAVE WAVE
all handled as binary value and fractions over 4 at first decimal
- - - - - - ↑ 82.08+1.32n 0.4
DAVE
32bit 382 DAVE point are counted as one. 131+1.44n 0.4
Subroutine is closed when the conditions are met, and
Conditional return 285 CRET CRET applicable subroutine is called and executed from step next to - - - - - - - 5.40 0.16
CALL command.
External I/O of K byte portion from D address are
Area designated I/O refresh 295 ARIO ARIO D K - - - - - - ↑ 16.00+2.40n 0.32
Others
refreshed.
Applied command flag clear Set up so that applied command flag is cleared at
300 SYS SYS 4 1 0 81.70 0.4
mode setting reading of applied command .
- - - - - - -
Applied command flag clear Set up so that applied command flag is not cleared at
300 SYS SYS 4 0 0 82.10 0.4
mode resetting reading of applied command.
SYS Clock adjustment SYS 5 S 0 The clock in CPU is adjusted by “the minute second
instruction (PC3J series 300 SYS day hour year month week” of the 4-word which - - - - - - ↑
ver2.6~) *1 makes the address of S a head.
*1 PC3JG PC3JBG PC3JP can use this instruction.PC3JL,PC3JD,PC3JB,PC3JM can use this instruction since version 2.6.
PC3J PC3JNF PC3JNM can not use this instruction.
5-120
(6) Exclusive applied commands for PC3JG
Execution time
Flag
Command (µs)
V56 V55 V54 V53 V52 V51 V50
Not
execution
The Indirect address of the buffer
register
register(EB) specified S is set to the
address 371 BRSET BRSET S D
2 word area with D as the head
- - - - - - ↑ 0.96 0.4
setting
address.
Transfer commands
Data in buffer registers which of

address is the content of 2 word
Indirect 372 WBR
WBR S D K area with S as the head address is
- - - - - - ↑
Buffer loading transferred to registers with D as the
80+2n 0.4
register head address.
transfer
Size is K.
Registers with S as the head
address is transferred to buffer
Indirect 373 WBW WBW S D K
registers which of address is the
- - - - - - ↑ 80+2n 0.4
saving content of 2 word area with D as the
head address.
Size is K.
Message of the number indicated
with H which of head address is S
are transferred to Dlink-M2 indicated
Order the message
command for Dlink-M2
302 MSET MSET H S D with H. - - - - - - ↑ 80+4n 0.4
The response data from Dlink-M2
Others
are transferred to the area which of

head address is D.
I/O register read-out instruction of
the number indicated with H which of
Order the I/O register CSET H S D head address is S are transferred to
read-out instruction for 370 CSET PCS. - - - - - - ↑ 60+4n 0.4
TOYOPUC-PCS The response data from PCS are
transferred to the area which of head
address is D.
- 5-121 -
5.4.1. Transfer instructions
Transfer instruction is used to store numeric data into register or to transfer data between registers.
Transfer instructions are classified as follows.
Constant transfer…….Stores numeric data into register.
Register to register……Transfers one piece of data from register to register

transfer.
Block transfer…………..Transfers packages of data from register to register
Data delivery……………Inserts data into a data block.
Data extraction…………Fetches data from a data block.
Data exchange…………Exchanges data between registers.
JIS code storage……….Stores character data into register.
Data fill…………………..Stores the same data into successive register locations.
Clear verification……….Transfers data to register if its contents are filled with 0.
External in/out………….Directly outputs data to the external output unit, or directly transfer
inputs data from the external input unit.
File register to other.......Transfers data between file register and another register.
register
5-122
1. MOV 2-digit Hex constant transfer (FUN100)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a hexadecimal constant into the register. The available constants are 0 to FF for MOV
instruction.
(5) Flag
No change
Stores "3F" (hex) into lower 8-bit field of D0000, if M0000 is ON.
5-123
2. WMOV 4-digit Hex constant transfer (FUN101)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a hexadecimal constant into the register. The available constants are 0 to FFFF for
WMOV.
(5) Flag
No change
Transfers "AAAA",(hex) to Y010-Y01F after the OFF to ON transition of X001.
5-124
3. DMOV 8-digit Hex constant transfer (FUN102)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a hexadecimal constant into the register. The available constants are 0 to FFFFFFFF for
DMOV.
(5) Flag
No change
Transfers "FEDCBA98" (hex) to data register D0003 and D0002 when K000 is ON.
5-125
4. MOVP 2-digit BCD constant transfer (FUN103)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a BCD constant into register. The available constants are 0 to 99 for MOVP instruction.
Except for the fact that letters A to F cannot be used in a value, the function is same as that of
the hexadecimal constant transfer.
(5) Flag
No change
Stores "12" (BCD) into upper 8-bit field of D0004, if M000 is ON.
5-126
5. WMOVP 4-digit BCD constant transfer (FUN1)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a BCD constant into register. The available constants are 0 to 9999 for WMOVP
instruction.
(5) Flag
No change
Transfers "7890" (BCD) to Y010-Y01Fafter the OFF to ON transition of X001.
5-127
6. DMOVP 8-digit BCD constant transfer (FUN104)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a BCD constant into register. The available constants are 0 to 99999999 for DMOVP
instruction.
(5) Flag
No change
Transfers "12345678" (BCD) to data register D003 and D0002 when K000 is ON.
5-128
7. MOVR 3-digit decimal constant transfer (FUN105)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores a decimal constant into register after converting it into BIN data. The available constants
are 0 to 255 for MOVR instruction.
(5) Flag
No change

Stores "255" (decimal ("FF" in hexadecimal) into lower 8-bit filed of D0008 if M000 is ON.
5-129
8. WMOVR 5-digit decimal constant transfer (FUN7)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
are 0 to 65535 of or WMOVR instruction.
(5) Flag
No change

Transfers "12345" (decimal ("3039" in hexadecimal) to data register D0123 after the OFF to ON
transition of X101.
{bmc
5-130
9. DMOVR 10-digit decimal constant transfer (FUN106)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
are 0 to 4294967295 for DMOVR instruction.
(5) Flag
No change

Transfers "987654321" (decima1) ("3ADE68B1" in hexadecimal) to link register R004 and R003
when K000 is ON.
5-131
10. MOVQ 3-digit octal transfer (FUN107)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Stores an octal constant into register after converting it into BIN data. The available constants
are 0 to 377 for MOVQ instruction.
(5) Flag
No change

Stores "377" (octal)("FF" in hexadecimal) into upper 8-bit filed of D000A if M000 is ON.
5-132
11. WMOVQ 6-digit octal transfer (FUN8)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
are 0 to 177777 for WMOVQ instruction.
(5) Flag
No change

Stores "177777" (octal)("FFFF" in hexadecimal)to data register D0123 after the OFF to ON
transition of X001.
5-133
12. DMOVQ 11-digit octal transfer (FUN108)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
are 0 to 37777777777 for DMOVQ instruction.
(5) Flag
No change

Stores "1234567" (octal) ("53977" in hexadecimal)to link register R004 K003 is ON.
5-134
13. MOVT 2-digit Hex constant transfer to two places (FUN62)
(1) Usable devices
OP1 O
PC3 OP1
extended
(3) Symbol
(4) Function
Stores the same Hex constant into two registers, the available constants are 0 to FF for MOVT
instruction.
(5) Flag
No change

Transfers "A9" (hex) into lower 8-bit field of D0100 and Y010-Y017 if M000 is ON.
5-135
14. WMOVT 4-digit Hex constant transfer to two places (FUN 110)
(1) Usable devices
OP1 O
PC3 OP1
extended
(3) Symbol
(4) Function
Stores the same Hex constant into two registers, the available constants are 0 to FFFF for
WOVT instruction.
(5) Flag
No change

Transfers "1234" (hex) to data register D0000 and D0100 after the OFF to ON transition of
X001.
5-136
15. MOVE 1-byte data direct transfer (FUN90)
(1) Usable devices
PC3 OP1 O O O O O O O O O O O O O O O
(3) Symbol
(4) Function
Transfers data from OP1 register to OP2register, leaving OP1 register data intact.
(5) Flag
No change

Transfers the data in lower 8-bit filed of D0000 to upper 8-bit field of D0100 if M000 is ON.
5-137
16. WMOVE 2-byte data direct transfer (FUN0)
(1) Usable devices
(3) Symbol
(4) Function
(5) Flag
No change

Transfers the data in data register D0123 to Y020-Y02F after the OFF to ON transition of X001.
5-138
17. DMOVE 4-byte data direct transfer (FUN111)
(1) Usable devices
(3) Symbol
(4) Function
(5) Flag
No change

Transfers the 32-bit data in data register D0001 and D0000 to D0101 and D0100 if K000 is ON.
5-139
18. MOVF 1-byte data indirect transfer 1 (FUN74)
(1) Usable devices
Transfer
O O O O O O O O O O O O O
destination
Transfer
O O O O O O O O O O O O O O O
destination
(3) Symbol
(4) Function
Transfers data from OP1 register to the register addressed by the content of OP2 register. The
data in the OP1 register remains intact.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER): Is set when the transfer destination is outside of the data memory area.
5-140
19. WMOVF 2-byte data indirect transfer 1 (FUN112)
(1) Usable devices
Transfer
destination
Transfer
destination
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
5-141
20. DMOVF 4-byte data indirect transfer 1 (FUN113) *
(1) Usable devices
Transfer
destination
Transfer
destination
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
5-142
21. MOVG 1-byte data indirect transfer 2 (FUN75)
(1) Usable devices
Transfer
source
Transfer
source
(3)Symbol
(4) Function
Transfers the data in the register addressed by the content of the OP1 register to the OP2
register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER): Is set when the transfer source is outside of the data memory area.
5-143
22. WMOVG 2-byte data indirect transfer 2 (FUN114)
(1) Usable devices
Transfer
source
Transfer
source
(3) Symbol
(4) Function
register.
(5) Flag
CY BO Z > = < ER
↑
5-144
23. DMOVG 4-byte data indirect transfer 2 (FUN115) *
(1) Usable devices
Transfer
source
Transfer
source
(3) Symbol
(4) Function
register.
(5) Flag
CY BO Z > = < ER
↑
5-145
24. MOVH 1-byte data indirect transfer 3 (FUN76)
(1) Usable devices
Transfer source
and destination
extended
Transfer source
and destination
(3) Symbol
(4) Function
Transfers the data in the register addressed by the content of the OP1 register to the register
addressed by the content of the OP2 register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer source and destination are outside of the data
memory area.
5-146
25. WMOVH 2-byte data indirect transfer 3 (FUN116)
(1) Usable devices
Transfer source
and destination
extended
Transfer source
and destination
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER): Is set when the transfer source and destination are outside of the data memory
area.
5-147
26. DMOVH 4-byte data indirect transfer 3 (FUN117) *
(1) Usable devices
Transfer source
and destination
extended
Transfer source
and destination
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
area.
5-148
27. BMOV1 Byte data block transfer 1 (FUN70)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers data from OP1 register to the areas covered by OP2 and OP3 registers. The
maximum transferred data is 768 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER): Is set when the transfer source is outside of the data memory area, when the
OP2 address is smaller than the OP3 address, or when the transferred data exceeds the
specified value.

Transfers the data in the field from upper 8bits of D0100 to lower 8bits of D1002 to the field
from upper 8bits of D0110 to lower 8bits of D0112 after the OFF to ON transition of X000.
5-149
28. BMOV2 Byte data block transfer 2 (FUN118) *
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Transfers data in OP1 and subsequent registers to locations covered by OP2 and subsequent
registers with the number of data being specified by OP3. The maximum transferred data is 768
bytes.
(5) Flag
CY BO Z > = < ER
↑
memory area or when the transferred data exceeds the specified value.

Transfers 768 bytes of data from lower 8-bit field of D0000 to the locations starting at the upper
8bits of D10000, on the OFF to ON transition of X000.
5-150
29. WBMOV Word data block transfer (FUN119) *
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers data in OP1 and subsequent registers to locations covered by OP2 and subsequent
registers with the number of data being specified by OP3. The maximum transferred data is
1024 words for WBMOV.
(5) Flag
CY BO Z > = < ER
↑
area or when the transferred data exceeds the specified value.

Transfers 10 words of data from D0000 to the locations starting at D10000, when M000is ON.
5-151
30. BMVI Byte data indirect block transfer (FUN71)
(1) Usable devices
Transfer source
and destination
extended
Transfer source
and destination
(3) Symbol
(4) Function
Transfers contents of the registers starting at the location addressed by the content of OP1
register to the registers starting at the address specified by the content of OP2 register; the
number of pieces of data to be transferred being specified by the content of OP3 register. The
maximum transferred data is 768 bytes for BMVI.
(5) Flag
CY BO Z > = < ER
↑
5-152
31. WBMVI Word data indirect block transfer (FUN120) *
(1) Usable devices
Transfer source
and destination
extended
Transfer source
and destination
(3) Symbol
(4) Function
Transfers contents of the registers starting at the location addressed by the content of OP1
register to the registers starting at the address specified by the content of OP2 register; the
number of pieces of data to be transferred being specified by the content of OP3 register. The
maximum transferred data is 1024 words for WBMVI.
For indirect addressing, refer to paragraph (4) in 4.2.2 "Data memory address".
(5) Flag
CY BO Z > = < ER
↑
area or when the transferred data exceeds the specified value.
5-153
32. DIV Byte data delivery (FUN5)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the content of OP1 register to the location addressed by the sum of register
address(defined by OP2) and offset (defined by the content of OP3).
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer source is outside of the data memory area.

Transfers the content of lower 8-bit field of D0123 to upper 8-bit field of D0234 if M000 is OFF.
Transfers the content of lower 8-bit field of D0123 to lower 8-bit field of D0235 if M000 is ON.
5-154
33. WDIV Word data delivery (FUN122)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the content of D0040 to D0052 if M000 is OFF.
Transfers the content of D0040 to D0055 if M000 is ON.
5-155
34. DDIV 32-bit data delivery (FUN123) *
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the contents of D0043 and D0042 to D0061 and D0060 if M000 is OFF.
Transfers the contents of D0043 and D0042 to D0063 and D0062 if M000 is ON.
5-156
35. BDIV Byte data block delivery(FUN72)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the number of pieces of data (specified by the content of OP3) starting at the location
(specified by the sum of OP1 address and offset defined by the content of OP1) to the locations
starting at the address specified by the content of OP2. The maximum number of transferable
pieces of data is 768 bytes for EDIV.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the transfer source and destination are outside of the data memory
area; or if OP3 requires a transfer of data exceeding the specified number of
pieces.
5-157
36. WBDIV Word data block delivery(FUN126)
(1) Usable devices
extended
(3) Symbol
(4) Function
(specified by the sum of OP1 address and offset defined by the content of OP1) to the locations
starting at the address specified by the content of OP2. The maximum number of transferable
pieces of data is 1024 words for WBDIV.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER): Is set if the transfer source and destination are outside of the data memory area;
or if OP3 requires a transfer of data exceeding the specified number of pieces.
5-158
37. PUP Byte data extraction (FUN6)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the contents in the location (addressed by the sum of OP1 address and offset defined
by the content of OP2) to the location addressed by the content of OP3.
(5) Flag
CY BO Z > = < ER
↑

Transfers the content of upper 8-bit field of D1234 to lower 8-bit field of D2345 if M000 is OFF.
Transfers the content of lower 8-bit field of D1235 to lower 8-bit field of D2345 if M000 is ON.
5-159
38. WPUP Word data extraction (FUN124)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the content of D0052 to D004E if M000 is OFF.
Transfers the content of D0055 to D004E if M000 is ON.
5-160
39. DPUP 32-bit data extraction (FUN125) *
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the content of D0061 and D0060 to D0054 and D0053 if M000 is OFF.
Transfers the content of D0063 and D0062 to D0054 and D0053 if M000 is ON.
5-161
40. BPUP Byte data block extraction(FUN73)
(1) Usable devices
extended
(3) Symbol
{bmc CMD_Bpup.bmp}
(4) Function
specified by the content of OP1 to the locations starting at the address specified by the sum of
OP2 address and the offset defined by the content of OP2. The maximum number of
transferable data is 768 bytes for BPUP.
(5) Flag
CY BO Z > = < ER
↑
memory area; or if OP3 requires the transfer of data exceeding the specified
number of pieces.
5-162
41. WBPUP Word data block extraction(FUN127)
(1) Usable devices
extended
(3) Symbol
(4) Function
specified by the content of OP1 to the locations starting at the address specified by the sum of
OP2 address and the offset defined by the content of OP2. The maximum number of
transferable data is 1024 words for WBPUP.
(5) Flag
CY BO Z > = < ER
↑
memory area; or if OP3 requires the transfer of data exceeding the specified
number of pieces.
5-163
42. SXCH 4-bit data exchange(FUN53)
(1) Usable devices
(3) Symbol
(4) Function
Swaps the contents of upper 4-bit field and lower 4-bit field of OP1 and stores the result into
OP2 register. The content of OP1 register remains unchanged.
(5) Flag
No change

When M000 changes from OFF to ON, transfers ON/OFF data of Y000-Y003 to Y004-Y007 and
ON/OFF data of Y004-Y007 to Y000-Y003.
5-164
43. XCH 8-bit data exchange(FUNl32)
(1) Usable devices
(3) Symbol
(4) Function
Swaps the contents of OP1 register and those in OP2.
(5) Flag
No change

Exchanges data in Y000-Y007 with the content in lower 8-bit field of D0070 after the OFF to ON
transition of M000.
5-165
44. WXCH 16-bit data exchange(FUN2)
(1) Usable devices
(3) Symbol
(4) Function
(5) Flag
No change

Exchanges the current value of the counter C020(content of the current value register N020)
with the content of D0020 after the OFF to ON transition of X000.
5-166
45. DXCH 32-bit data exchange(FUN133) *
(1) Usable devices
(3) Symbol
(4) Function
(5) Flag
No change

Exchanges the contents of D0001 and D0000 with the contents of D0003 and D0002 after the
OFF to ON transition of Y010.
5-167
46. BXCH Byte data block exchange(FUN134)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Swaps data stored in the locations starting at OP1 address with the data in the locations
starting at OP2 address. The number of piece of data to be swapped is up to 256 each and
specified by OP3.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the locations to be exchanged are outside of the data memory area
or if the number of pieces of data to be exchanged is more than 256.

Exchanges the data in the 3-byte area from upper 8-bit field of D0000 with the data in the 3-
byte area of lower 8-bit field of D0100 after the OFF to ON transition of M000.
5-168
47. WBXCH Word data block exchange (FUN 135)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Swaps data stored in the locations starting at OP1 address with the data in the locations
starting at OP2 address. The number of piece of data to be swapped is up to 256 each and
specified by OP3.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the locations to be exchanged are outside of the data memory area
or if the number of pieces of data to be exchanged is more than 256.

Exchanges the current values of counters C000-C004 (contents of current value register
N00ON004)with the contents of D0100-D0104.
5-169
48. JIS Storage in JIS code (FUN 109)
(1) Usable devices
OP1 O
PC3 / PC2 OP2 O
PC3 OP1
OP2
extended
(3) Symbol
(4) Function
Stores the JIS code of the character represented by OP1 and OP2 into 4-byte location starting
at the address of OP3.
(5) Flag
C BO Z > = < E
Y R
↑
Error flag(ER) : Is set when the transfer destination is outside of the data memory area.

Stores JIS codes (hex. 41 and 42) representing character string "AB" into 2-byte location
starting from upper 8bits of D0200.
5-170
49. FIL1 Byte data fill 1 (FUN 77)
(1) Usable devices
OP1 O
PC3 OP1
extended
(3) Symbol
(4) Function
Stores 2-digit hexadecimal constant defined by OP1 to the location starting at the address
specified by OP2 and ending at the address specified by OP3. The maximum length of the
location is 1024 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the addresses of OP2 and OP3 are in reversed order, when the
transfer destination is outside of the data memory area, when the length of
the location exceeds 1024 bytes.

Fills with FF(hex) all the 1024-byte location, from lower 8 bits of D0123 to upper 8bits of
D0150on the OFF to ON transition of M001.
5-171
50. FIL2 Byte data fill 2 (FUN 128) *
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Stores the Hex constant to the location starting at the address specified by content of OP2 and
has the number of data specified by OP3.
The length of the location is 1024 data at maximum.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer destination is outside of the data memory or when
the length of the location exceeds 1024 bytes.

Fills the 1024-byte area starting from lower 8-bit field of D1234 with hexadecimal "FF" after the
OFF to ON transition of X000.
5-172
51. WFIL Word data fill (FUN 129) *
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Stores the Hex constant to the location starting at the address specified by content of OP2 and
has the number of data specified by OP3.
The length of the location is 1024 data at maximum.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer destination is outside of the data memory or when

Fills all 512 words, N000-N1FF, of the current value register with "0" when X000 is ON.
5-173
52. FILI1 Byte data indirect fill 1 (FUN 78)
(1) Usable devices
Transfer
destination
Transfer
destination
(3) Symbol
(4) Function
Stores the contents of OP3 register to the location starting at the address specified by content
of OP2 and ending at the address specified by content of OP3 register. The maximum length of
location is 1024 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the contents of the OP2 and OP3 registers are in reversed order,
when the transfer destination is outside of the data memory area or when
5-174
53. FILI2 Byte data indirect fill 2 (FUN 130) *
(1) Usable devices
Transfer
destination
Transfer
destination
(3) Symbol
(4) Function
Stores the contents of OP1 to the location starting at the address specified by the content of
OP2 register and has the number of data specified by the content of OP3.
The length of the location is 1024 bytes at maximum.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer destination is outside of the data memory area or
when the length of the location exceeds 1024 pieces of data.
5-175
54. WFILI Word data indirect fill (FUN 131) *
(1) Usable devices
Transfer
destination
Transfer
destination
(3) Symbol
(4) Function
Stores the contents of OP1 to the location starting at the address specified by the content of
OP2 register and has the number of data specified by the content of OP3.
The length of the location is 1024 bytes at maximum.
(5) Flag
CY BO Z > = < ER
↑
when the length of the location exceeds 1024 pieces of data.
5-176
55. CMOV Byte data transfer on clearance confirmation (FUN 20)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
If the data starting at the OP2 address and the number of subsequent pieces of data specified
by OP3 are zeroed, transfers the data at OP1 address and subsequent number of pieces of
data specified by OP3, to the location starting at OP2. The maximum number of transferable
pieces of data is 512.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set upon execution of transfer.

memory or when the transferred data exceeds the specified value.

If the 3bytes starting at lower 8bits of D1000 are all "0" and X001 is ON, transfers the 3bytes
starting at D000 lower 8bits to the area starting at D1000.
5-177
56. WCMOV Word data transfer on clearance confirmation (FUN 166)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
If the data starting at the OP2 address and the number of subsequent pieces of data specified
by OP3 are zeroed, transfers the data at OP1 address and subsequent number of pieces of
data specified by OP3, to the location starting at OP2. The maximum number of transferable
pieces of data is 512.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set upon execution of transfer.

memory or when the transferred data exceeds the specified value.

If D1000 and subsequent 512-word locations are all filled with "0" and X002 is ON, transfers
D0000 and subsequent 512 words to D10000 and subsequent locations
.
5-178
57. CLR Matching data clearance (byte) (FUN 21)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Compares area starting at OP1 address and containing the number of pieces of data specified
by OP3 with the area starting at OP2 address and containing the number of pieces of data
specified by OP3 and clears the latter area (zeroes all data) if the data in both areas match. The
maximum number of transferable pieces of data is 512.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set upon execution of clear.

Error flag(ER) : Is set when devices in the comparison areas are outside of the data memory
area, or when the number of pieces of data defined by OP3 exceeds the
specified value.

When X001 is ON and the contents of the 3bytes starting at lower 8bits of D0000 matches the
contents of the 3bytes starting at lower 8bits of D0100,fills the latter area with "0".
5-179
58. WCLR Matching data clearance (Word) (FUN 167)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Compares area starting at OP1 address and containing the number of pieces of data specified
by OP3 with the area starting at OP2 address and containing the number of pieces of data
specified by OP3 and clears the latter area (zeroes all data) if the data in both areas match. The
maximum number of transferable pieces of data is 512.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set upon execution of clear.

Error flag(ER) : Is set when devices in the comparison areas are outside of the data memory
area, or when the number of pieces of data defined by OP3 exceeds the
specified value.

When X002 is ON and the contents of 512 Words starting at D0000 match the contents of 512
Words starting at D0100, fills the latter area With "0".
5-180
!#
59. REF External input transfer (FUN 283)
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Transfers the bytes of external input data specified by OP3 from OP1 address to the area
starting at OP2 address.
(Input refresh for the specified area is carried out before transfer.) Input from the re11ote I/O is
not possible.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the transfer source or destination area exceeds the usable
device area.

When M005 is ON, transfers 32 points(4-byte) of external data from X0000 to 4-byte area
starting with D000L.
5-181
!#
60. REFO External output transfer (FUN 284)
(1) Usable devices
PC3 / PC2 OP2 O
OP3 O
OP2
extended
OP3
(3) Symbol
(4) Function
Transfers the bytes of external output data specified by OP3 from OP1 address to the output
starting at OP2 address.
(Output refresh for the specified area is carried out after transfer.)
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the source or destination device exceeds the usable device
area.

When M007 is ON, transfers the 4bytes starting at D0002L to the 32 (4-byte) points of external
output starting at Y068.
5-182
%&
61. MOVJ 1-byte transfer from register to file register (FUN 144)
(1) Usable devices
OP2 O
extended OP2
(3) Symbol
(4) Function
Transfers the content of OP1 register to OP2 file register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the location at destination address is not file register area.

Transfers thc content of upper 8-bitfield of D0094 to lower 8-bit field of B0000 after the OFF to
ON transition of M000.
5-183
%&
62. WMOVJ 2-byte transfer from register to file register (FUN 145)
(1) Usable devices
OP2 O
extended OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the content of D0095 to B0001 after the OFF to ON transition of M001.
5-184
%&
63. DMOVJ 4-byte transfer from register to file register (FUN 146)
(1) Usable devices
OP2 O
extended OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

Transfers the contents of D0097 and D0096 to B0003 and B0002 after the OFF to ON transition
of M002.
5-185
%&
64. MOVK 1-byte transfer from file register to register (FUN 147)
(1) Usable devices
PC3 / PC2 OP1 O
PC3 OP1
(3) Symbol
(4) Function
Transfers the content of OP1 file register to OP2register.
(5) Flag
No change

Transfers the content of upper 8-bit field of B0004 to lower 8-bit field of D0098 after the OFF to
ON transition of M003.
5-186
%&
65. WMOVK 2-byte transfer from file register to register (FUN 148)
(1) Usable devices
PC3 / PC2 OP1 O
PC3 OP1
(3) Symbol
(4) Function
(5) Flag
No change

Transfers the content of B0005 to D0099 after the OFF to ON transition of M004.
5-187
%&
66. DMOVK 4-byte transfer from file register to register (FUN 149)
(1) Usable devices
PC3 / PC2 OP1 O
PC3 OP1
(3) Symbol
(4) Function
(5) Flag
No change

Transfers the contents of B0007 and B0006 to D0101 and D0100 after the OFF to ON transition
of M005.
5-188
5.4.2. Arithmetic operations
Instructions which carry out arithmetic operation on contents of registers are divided into the
following four.
Addition................Adds data of register to another register and stores the result into another
register.
Subtraction...........Subtracts data of register from another register and stores the result into
another register.
Multiplication........Multiplies data of register with another register and stores the result into
another register.
Division................Divides data of register by data of another register and stores the register
into another register.
5-189
67. + Byte data binary addition (FUN 168)
(1) Usable devices
extended
(3) Symbol
(4) Function
Adds the content of OP1 register to that of OP2 and stores the result to OP3 register. All data is
processed as binary numbers.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set when a carry is generated in add operation.

Zero flag(Z) : Is set when add operation results in 0.

When X000 is ON, adds the content of lower 8bits of D0145 to the content of D0146 upper 8bits
and stores the result into D0147 lower 8bits.
5-190
68. W+ Word data binary addition (FUN 92)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑


When X001 is ON, adds the current value of counter C000 (content of N000) to the current
value of counter C001 (content of N001) and stores the result into D0234.
5-191
69. D+ 32-bit data binary addition (FUN 169)
(1) Usable devices
extended
(3) Symbol
D+
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑


When M000 turns ON from OFF, adds the contents of D0149 and D0148 to the contents of
D014B and D014A and stores the result into D014D and D014C.
5-192
70. +P 2-digit BCD addition (FUN 177)
(1) Usable devices
extended
(3) Symbol
(4) Function
Adds the content of OP1 register to that of OP2 register, both as BCD codes, and stores the
resultant BCD codes into OP3 register.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑

Error flag(ER) : Is set if content of OP1 register or OP2 register is not in BCD format

Adds BCD 2-digit input data into X000-X007 to BCD 2-digit input data into X008-X00F and
stores the result into lower 8 bits of D0000.
5-193
71. W+P 4-digit BCD addition (FUN 10)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑


When X010 is ON, adds BCD 4-digit data stored in D0123 to that of D0234 and outputs the
result into Y000-Y00F.
5-194
72. D+P 8-digit BCD addition (FUN 178)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑


When M000 changes from OFF to ON, adds BCD 8-digit data stored in D0149 and D0148 to
that of D014B and D014A and stores the result into D014D and D014C.
5-195
73. - Byte data binary subtraction (FUN 170)
(1) Usable devices
extended
(3) Symbol
(4) Function
Subtracts the content of OP2 register from that of OP1 register and stores the result into OP3
register. All data in binary format.
(5) Flag
CY BO Z > = < ER
↑ ↑
Borrow flag(BO) : Is set when subtract operation results in a borrow (negative carry)(the
content of OP2 is larger than that of OP1).
Zero flag(Z) : Is set when subtract operation results in 0.

When X000 is ON, subtracts the content of D0146 upper 8bits from the content of D0145 lower
8bits and stores the result into D0147 lower 8bits.
5-196
74. W- Word data binary subtraction (FUN 93)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When X001 is ON, subtracts the current value of counter C001 (content of N001) from the
current value of counter C001 (content of N000) and stores the result into D0234.
5-197
75. D- 32-bit data binary subtraction (FUN 171)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M000 turns ON from OFF, subtracts the contents of D014B and D014A from the contents
of D0149 and D0148 and stores the result into D014D and D014C.
5-198
76. -P 2-digit BCD subtraction (FUN 179)
(1) Usable devices
extended
(3) Symbol
(4) Function
Subtracts the content(BCD code)of OP2register from that(BCD code)of OP1 register and
stores the result into OP3register in BCD code.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
Borrow flag(BO) : Is set when subtract operation results in a borrow(negative carry)(the

Error flag(ER) : Is set when the content of OP1 register or OP2 register is not in BCD
format.

Subtracts BCD 2-digit data inputted into X008-X00F from BCD 2-digit data inputted into X000-
X007 and stores the result into lower 8bits of D0000.
5-199
77. W-P 4-digit BCD subtraction (FUN 11)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑

format.

When X010 is ON, subtracts BCD 4-digit data stored in D0234 from that of D1234 and outputs
the result to Y020-Y02F.
5-200
78. D-P 8-digit BCD subtraction (FUN 180)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑

format.

When M000 changes from OFF to ON, subtracts BCD8-digit data stored in D014B and D014A
from that of D0149 and D0148 and stores the result into D014D and D014C.
5-201
79. * Byte data binary multiplication (FUN 172)
(1) Usable devices
extended
(3) Symbol
(4) Function
Multiplies contents of OP1 and OP2 registers and stores the result into OP3 register. All data
handled as binary numbers.
(5) Flag
No change

When X000 is ON, multiplies content of D0145 lower 8bits with that of D0146 upper 8bits and
stores the result into D0147 16bits.
5-202
80. W* Word data binary multiplication (FUN 94)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
No change

When X001 is ON, multiplies the current value(content of N000)of counter C000 with the
current value(content of N001)of C001 and stores the result into D0234 and D0235.
5-203
81. D* 32-bit data binary multiplication (FUN 173)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
No change

When M000 changes from OFF to ON, multiplies content of D0149 and D0148 with D014B and
D014A and stores the result into D014D and D014C, and D014D and D014E.
5-204
82. *P 2-digit BCD multiplication (FUN 181)
(1) Usable devices
extended
(3) Symbol
(4) Function
Multiplies the contents of OP1 and OP2 registers as BCD code and stores the resultant BCD
code into OP3 register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the content of OP1 register or OP2 register is not in BCD format.

Multiplies BCD2-digit data inputted in to X000-X007 with BCD 2-digit data inputted into X008-
X00F and stores the result into 16bits of D000.
5-205
83. W*P 4-digit BCD multiplication (FUN 182)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X010 is ON, multiplies BCD 4-digit data stored in D0123 with that in D0234 and outputs
the result to Y000-Y01F.
5-206
84. D*P 8-digit BCD multiplication (FUN 183)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
When M000 turns ONfrou1OFF, multiplies BCD 8-digit data stored in D0149 and D0148 with
that in D014B and D014A and stores the result into D014D and D014C, and D014D and D014E.
5-207
85. W/B Word data binary division 1 (FUN 95)
(1) Usable devices
extended
(3) Symbol
(4) Function
Divides the content of OP1 register by that of OP2 register and stores the quotient into OP3
register and the remainder into the register at the address following that of OP3.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the content of OP2 register is ON.

When M000 is ON, divides the content of D0123 by the content of D0206 lower 8bits and stores
the quotient into D0234 and the remainder into D0235.
5-208
#
86. / Byte data binary division (FUN 174)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, divides the content of D0145 lower 8bits by the content of D0146 upper 8bits
and stores the quotient into D0147 lower bits and the remainder into D0147 upper 8 bits.
5-209
#
87. W/ Word data binary division 2 (FUN 175)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X001 is ON, divides the current value of counter C000 (content of N000) by the current
value of counter C001 (content of N001) and stores the quotient into D0234 and the remainder
into D0234.
5-210
#
88. D/ 32-bit data binary division (FUN 176)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M000 turns ON from OFF, divides the contents of D0182 and D0181 by the contents of
D0184 and D0183 and stores the quotient into D0186 and D0185 and the remainder into D0188
and D0187.
5-211
89. /P 2-digit BCD division (FUN 184)
(1) Usable devices
extended
(3) Symbol
(4) Function
Divides the content of OP1 register(BCD code) by the content of OP2 register (BCD code) and
stores the quotient into OP3 register and the remainder into the register at the address
following that of OP3.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the content of OP1 register or OP2 register is not in BCD format
or when the content of OP2 register is 0.

Divides BCD 2-digit data inputted into X000-X007 by BCD 2-digit data inputted into X008-X00F
and stores the quotient into D0000 lower 8bits and the remainder into D0000 upper 8bits.
5-212
90. W/P 4-digit BCD division (FUN 185)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X010 is ON, divides. BCD4-digit data stored in D0224 by BCD4-digit data stored in
D0225 and outputs the quotient to Y000-Y00F and the remainder to Y010-Y01F.
5-213
91. D/P 8-digit BCD division (FUN 186)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M000 turns ON from OFF, BCD8-digit data stored in D0228 and D0227 by BCD 8-digit
data stored in D022A and D0229 and stores the quotient into D022C and D022B and the
remainder into D022E and D022D.
5-214
5.4.3 Logical operation instructions
Instructions carrying out logical operations on contents of registers are classified as follows.
Logical product (AND)…….Carries out AND operation between data in registers and stores the
result into another register.
Logical sum (OR)…………..Carries out OR operation between data in registers and stores the
result into another register.
Inversion (NOT)…………....Inverts register data and stores the result into another register.
Exclusive logical sum ……..Carries out exclusive OR between register (XOR) data and stores
the result into another register.
5-215
92. AND Byte data logical product(AND) (FUN 13)
(1) Usable devices
extended
(3) Symbol
(4) Function
Carries out AND operation between contents of OP1 and OP2 registers and stores the result
into OP3 register.
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z) : Is set when the operation result is 0.

When X000is ON, carries out AND operation between X010-X017 data and lower 8bits of
D0123 and outputs the result to Y018-Y01F.
5-216
93. WAND Word data logical product(AND) (FUN 187)
(1) Usable devices
extended
(3) Symbol
(4) Function
into OP3 register.
(5) Flag
CY BO Z > = < ER
↑

When X001 is ON, sets the highest digit of BCD 4-digit data stored in D0234 to 0 and stores the
result back into D0234.
5-217
94. DAND 32-bit data logical product(AND) (FUN 188)
(1) Usable devices
extended
(3) Symbol
(4) Function
into OP3 register.
(5) Flag
CY BO Z > = < ER
↑

When M000 is ON, carries out AND operation between the contents of D0237 and D0236 and
the contents of D0239 and D0238 and outputs the result to Y000-Y01F.
5-218
95. OR Byte data logical sum(OR) (FUN 14)
(1) Usable devices
extended
(3) Symbol
(4) Function
Carries out OR operation between contents of OP1 and OP2 registers and stores the result into
OP3register.
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z) : Is set when the result is 0.

When X000 is ON, carries out OR operation between X010-X017 data and lower 8bits of D0123
and outputs the result to Y018-Y01F.
5-219
96. WOR Word data logical sum(OR) (FUN 189)
(1) Usable devices
extended
(3) Symbol
(4) Function
OP3register.
(5) Flag
CY BO Z > = < ER
↑

When X001 is ON, sets the upper 8bits of data stored in D0234 to "1".
5-220
97. DOR 32-bit data logical sum(OR) (FUN 190)
(1) Usable devices
extended
(3) Symbol
(4) Function
OP3register.
(5) Flag
CY BO Z > = < ER
↑

When M000 is ON, carries out OR operation between the contents of D237 and D236, and
D239 and D238, and outputs the result to Y000-Y01F.
5-221
98. NOT Byte data inversion (FUN 9)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Inverts the contents of OP1 register ("1"bit to "0" and "0" bit to "1") and stores them into OP2
register.
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, inverts all ON/OFF data of X010·X017 and outputs the result to Y018-Y01F.
5-222
99. WNOT Word data inversion (FUN 191)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
register.
(5) Flag
CY BO Z > = < ER
↑

When X001 turns ON from OFF, inverts the data stored in D0234 and stores the result back to
D0234.
5-223
100. DNOT 32-bit data inversion (FUN 192)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
register.
(5) Flag
CY BO Z > = < ER
↑

When M000 is ON, inverts the data stored in D0254 and D0233 and stores the result to D0256
and D0255.
5-224
101. XOR Byte data exclusive logical sum(XOR) (FUN 18)
(1) Usable devices
extended
(3) Symbol
(4) Function
Carries out exclusive OR (XOR) between contents of OP1 and OP2 registers and stores the
result into OP3 register.
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z) : Set when the result is 0.

When X000is ON, carries out XOR operation between X010-X017 data and lower 8bits of
D0123 and outputs the result to Y018-Y01F.
5-225
102. WXOR Word data exclusive logical sum(XOR) (FUN 193)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z) : Set when the result is 0.

When X001 is ON, carries out XOR operation between the content of D0233 and the content of
D0234 and stores the result into D0235.
5-226
103. DXOR 32-bit data exclusive logical sum(XOR) (FUN 194)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z): Set when the result is 0.

When M000 is ON, carries out XOR operation between the contents of D0237 and D0236 and
the contents of D0239 and D0238 and outputs the result to Y000-Y01F.
5-227
5.4.4 Increment and decrement
Execution of this instruction will increment or decrement data by one.
Increment……..Increases data value by 1.
Decrement……..Decreases data value by 1.
5-228
104. INC Byte data binary increment (FUN 195)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Increments the content of OP2 register by l and compares the new value with the content of
OP1 register. Data is regarded as binary numbers.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
Carry flag(CY) : Is set when the content of OP2 register overflows after operation.
Zero flag(Z) : Is set when the content of OP2 register is 0 after operation.
Equal flag(=) : Is set when contents of OP2and OP1 registers are verified coincident by the
operation.

When X000changes from OFF to ON, increments the content of lower 8bits of D0266 by 1 and
if the result overflows, sets Y010 to ON.
5-229
105. WINC Word data binary increment (FUN 63)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
operation.

Increments the content of D1234 by 1 upon the OFF to ON transition of X001.
(D0123 of OP1 has no effect on operation.)
5-230
106. DINC 32-bit data binary increment (FUN 196)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
operation.

When M000 changes from OFF to ON, increments the content of D0269 and D0268 by 1 and if
the result is "FFFFFFFF" (hex), sets Y010 to ON.
5-231
107. INCP 2-digit BCD increment (FUN 199)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Increments the content of OP2 register by 1 and compares the new value with the content of
OP1 register. Data is regarded as BCD numbers.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑ ↑
Equal flag(=) : Is set when contents of OP2 and OP1 register are verified coincident by the
operation.
Error flag(ER) : Is set When content of OP1 register or OP2 register is not in BCD format.

When X000 changes from OFF to ON, increments BCD data stored in the lower 8bits of D0273
by 1 and if the result reaches "50", sets Y010 to ON.
5-232
108. WINCP 4-digit BCD increment (FUN 200)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑ ↑
operation.

Increments BCD data stored in D0275 by 1 upon the OFF to ON transition of X001. (D0275of
OP1 has no effect on operation.)
5-233
109. DINCP 8-digit BCD increment (FUN 201)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑ ↑
operation.

Counts ONs of M000 in BCD number and turns on Y010 when the counter reaches "50000000"
5-234
110. DEC Byte data binary decrement (FUN 197)
(1) Usable devices

PC3 / PC2
(3) Symbol
(4) Function
Decrements content of OP1 register by 1. Data is regarded as binary numbers.
(5) Flag
CY BO Z > = < ER
↑ ↑
Borrow flag(BO) : Is set if the operation results in negative, i.e. the data before operation
was 0.

When X000 changes from OFF to ON, decrements lower 8bits of D0271 by 1.
5-235
111. WDEC Word data binary decrement (FUN 64)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑
was 0.

When X001 changes from OFF to ON, decrements content of D0123 by 1 and if the result is 0,
sets Y010 to ON.
5-236
112. DDEC 32-bit data binary decrement (FUN 198)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑
was 0.

When M000 changes from OFF to ON, decrements content of D0273 and D0272 by 1.
5-237
113. DECP 2-digit BCD decrement (FUN 202)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
Decrements content of OP1 register by 1. Data is regarded as BCD numbers.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
was 0.
Error flag(ER) : Is set when the content of OP1 register is not in BCD format.

When X000 changes from OFF to ON, decrements BCD data stored in lower 8bits of D0281 by
1.
5-238
114. WDECP 4-digit BCD decrement (FUN 203)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
was 0.

When X001 changes from OFF to ON, decrements BCD data stored in D0282 by 1 and if the
result is 0, sets Y010 to on.
5-239
115. DDECP 8-digit BCD decrement (FUN 204)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
was 0.

When M000 changes from OFF to ON, decrements BCD data stored in D0284 and D0283by 1.
5-240
5.4.5. Search
Instruction used to locate specified data in a group of data.
5-241
116. SRH1 Byte data search 1 (FUN 88)
(1) Usable devices
extended
(3) Symbol
(4) Function
Searches the locations from OP2 address to OP3 address for data that matches the content of
OP1 register and when it is found, sets the carry flag (CY). Then stores the location data (Nth
address with respect to OP2 address =0) into the register following OP1.
When the same data exists in different locations, lowest-address location is given the highest
priority. SRH1 can cover up to 256-byte length.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set when the data designated by OP1 exists in the specified range.
Error flag(ER) : Is set when the area is outside of the data memory area or larger than the
specified value or when the OP2 address is larger than OP3 address.
5-242
When X000 is ON, searches the area from D0100 lower byte to D017F upper byte for the data
that matches the content of D0000 lower byte register. When the data is found, sets the carry
flag(CY)and stores the location data into the D0000 upper byte register.
5-243
117. WSRH1 Word data search 1 (FUN 89)
(1) Usable devices
extended
(3) Symbol
(4) Function
Searches the locations from OP2 address to OP3 address for data that matches the content of
OP1 register and when it is found, sets the carry flag (CY). Then stores the location data (Nth
address with respect to OP2 address =0) into the register following OP1.
When the same data exists in different locations, lowest-address location is given the highest
priority. WSRH1 can search up to 512 words.
(5) Flag
CY BO Z > = < ER
↑ ↑
specified value or when the OP2 address is larger than OP3 address.
5-244
When X000 is ON, searches the area between D0100 and D01FF for the data that matches the
content of D0000 register. When the data is found, sets the carry flag (CY) and stores the
location data in the D0001 register.
5-245
118. SRH2 Byte data search 2 (FUN 212)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Searches the area, starting at OP2 address and containing the number of data specified by
OP3, for the data matching the content of OP1 register. If found, sets carry flag(CY) and stores
the location data(the Nth address with respect to OP2 address =1) into the word address
location following OP1.
Also stores the number of pieces of coincident data into address location next to the address
following the OP1 address. The maximum area can be searched is 256 pieces of data long.
(5) Flag
CY BO Z > = < ER
↑ ↑
specified value.
5-246
When X000 is ON, searches the area, starting at D0100 lower byte and containing the number
of pieces of data specified by OP3,for the data matching the content of D0000 lower byte
register. If found, sets the carry flag (CY),stores the location data into D0001 and the number of
coincident data into D0002.
5-247
119. WSRH2 Word data search 2 (FUN 213)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑
specified value.
5-248
When X000 is ON, searches the area, starting at D1000 and containing the number of pieces of
data specified by OP3, for the data matching the content of D0000 register. If found, sets the
carry flag(CY),stores the location data into D0001 and the number of pieces of coincident data
into D0002.
5-249
120. DSRH 32-bit data Search (FUN 214)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑
specified value.
5-250
When X000is ON, searches the area, starting at D0100 and D0101, and containing the number
of data specified by OP3, for the data matching the content of D0000 and D0001 registers. If
found, sets the carry flag(CY), stores the location data into D0002 and the number of pieces of
coincident data into D0002.
5-251
5.4.6 Parity
This instruction is used to give data a parity bit and to perform parity check. The instruction is
classified as follows.
Parity bit composition…..Sets or resets the highest bit in the data and carries an even or odd
parity in the data.
Parity check……………..Tests data for parity.
5-252
121. MKP1 Odd parity composition (FUN 83)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
MKP1 sets or resets the highest bit (bit 7) of the content of OP1 register so that there are an
odd number of one-bits in the 8bits. The altered content carrying odd parity is stored into the
OP2 address location.
(5) Flag
No change

When X000 is ON, sets or resets the highest bit(bit 7) of lower byte of D0000 to have odd
number of is in the content, and stores the altered bits into D0000 upper byte address location.
5-253
122. MKP2 Even parity composition (FUN 81)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
MKP1 sets or resets the highest bit (bit 7) of the content of OP1 register so that there are an
odd number of one-bits in the 8bits. The altered content carrying odd parity is stored into the
OP2 address location.
(5) Flag
No change

When X000 is ON, sets or resets the highest bit(bit 7) of lower byte of D0000 to have even
number of is in the content, and stores the altered bits into D0000 upper byte address location.
5-254
123. PCH1 Odd parity check (FUN 84)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
Tests the parity of the content of register specified. PCH1 will set carry flag(CY) if the number of
one-bits in the data is not odd.
(5) Flag
CY BO Z > = < ER
↑
Carry flag(CY) : Is set if an error is found in the specified data by the parity check, i.e. the
number of one-bits is not odd(when tested by PCH1).

When X000 is ON, tests D0000 lower byte register for parity and if the number of one-bits is not
odd, sets the carry flag(CY).
5-255
124. PCH2 Even Parity check (FUN 82)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
Tests the parity of the content of register specified. PCH1 will set carry flag(CY) if the number of
one-bits in the data is not odd.
(5) Flag
CY BO Z > = < ER
↑
Carry flag(CY) : Is set if an error is found in the specified data by the parity check, i.e. the
number of one-bits is not odd(when tested by PCH1).

When X000 is ON, tests D0000 lower byte register for parity and if the number of one-bits is not
even, sets the carry flag(CY).
5-256
5.4.7. Data conversion
Used to convert data format and are classified into the following.
BCD to binary…….........Converts BCD format data into binary data.
Binary to BCD……........Coverts binary data into BCD data.
JIS to binary……….......Coverts JIS code representing numeric values to binary data.
Binary to JIS……………Converts binary data to JIS code expressions.
4 to 16 decoder………..Sets one of 16 bits which represents equivalent of the value expressed

by 4-bit binary.
16 to 4 decoder………..Sets bit(s) in a set of 4 bits which represents equivalent of the value

expressed by one of 16 bits.
7 segment decode…….Generates code for 7-seg display.
Hours, minutes, ……….Converts time data consisting of hours, minutes and seconds
seconds, to seconds into integrated second data only.
Seconds to hours, …….Converts seconds data into three-part data : seconds, minutes
minutes and seconds and hours.
Code conversion………Prepares data conversion table and converts data by consulting this
table.
5-257
125. BIN 2-digit BCD to 8-bit binary (FUN 152)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Converts BCD data stored in OP1 register into binary data and stores it into OP2register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the data stored in OP1 register is not in BCD format.

When X000 is ON, converts 2-digit BCD data stored in the lower byte of D0000 into binary data
and stores the new data in the upper byte of D0000.
5-258
126. WBIN 4-digit BCD to 16-bit binary (FUN 3)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, converts 4-digit BCD data stored in D0000 into binary data and stores the
new data into D0001.
5-259
127. DBIN 8-bit BCD to 32-bit binary (FUN 153)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, converts 8-digit BCD data stored in D0001 and D0000 into binary data and
stores the new data into D0003 and D0002.
5-260
128. BCD 8-bit binary to 2-digit BCD (FUN 154)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Converts binary data stored in OP1 register into BCD data and stores it into OP2 register.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the BCD code converted from OP1 register data exceeds the
maximum limit value: 99 when BCD, 9999 when WBCD and 99999999 when
DBCD.

When X000 is ON, converts binary data stored in the lower byte of D0000L into 2-digit BCD
data and stores the new data into D0000H.
5-261
129. WBCD 16-bit binary to 4-bit BCD (FUN 4)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
DBCD.

When X000 is ON, converts binary data stored in D0000 into 4-digit BCD data and stores the
new data into D0001.
5-262
130. DBCD 32-bit binary to 8-digit BCD (FUN 155)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
DBCD.

When X000 is ON, converts binary data stored in D0001 and D0000 into 8-digit BCD data
and-stores the new data into D0003 and D0002.
5-263
131. JBIN JIS code to binary (FUN 156)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Interprets a string of JIS code data, starting at OP1 address and equivalent of the number of
characters specified by OP3, as hexadecimal numeric values and converts this data into binary
values and then stores them into an area starting at OP2 address. The maximum number of
convertable pieces of data is 32.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the JIS code data read from OP1 has a character representing other
than hexadecimal value (0 to 9,A to F), or if the number of characters
defined by OP3 is greater than 32.
1) When X100 is ON, converts JIS codes equivalent of 5 characters in the lower byte of
D0123 and subsequent into binary numbers and stores them into area starting address of
lower byte of D0160.
Mark* shows no change.

(remains as it was before execution)
5-264
2) When X101 is ON, converts JIS codes equivalent of 4 characters in X11F input card from
X100 into binary numbers and stores them into an area starting at address of lower byte of
D100.
E8
(E)
5-265
132. BJIS Binary to JIS code (FUN 157)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Interprets the binary data stored, starting at OP1 address, as hexadecimal numeric value with
the number of characters specified by OP3, and converts the data into JIS codes and then
stores them into area starting at OP2 address.
The maximum number of convertable pieces of data is 32.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the number of digits specified by OP3 exceeds 32.

1) When X100 is ON, converts binary data stored in D013F lower byte and subsequent bytes,
equivalent of 6 digits, into JIS code and stores them into area starting with address of the
lower byte of D0120.
5-266
2) When X101 is ON, converts binary data stored in D0150 lower byte and subsequent bytes,
equivalent of 4digits, into JIS code and outputs them to Y100-Y11F output card.
6D 44 (D)
5-267
133. DECO 4 to 16 decoder (FUN 50)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Decodes lower 4 bits of the content of OP1 register into 16-bit data and stores it in OP2
address location.
(5) Flag
No change

1) When X100 is ON, decodes lower 4 bits of D0110 lower byte into 16-bit data and stores it
into D0125.
5-268
2) When X001 is ON, decodes lower 4 Points of input cards, X100-X107, and distributes the
decoded data to output cards, M000-Y10F.
5-269
134. ENCO 16 to 4 encoder (FUN 51)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Converts the decimal Place(s) (0-15) represented by ON-bit ("1") of 16-bit content of OP1
register into binary equivalents and stores the resultant bits into lower 4-bit field of OP2
register.
If there is more than one ON-bit, lower one has priority. If no ON-bit, zero flag(Z) is set and
content of OP2 register remains unchanged.
(5) Flag
CY BO Z > = < ER
↑
Zero flag(Z) : Is set if the 16-bit content of OP1 register is all OFF(filled with 0).

1) When X100is ON, encodes the data of D0200(finds ON-bit) and stores the equivalent value
in the lower 4bits of D0210 lower byte.
B4-b7 of D0210L are retained as they

were before execution.
No change
5-270
2) When X101 is ON, encodes the data of D0220 and routes the result to lower 4points of
output cards, Y100-Y10F.
5-271
135. SEG 7-segment decode (FUN 52)
(1) Usable devices
OP3 O
extended
OP3
(3) Symbol
(4) Function
Converts the 4-bit binary data in the area from OP1 and subsequent addresses into 7segment
display drive data and stores them into the area starting with OP2 address. Repeats this for the
number of digits specified by OP3.The maximum number of convertable digits is 256.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set When the conversion source and destination are outside of the data
memory area or when the number of digits specified exceeds the specified
value.
5-272
When X100 is ON, converts data for each of specified 3 digits, stored in the area starting at
D0175 and subsequent locations, into 7-seg data and outputs them to output cards, Y000 and
subsequent cards thereafter.
1st digit
2nd digit
3rddigit
5-273
136. WTIM1 Hours, minutes, and seconds to seconds (FUN 158)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Converts hours, minutes and seconds data in BCD format stored in 4-byte area starting at OP1
address (where data is 0.1 second followed by seconds, minutes and hours in that order) into
binary data in unit of 0.1sec. and stores the data in OP2 address location.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if time data is not in BCD format, or if the total number of 0.1-sec data
after conversion exceeds 65535.

1) When X100 is ON, converts hours, minutes and seconds BCD data stored in D0120 lower
byte and subsequent locations into second data and stores it in D0240.
5-274
2) When X001 is ON, converts hours, minutes and seconds data coming in input cards,
X100-X11F,in BCD format, into second data and stores it in D0250.
5-275
137. WTIM2 Seconds to hours, minutes and seconds (FUN 159)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Assumes the contents of OP1 register as a set of 0.1 second data in binary format and converts
it into hours, minutes and seconds data in BCD format and then stores it separately into
locations starting with OP2 address (where data is 0.1 second followed by seconds, minutes
and hours in that order).
(5) Flag
No change

1) When X100 is ON, converts binary data stored in D0150 into BCD data of hours, minutes,
seconds and 0.1 second and then stores it into 41-byte locations, independently, starting
with D0200 lower byte.
5-276
2) When X101 is ON, converts binary data stored in the timer current value register N000 into
hours, minutes, seconds and 0.1 second data of BCD format and then stores it into
locations starting with D0170 lower byte.
5-277
138. CDSET Code conversion set (FUN 85)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the content of OP1 register to the register addressed by the sum of OP3 address and
the content of OP2 register. The content of OP2 register is in BCD format.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set When the transfer destination is outside of the data area or when the
content of OP2 register is not in BCD format.

When X100 is ON, transfers the data stored in the lower byte of-D0110 to the register
addressed by the sum of D0200 lower byte data and D0120 address.
If 04 is stored in D0200L, adding this 04 to D0120L makes register address D0122L to which
the content value, 3E, of D0110L is transferred.
5-278
139. CDO1 Code conversion output 1 (FUN 86)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the content of the register addressed by the sum of OP2 address and the content
OP1 register to OP3 register. The content of OP1 register is treated in BCD format.
(5) Flag
CY BO Z > = < ER
↑
when the content of OP2 register is not in BCD format.

When X100 is ON, transfers the data stored in the lower byte of D0140 and the content of the
register address, with D0160L added, to the lower byte of D0190.
If 05 is stored in D0140L, adding D0160L makes register address D0162H whose data, D7, is
stored into D0190L.
5-279
140. CDO2 Code conversion output 2 (FUN 87)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the BCD data in the register addressed by(OP2 address added with content of OP1
register) to the location addressed by (incremented-by-1 OP3 address). Also converts the BCD
data into binary data and transfers it to OP3 register. The content of OP1 register is treated as
BCD.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the source data or content of OP1 register is not in BCD format,
or when the transfer source is outside of the data memory area.

When X100 is ON, transfers BCD data (56) stored in the register addressed by (sum of the
content of D0100 lower byte and the lower byte of D0200) to the upper byte of D0220. Also
converts the BCD data into binary numbers and transfers it to the lower byte of D0220.
5-280
5.4.8 Comparison
Instruction used to compare the size of data.
5-281
141. CP Byte data comparison (FUN 17)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Compares contents of OP1 and OP2 registers and sets either of >, = or < flag, depending on
which one of the contents is larger.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
Greater-than flag(>) : Is set if the content of OP1 register is greater than that of OP2 register.
Equal flag (=) : Is set if the content of OP1 register equals that of OP2 register.
Less-than flag(<) : Is set if the content of OP1 register is smaller than that of OP2 register.

When X000 is ON, compares upper 8 bits of D000 and lower 8 bits of D0100 and sets or
resets appropriate flag.
5-282
142. WCP Word data comparison (FUN 12)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑

When X000 is ON, compares upper 8 bits of D0100 and that of D0200 and sets or resets
appropriate flag.
5-283
143. DCP 32-bit data comparison (FUN 211)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑

When M000 is ON, compares the contents of D0201 and D0200 and those of D0301 and D0300
and sets or resets appropriate flag.
5-284
5.4.9. Bit operation
Used to test ON or OFF state of bits and to set or reset a bit. The instructions are classified as
follows :
Bit set……………..Sets (ON) the specified bit.
Bit reset…………...Resets (OFF) the specified bit.
Bit extraction………Tests the status (ON/OFF) of the specified bit.
ON-bit count………..Counts the number of ON-state bits in the specified data.
5-285
144. BSET Byte data bit set (FUN 136) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Sets a bit(s) to ON ("1") in the content of OP2 register, when that bit(s) is designated by the
content of OP1 register.
The number of OP1 register bits used with bit set instruction differs between instructions: lower
3 bits (0 - 7) for BSET with remaining upper bits made ignored, respectively.
(5) Flag
No change

When X000 is ON, sets bit 3 of D0000L. If D0000 = 1 before execution of this instruction, then
D0000 = 9 after execution.
5-286
145. WBSET Word data set (FUN 137)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
4 bits (0 - 15) for WBSET with remaining upper bits made ignored, respectively.
(5) Flag
No change

When X001 is ON, sets bit 10 of D0200. If D0200 = 8000H before execution of this instruction,
then D0200 = 8400H after execution.
5-287
146. DBSET 32-bit data bit set (FUN 138) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
5 bits (0 - 31) for DBSET with remaining upper bits made ignored, respectively.
(5) Flag
No change

When M000 is ON, sets bit 16 (bit 0 of D0101) of D0101 and D0100. If D0101 and D0100 =
12345678H before execution of this instruction, then D0101 and D0100 = 12345678H after
execution.
5-288
147. BRST Byte data bit reset (FUN 139) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Resets a bit(s) to OFF ("0") in the content of OP2 register, when that bit is designated by the
The number of OP1 register bits used with bit reset instruction differs between instructions:
lower 3 bits (0 - 7) for BRST with remaining upper bits ignored, respectively.
(5) Flag
No change

When X000 is ON, resets bit 0 of D0000L. If D0000 = 1 before execution of this instruction,
then D0000 = 0 after execution.
5-289
148. WBRST Word data bit reset (FUN 140)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
lower 4 bits (0 - 15) for WBRST with remaining upper bits ignored, respectively.
(5) Flag
No change

When X001 is ON, resets bit 15. If D0200 = 8123H before execution of this instruction, then
D0200 = 0123H after execution.
5-290
149. DBRST 32-bit data bit reset (FUN 141) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
lower 5 bits (0 - 31) for DBRST with remaining upper bits ignored, respectively.
(5) Flag
No change

When M000 is ON, resets bit 31 (bit 15 of D0101) at D0101 and D0100. If D0101 and D0100 =
98765432H before execution of this instruction, then D0101 and D0100 = 88765432H after
execution.
5-291
150.BPU Bit extraction (FUN 54) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Transfers a bit in the content of OP2 register, when that bit is designated by the content of
OP1 register, to the carry flag (CY).
The number of OP1 register bits used between instructions: lower 3 bits (0 - 7) for BPU with
remaining upper bits ignored, respectively.
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY): Is set if the designated bit is "1".

When M000 is ON, transfers the state of bit 10 of D0090H to the carry flag (CY).
IF D0090H = 0300H, then execution of this instruction resets the carry flag (CY).
7d
5-292
151. WBPU Word data bit extraction (FUN 142)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Transfers a bit in the content of OP2 register, when that bit is designated by the content of OP1
register, to the carry flag (CY).
The number of OP1 register bits used between instructions: lower 4 bits (0 - 15) for WBPU
with remaining upper bits ignored, respectively.
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, transfers the state of bit 9 of D0000 to the carry flag (CY).
IF D0000 = 0200H, then execution of this instruction sets the carry flag (CY), leaving D000
unchanged.
5-293
152. DBPU 32-bit data extraction (FUN 143) *
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Transfers a bit in the content of OP2 register, when that bit is designated by the content of OP1
register, to the carry flag (CY).
The number of OP1 register bits used between instructions: lower 5 bits (0 - 31) for DBPU
with remaining upper bits ignored, respectively.
(5) Flag
CY BO Z > = < ER
↑

When X001 is ON, transfers the state of bit 17 of D0101 and D0100 (bit 1 of D0101) to the carry
flag (CY).
IF D0101 and D0100 = FFFD and FFFFH, then execution of this instruction resets the carry flag
(CY).
5-294
153. SUM Byte data ON-bit count (FUN 208)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Count all ON-bits ("1" level) in the content of OP1 register and stores the number data into
OP2.
(5) Flag
No change

When X000 is ON, stores the total number of "1" bits in D0000L into D0100L. When D0000L =
95H, then D0100L = 4H after execution of this instruction.
5-295
154. WSUM Word data ON-bit count (FUN 209)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
OP2.
(5) Flag
No change

When X001 is ON, stores the total number of "1" bits in D0200 into D0300L. When D0200 =
1234H, then D0300L = 5H after execution of this instruction.
5-296
155. DSUM 32-bit data ON-bit count (FUN 210)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
OP2.
(5) Flag
No change

When M000 is ON, stores the total number of "1" bits in D0100 and D0101 into D0200L. When
D0101 and D0100 = FFFFFFFFH, then D0200L = 20H after execution of this instruction.
5-297
5.4.10 Shift
Instructions used for shifting which are classified as follows :
1 bit shift……….Shifts data left or right 1 bit position.
n bits shift……...Shifts data left or right any bit positions within the length of data.
Data shift……….Shifts addresses of data group forward or backward in unit of data set.
FIFO…………….Forms first-in-first-out register.
5-298
156. SFR Byte data 1 bit right shift (FUN 217) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register right 1 bit position (lower digit).
After the shift the content of D input enters the highest bit and the lowest bit enters the carry
flag (CY).
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set if the LSB is "1" before shift.

When X000 changes from OFF to ON, shifts D0000L 1 bit right.
When this instruction is executed while D0000L = 49H and X001 is ON, D0000L becomes A4H
and the carry flag (CY) is set after the shift.
5-299
157. WSFR Word data 1 bit right shift (FUN 36) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
flag (CY).
(5) Flag
CY BO Z > = < ER
↑

When M000 changes from OFF to ON, shifts D0100 1 bit right.
When this instruction is executed while D0100 = 8024H and M001 is OFF, D0100 becomes
4012H and the carry flag (CY) is reset after the shift.
5-300
158. DSFR 32-bit data 1 bit right shift (FUN 218) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
flag (CY).
(5) Flag
CY BO Z > = < ER
↑

When X100 changes from OFF to ON, shifts D0101 and D0100 1 bit right.
When this instruction is executed while D0101 and D0100 = 12345678H and X101 is ON,
D0101 becomes 891A2B3CH and the carry flag (CY) is reset after the shift.
5-301
159. BSFR Byte data n bits right shift (FUN 224) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Shifts the content for OP1 register right (lower digit) N bit positions with N being specified by
OP2. The upper unoccupied bit positions will be filled with "0s" , and the lowest bit will enter the
carry flag (CY). When number of bits specified by OP2 is larger than data length, the data bits
and carry flag (CY) are zeroed.
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set if Nth bit to LSB is "1" before shift.

When X000 changes from OFF to ON, shifts D0000L 3 bits right.
When this instruction is executed while D0000L = 84H, D0000L become 10H and the carry flag
(CY) is set after the shift.
5-302
160. WBSFR Word data n bits right shift (FUN 225) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X001 changes from OFF to ON, shifts D0100 5 bits right.
When this instruction is executed while D0100 = 4000H, D0100 become 0200H and the carry
flag (CY) is reset after the shift.
5-303
161. DBSFR 32-bit data n bits right shift (FUN 226) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M000 changes from OFF to ON, shifts D0101 and D0100 2 bits right.
When this instruction is executed while D0101 and D0100 = 12345678H, D0101 become
48D159EH and the carry flag (CY) is reset after the shift.
5-304
162. SFL Byte data 1 bit left shift (FUN 219) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
If T input condition is met, shifts the content of OP1 register left 1 bit position (upper digit). After
the shift the content of D Input enters the lowest bit and the highest bit enters the carry flag
(CY).
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set if the MSB is "1" before shift.

When X000 changes from OFF to ON, shifts D0000L 1 bit left.
When this instruction is executed while D0000L = 83H and X001 is ON, D0000L becomes 07H
and the carry flag (CY) is set after the shift.
5-305
163. WSFL Word data 1 bit left shift (FUN 37) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(CY).
(5) Flag
CY BO Z > = < ER
↑

When M000 changes from OFF to ON, shifts D0100 1 bit left.
When this instruction is executed while D0100 = 1234H and M001 is ON, D0100 becomes
2469H and the carry flag (CY) is reset after the shift.
5-306
164. DSFL 32-bit data 1 bit left shift (FUN 220) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(CY).
(5) Flag
CY BO Z > = < ER
↑

When X000 changes from OFF to ON, shifts D0101 and D0100 1 bit left. When this instruction
is executed while D0101 and D0100 = 87654321H and X101 is OFF, D0101 and D0100
becomes 0ECA8642H and the carry flag (CY) is set after the shift.
5-307
165. BSFL Byte data n bits left shift (FUN 227) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Shift the content of OP1 register left (upper digit) N bit position with N being specified by OP2.
The lower unoccupied bit positions will be filled with "0s", and the highest bit will enter the carry
flag (CY). When number of bits specified by OP2 is larger than data length, the data bits and
carry flag (CY) are zeroed.
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set if Nth bit from MSB is "1" before shift.

When X000 changes from OFF to ON, shifts D0000L 3 bits left. When this instruction is
executed while D0000L = A4H, D0000L becomes 20H and the carry flag (CY) is set after the
shift.
5-308
166. WBSFL Word data n bits left shift (FUN 228) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X001 changes from OFF to ON, shifts D0100 5 bits left. When this instruction is
executed while D0100 = 4821H, D0100 becomes 0420H and the carry flag (CY) is set after the
shift.
5-309
167. DBSFL 32-bit data n bits left shift (FUN 229) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M000 changes from OFF to ON, shifts D0101 and D0100 2 bits left. When this
instruction is executed while D0101 and D0100 = 12345678H, D0101 and D0100 become
48D159E0 and the carry flag (CY) is reset after the shift.
5-310
168. SRL Byte data 1 bit right-left shift (FUN 221) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
If T input condition is met when L/R input is ON, shifts the content of OP1 register left (upper) 1
bit position. After the shift, D input is shifted into the lowest bit position and the highest bit into
the carry flag (CY).
If T input condition is met when L/R input is ON, shifts the content of OP1 register right (lower) 1
bit position. After the shift, D input is shifted into the highest bit position and the lowest bit into
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set when MSB is "1" before shift if L/R input is ON.
Is set when LSB is "1" before shift if L/R input is OFF.

When X002 is ON and X000 changes from OFF to ON, shifts D0000L 1 bit left. When this
instruction is executed while D0000L = 83H and X001 is ON, D0000L becomes 07H and the
carry flag (CY) is set after the shift.
5-311
169. WSRL Word data 1 bit right-left shift (FUN 222) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M002 is OFF and M000 changes from OFF to ON, shifts D0100 1 bit right. When this
instruction is executed while D0100 = 8024H and M001 is OFF, D0100 becomes 4012H and the
carry flag (CY) is reset after the shift.
5-312
170. DSRL 32-bit data 1 bit right-left shift (FUN 223) *
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X102 is ON and X100 changes from OFF to ON, shifts D0101 and D0100 1 bit left. When
this instruction is executed while D0101 and D0100 = 87654321H and X101 is OFF, D0101 and
D0100 become 0ECA8642H and the carry flag (CY) is set.
5-313
171. BSRL Byte data n bits right-left shift (FUN 230)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
If T input condition is met when L/R input is ON, shifts the content of OP1 register left (upper) N
bit with the N being specified by the content of OP2. After the shift, the unoccupied lower N bit
positions are filled with 0s and the data in Nth bit to MSB enters the carry flag (CY).
If T input condition is met when L/R input is OFF, shifts the content of OP1 register right (lower)
N bits with N being specified by the content of OP2. After the shift, unoccupied upper N bit
positions are filled with 0s and the data in Nth bit to LSB enters the carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑
Carry flag (CY) : Is set when Nth bit from MSB is "1" before shift if L/R input is ON.
Is set when Nth bit from LSB is "1" before shift if L/R input is OFF.

When X001 is ON and X000 changes from OFF to ON, shifts D0000L 3 bits left. When this
instruction is executed while D0000L = A4H, D0000L becomes 20H and the carry flag (CY) is
set after the shift.
5-314
172. WBSRL Word data n bits right-left shift (FUN 231)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When M001 is OFF and M000 changes from OFF to ON, shifts D0100 5 bits right. When this
instruction is executed while D0100 = 4000H, D0100 becomes 0200H and the carry flag (CY) is
reset after the shift.
5-315
173. DBSRL 32-bit data n bits right-left shift (FUN 232)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X101 is ON and X100 changes from OFF to ON, shifts D0100 2 bits left. When this
instruction is executed while D0101 and D0100 = 12345678H, D0101 and D0100 become
48D159E0 and the carry flag (CY) is reset.
5-316
174. SUP 4 bit data upper-digit direction shift (FUN 251)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Shifts each piece of 4-bit data within a range (specified by the number of pieces of data by OP2,
starting at OP1), upward (larger address) 1 data position.
After the shift, the lowest data field contains 0s.
The maximum size of the shift area is 128 bytes (256 pieces of data).
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set when the shift area is outside of the data memory area or larger than
the specified value.

When X000 changes from OFF to ON, shifts each piece of data (1 data = 4 bit) upward within 5
data pieces range. After the shift, the lowest data field is filled with "0s" and the uppermost is
lost (replaced by the second uppermost one). If D0100L = 21H, D0100H = 43H and D0101L =
65H, then D0100L = 10H, D0100H = 32H and D0101L = 64H after the shift.
5-317
175. UP1 Byte data upper-digit direction shift 1 (FUN 91)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Shifts each piece of data by a unit of byte within the range between OP1 address and OP2
address. Shift direction is toward higher address when OP2 address is larger than that of OP1
and toward lower when OP2 is smaller than OP1. In this case the lowest data is unchanged.
The maximum size of the shift area is 768 bytes.
(5) Flag
CY BO Z > = < ER
↑

When X000 is ON, shifts each piece of data by a unit of byte within the range between D0100L
and D0101H.
If D0100L = 2H, D0100H = 43H and D0101L = 65H, then D0101H = 87H, then D0100L = 21H,
D0100H = 21H, D0101L = 43H and D0101H = 65H after the shift.
5-318
176. UP2 Byte data upper-digit direction shift 2 (FUN 252)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Shifts each pieces of data within a range (specified by the number of pieces of data by OP2,
starting address is OP1), upward (larger address) 1 data position. After the shift, the lowest
data field contains 00.
The maximum size of the shift area is 768 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set if the shifted data enters location for a device which is not available
for the current purpose or if the shift range exceeds the limits.

When X000 changes from OFF to ON, shifts each piece of data within a 4-byte area starting at
D0100L upward 1 byte position. If D0100L = 21H, D0100H = 43H, D0101L = 65H and D0101H =
87H, then D0100L = 00H, D0100H = 21H, D0101L = 43H and D0101H = 65H after the shift.
5-319
177. WUP Word data upper-digit direction shift (FUN 253)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
The maximum size of the shift area is 1034 words.
(5) Flag
CY BO Z > = < ER
↑

When X000 changes from OFF to ON, shifts each piece of data within a 4-word area starting at
D0100 upward 1 byte position. If D0100 = 4321H, D0101 =87653H, D0102 = CBA9H, D0103 =
0FED, then D0100 = 0000H, D0101 = 4321H, D0102 = 8765H and D0103 = CBA9H after the
shift.
5-320
178. DUP 32-bit data upper-digit direction shift (FUN 254)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
The maximum size of the shift area is 1024 words (512 pieces of data).
(5) Flag
CY BO Z > = < ER
↑
5-321
When X000 changes from OFF to ON, shifts each piece of data within a 8-word area starting
at D0100 upward 2-word positions. If D0101/D0100 = 00020001H, D0103/D0102 =
00040003H, D0105/D0104 = 00060005H, D0107/D0106 = 00080007H, then D0101/D0100 =
00000000H, D0103/D012 = 00020001H, D0105/D014 = 00040003H and D0107/D016 =
00060005H.
5-322
179. SDOWN 4 bit data lower-digit direction shift (FUN 255)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Shift each piece of 4-bit data within a range (specified by the number of pieces of data by op2,
starting at OP1), downward (smaller address) 1 data position. After the shift, the highest data
field contains 0s. The maximum size of the shift area is 128 byte (256 pieces of data).
(5) Flag
CY BO Z > = < ER
↑

When X000 change from OFF to ON, shifts each piece of data (1 data = 4 bit) downward within
5-data range. After the shift, the highest data field is filled with "0s" and the lowest is lost
(replaces by the second lowest one). If D0100L = 65H, D0100H = 43H and D0101L = 21H, then
D0101L = 60H, D0100H = 54H and D0100L = 32H after the shift.
5-323
180. DOWN Byte data lower-digit direction shift (FUN 256)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
starting address is OP1), downward (smaller address) 1 data position. After the shift, the
highest data field contains 0s.
The maximum size of the shift area which can be specified by OP2 is 768 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set when the shifted data enters location for a device which is outside of
the data memory area or when the shift range exceeds the limits.

When X000 changes from OFF to ON, shifts each piece of data within a 4-byte area starting at
D0100L downward 1 byte position. If D0101H = 87H, D0101L = 65H, D0100H = 43H and
D0100L = 21H, then D0101H = 00H, D0101L = 87H, D0100H = 65H and D0100H = 43H after
the shift.
5-324
181. WDOWN Word data lower-digit direction shift (FUN 257)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
The maximum size of the shift area which can be specified by OP2 is 1024 words.
(5) Flag
CY BO Z > = < ER
↑

D0100 downward 1 word position. If D0103 = 0FEDH, D0102 = CBA9HH, D0101 = 8765H,
D0100 = 43210FED, then D0103 = 0000H, D0102 = 0FEDH, D0101 = CBA9H and D0100 =
8765H after the shift.
5-325
182. DDOWN 32-bit data lower-digit direction shift (FUN 258)
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
The maximum size of the shift area which can be specified by OP2 is 1024 words (512 pieced
of data).
(5) Flag
CY BO Z > = < ER
↑
5-326
D0100 downward 2-word positions. If D0107/D0106 = D008007H, D0105/D0104 = 00060005H,
D0103/D0102 = 00040003H, D0101/D0100 = 00020001H, then D0107/D0106 = 00000000H,
D0105/D014 = 00080007H, D0103/D0102 = 00060005H and D0101/D0100 = 00040003H.
5-327
183. FIFW Byte data FIFO write (FUN 160)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the content of OP1 register to the location addressed the sum of OP2 address and the
content of OP3 register, and increments the content of OP3 register by 1.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set when the device at the destination address is outside of the data
memory area or when the content of OP3 register is 512 or greater.

When X000 changes from OFF to ON transfers the content of D0000L to D0101L. D0001
contains 3 after the transfer.
5-328
184. WFIFW Word data FIFO write (FUN 161)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑

When X001 changes from OFF to ON transfers the content of D0100 to D0303. D0000 contains
4 after the transfer.
5-329
185. DFIFW 32-bit data FIFO write (FUN 162)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
5-330
When M000 changes from OFF to ON transfers the content of D0101 and D0100 to D0205 and
D0204. D0000 contains 3 after the transfer.
5-331
186. FIFR Byte data FIFO read (FUN 163)
(1) Usable devices
extended
(3) Symbol
(4) Function
Shifts the data in the location beginning with OP1 address and the subsequent (the number of
data being specified by the content of OP2 register) downward (smaller address) and transfers
the content of OP1 register to OP3 register. After the execution, the end data field of the
location is filled with 0s and the content of OP2 register is decremented by 1.
(5) Flag
CY BO Z > = < ER
↑
the data memory area or when the shift range exceeds 512 data pieces.
5-332
When X000 changes from OFF to ON, transfers the content of D0100L to D0000L, shifts the
data in the location between D0100L to D0101H downward 1 byte each. D0001 contains 3 after
the shift.
5-333
187. WFIFR Word data FIFO read (FUN 164)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
5-334
When X001 changes from OFF to ON, transfers the content of D0100 to D0000, shifts the data
in the location between D0100 to D0102 downward 1 word each. D0001 contains 2 after the
shift.
5-335
188. DFIFR 32-bit data FIFO read (FUN 165)
(1) Usable devices
extended
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑
5-336
When M000 changes from OFF to ON, transfers the content of D0101 and D0100 to D0001 and
D0000, shifts the data in the location between D0100 to D0105 downward 2 word. D0002
contains 2 after the shift.
5-337
189. SFIN Accumulation shift input (FUN 68)
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Data in the area between OP1 and OP2 address locations are stacked in OP1 register.
Location containing only 0s is regarded as having no data. The data found in between "0" and
"0" is handled as "no data". The maximum size of the shift area is 512 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set if: OP1 address is larger than that of OP2; a device in the stack area
is outside of the data memory area; or the area of stack is longer than 512
bytes.
5-338
When X000 changes from OFF to ON, transfers the content of D0000L to the register having
data 00 and the highest address among registers containing 00, if any, in the stacking area.
After the transfer, D000L will contain 00.
5-339
190. SFOUT Accumulation shift output (FUN 69)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the content of OP2 register to OP3 register and shifts data in each of the registers
(from OP1 address up to the address next to OP2) upward (larger address) one data position.
After the shift, OP1 register is loaded with 0s. The maximum size of the shift area is 512 bytes.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Is set if: OP1 address is larger than that of OP2, a device in the stack area
is outside of the data memory area, or the area of stack is longer than 512
bytes.
5-340
When X000 changes from OFF to ON, transfers the content of D0003H to D0100L, shifts the
data in the location between D0000L and D0003H upward 1 byte. After the shift D000L will
contain 00.
5-341
5.4.11. Rotate
Instructions used to rotate or circulate data are classified as follows :
Rotate with carry……..Rotates any number of bit-data right or left with a carry flag.
Rotate without carry…..Rotates any number of bit-data right or left without a carry flag.
5-342
191. RRC Byte data right rotate with carry (FUN 233) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Rotates contents of OP1 register and carry flag (CY) right (lower bit) (N) bits specified by OP2.
During the rotation, the content of carry flag (CY)shifts to the MSB position and the LSB to the
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set when the Nth bit from the pre-rotate LSB is "1".
Error flag(ER) : Is set if the number of bits specified by OP2 is larger than the data length.

When M000 changes from OFF to ON, rotates the lower 8bits of D0100 and carry flag (CY)
(special relay V56) right (lower bit) 3 bits, storing them in D0100L and in the carry flag(CY).
5-343
192. WRRC Word data right rotate with carry (FUN 234) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M010 changes from OFF to ON, rotates 16 bits of D1000 and carry flag (CY) (special
relay V56) right (lower bit) 1 bit, storing them in D1000 and in the carry flag(CY).
5-344
193. DRRC 32-bit data right rotate with carry (FUN 235) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M011 changes from OFF to ON, rotates 32bits of D0301 and D0300 and carry flag (CY)
special relay (V56) right (lower bit) 12 bits, storing them in D0301 and D0300 and in the carry
flag (CY).
5-345
194. RR Byte data right rotate without carry (FUN 242) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Rotates content of OP1 register right (lower bit) by the number of bits specified by OP2. The
LSB is shifted into MSE position and also into carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M012 changes from OFF to ON, rotates D0110 lower 8 bits right (lower bit position) 4 bits,
storing them in D110L. After the rotation, MSB of D0100L is copied in the carry flag (CY)
(special relay V56).
5-346
195. WRR Word data right rotate without carry (FUN 243) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M013 changes from OFF to ON, rotates 16 bits of D0123 right (lower bit position) 3 bits,
storing them in D0123. After the rotation, MSB of D0123 is copied in the carry flag (CY) (special
relay V56).
5-347
196. DRR 32-bit data right rotate without carry (FUN 244) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M014 changes from OFF to ON, rotates 32 bits of D0101 and D0100 right (lower bit
position) 10 bits, storing them in D0101 and D0100. After the rotation, MSB of D0101 is copied
in the carry flag (CY) (special relay V56).
5-348
197. RLC Byte data left rotate with carry (FUN 236) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Rotates content of OP1 register and carry flag (CY) left (upper bit) (N) bits specified by OP2.
During the rotation, the content of carry flag (CY) shifts to the LSB position and the MSB to the
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set when the Nth bit from the pre-rotate MSB is "1".

When M015 changes from OFF to ON, rotates the lower 8 bits of D0100 and carry flag (CY) left
(upper bit) 3 bits, storing them in D0100L and in the carry flag (CY).
5-349
198. WRLC Word data left rotate with carry (FUN 237) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M016 changes from OFF to ON, rotates 16 bits of D0101 and carry flag (CY) left (upper
bit) 4 bits, storing them in D0101 and in the carry flag (CY).
5-350
199. DRLC 32-bit data left rotate with carry (FUN 238) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M017 changes from OFF to ON, rotates 32 bits of D0103 and D0102 and carry flag (CY)
left (upper bit)10 bits, storing them in D0103 and D0102 and in the carry flag (CY).
5-351
200. RL Byte data left rotate without carry (FUN 245) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Rotates content of OP1 register left (upper bit) by the number of bits specified by OP2. The
MSB is shifted into LSB position and also into carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑

When M018 changes from OFF to ON, rotates D0200 lower 8 bits left (upper bit position) 3 bits,
storing them in D0200L. After the rotation LSB of D0200L is copied in the carry flag (CY).
5-352
201. WRL Word data left rotate without carry (FUN 246) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M019 changes from OFF to ON, rotates 16 bits of D0202 left (upper bit position) 7 bits,
storing them is D0202. After the rotation, LSB of D0202 is copied in the carry flag (CY).
5-353
202. DRL 32-bit data left rotate without carry (FUN 247) *
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
(5) Flag
C BO Z > = < E
Y R
↑ ↑

When M01A changes from OFF to ON, rotates 32 bits of D0205 and D0204 left (upper bit
position) 12 bits, storing them in D0205 and D0204. After the rotation, LSB of D0204 is copied
in the carry flag (CY).
5-354
203. RLRC Byte data right-left rotate with carry (FUN 239)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
If T input condition has been met when R/L input is ON, rotates contents of OP1 register and
carry flag left (upper bit Position) N bits specified by OP2. During the rotation, the content of
carry flag (CY) shifts to LSB position and MSB to carry flag (CY).
If T input condition has been met when R/L input is OFF, rotates contents of OP1 register and
carry flag right (lower bit) N bits specified by OP2. During the rotation, the content of carry flag
(CY) shifts to MSB position and LSB to carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set if Nth bit from pre-rotate MSB is "1", when R/L input is ON. Is set if
Nth bit from pre-rotate LSB is set "1" when R/L input is off.

When M020 changes from OFF to ON, rotates 8 bits of D002L and carry flag (CY) right (M021 =
OFF) 2 bits or left (M021 = ON) 2 bits, and stores them in D00021 and in the carry flag (CY).
5-355
204. WRLRC Word data right-left rotate with carry (FUN 240)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M022 changes from OFF to ON, rotates 16 bits of D003 and carry flag (CY) right (M023 =
OFF) 2 bits or left (M023 = ON) 2 bits, and stores them in D003 and in the carry flag.
5-356
205. DRLRC 32-bit data right-left rotate with carry (FUN 241)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑
When M024 changes from OFF to ON, rotates 32 bits of D0005 and D0004 and carry flag (CY)
right (M025 = OFF) 5 bits or left (M025 = ON) 5 bits, and stores them in D0005 and D0004.
5-357
206. RLR Byte data right-left rotate without carry (FUN 248)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
If T input condition has been established when R/L input is ON,rotates contents of OP1 register
left (upper bit) N bits specified by OP2. While rotating, data shifting from MSB to LSB also
enters carry flag (CY).
If T input condition has been established when R/L input is OFF, rotates contents of OP1
register right (lower bit) N bits specified by OP2. While rotating, data shifting from LSB to MSB
position also enters carry flag (CY).
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry flag(CY) : Is set if Nth bit from pre-rotate MSB is "1" when R/L input is ON. Is set if Nth
bit from pre-rotate LSB is set "1" when R/L input is OFF.
Error flag (ER) : Is set if the number of bits specified by OP2 is larger than the data length.

When M026 changes from OFF to ON, rotates 8 bits of D0050L right or left (depending on the
content of M027) 3 bits and stores them in D0050L. After the rotation, the LSB (when N027 is
ON) or MSB (when M027 is OFF) of D0050L will be copied in the carry flag (CY).
5-358
207. WRLR Word data right-left rotate without carry (FUN 249)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M028 changes from OFF to ON, rotates 16 bits of D0100 right or left (depending on the
content of M029) the LSB (when N029 is ON) or MSB (when M029 is OFF) of D0100 will be
copied in the carry flag (CY).
To right when M029 is OFF and left when M029 is ON.
5-359
208. DRLR 32-bit data right-left rotate without carry (FUN 250)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑

When M02A changes from OFF to ON, rotates 32 bits of D0121 and D0120 right or left
(depending on the content of M02B) 8 bits and stores them in D0121 and D0120. After the
rotation, the LSB of D0120 (when M02B is ON) or MSB of D0121(when M02B is OFF) will be
copied in the carry flag (CY).
To right when M02B is OFF and left when M02B is ON.
5-360
5.4.12. Programmed branch
Instruction used to change program execution order and classified as follows :
Jump………………..Executes a program starting with the specified label first.
Subroutine call........Executes a subroutine bearing the specified label.
Repetition…………..Repeats the specified loop any desired times.
5-361
209.JMP JUMP (FUN 272)
(1) Usable devices
Constant
PC3 / X Y M K V T C L P D R N S B
L S EL
PC2 OP1 O O
extended OP1
(3) Symbol
(4) Function
When the input condition is ON, executes a program bearing the label number specified by
OP1.
When the input condition is OFF, executes the program at the next step. Labels numbered
L0-L255 are available for this instruction.
For PC3J series, EL0000 – EL1023(common with subroutine command) are usable.
(5) Flag
No change

When M015 is ON, jumps to label numbered L3.
When M013 is off, executes the program at the next step, without jumping.
5-362
210.CALL Subroutine call (FUN 273)
(1) Usable devices
Constant
PC3 / X Y M K V T C L P D R N S B
L S EL
PC2 OP1 O O
extended OP1
(3) Symbol
(4) Function
When the input condition is ON, executes a subroutine bearing the label number specified by
OP1 and will reenter the main program on the "RET" instruction, then go to a step following
the step where it branched. When the input condition is OFF, executes the next program step.
Labels numbered S0-S127 are available.
For PC3J series, EL0000 – EL1023(common with jump command) are usable.
(5) Flag
No change

When M016 is ON, executes the subroutine having label number S0. When N016 is OFF,
executes the next program stop, without jumping to a subroutine.
Subroutine is written between the END and PEND instructions, starting with the LABEL instruction
and ending with the RET instruction.
Nesting is allowed, that is another subroutine call can be made in a current subroutine.
5-363
211. RET Return from subroutine (FUN 464)
(2) Symbol
(3) Function
Indicates the end of subroutine called by the CALL instruction.
This instruction, when executed forces the system to go to a step following the step where the
CALL instruction was executed to call the subroutine.
(4) Flag
No change

Terminates subroutine S0 and executes the program at the step following the step where the
CALL instruction was used to call the subroutine.
The RET instruction cannot include condition (contact).
5-364
#
212. FOR Start repetition (FUN 472)
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1
(3) Symbol
(4) Function
Repeatedly executes the program between this and NEXT instruction for the number of times
defined by OP1. The number of repetitions definable from OP1 is 0-65535. Number 0 executes
the program between FOR and NEXT only once. Additional FOR-NEXT or FORN-NEXT
instruction can be put into FOR-NEXT loop up to 128 levels. This multi-looping of FOR-NEXT is
called nesting.
(5) Flag
No change

Executes program between this and NEXT instructions 10 times.
The FOR instruction cannot include condition (contact).
5-365
#
213. FORN Start repetition (indirect) (FUN 476)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
Repeats the program between this instruction and NEXT for the number of times defined by the
content of OP1 register which will decrement the counts by 1 upon execution of this instruction.
The program between FORN and NEXT is executed only once if OP1 register contains a 0.
Additional FOR-NEXT or FORN-NEXT instruction (called nesting) can be put into FORN-NEXT
loop up to 128 levels.
(5) Flag
No change

Repeats the program between this instruction and NEXT for the number of times defined by the
content of register D0100.
The FORN instruction cannot include condition (contact). When the program has run for the number
specified, D1000 will contain 0.
The FORN is always paired with NEXT instruction when used.
5-366
#
214. NEXT End of repetition (FUN 480)
(2) Symbol
(3) Function
Runs the program between FOR or FORN instruction and this instruction for the number of
times defined by the FOR or FORN instruction.
(4) Flag
No change

Runs the program written between FOR instruction and this instruction 5 times.
The NEXT instruction is paired with FOR or FORN instruction.

The NEXT instruction cannot include condition(contact).
5-367
5.4.13 Master control
Sets the range of master control.
5-368
215. MC Master control set (FUN 440)
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1
(3) Symbol
(4) Function
This instruction indicates the start of the master control whose number is defined by OP1. The
range of the master control begins with this instruction and ends with MCR instruction starting
the same master control number with this instruction. When the input condition is ON, normal
program operation is performed within the area of master control. If the input condition is OFF,
however, all output instructions within the area are made off, and output type application
instructions cannot be executed. Master control numbers selectable from OP1 are 0 to 255 but
can be nested up to 16 levels.
(5) Flag
No change

Executes the program written between No.5 MC instruction and No.5 MCR instruction while
M017 is ON. During off state of M017, output instructions are turned OFF regardless of the
input condition and any output type application instruction is not executed.
(When M017 is OFF, (L0 = OFF and W0VEare not executed regardless of X0 and X1 statuses.)
MC instruction is always paired with MCR instruction when used, MCR instruction cannot
include a condition (contact).
5-369
216. MCR Master control reset (FUN 444)
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1
(3) Symbol
(4) Function
This instruction indicates the end of master control whose number is defined by OP1.
The range of the master control begins with MC instruction and ends with this MCR instruction.
Both instruction should carry the same master control number. For details, refer to MC
instruction described above.
(5) Flag
No change
5-370
5.4.14. Input/output control
This instruction controls data transfer between external input/output devices and image
memory.
By using an input/output control instruction, the ON/OFF state information of the image memory
at the time the input/output control instruction is executed can be output to the output card or
the information on the input card can be read out onto the image memory.
For the external I/O devices and image memory, refer to “2-1 Processing operation.”
5-371
!
217. RIO Input/output refresh (FUN 280)
(2) Symbol
(3) Function
Transfers ON/OFF information of external input to device X.
And transfers ON/OFF information of device Y to external output.
This instruction covers all data transmission between external input/output devices and X and Y.
Note that data transfer to Remote I/O and communication module is not covered by this
instruction.
(4) Flag
No change

When M018 is ON, routes ON/OFF information of image I/O to output card, and inputs data
from input cards into image I/O.
(This is performed on entire X and Y areas.)
5-372
218. RI Input refresh (FUN 281)
(1) Usable devices
PC3 / PC2 OP1 O
OP2 O
PC3
OP1
extended
OP2
(3) Symbol
(4) Function
Transfers the number of bytes of external input data, specified by OP2 and starting at OP1
address, to device X.
instruction.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when device X does not exist in the destination area.

When M018 is ON, transfers 4 bytes of input card data, X00L-X01H, to the image I/O.
5-373
219. RO Output refresh (FUN 282)
(1) Usable devices
PC3 / PC2 OP1 O
OP2 O
PC3
OP1
extended
OP2
(3) Symbol
(4) Function
Transfers to external output the number of bytes of ON/OFF data of device Y, specified by OP2
and starting at OP1 address.
instruction.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when Y does not exist in the source area.

When M019 is ON, transfers 2 bytes of image I/O data. Y10L-Y10H, to specified output card.
5-374
5.4.15. Sequential interrupt
Enables or inhibits sequential interrupt (external interrupt and fixed-cycle interrupt).
5-375
%
220. DI Interrupt inhibit (FUN 276)
(2) Symbol
(3) Function
Inhibits interrupt programs (fixed-cycle interrupt Program and external interrupt) until EI
instruction is executed.
(4) Flag
No change

Inhibits interrupt when M01A switches from OFF to ON.
The DI instruction effectively inhibits interrupts until EI instruction is released: no need to repeat
DI instruction every scan cycle.
5-376
%
221. PDI Partial interrupt inhibit (FUN 278)
(1) Usable devices
PC3 / PC2 OP1 O
OP2 O
PC3
OP1
extended
OP2
(3) Symbol
(4) Function
Inhibits the sequential interrupts (fixed-cycle and externa1) lying between the level specified by
OP1 and the level specified by OP2.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the specified interrupt levels are out of the range 0-67.

When M01B switches from OFF to ON, inhibits 3 interrupts having interruption level of 9, 10
and 11, respectively.
The PDI instruction remains effective until the inhibit state is released by the PEI instruction; no
need to issue PDI instruction every scan cycle.
5-377
%
222. EI Interrupt enable (FUN 277)
(2) Symbol
(3) Function
Releases interrupt inhibit status kept after power-up, reset-start or DI instruction and enables
execution of interrupt program.
(4) Flag
No change

Enables interrupt when M01C switches from OFF to ON.
Once executed, the DI instruction remains effective until the DI instruction is issued or an
interrupt is generated; no need to issue DI instruction every scan.
The interrupts which are inhibited by the PDI instruction or parameter will not become enabled
status if the DI instruction is active.
5-378
%
223. PEI Partial interrupt enable (FUN 279)
(1) Usable devices
PC3 / PC2 OP1 O
OP2 O
PC3
OP1
extended
OP2
(3) Symbol
(4) Function
Enables such sequential interrupts (fixed-cycle interrupt and external interrupt) that have been
inhibited by the PDI instruction.
Interrupts lying between interruption levels specified by OP1 and OP2 are enabled.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Set if the specified interruption level is outside the range 0-67.

When M01D changes from OFF to ON, enables interruption levels 9, 10 and 11 that have been
inhibited by the PDI instruction.
Once executed, the PEI instruction remains effective until it is made inactive by the PDI
instruction. It is not necessary to reissue PEI instruction for every scan.
Interrupts which are inhibited by the DI instruction or parameter will not be enabled even if the
PEI instruction becomes active.
5-379
%
224. RETI Return from interrupt routine (FUN 468)
(2) Symbol
(3) Function
This instruction indicates the end of interrupt program.
The Program that has been interrupted by the interrupt input can start again at the next step.
(4) Flag
All flags arc returned back to the state where they where before interrupt.

Indicates the end of interrupt Program E0 (external interruption level 0) and I0 (fixed-cycle
interruption level 0).
The RETI instruction cannot contain condition(contact).

Interrupt programs are to be written between END and PEND instructions. Execution of RETI
produces EI status; no need to execute El instruction before RETI instruction.
5-380
5.4.16. Label
This instruction is used to define a program range and to indicate a jump address.
5-381
225. START Main program start (FUN 448)
(2) Symbol
(3) Function
Indicates the start of main sequential program. When the END instruction has been executed,
the system returns back to the step which contains this instruction.
(4) Flag
No change
Main program
External interrupt program

Level 0
Periodic interrupt program

Level 0
START, END, LABEL, RET, RETI and PEND instructions cannot contain condition (contact).
The initial program runs only once upon power-up or reset-start.
START and LABEL instruction are non-operative instructions i.e. they do not perform effective
operation even when executed.
5-382
226. END Main program end (FUN 452)
(2) Symbol
(3) Function
Indicates the end of main sequential Program.
Performs I/O refreshing between the image I/O and I/O cards.
Also refreshes the link area when link card is inserted.
After completion of this instruction, SIART instruction is used to run the program (restart of the
main sequence program from the beginning).
(4) Flag
No change

Refer to 225. START instruction.
5-383
227. PEND End of program (FUN 456)
(2) Symbol
(3) Function
Indicates the end of sequential program including subroutines and interrupt programs.
(4) Flag
No change

Refer to 225. START instruction.
(This instruction is not used during normal operation. When this instruction is executed, it
causes a program format error; the program stops and an error message will be issued.)
5-384
228. LABEL Label (FUN 460)
(2) Symbol
(3) Function
Indicates the jump destination upon issuing of JMP instruction, CALL instruction or interrupt.

1) Indicates that the jump destination of JMP instruction is L0.
Indicates that the jump destination of JMP instruction is L0-L255. (decima1)
2) Indicates that the jump destination of CALL instruction is S0.
Indicates that the jump destination of CALL instruction is S0-S127.
3) Indicates that the jump destination of external interrupt is E1.
Indicates that the jump destination of external interrupt is E0-E63.
4) Indicate that the jump destination of fixed-cycle interrupt is E0-E63. (decinla1)
Indicate that the jump destination of external interrupt is I0-I3.
LABEL instruction cannot contain condition(contact).
5-385
5.4.17 Special module data transfer
This instruction is used to transfer/receive data to/from special modules such as A/D module
and high-speed counter module and communication modules. This instruction cannot be used
for any module mounted to the remote I/O satellite station.
Therefore, any module which uses this instruction (SIO, high-speed counter, A/D*, and
others)cannot be mounted to the remote I/O satellite station.
* Since the A/D module of the PC2J can be used without use of this instruction (can be used
by switch setting), it can be mounted to the remote I/O satellite station.
5-386
229. SPR Special module byte-data readout
(for readout of file for the SIO module) (FUN 304)
(1) Usable devices
extended
(3) Symbol
(4) Function
Preliminarily set:
In D0 : The link No. (the number set up by a link parameter) of the SIO whose file is to be
read out and the number of bytes to be read out.
In D1 : The file address (an address in the file) from which the readout is to be started.
In D2 : The register address to which the data read out from the file is to be transferred.
Execution of the above instruction transfers the data as follows:
5-387
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER):
1. Setting of link No. to a number other than 1 to 8 results in application instruction error 1.
2. Absence of the special module corresponding to a designated link number results in
application instruction error l.
3. File address exceeding 810h or the number of bytes to be read out in excess of 320
bytes results in application instruction error 2.
4. No response from the special module (SIO) results in application instruction error 2.
5. A device other than file register (device code B) is usable for each operand.
6. Register address, to which data is transferred, other than the following results in
application instruction error 1.
PC2/L2 (0 - 7FFFh, C000 - FFFFh),
PC2J (0 - 23Fh, 300 - 3FFFh)
7. Write with link instruction usable flag OFF results in application instruction error 1,
requiring an interlock by the use of the flag.
8. When application instruction error 1 occurs, the CPU's special relay V50 turns ON. When
application instruction error 2 occurs, VC9 turns ON.
5-388
230. SPW Special module byte-data write
(for writing of file for the SIO module) (FUN 306)
(1) Usable devices
extended
(3) Symbol
(4) Function
Preliminarily set:
In D0 : The link No. of the SIO in whose file Write is performed, and the number of bytes to
be written.
In D1 : The register address of CPU from which data is transferred.
In D2 : The file address of the SIO in which the data is written.
Execution of the above instruction transfers the data as follows:
5-389
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER):

1. Setting of link No. to a number other than 1 to 8 results in application instruction error 1.
2. Absence of the special module corresponding to a designated link No. results in
3. The register address, from which data is transferred, other than the following results in
PC2/L2 (0 - 7FFFh, C000 - FFFFh),
PC2J (0 - 23Fh, 300h - 3FFFh).
4. The register, to which data is transferred, exceeding 810h or the number of bytes to be
written in excess of 320 bytes results in application instruction error 2.
5. No response from the special module (SIO) results in application instruction error 2.
6. A device other than file register is usable for each operand.
7. Readout with link instruction usable flag OFF results in application instruction error 1,
requiring an interlock by the use of the flag.
8. When application instruction error 1 occurs, the CPU's special relay V50 turns ON. When
application instruction error 2 occurs, VC9 turns ON.
5-390
!
231. HCR High-speed counter data readout (FUN 316)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Reads out the current value of the high-speed counter at the address specified by OP2 when
the start address of the I/O occupied by the high-speed counter is specified in OP1.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set when the area designated as the transfer source or destination is
other than a usable device.

Reads out the current value of the high-speed counter at D100 when X04 is ON.
5-391
!
232.HCW High-speed counter data write (FUN 317)
(1) Usable devices
OP1 O
PC3 / OP2 O O O O O O O O O O O O
PC2
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Writes the data which has the start address specified in OP2, onto the high-speed counter
when the start address of the I/O occupied by the high-speed counter is specified in OP1. The
number of data items to be written is specified by the lower 2 digits of OP3 and the address of
writing destination (in the high-speed counter) is specified by the higher 2digits.
(5) Flag
CY BO Z > = < ER
↑
other than that for a usable device.

Writes six data items whose start address is D0000 to the high-speed counter when X04 is
ON.
address of writing destination
number of data items to be written
5-392
!
233. IOR Shared I/O unit data readout (for A/D module) (FUN 318)
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Reads the data starting from the address specified in OP2 when the start address of the I/O
occupied by the AD module is specified in OP1. The address of reading source is specified by
the higher 2 digits of OP3and the number of data items to be read out is specified by the lower
2 digits.
(5) Flag
CY BO Z > = < ER
↑
other than that for a usable device.

Reads the data at parameter address A to 11H of the AD module out onto the data register
D0010 to D0017 when X10 is ON.
5-393
!
234. IOW Shared I/O unit data write (for A/D module) (FUN 319)
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Data whose start address is specified in OP2 is written onto the AD module when the start
address of the I/O occupied by the AD module is specified in OP1. The address of the writing
destination is specified by the higher 2 digits of OP3 and the number of data items to be written
is specified by the lower 2 digits.
(5) Flag
CY BO Z > = < ER
↑
outside of the usable device.

Stores the contents of D0000 (5d) into parameter address 0 of the AD module when X35 is ON.
5-394
5.4.18. Sequential debug
This instruction is effective while tracing is functioning in the debug mode and establishes
conditions for trace enable and trigger.
5-395
235. ENB Trace enable (FUN 274)
(2) Symbol
(3) Function
Established enable conditions for trace function in the debug mode. Has no effect during
operations other than trace.
For details, refer to the instruction manual for debug function.
(4) Flag
No change

When M0 is ON, enable condition is established.
5-396
236. TRG Trace trigger (FUN 275)
(2) Symbol
(3) Function
Establishes enable conditions for trigger function in the debug mode. Has no effect during
operations other than trace.
For details, refer to the instruction manual for debug function.
(4) Flag
No change

Trigger condition is established only when the enable condition has been prepared and M100 is
ON.
5-397
5.4.19. I/O monitor control
This instruction manages key input and display output when I/O monitor is operated in the user
mode.
Setting the user mode [1]
Using the I/O monitor :
Operation
Setting the user mode [2]
The user mode can be set using the special-purpose application instruction
Refer to “244.SYS.”
5-398
User-mode keys and codes
5-399
ACII codes for user-made annunciator
5-400
%#
237. KEY I/O monitor key input (FUN 294)
(1) Usable devices
PC3 / PC2
(3) Symbol
(4) Function
When the I/O is used in the user mode, transfers the I/O monitor key code stored in the special
register S00B into OP1 register, turning off the special relay V07 used for key input checking.
This instruction has no effect when the I/O monitor is not in the user mode.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the destination addressed by OP1 is not a location for available
device for the intended use.

Transfers the entered key code to D1000L.
5-401
%#
238. LEDD I/O monitor display (FUN 289)
(1) Usable devices
PC3 / PC2 OP2 O
OP3 O
OP2
extended
OP3
(3) Symbol
(4) Function
When I/O monitor is operating in the user mode, transfers the JIS codes which are stored in the
number of bytes of area specified by OP3and starting at OP1 address, to the I/O monitor
display and start display at the positions in the order specified by OP2.
This instruction has no effect when the I/O monitor is not in the user mode.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the data storage area is not for the device currently to be used, or if
the display data entering the I/O monitor display is outside the range 0-F.
5-402
When M100 switches from OFF to ON, displays 6 characters stored in D2000L to D2002H on
the I/O monitor, starting at D position on the display unit.
5-403
%#
239. LEDC I/O monitor display clear (FUN 290)
(2) Symbol
(3) Function
Turns off ah digit of display unit on the I/O monitor.
Has no effect in the modes other than user mode.
(4) Flag
No change

When M123 is ON, turns off ah digits on the display of the I/O monitor.
5-404
5.4.20. Application instruction for memory card
The following instructions are used for data transfer between the memory card and the CPU’s data
memory area when using the memory card as an additional data register in DATA CARD MODE.
(Can be used only by SCPU-4.10 or later version. WCPU is irrelevance)
Memory card address
A memory card address is not accompanied by an identifier.
Addresses are assigned in units of words (16 bits) and cannot be handled in units of bits or
bytes (8 bits).
The memory card capacity is 64K words.
5-405
$
240. CDR Memory card data read (FUN 296)
(1) Usable devices
OP1 O
OP3 O
PC3 OP1
extended
OP3
(3) Symbol
(4) Function
Transfers the data on the memory card (amount-indicated by OP3 starting from OP1's address)
to the area starting from OP2's register.
The maximum size of transferred data is 512 words.
(5) Flag
CY BO Z > = < ER
↑
memory area or when the transferred data exceeds the specified value. Is
also set when the CPU mode is not "DATACARD M0DE" or when the memory
card is not mounted.

To transfer 128-Word data starting from 0000h of the memory card to the area starting from
D0100 when M000 turns ON:
5-406
$
241. CDW Memory card data write (FUN 297)
(1) Usable devices
PC3 / PC2 OP2 O
OP3 O
OP2
extended
OP3
(3) Symbol
(4) Function
Transfers the data on the memory card (amount indicated by OP3 starting from OP1's register)
to the area starting from OP2's address of the memory card. The maximum size of transferred
data is 512 words.
(5) Flag
CY BO Z > = < ER
↑
Is also set when the CPU mode is not "DATACARD M0DE" or when the
memory card is not mounted or the ROM card is mounted.

To transfer l28-Word data starting from D0000 to the area starting from 0100h of the memory
card M000 turns ON:
5-407
$
242. CDIR Indirect memory card data read (FUN 298)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the data on the memory card whose address is the content of the OP1's register to
the area starting from the register whose address is the content of OP2's register. How many
data pieces to be transferred is indicated by the content of OP3's register. The maximum size of
transferred data is 512 words.
(5) Flag
CY BO Z > = < ER
↑
Is also set when the CPU mode is not "DATACARD M0DE" or when the
memory card is not mounted.
5-408
$
243. CDIW Indirect memory card write (FUN 299)
(1) Usable devices
extended
(3) Symbol
(4) Function
Transfers the data starting from the register whose address is the content of OP1's register to
the area starting from the address on the memory card which is the content of-OP2's register
address. How many data pieces to be transferred is indicated by the content of OP3's register.
The maximum size of transferred data is 512 words.
(5) Flag
CY BO Z > = < ER
↑
Is also set when the CPU mode is not "DATACARD MODE" or when the
memory card is not mounted or the ROM card is mounted.
5-409
5.4.21. Other application instruction
128 words from S250 to S2CF in the special register are reserved as the exclusive register for
annunciator messages and the times when the messages occurred. This area can store a
maximum of 8 messages by user programs and can be used for equipment diagnosis.
5-410
244. SYS Setting/resetting of I/O monitor error automatic indication
$
Setting/resetting of I/O monitor user mode (FUN 300)
(1) Usable devices
OP1 O
PC3 / PC2 OP2 O
OP3 O
PC3 OP1
OP2
extended
OP3
(3) Symbol
(4) Function
Sets and resets the automatic indication for I/O monitor error and sets and resets the I/O
monitor user mode.
(5) Flag
No change
(Note) The I/O monitor user mode can be used from version SCPU-4.10. It is not available with
version SCPU-3.**.
5-411
245. ANN Annunciator (FUN 291)
(1) Usable devices
PC3 / PC2 OP1 O
PC3
OP1
extended
(3) Symbol
(4) Function
Transfers the annunciator codes defined by OP1 and message data stored in the 16-byte area
starting with OP2 address, into 'annunciator 0' (S250-S25F), the first of the annunciator field
(S250-S2CF) of the special register.
Execution time of this instruction is timed by the built-in clock and automatically recorded.
The annunciator area consists of a shift register which can store up to 8 messages delivered by
this instruction. When this instruction is executed, the contents of areas annunciator 0 to 6 will
be shifted to areas annunciator 1 to 7 and a new message will be stored in 'annunciator 0'. The
contents of 'annunciator 7' will be lost, The sored message can be displayed on the I/O monitor.
Note: The annunciator codes definable from OP1 are 00-FF in hexadecimal format.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the message data storage area is not for device available for
intended use.

When M0 turns ON, transfers message data stored in D2000L-D2007H to the annunciator area,
giving the data hexadecimal code 12H.
5-412
246. USC User defined clock (FUN 293)
(1) Usable devices
OP1 O
PC3 / PC2 OP2 O
OP3 O
PC3 OP1
OP2
extended
OP3
(3) Symbol
(4) Function
Sets the operation of user defined special relay clocks 1 and 2 (V79 and V7A).
Turns on the clock specified by a clock number (1 or 2) from OP1 for the number of scans
defined by OP2 and then stops the clock for the number of scans defined by OP3. This
operation starts at the scan immediately follows this instruction.
Executing this instruction with 0 defined by OP2 stops the clock.
Notes:
1. Definable range is 1-2 for OP1 and 0-255 for OP2 and OP3.
2. If OP3 defines 0 and OP2 defines a number other than 0, the clock keeps running.
3. Initially the clock is set in stop mode.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the content of OP1 is a number other than 1 and 2.

When M0 switches ON from OFF, starts the user defined clock 1 as a clock which runs for 5
scans and stops for 10 scans.
5-413
!
247. ADJ Built-in clock 30-second adjustment (FUN 292)
(2) Symbol
(3) Function
Adjusts the built-in clock by rouding off seconds to a 30-second unit.
(4) Flag
No change

Adjusts the internal clock in unit of 30 seconds when M100 goes ON.
PC2JS and PC2JR are not equipped with the built-in clock.
The instruction is ignored and does not develop an error.
(The sequence for PC2J can be used as is.)
5-414
#
248. BAUD Peripheral device communication speed setting (FUN 288)
(1) Usable devices
PC3 / PC2
OP1 O
extended OP1
(3) Symbol
(4) Function
Sets peripheral device communication speed between Peripheral devices to the speed
specified by OP1. The communication speeds selectable by OP1 are as follows.
(5) Flag
CY BO Z > = < ER
↑
Error flag(ER) : Is set if the value defined by OP1 is other than 0-3.

Sets the communication speed to 19200bps when M0 goes ON from OFF.
(Note) The baud rate of peripheral devices for T0YOPUC-PC2 series controllers is fixed to
38400bps at present. Changing the baud rate using this instruction will disable
communication with the peripheral device.
5-415
249. STOP Program stop (FUN 287)
(2) Symbol
(3) Function
Halts the running sequential program.
(4) Flag
No change

Stops the sequential program when M100 is ON.
5-416
250. WDR Scan timer reset (FUN 46)
(2) Symbol
(3) Function
Resets the scan time monitor timer.
(4) Flag
No change

Resets the scan time monitor timer when M100 is ON.
The setup value for the scan time monitor timer can be set by parameter (refer to Chapter 3
"PARAMETER"). When the scan time is longer than the time set by the scan time monitor timer
due to the program construction, the CPU will output an error. When you don't want it to be an
error, either change the scan time setup value parameter or reset the current value of the scan
time monitor timer.
5-417
5.4.22. Extension of applied commands for PC3J series PC3J
(1) Extended label

1024 extended labels (EL0000 ~ EL1023) corresponding to CALL commands and JMP
commands are added to the PC3J from the PC2 Series.
Sequence programs are expressed as ever. "E" representing extension is prefixed to each
label..
· · · ·
When M000 is OFF When M000 is ON, jumped to EL0000.

· · · ·
· · · ·
· · · ·
When M000 is OFF When M001 is ON, subroutine EL0200 is

t d
· · · ·
· · · ·
Subroutine
5-418
(2) Extended register
The extended registers listed below are added to the PC3J from the PC2 Series. As listed,
extended input/output, extended internal relay, extended keep-relay, extended timer/counter,
extended link relay, extended special relay, extended timer/counter setup value registers,
present setup value register, extended special register and extended data register are
available. The capacity of extended data register differs depending on CPU operation mode.
And extended registers are common to each program.
Data
Identifier
Number Hold
Name Word address area at
of words
power
cut-off
EX Extended input
EX,EY00W ~ 7FW 128 -
EY Extended output
EM Extended internal relay EM00W ~ 1FFW 512 -

EK Extended keep-relay EK00W ~ FFW 256 O
ET Extended timer
ET,EC00W ~ 7FW 128 -
EC Extended counter
EL Extended link relay EL00W ~ 1FFW 512 -

EV Extended special relay EV00W ~ FFW 256 -
EN Extended present value register EN0000 ~ 07FF 2048 O
H Extended setup value register H0000 ~ 07FF 2048 O
ES Extended special register ES0000 ~ 07FF 2048 O
U Extended data register U0000 ~ 7FFF 32768*1 O
*1 The capacity of extended data register U differs depending on CPU operation mode.
Division mode : 1 ~3 : No , Division mode 4, 5 : 16KW
Single mode : 1 ~3 : No , Single mode 4, 6 : 16KW , Single mode 5 : 32KW
Relationship of CPU operation mode to program capacity and data capacity

Basic area data Extended area
Program capacity KW data capacity KW
capacity KW
Mode ( )showing
PRG.1 PRG.2 PRG.3 PRG.1 PRG.2 PRG.3 extended data
register
Division mode1 16 16 16 8 8 8 8( 0)
Division mode2 32 - 16 16 - 8 8( 0)
Division mode3 16 32 - 8 16 - 8( 0)
Division mode4 16 16 - 8 16 - 24(16)
Division mode5 16 - 16 16 - 8 24(16)
PC3 Single mode 1 16 16 16 24*2 8( 0)
Single mode 2 32 - 16 24*2 8( 0)
Single mode 3 16 32 - 24*2 8( 0)
Single mode 4 32 - - 24*2 24(16)
Single mode 5 16 - - 24*2 40(32)
Single mode 6 16 16 - 24*2 24(16)
PC2 interchange mode 32 - - 24 - - -
*2 Basic area data in single mode are common to each program.
5-419
(3) Designation of inter-program data
The PC3J can execute two or more programs , that is, three different sequence programs
maximum. Any program data can be mutually utilized among these programs without
special setting. Sequence program is expressed as ever.
When the CPU operation mode is "Data area division mode", inter-program data can be
mutually utilized each other by adding Program No. to the address head.
However, inter-program data can not be designated under "Data area single mode" and
"PC2 interchange mode" because the data area in each program is common to other
programs under these modes.
Data area division mode : Basic area data are independent every each program.
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
M100 M100 Y200 M100
=H P2-M10L=34h =H P3-D0000L=12h
Sequence
X000 EM000 Y200
program P3-M100 P1-M100
WDEC P2-D0000
·····
·····
·····
END END END
PEND PEND PEND
X000
I/O area Y200
M100 M100 M100
Basic
area data D0000 D0000
Extended EM00
area data
Data area single mode: The data area in each program are common to other programs.
PRG.1 PRG.2 PRG.3
START START START

·····
·····
·····
M100 M200 Y200 M300

=H M10L=34h =H D0000L=12h
Sequence
program X000 EM000 Y200
EM000 X000
WDEC D0000
·····
·····
·····
END END END

PEND PEND PEND
X000
I/O area Y200
M100
Basic
area data D0000
Extended EM00
area data
5-420
(4) Applied commands
The extended areas of the data memory are added in the PC3J. Where these extended
areas are used with the conventional applied commands, re-read the usable devices as
follows .
1) The conventional areas can be used as are in each program of the PC3J.
X Y M K V T C L P D R N S B
2) The extended areas can be used corresponding them to the conventional areas as
follows.
X Y M K V T C L P D R N S B Conventional area
EX EY EM EK EV ET EC EL EP U H EN ES Extended area
5-421
251.BBMOV Bit Block Transfer (move) (FUN 121) PC3J
(1) Usable devices
OP3 O
OP3
(3) Symbol
(4) Function
Area of bit number shown in OP3 from the bit address of OP1 is transferred (moved) to the area
from OP2.
The maximum transferable bit number is 255 bits.
(5) Flag
CY BO Z > = < ER
Error flag (ER) : Turns ON when transfer source and transfer destination are out of the
data memory area.
(6) Program (EX.)

Program to transfer X006 ~ X022 tOP2-D801-B ~ P2-D803-7 when X000 is ON.
(Note) In case that the destination area is over the byte unit, the bits in the lowest byte area
except the destination area are irregular.
X02L X01H X01L X00H X00L
7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1
over the byte unit
P2-D803L P2-D802H P2-D802L P2-D801H

7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8
1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 - - -
The 29 bits (X006~X022) are transferred to the area irregular

(P2-D801-B~P2-D803-7).
If the source area divides into the 5bits (X006~X00A) and the 24 bits (X00B~X022), it is
prevented that the bits in the lowest byte area except the destination area are irregular.
5-422
252.STURN 4bits inversion (FUN 259) PC3J
253.TURN 8bits inversion (FUN 260) PC3J
254.WTURN 16bits inversion (FUN 261) PC3J
(1) Usable devices
OP3 O
OP3
(3) Symbol
(4) Function
Using the address of OP1 as its head address, this function inverses upside down the data in the
areas of data number only shown in OP3 and transfers them to the area which uses the address
of OP2 as its head address.
The maximum transferable bit number is 256 bits.
(5) Flag
CY BO Z > = < ER
↑
Error flag (ER) : Turns ON when transfer source and transfer destination are out of the data
memory area or the transfer data number designated in OP3 exceeds 256.
(6) Program (EX.)

1) Program to inverse upside down the contents of P2-D000L ~ P2-D00002L at unit of 4bits and
to transfer them to M00H ~ M02H, when X000 is ON.
P2-D0000L 2 1 M00H 9 A
P2-D0000H 4 3 M01L 7 8
P2-D0001L 6 5 M01H 5 6
P2-D0001H 8 7 M02L 3 4
P2-D0002L A 9 M02H 1 2
5-423
2) Program to inverse upside down the contents of EL00H ~ EL01H at unit of 8bits and to
transfer them tOP3-R000L ~ P3-R001L, when X000 is ON.
P3-
EL000L 12 56
R000L
P3-
EL000H 34 34
R000H
P3-
EL001L 56 12
R001L
3) Program to inverse upside down the contents of D0010 ~ D0013 at unit of 16bits and to
transfer them to X00W ~ X003W , when M000 is ON.
D0010 0123 X00W CDEF

D0011 4567 X01W 89AB
D0012 89AB X02W 4567
D0013 CDEF X03W 0123
5-424
255.MOVAD Address Constant Transfer (Move) (FUN 320) PC3J
(1) Usable devices
PC3
extended
(3) Symbol
(4) Function
Stores indirect address of OP1 to OP2.
(5) Flag No variation
(6) Program (EX.)

Program to transfer D0000 content to L2W when X000 is OFF and D0000 content to L1W when
X000 is ON.
5-425
256.+H Addition of hexadecimal 2-digit constant (FUN 323) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Adds the register content of OP1 and hexadecimal number and stores the result in the register of
OP3. The range of constants is 0 ~ FF.
(5) Flag
CY BO Z > = < ER
↑ ↑
Carry Flag (CY) : Turns ON when digit-up is required upon adding.
Zero Flag (Z) : Turns ON when the result of addition is 0.
(6) Program (EX.)

Program to add the content of lower significant 8 bits of D0145 and hexadecimal "3F" and to
store the result in the lower significant 8bits of D147.
5-426
257.W+H Addition of hexadecimal 4-digit constant (FUN 324) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
OP3. The range of constants is 0 ~ FFFF.
(5) Flag
CY BO Z > = < ER
↑ ↑
(6) Program (EX.)

Program to adds hexadecimal "AB12" from the present value (content of N000) of counter C000,
when X001 is ON, and to store the result in D0234.
5-427
258.D+H Addition of hexadecimal 8-digit constant (FUN 325) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
address wherein 2 is added to the address of OP1. The range of constants is 0 ~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑ ↑
(6) Program (EX.)

Program to add the contents of D0149, D0148 and hexadecimal "FEDCBA98" and to store the
result in D014B, D014A respectively.
5-428
259.+HP Addition of BCD 2-digit constant (FUN 326) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Deeming register content of OP1 as BCD code, adds it together with BCD constant and stores
the result in the register of OP3. The range of constants is 0 ~ 99.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
Error Flag (ER) : Turns ON when register content of OP1 is not BCD format.
(6) Program (EX.)

Program to add the BCD 2-digit data to be input in X000 ~ X007 and BCD "12" and to store the
result in the lower significant 8bits of D0000.
5-429
260.W+HP Addition of BCD 4-digit constant (FUN 327) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
(6) Program (EX.)

Program to add the BCD 4-digit data stored in D0123, when X010 is ON, and "3456" of BCD and
to output the result to Y000 ~ Y00F.
5-430
261.D+HP Addition of BCD 8-digit constant (FUN 328) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
the result in the register of address wherein 2 is added to the address of OP1. The range of
constants is 0 ~ 99999999.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
(6) Program (EX.)

Program to add BCD 8-digit data stored in D0149, D148, when M000 turned ON from OFF, and
"12345678" of BCD, and to store the result in D014B and D014A respectively.
5-431
262. -H Deduction of hexadecimal 2-digit constant (FUN 329) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Deducts hexadecimal 2-digit constant from the register content of OP1 and stores the result in
OP3 register. The range of constants is 0 ~ FF.
(5) Flag
CY BO Z > = < ER
↑ ↑
Borrow Flag (BO) : Turns ON when digit-down is required upon deduction ( Constant is
greater than the content of OP1).
Zero Flag (Z) : Turns ON when the result of deduction is O.
(6) Program (EX.)

Program to deduct hexadecimal "3F" from the content of lower significant 8bits of D0145, when
X000 is ON, and to store the result in lower significant 8bits of D147.
5-432
263.W-H Deduction of hexadecimal 4-digit constant (FUN 330) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
CY BO Z > = < ER
↑ ↑
(6) Program (EX.)

Program to deduct hexadecimal "AB12" from the present value (content of N000) of counter
C000, when X001 is ON, and to store the result in D0234.
5-433
264.D-H Deduction of hexadecimal 8-digit constant (FUN 331) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
the register of address wherein 2 was added to the address of OP1. The range of constants is 0
~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑ ↑
(6) Program (EX.)

Program to deduct hexadecimal "FEDCBA98" from the contents of D0149, D0148, when M000
turned ON from OFF and to store the result in D014B,D014A .
5-434
265.-HP Addition of BCD 2-digit constant (FUN 332) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
(6) Program (EX.)

Program to deduct BCD "12" from the BCD 2-digit data to be input in X000 ~ X007 and to store
the result in lower significant 8bits of D0000.
5-435
266.W-HP Addition of BCD 4-digit constant (FUN 333) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
(6) Program (EX.)

Program to deduct BCD "3456" from BCD 4-digit data stored in D0123, when X010 is ON, and to
output the result to Y000 ~ Y00F.
5-436
267.D-HP Addition of BCD 8-digit constant (FUN 334) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, deducts BCD constant and stores the result
in the register of address wherein 2 was added to the address of OP1. The range of constants
is 0 ~ 99999999.
(5) Flag
CY BO Z > = < ER
↑ ↑ ↑
(6) Program (EX.)

Program to deduct BCD "12345678" from BCD 8-digit data which was stored in D0149, D148
when M000 turned ON from OFF, and to store the result in D014B,D014A .
5-437
268. *H Multiplication of hexadecimal 2-digit constant (FUN 335) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Multiplies the register content of OP1 by hexadecimal constant and stores the result in OP3.
The range of constants is 0 ~ FF.
(6) Program (EX.)

Program to multiply the content of lower significant 8bits of D0145 by hexadecimal "3F" and to
store the result in 16bits of D147.
5-438
269. W*H Multiplication of hexadecimal 4-digit constant (FUN 336) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Multiplies the register content of OP1 by hexadecimal constant and stores the result in OP3.
The range of constants is 0 ~ FFFF.
(6) Program (EX.)

Program to multiply present value (content of N000) of counter C000 by hexadecimal "AB12" ,
when X001 is ON, and to store the result in D0234, D0235.
5-439
270. D*H Multiplication of hexadecimal 8-digit constant (FUN 337) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Multiplies the register content of OP1 by hexadecimal constant and stores the result in the
register of address wherein 2 was multiplied the address of OP1. The range of constants is 0
~ FFFFFFFF .
(6) Program (EX.)

Program to multiply the contents of D0149, D0148 by multiplication "FEDCBA98" and to store
the result in D014D, D014C, D014B and D014A respectively.
5-440
271. *HP Multiplication of BCD 2-digit constant (FUN 338) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, multiplies BCD constant and stores the result
in the register of OP3. The range of constants is 0 ~ 99.
(5) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when the register content of OP1 is not BCD format.
(6) Program (EX.)

Program to multiply BCD 2-digit data to be input in X000 ~ X007 by BCD "12" and to store the
result in 16bits of D0000.
5-441
272. W*HP Multiplication of BCD 4-digit constant (FUN 339) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
in the register of OP3. The range of constants is 0 ~ 9999.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to multiply BCD 4-digit data stored in D0123, when X100 is ON, by BCD "3456" and to
store the result in Y000 ~Y01F.
5-442
273. D*HP Multiplication of BCD 8-digit constant (FUN 340) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
in the register of OP1. The range of constants is 0 ~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to multiply BCD 8-digit data stored in D0149, D148 by BCD "12345678", when M000
turned ON from OFF, and to store the result in D014D, D014C, D014B and D014A respectively.
5-443
274./H Divide of hexadecimal 2-digit constant (FUN 341) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Divides the register content of OP1 by hexadecimal constant and stores the quotient in OP3
register and remainder in the register of address next to OP3. The range of constants is 0 ~ FF.
(5) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when OP2 constant is 0.
(6) Program (EX.)

Program to divide the content of lower significant 8bits of D0145 by hexadecimal "3F" , when
X000 is ON, and to store the quotient in lower significant 8 bits of D147 and the remainder in
upper significant 8bits of D147.
5-444
275.W/H Divide of hexadecimal 4-digit constant (FUN 342) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Divides the register content of OP1 by hexadecimal constant and stores the quotient in OP3
register and remainder in the register of address next to OP3. The range of constants is 0 ~
FFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to divide the present value( content of N000) of counter C000 by hexadecimal “AB12”,
when X001 is ON, and to stored the quotient in D0234 and remainder in D0235.
5-445
276.D/H Divide of hexadecimal 8-digit constant (FUN 343) PC3J
(1) Usable devices

OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
Divides the register content of OP1 by hexadecimal constant and stores the quotient in the
register of address wherein 2 was added to the address of OP1 and the remainder in the register
of address wherein 4 was added to the address of OP1. The range of constants is 0 ~
FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to divide the contents of D0149, D0148 by hexadecimal "FEDCBA98", when M000
turned ON from OFF, and to store the quotient in D014B, D014A and the remainder in D014D,
D014C.
5-446
277./HP Divide of BCD 2-digit constant (FUN 344) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Deeming the register content of OP1 as BCD code, divides it by BCD constant and stores the
quotient in OP3 register and the remainder in the register of address next to OP3. The range of
(5) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when OP2 constant is 0 or not in BCD format.
(6) Program (EX.)

Program to divide BCD 2-digit data input in X000 ~ X007 by BCD "12" and to store the quotient in
the lower significant 8bits of D0000 and the remainder in the upper significant 8bits of D000.
5-447
278.W/HP Divide of BCD 4-digit constant (FUN 345) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
quotient in OP3 register and the remainder in the register of address next to OP3. The range of
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to divide BCD 4-digit data stored in D0123, when X010 is ON, by BCD "3456" and to
output the quotient in Y000 ~ Y00F and the remainder to Y01F from Y010.
5-448
279.D/HP Divide of BCD 8-digit constant (FUN 346) PC3J
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
quotient in the register of address wherein 2 was added to the address of OP1 and the remainder
in the register of address wherein 2 was added to the address of OP1. The range of constants
is 0 ~ 99999999.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to divide BCD 8-digit constant stored in D0149 , D148 by BCD "12345678", when M000
turned ON from OFF, and to store the quotient in D014B,D014A and the remainder in D014D,
D014C.
5-449
280. ANDH Logical product (AND) of hexadecimal 2-digit constant (FUN 347) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Determines logical product (AND) of the register content of OP1 by hexadecimal constant and
stores the result in OP3 register. The range of constants is 0 ~ FF.
(5) Flag
CY BO Z > = < ER
↑
Zero Flag (Z) : Turns ON when the calculated result is 0.
(6) Program (EX.)

Program to determine logical product of X010 ~ X017 data by hexadecimal "3F", when X000 is
ON, and to output the result to Y028 ~ Y02F.
5-450
281. WANDH Logical product (AND) of hexadecimal 4-digit constant (FUN 348) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
stores the result in OP3 register. The range of constants is 0 ~ FFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to bring the most significant digit of BCD 4-digit data stored in D0234, when X001 is ON,
and to re-store it in D0234.
5-451
282. DANDH Logical product (AND) of hexadecimal 8-digit constant (FUN 349) PC3J
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
stores the result in the register of address wherein 2 was added to the address of OP1. The
range of constants is 0 ~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine logical product of the contents of D0237, D0236 by hexadecimal
"FEDCBA98", when M000 is ON, and to store the result in D0239, D0238.
5-452
283. ORH Logical sum (OR) of hexadecimal 2-digit constant (FUN 350) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Determines logical sum (OR) of the register content of OP1 and hexadecimal constant and
stores the result in OP3 register. The range of constants is 0 ~ 99.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine logical sum (OR) of X010 ~ X017 data and hexadecimal "3Fh" , when
X000 is ON, and to output the result to Y028 ~ Y02F.
5-453
284. WORH Logical sum (OR) of hexadecimal 4-digit constant (FUN 351) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
stores the result in OP3 register. The range of constants is 0 ~ 9999.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to bring all upper significant 8bits of data stored in D0234 to "1" , when X001 is ON.
5-454
285. DORH Logical sum (OR) of hexadecimal 8-digit constant (FUN 352) PC3J
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
stores the result in the register of address wherein 2 was added to the address of OP1. The
range of constants is 0 ~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine logical sum of the data stored in D0237, D0236 and hexadecimal
"FEDCBA98h", when M000 is ON, and to store the result in D0239, D0238.
5-455
286. XORH Exclusive logical sum (XOR) of hexadecimal 2-digit constant (FUN 353) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
Determines exclusive logical sum (XOR) of the register content of OP1 and hexadecimal
constant and stores the result in OP3 register. The range of constants is 0 ~ 99.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine exclusive logical sum (XOR) of X010 ~ X017 data and hexadecimal "3Fh" ,
when X000 is ON, and to output the result to Y028 ~ Y02F.
5-456
287. WXORH Exclusive logical sum (XOR) of hexadecimal 4-digit constant (FUN 354) PC3J
(1) Usable devices
PC3 / PC2 OP2 O
OP2
(3) Symbol
(4) Function
constant and stores the result in OP3 register. The range of constants is 0 ~ 9999.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine exclusive logical sum (XOR) of the data stored in D0233 and hexadecimal
"AB12" , when X001 is ON, and to store the result in D0234.
5-457
288. DXORH Exclusive logical sum (XOR) of hexadecimal 8-digit constant (FUN 355) PC3J
(1) Usable devices
OP2 O
PC3
extended
OP2
(3) Symbol
(4) Function
constant and stores the result in the register of address wherein 2 was added to the address of
OP1. The range of constants is 0 ~ FFFFFFFF.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

Program to determine exclusive logical sum (XOR)of the data stored in D0237, D0236 and
hexadecimal "FEDCBA98h", when M000 is ON, and to store the result in D0239, D0238.
5-458
289. STI1 Byte data sum (FUN 362) PC3J
290. WSTI1 Word data sum (FUN 363) PC3J
291. DSTI1 32-bit data sum (FUN 364) PC3J
(1) Usable devices

(3) Symbol
(4) Function
Determines the sum of data in the area wherein the head address is OP1 register and the data
number is the register content of OP3, and store the result in OP2 register. The maximum data
number is 128 pieces.
(5) Flag
CY BO Z > = < ER
↑ ↑
Zero Flag (Z) : Turns ON when the calculated result is 0

Error Flag (ER) : Turns ON when the data number is 129 or more.
(6) Program (EX.)

1) Program to determine the sum of data of 30byte portion shown in D0001 from head address
R0000L, when X000 is ON, and to store the result in D0000.
2) Program to determine the sum of data of 128-word portion shown in D0000 from the head
address D1000, when X001 is ON, and to output the result to Y000 ~ Y01F.
3) Program to determine the sum of data of several-piece portion input with X010 ~ X01F from
the head address D0000, when M000 is ON, and to store the result in D0202, D0201, D0200.
5-459
292. MAX Byte data maximum value retrieve (FUN 374) PC3J
293. WMAX Word data maximum value retrieve (FUN 375) PC3J
294. DMAX 32-bit data maximum value retrieve (FUN 376) PC3J
(1) Usable devices
(3) Symbol
(4) Function
Determines the maximum value from the data in the area wherein the head address is the
address of OP1 and the data number is the register content of OP3, and stores the result in the
register of OP2. The maximum data number is 128 pieces.
(5) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when the data number is 129 pieces or more.
(6) Program (EX.)

1) Program to determine the maximum value the data of 30byte portion shown in D0001 from
head address R0000L, when X000 is ON, and to store the result in D0000L.
2) Program to determine the maximum value from the data of 128-word portion shown in
D0000 from the head address D1000, when X001 is ON, and to output the result to Y000 ~
Y00F.
3) Program to determine the maximum value from the data of several-piece portion input with
X010 ~ X01F from the head address D000 , when M000 is ON, and to store the result in
D0201, D0200.
5-460
295. MIN Byte data minimum value retrieve (FUN 377) PC3J
296. WMIN Word data minimum value retrieve (FUN 378) PC3J
297. DMIN 32-bit data minimum value retrieve (FUN 379) PC3J
(1) Usable devices
(3) Symbol
(4) Function
Determines the minimum value from the data in the area wherein the head address is the
address of OP1 and the data number is the register content of OP3, and stores the result in the
register of OP2. The maximum data number is 128 pieces.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

1) Program to determine the minimum value from the data of 30byte portion shown in D0001
from head address R0000L, when X000 is ON, and to store the result in D0000L.
2) Program to determine the minimum value from the data of 128-word portion shown in D0000
from the head address D1000, when X001 is ON, and to output the result to Y000 ~ Y00F.
3) Program to determine the minimum value from the data of several-piece portion input with
X010 ~ X01F from the head address D0000, when M000 is ON, and to store the result in
D0201, D0200.
5-461
298. AVE Byte data average (FUN 380) PC3J
299. WAVE Word data average (FUN 381) PC3J
300. DAVE 32-bit data average (FUN 382) PC3J
(1) Usable devices
(3) Symbol
(4) Function
Determines the average of the data in the area wherein the head address is OP1 register and the
data number is the register content of OP3, and stores the result in the register of OP2. In
averaging the fraction of 5 and over at decimal place is counted as 1. The maximum data
number is 128 pieces.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

1) Program to determine the average value the data of 30byte portion shown in D0001 from
head address R0000L, when X000 is ON, and to store the result in D0000L.
2) Program to determine the average value from the data of 128-word portion shown in D0000
from the head address D1000, when X001 is ON, and to output the result to Y000 ~ Y00F.
3) Program to determine the average value from the data of several-piece portion input with
X010 ~ X01F from the head address D0000, when M000 is ON, and to store the result in
D0201, D0200.
5-462
5.
301. CRET Return from subroutine (FUN 285) PC3J
(2) Symbol
(3) Function
Terminates the subroutine if the calculated result up to CRET is ON .
(5) Program (EX.)

Program to terminate subroutine when M000 is ON.
5-463
5.
302.ARIO Area-designated I/O refresh (FUN 295) PC3J
(2) Symbol
(3) Function
Transfers external input ON/OFF information in the areas of byte number designated with OP2
from the address of OP1 to Device-X and, in addition, transfers the ON/OFF information of
Device-Y to external output unit.
Data transfer to remote I/O and communication modules is not available.
(4) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when the transfer area is other than X, Y.
(5) Program (EX.)

Program to transfer image I/O information in the areas of X04H ~ X06H to output card , when
M000 is ON, and to input the information in the image I/O module from the input card.
5-464
303.SYS Applied command flag clear mode setting (FUN 300) PC3JApplied command flag clear mode
clear
(1) Usable devices
OP1 O
PC3 / PC2 OP2 O
OP3 O
extended OP1
OP2
OP3
(3) Symbol
Applied command flag clear mode setting
Applied command flag clear mode clear
(4) Function
Sets / reset(release) the applied command flag clear mode before executing applied
commands.
(6) Program (EX.)
For applied commands executed, the

applied command flag is cleared in
this area, before the commands are
executed.
5-465
304.BRSET Buffer register(EB) address set (FUN 371) PC3JG
(1) Usable devices
PC3 / PC2 OP1
PC3
OP1 O
extended
(3) Symbol
BRSET BRSET EB13000 → D0000
(4) Function
The Indirect address of the buffer register(EB) specified OP1 is set to the 2 word area with
OP2 as the head address. OP2 is not the other program area.
(5) Flag
CY BO Z > = < ER
↑
Error Flag (ER) : Turns ON when the area to save is exceeded the data memory area.
(6) Program (EX.)

If M0 turns ON, the Indirect address of EB13000 is saved to D0000/D0001.
After this command is instructed, D0000 is 3000h and D0001 is 0001h.
M000
BRSET EB13000 → D0000
OP1=EB13000
OP2=D0000
5-466
305.WBR Data loading from the buffer register(EB) (FUN 372) PC3JG
(1) Usable devices
OP3 O
OP3
(3) Symbol
WBR WBR (D0000) → D0100 N=10d
(4) Function
Data in buffer registers which of address is the content of 2 word area with OP1 as the head
address is transferred to registers with OP2 as the head address. Size is OP3.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

If M0 turns ON, the 10 words data (EB13000 – EB13009) is copied to D0100 – D0109.
M000
OP1=EB13000
BRSET EB13000 →D0000
OP2=D0000
M000
OP1=D0000
WBR (D0000) →D0100 N=10d
OP2=D0100
OP3=10d
5-467
306.WBW Data saving to the buffer register(EB) (FUN 373) PC3JG
(1) Usable devices
OP3 O
OP3
(3) Symbol
WBW WBW D0100 → (D0000) N=10d
(4) Function
Registers with OP1 as the head address is transferred to buffer registers which of address is
the content of 2 word area with OP2 as the head address. Size is OP3.
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

If M0 turns ON, the 10 words data (D0100 – D0109) is copied to EB13000 – EB13009.
M000 OP1=EB13000
BRSET EB13000 →D0000 OP2=D0000
M000
OP1=D0100
WBW D0100 → (D0000) N=10d OP2=D0000
OP3=10d
5-468
307.MSET Output of the message for DLNK-M2 (FUN 302) PC3JG
(1) Usable devices
OP1 O
OP1

(3) Symbol
MSET
MSET 1330h D0100L D0200L
(4) Function
The message of the number indicated with OP1 which of head address is OP2 are transferred to
DLNK-M2 indicated with OP1.
The response data from DLNK-M2 are transferred to the area which of head address is OP3.
The receive completed flag (Top 1word) is added for received data. Register area size for response
is 1 word + response size from slave.
The response data is not set, even if the function instruction is completed. After the response data
is set in the register, 1 is set in one first word register of the response data storage area.
1)example for format of commmand (In case of DLNK-M2)
Relative word address Item Size Range
Destination node address
+00W 1Word 0000h∼003Fh
(MAC ID)
+01W Service Code 1Word 0000h∼00FFh
+02W Class ID 1Word 0000h∼FFFFh
+03W Instance ID 1Word 0000h∼FFFFh
+04W Service data size 1Word 0000h∼0080h
+05W 0∼64
| Service data -
+44W Word
2)example for format of response (In case of DLNK-M2)

Relative word address Item Size Range
+00W Receive completed flag 1Word 0001h
Destination node address
+01W 1Word 0000h∼003Fh
(MAC ID)
+02W Service Code 1Word 0000h∼00FFh
+03W Reserved 1Word -
+04W Reserved 1Word -
+05W Service data size 1Word 0000h∼0080h
+06W 0∼64
| Service data -
+45W Word
OP1 format (Link No. ＋ message size)

F 7 0
Link program No. Link No. message size

(1 - 3) (1 - 8) (10 – 138 Byte)
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)
If M0 turns ON and the link command of Prg1-Link3 is usable, the message (in D0100 – D0117,
size is 48 byte) is commanded for the DLNK-M2 which is set in Prg1-Link3. The response is
saved to the area with U0000 as the head address.
M000 V94 OP1=1330h
MSET 1330h D0100L U0000L OP2=D0100
OP3=U0000
5-469
308.CSET I/O Register read-out instruction issue to TOYOPUC-PCS (FUN 370) PC3JG
(1) Usable devices
OP1 O
PC3 OP1
(3) Symbol
CSET CSET 100Ah D0100 U0000
(4) Function
I/O Register read-out instruction of the number indicated with OP1 which of head address is
OP2 are transferred to TOYOPUC-PCS.
The response data from TOYOPUC-PCS are transferred to the area which of head address
is OP3.
The response data is not set though the application instructions is completed. After the set of
the response data is completed, the permission flag to use of the link command is set.
OP1 format (command size)

F 7 0
10h command size

(9-517 byte)
Usable I/O Register read-out instruction
1.Loding I/O register by word data
The command for loading I/O and register by word data
The specified word size data are loaded from the specified address. (size ≤ 200h)
Address = Indirect word address (= Byte address / 2)
Command format
word size
word size
address
address
high
high
low
low
1C
00
00
05
05
00
00
Response format
DataN
Data1
Data2
High
Size
Size
low
RC
SC
1C
00
00
Size
RC : response code
06h : normal
15h : error
SC : Sum check
5-470
2: Saving I/O register by word data
The specified data is saved to the specified address.(max 200h word data)
Command format
address
address
DataN
Data1
Data2
High
Size
Size
high
low
low
1D
00
00
05
00
Response format
RC
SC
1D
00
00
01
00
RC : response code
06h : normal
15h : error
SC : Sum check
(5) Flag
CY BO Z > = < ER
↑
(6) Program (EX.)

If M0 turns ON and the link command of TOYOPUC-PCS is usable, the I/O Register
read-out (in D0100 – D0104, size is 10 byte) is commanded. The response is saved to the
area with U0000 as the head address.
M000 P000 S130-8

OP1=100Ah
CSET 100Ch D0100 U0000
OP2=D0100
OP3=U0000
5-471
309. SYS Clock adjustment instruction (FUN 300) PC3J Version 2.6~(note)
(1) Usable devices
X Y M K V T C L P D R N S B 定数
ＯＰ１ ○
PC3/PC2
ＯＰ２ ○
ＯＰ３ ○
ＰＣ３ＯＰ１
extended ＯＰ２
ＯＰ３
(2) Number of steps ５
(3) Symbol
SYS SYS 0005 2000 0000
(4) Function
The clock adjustment function is executed.
OP1 is a system call number 5h(5d) (fixation).
OP2 inputs the head address of an adjustment data address. It specifies it by indirect addressing in own area.
If it is D000, 2000h is put.(word address) When you input it by the odd number head number, the data of the
0th bit is disregarded.
OP3 is 0 (fixation).
(5) Flag
C B Z > = < E
Y O R
↑
Error flag(ER) ：The flag is turned on at time beyond the limits of the clock data the adjustment data.
（EX01/07/1F/18:81:00 (Fri)）
(6) Program(EX)
M000 P000
OP1=0005h
SYS 0005 2000 0000
OP2=2000h
OP3=0000h
When M000 is turned on, the data of four words that starts from D000 is reflected in the system as clock data.
The data of four words that starts from D000 is (minute/second) (day/time) (year/month) (Day of the week)
As for the day of the week data, 0~6 corresponds to Sunday~Saturday.
When D000,D001,D002,D003 is 1800, 1218,0107,0004,the clock is at ‘01/07/12/18:18:00(Thursday)
(note)
PC3JG PC3JBG PC3JP can use this instruction.PC3JL,PC3JD,PC3JB,PC3JM can use this instruction since
version 2.6.PC3J PC3JNF PC3JNM can not use this instruction.
5-472
ꞏ The descriptive contents of this Manual are subject to change due
to better improvement of applicable product without prior notice.
ꞏ This Manual is issued after careful check and review of the contents
thereof. However, should any doubt or any descriptive error be
found in the contents, please feel free to contact us.
ꞏ It is prohibited to copy and transfer , wholly or partly, the descriptive
contents of this Manual to others.
1st Edition : June.2003

10th Edition : March.2022
 We are ready to comply with your request for maintenance ,
Please forward: Phone: +81-566-25-8291
FAX: +81-566-25-5469
1-1 Asahimachi, Kariya, Aichi 448-8652 Japan
Manual No.
© JTEKT CORPORATION 2010-2022.

T-307-10-E
* The specification and other given in this manual are subject to change due to improvement without prior notice.
* Any product applicable to the strategic goods (or the services) stipulated in the Foreign Exchange and Foreign Trade Control Act is
subject to export license of the Japanese Government, where exported to overseas.

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Programmable Controller

4. USER MEMORY STRUCTURE 4

Thank you very much for purchasing our Programmable Controller.

This operation manual is the programming manual for TOYOPUC-PC2/3 series.

Failure to observe the instructions given in this Manual could result

Failure to observe the instructions given in this Manual could result in

Regarding safe-related signals and emergency stop circuit, etc.,

Don't touch directly the electronic circuits inside the module.

1 2003.06.30 1st revision

PC2J series-specific function------------PC2J

32KW PC2JNM PC2J-32KW

Ver.---------This is usable for the specific version or later.

- Byte data binary subtraction (FUN 170) 5-196

ADJ Built-in clock 30-second adjustment (FUN 292) ! 5-414

BAUD Peripheral device communication speed setting (FUN 288) # 5-415

CALL Subroutine call (FUN 273) 5-363

D- 32-bit data binary subtraction (FUN 171) 5-198

ECNT Extended Counter (UP) 5-45

FIFR Byte data FIFO read (FUN 163) 5-332

HCR High-speed counter data readout (FUN 316) ! 5-391

INC Byte data binary increment (FUN 195) 5-229

JBIN JIS code to binary (FUN 156) 5-264

KEY I/O monitor key input (FUN 294) %# 5-401

LABEL Label (FUN 460) 5-385

NEXT End of repetition (FUN 480) # 5-367

OR Byte data logical sum(OR) (FUN 14) 5-219

-P 2-digit BCD subtraction (FUN 179) 5-199

REF External input transfer (FUN 283) !# 5-181

SDOWN 4 bit data lower-digit direction shift (FUN 255) 5-323

TMR (Direct mode 100ms timer) 5-27

UP1 Byte data upper-digit direction shift 1 (FUN 91) 5-318

W- Word data binary subtraction (FUN 93) 5-197

XCH 8-bit data exchange(FUNl32) 5-165

1.1. Usage of TOYOPUC

1.1.1. Connection between I/O devices and TOYOPUC

1.1.2. I/O address

(1) I/O coding

(2) Specifying rack number

Example 1 : For PC2/L2

Example2 : For PC2J/3J

000 010 020 030 040 050 060 070 Address

Machine unit (A) Machine unit(B)

Input Logic Output Input Logic Output

1.3.1. Input section

Address Example of Example of symbol

Devices to which TOYOPUC sends outputs (such as solenoid-operated

Address Example of Example of symbol

1.4.1. Internal relay (dummy output)

Address Example of Example of symbol

End of advance timer

Address Example of Example of symbol

Address Example of Example of symbol

Relays used to hold the current condition when power is removed.

Work finish setting

Address Example of Example of symbol

Store set value

Address Example of Example of symbol

(Note) The address must not be used duplication.

Address Example of Example of symbol

(1) In case of PC2/L2,PC2J

# : Can be used with SCPU-4.10 or later version CPU.

V92 LINK2 COMMAND USE PERMIT

V98 LINK5 COMMAND USE PERMIT

LABEL 4 LABEL 4 LABEL *4