Journal of Materials Science & Technology 97 (2022) 254–263

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Journal of Materials Science & Technology

journal homepage: www.elsevier.com/locate/jmst

Research article

Controllable resistive switching of STO:Ag/SiO2 -based memristor

synapse for neuromorphic computing
Nasir Ilyas a,c, Jingyong Wang a, Chunmei Li a, Hao Fu c,∗, Dongyang Li a, Xiangdong Jiang a,
Deen Gu a, Yadong Jiang a,b, Wei Li a,b,∗
a
School of Optoelectronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China
b
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
c
School of Physics, University of Electronic Science and Technology of China, Chengdu 610054, China

a r t i c l e i n f o a b s t r a c t

Article history: Resistive random-access memory (RRAM) is a promising technology to develop nonvolatile memory
Received 2 February 2021 and artificial synaptic devices for brain-inspired neuromorphic computing. Here, we have developed a
Revised 20 April 2021
STO:Ag/SiO2 bilayer based memristor that has exhibited a filamentary resistive switching with stable en-
Accepted 22 April 2021
durance and long-term data retention ability. The memristor also exhibits a tunable resistance modula-
Available online 12 July 2021
tion under positive and negative pulse trains, which could fully mimic the potentiation and depression
Key words: behavior like a bio-synapse. Several synaptic plasticity functions, including long-term potentiation (LTP)
Ag/STO:Ag/SiO2 /p++ -Si memristor and long-term depression (LTD), paired-pulsed facilitation (PPF), spike-rate-dependent-plasticity (SRDP),
Filamentary resistive switching and post-tetanic potentiation (PTP), are faithfully implemented with the fabricated memristor. More-
Resistance/weight modulation over, to demonstrate the feasibility of our memristor synapse for neuromorphic applications, spike-time-
Synaptic plasticity dependent plasticity (STDP) is also investigated. Based on conductive atomic force microscopy observa-
Normomorphic computing
tions and electrical transport model analyses, it can be concluded that it is the controlled formation and
rupture of Ag filaments that are responsible for the resistive switching while exhibiting a switching ratio
of ~103 along with a good endurance and stability suitable for nonvolatile memory applications. Before
fully electroforming, the gradual conductance modulation of Ag/STO:Ag/SiO2 /p++ -Si memristor can be re-
alized, and the working mechanism could be explained by the succeeding growth and contraction of Ag
filaments promoted by a redox reaction. This newly fabricated memristor may enable the development of
nonvolatile memory and realize controllable resistance/weight modulation when applied as an artificial
synapse for neuromorphic computing.
© 2021 Published by Elsevier Ltd on behalf of Chinese Society for Metals.

1. Introduction Therefore, emerging computing systems with novel architectures

Biological brains can effectively handle complicated neural tasks
through an energy-efficient and fault-tolerant manner due to in-
trinsic fusion of storage and computation [1,2]. In the brain, mem-
ory and information processing tasks are associated with activated
biological connecting points known as "synapses" between neurons
[3]. Therefore, brain-like (neuromorphic) computing is a promis-
ing idea as a new computing system that has the potential to
overcome the limitations of traditional von Neumann computa-
tional architecture. The classical von Neumann computing archi-
tecture is typically composed of very-large-scale integration (VLSI)
chips containing digital processing cores with dedicated memory
structures [4,5] that do not directly emulate real neural systems.
∗
Corresponding authors.
E-mail addresses: fuhao@uestc.edu.cn (H. Fu), wli@uestc.edu.cn (W. Li).
have been in high demand for achieving parallel networks which
can mimic the biological brain, leading to large-scale and energy-
efficient computation [2,6–8]. Recently, to realize the essential stor-
age and computation functions in parallel, a two-terminal resistive
random-access memory (RRAM) device known as “memristor” has
been proposed as an artificial synapse, in which electrical signal
transduction and synaptic weight change can be realized [9–12].
Generally, the resistive switching of memristors can be clas-
sified into two modes: digital and analog [13]. The analog resis-
tive switching has attracted research attention due to the gradual
change of the resistance, resembling the adaptive learning process
and mimicking the synaptic functions [14]. By using mixed-signal
(digital and/or analog) in a single device, neuromorphic engineer-
ing researchers have being developed novel hardwares to imple-
ment neural and synaptic dynamics, resulting in the reduction of
manufacturing complexity. It is noted that an analog neuromorphic

https://doi.org/10.1016/j.jmst.2021.04.071
1005-0302/© 2021 Published by Elsevier Ltd on behalf of Chinese Society for Metals.
N. Ilyas, J. Wang, C. Li et al.
computing system with a crossbar-based analog memristor and a
digital-assisted noise-eliminating training circuit has been realized
recently by Liu et al. [15]. Nevertheless, a memristor with both
analog and digital resistive switching in a single cell is rarely re-
ported [16,17].
It is known that both analog and digital are fundamentally dif-
ferent types of switching, and various physical models have been
suggested to explain these behaviors in memristors. For example,
the memristor could behave through (i) the migration of ions or
the carrier trapping-releasing process [18–20], (ii) the resistance
modification of the metal/insulator interface [21], and (iii) the for-
mation of localized metal-atom chains which are bridging elec-
trode materials [22]. Various device engineering and experimen-
tal methods have been proposed to realize both analog and digital
switching with the ability to exhibit synaptic features in the same
single cell device, such as Ag/NiO/Pt [23], Ag/CH3 –NH3 PbI3 x Clx /FTO
[24], Ni/Ta2 O5 /Si [25] etc.,. SrTiO3 (STO) and SiO2 have also been
widely employed in memristors as active resistive switching oxides
with promising results [26–30]. These two materials show excel-
lent wafer-scale uniformity and have conformity with conventional
metal-oxide-semiconductor (CMOS) technology. In these two kinds
of material systems, during the resistive switching process, asso-
ciated physical mechanisms are related to the formation of con-
ducting nanofilaments, either due to the reduction (i.e., Si atoms
from SiOx and Ti atoms from STO) or due to the drift/diffusion
of the metallic electrode through the oxide layer. However, it is
found that the porous structure of STO material could facilitate the
accumulation of metal ions in the memristive layer and decrease
the diffusion rate, giving rise to a significantly reduced initial re-
sistance and hence resulting in a small on/off ratio [31,32]. It is re-
ported that a multilayer structure as a memristor storage medium
can achieve stable and controllable resistive switching performance
than a single layer approach [33,34]. These multilayer structures
can improve the switching uniformity by mitigating the stochas-
tic nature of filament and the controllability of attaining synap-
tic characteristics. Up to now, although many multilayer material
structures have been reported [35–38], the possibility of using the
STO/SiO2 -based memristor as the artificial synapse has not been
investigated yet.
In this work, we have proposed a STO:Ag/SiO2 bilayer based
memristor using Ag as a top electrode (TE) and p++ -Si as a bottom
electrode (BE). It is demonstrated that the switching characteristics
and the resistance of Ag/STO:Ag/SiO2 /p++ -Si device can be tuned
under both positive and negative pulse trains, respectively, which
are beneficial to obtain a reliable "analog" switching behavior to
mimic bio-synaptic functions. It has also shown that long-term
potentiation (LTP), long-term depression (LTD), spike-rate depen-
dent plasticity (SRDP), paired-pulse facilitation (PPF), post-tetanic
potentiation (PTP), and spike-time-dependent plasticity (STDP)
have been successfully demonstrated in our Ag/STO:Ag/SiO2 /p++ -
Si memristors. Analog and/or digital switching can easily be deter-
mined depending on the applied voltage under both DC sweep and
pulse train conditions. The physical mechanism of the device could
mainly be attributed to Ag ion migration and formation/rupture
of conductive filaments inside the memristor. The present work
would promote a more accurate mix of analog/digital switching in
memristor for use in neuromorphic computing.
2. Experimental details
2.1. Fabrication of a RRAM device
Both the Ag/STO:Ag/SiO2 /p++ -Si and Ag/STO/SiO2 /p++ -Si de-
vices were fabricated as follows. A commercially available p++ -
Si substrate was used for device fabrication. First, a 70 nm thick
SiO2 layer was deposited on a p++ -Si substrate via radio frequency
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Journal of Materials Science & Technology 97 (2022) 254–263
(RF) magnetron sputtering at room temperature with a SiO2 target.
Then, a 70 nm thick pure STO layer and a 70 nm thick Ag-doped
STO (STO:Ag) layer were deposited separately by using RF mag-
netron sputtering (pure STO layer) or co-sputtering (STO:Ag layer)
from pure SrTiO3 ceramic target without or with Ag slices. Finally,
while attaching a shadow mask containing circles with a diameter
of 100 μm, a 50 nm thick Ag film patterning was sputtered with
an Ag target and completed after removing the mask. All the de-
position processes were carried out at room temperature. The Ag
film was used as the top electrode (TE), and the cleaned p++ -Si
substrate with a low resistivity of 0.0 01–0.0 05 Ω cm was used as
a bottom electrode in our devices.
2.2. Characterization methods
For the structural characterization and energy-dispersive X-ray
spectroscopy (EDS) analysis, a cross-sectional TEM sample was pre-
pared by a focus ion beam method utilizing an FEI Quanta 3D FEG
dual-beam instrument and then conducted/observed by JEOL JEM-
2100F TEM. Conduction atomic force microscopy (C-AFM, JEOL,
JSPM-5200) was taken to investigate the sample surface after a
high voltage was applied. All the electrical characterizations were
carried out using a prob-system hooked with a Keithley 2636B
power source at room temperature.
3. Results and discussion
Fig. 1(A) shows the graphical illustration of the fabricated
Ag/STO:Ag/SiO2 /p++ -Si memristor. The two-terminal circuit con-
figuration of the memristor indicates that Ag TE is biased posi-
tively or negatively, and p++ -Si BE is always grounded. The cross-
sectional TEM image is shown in Fig. 1(B), indicating that both
STO:Ag and SiO2 layers have a uniform distribution of physical
thickness. Additionally, the TEM-EDS mapping was employed fur-
ther to confirm the thickness and chemical composition of bilayer
films. Fig. 1(C) shows the elemental composition across the cross-
section of layers, including STO:Ag, SiO2 , TE, and BE of the yellow
region shown in Fig. 1B, indicating the elemental percentage inside
the formed STO:Ag and SiO2 films. From each elemental composi-
tion and its related distribution, the memristive film thickness can
also be well identified in the structure of Ag/STO:Ag/SiO2 /p++ -Si
device, each of which is approximately ~70 nm. The TEM-EDS el-
emental mappings shown in Fig. 1(D-H) for Si, O, Sr, Ti, and Ag
correspond to the deposited layers, further confirming the physical
thickness and elemental distributions.
Based on the analysis from Fig. 1(B-H), it can be concluded
that a bilayer STO:Ag/SiO2 film with a total physical thickness of
~140 nm can be obtained using the sputtering method and that
well elemental distributions with uniform interfacial states can
also be realized.
As for comparison, the resistive switching properties of single-
layered SiO2 and single-layered STO memristors are also studied.
Firstly, the representative I-V curves of Ag/SiO2 /p++ -Si structure (il-
lustrated in the inset of Fig. 2(A)) by applying a voltage sweep (i.e.,
0 V → 5.0 V → 0 V → −5.0 V → 0 V) with a compliance current
(Icc ) of 10 mA are shown in Fig. 2(A). The voltage scan rate for
both set and reset processes is 100 mV/s. After applying forward-
biased sweep, the obtained I-V curves show that the device ex-
hibits an abrupt resistance change from a high-resistance state
(HRS) to a low-resistance state (LRS) known as the “set” state, the
same as that has been shown in Ag/SiO2 /Pt memristor [39]. In con-
trast, the reverse-biased sweep switches the device to attain the
HRS again (“reset” state). Secondly, the representative I-V curves of
Ag/STO/p++ -Si structure (illustrated in the inset of Fig. 2(D)) by ap-
plying a voltage sweep (i.e., 0 V → 5.0 V → 0 V → −5.0 V → 0 V)
with a compliance current (Icc ) of 1 mA are shown in Fig. 2(D).
N. Ilyas, J. Wang, C. Li et al. Journal of Materials Science & Technology 97 (2022) 254–263

Fig. 1. (A) Schematic model of the Ag/STO:Ag/SiO2 /p++ -Si memristor. (B) Cross-sectional TEM image of the Ag/STO:Ag/SiO2 /p++ -Si memristor. (C–H) TEM-EDS spectrum and
elemental-mapping images of the region indicated by yellow square for Sr, Ti, Ag, O and Si, respectively.

Fig. 2. (A, D) I-V curves of Ag/SiO2 /p++ -Si and Ag/STO/p++ -Si devices, respectively, the insets are the demonstrating structures differently. (B, C) Cumulative distribution of
resistance values at HRS/LRS and histogram of Ag/SiO2 /p++ -Si device for set and reset of consecutive 100 sweep cycles drawn from Fig. S1. (E, F) Cumulative distribution of
resistance values at HRS/LRS and histogram of Ag/STO/p++ -Si device for set and reset of consecutive 100 sweep cycles drawn from Fig. S1.

The device also exhibits the resistance transition from HRS to LRS
when Ag TE is positively biased and from LRS to HRS when Ag
TE is negatively biased. Both devices exhibit obvious I-V hysteresis
phenomenon at the positive and negative voltage regions. It is wor-
thy of notice, however, that the I-V hysteresis of the Ag/SiO2 /p++ -Si
device is larger than that of the Ag/STO/p++ -Si device, attributing
a smaller set voltage and a larger flux caused by the large diffusion
coefficient of Ag+ ions in SiO2 compared to those in STO, resulting
in a high volume of Ag filaments as well as a lower LRS. Fig. 2(D)
shows that the reduced initial current and the low LRS/HRS ra-
tio with smaller I-V hysteresis might have resulted from the slow
growth of Ag-filaments in the STO layer. It has been reported that
a more robust filament, which is challenging to be ruptured, re-
quires a higher reset voltage [40,41]. Compared to a reset voltage
of ~ −1.8 V in the Ag/STO/p++ -Si device, a higher reset voltage of
~ −2.2 V is required in the Ag/SiO2 /p++ -Si device, confirming the
formation of a more robust filament in a single-layered SiO2 de-
vice.
Meanwhile, to verify the performance endurance of the above
two devices, multiple cycles of DC sweeping are also carried out,
as shown in Fig. S1 (Supporting Information). The cumulative dis-
tribution of resistance values for LRS and HRS are extracted at
a read voltage of 0.5 V and shown in Fig. 2(B, E). The average
value (μ) and relative fluctuation of LRS and HRS are 0.79 V/35%
and −1.23 V/38% for Ag/SiO2 /p++ -Si device, and 0.79 V/25% and
−1.23 V/20% for Ag/STO/p++ -Si device, respectively. These high

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Fig. 3. (A) I-V curves of Ag/STO:Ag/SiO2 /p++ -Si memristor, the inset shows the electroforming of Ag/STO/SiO2 /p++ -Si device. (B) Evolution of resistance values at HRS and LRS
upto 50 0 0 consecutive set/reset cycles. (C) I-V curves of the Ag/STO:Ag/SiO2 /p++ -Si device under different compliance currents. (D) Retention characteristics of 5 resistance
states for over 103 s. (E, F) Cumulative distribution of HRS and LRS values and histograms of the reset/set operating voltage in 100 randomly selected devices.
variabilities in the above filamentary switching devices might re-
sult from the random rupture/formation of the filaments. Fig. S1
shows large fluctuations in cyclic reliability test after 100 consec-
utive sweeps. Again, a gradual decrease of the LRS/HRS ratio in
Ag/STO/p++ -Si device can be easily seen, and the slow diffusion
of Ag+ ions might cause it. Similar phenomena have also been re-
alized in Cu-based and oxygen-based devices [42].
The histogram and statistical chats in Fig. 2(C, F) show that the
set and reset voltages for 100 sweeps range from 0.8 V to 3.2 V and
from −1.4 V to −4.8 V in the single-SiO2 -layered memristor, but
those from 1.8 V to 4.0 V and from −1.5 V to −3.2 V in the single-
STO-layered memristor, respectively. These widespread resistance
states and operating voltage ranges could be considered from ran-
domly originated Ag conductive filaments in the two single-layered
memristor devices. In fact, to realize a better switching perfor-
mance in filamentary resistive switching devices, a controlled dy-
namic of metal filaments (here in our recent study, Ag filaments) is
highly required. Therefore, a new material system with a collabo-
rated manipulation of Ag+ ions dynamics and a controlled growth
of Ag filaments is required to address these challenges. Several
studies have published several studies, including in situ TEM ob-
servation. The dynamic process of forming and dissolving Ag fila-
ments in the dielectric layer can clearly be observed [43]. It has
also been reported that different diffusion rates of Ag+ ions in di-
verse dielectric materials could modify the growth and status of
Ag filaments, including their morphology, size, and density, finally
resulting in a controlled device resistance [44].
Here, to modify the Ag filament dynamics for realizing a con-
trolled filamentary resistive switching, STO:Ag/SiO2 layers are in-
troduced between Ag TE and p++ -Si BE, as shown in Fig. 1(B). This
bilayered memristor device with Ag/STO:Ag/SiO2 /p++ -Si structure
shows a stable I-V hysteresis phenomenon at both negative and
positive voltage ranges, and none of forming processes is required
for the switching behaviors, as shown in Fig. 3(A). As can be seen
in the inset of Fig. 3(A), however, the memristor device structured
as Ag/STO/SiO2 /p++ -Si still requires an electroforming process for
resistive switching. It demonstrates here that the presence of Ag
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Journal of Materials Science & Technology 97 (2022) 254–263
atoms inside the STO:Ag acts as a Ag ion reservoir for filament for-
mation in Ag/STO:Ag/SiO2 /p++ -Si device.
Interestingly, as in Fig. 3(B), different from single-layer
devices, a uniform resistive switching can be obtained in
Ag/STO:Ag/SiO2 /p++ -Si device by repeated I-V sweeps. In addition,
the stability and endurance of STO:Ag/SiO2 bilayer devices are fur-
ther tested under robust cyclic operation. The LRS and HRS are
measured at a read voltage of 0.5 V after set and reset opera-
tions. It can be seen in Fig. 3(B) that after repeated 50 0 0 I-V cycles,
the ratio of LRS/HRS named as switching window shows no degra-
dation. It has early been reported that different Icc could modify
the growth of Ag filaments, including their morphology, size, and
density, leading to a multiple controlled resistance at LRS of the
device [23,45]. The stability and reliability of multilevel resistance
states are further verified as shown in Fig. 3(D), in which the re-
tention time curves of different resistance levels at LRS last over
103 s. Fig. 3(C) shows several I-V curves resulted from a higher Icc
as 4 mA, 6 mA, 8 mA and 10 mA, indicating that a more robust
filament might be obtained at LRS.
The device-to-device variation of switching parameters from
randomly selected 100 devices is also analyzed to confirm the uni-
formity. The I-V characteristics of all of the devices shown in Fig.
S2 display a remarkable uniformity. Fig. 3(E, F) demonstrates the
cumulative distributions of resistance states (i.e., HRS and LRS) and
statistical analysis of operational voltages. It is shown in Fig. 3(E)
that both LRS and HRS values are tightly distributed regardless
of the random selection of the devices. The histogram plotted in
Fig. 3(F) shows that operating voltages are mainly in the range of
0.9 V to 3.1 V (set) and −0.7 V to −2.7 V (reset), respectively. Here,
a set or reset voltage is defined as the voltage at which the ab-
solute value of current increases or decreases. The standard devia-
tion (SD) of the switching voltages is also calculated. The statistical
chart in the inset of Fig. 3(F) indicates that there is a less scattered
statistical data and that the average standard deviation of operat-
ing voltages of −0.466 V/0.148 V (set) and 1.113 V/0.574 V (reset)
is obtained. These narrow distributions suggest a better uniformity
of resistive switching in all the devices.
N. Ilyas, J. Wang, C. Li et al. Journal of Materials Science & Technology 97 (2022) 254–263

Fig. 4. Schematic illustration, C-AFM current mapping images and I-V analysis in double logarithmic scale for physical mechanism involve in resistive switching behavior. (A)
Pristine Ag/STO:Ag/SiO2 /p++ -Si memristor. (B, C) The electroforming (SET) and RESET by Ag atoms migrated from the top electrode to the bottom electrode and vice versa.
(D-F) C-AFM current mapping images (read voltage: 0.5 V; SET voltage: 10 V; RESET voltage: −8.0 V). The insets show the profile lines of the current maps. The scanned
area is 5 μm × 5 μm. (G, H) Fitting results for set and reset from replotted I-V curve in double logarithmic scale. (I) Temperature effect of LRS state and linear fitting of
obtained data.

In the ECM device, the resistance switching of the memristor is
based on the formation and rupture of metallic (Ag, Cu, etc.) con-
ductive filaments inside the dielectric layer. As mentioned previ-
ously, random growth and dissolution of conductive filaments in
the ECM device will result in a broad operation distribution of
resistance states and operational voltages [34,46–48]. Here, how-
ever, our newly proposed memristor devices based on STO:Ag/SiO2
bilayer exhibit relatively uniform switching behaviors, and it is,
therefore, crucial to understand the resistive switching behavior
in Ag/STO:Ag/SiO2 /p++ -Si devices in which the formation and rup-
ture of conducting Ag filaments could be the most plausible ex-
planation in this kind of ECM devices [40,49]. Fig. 4(A) shows
a schematic diagram of a pristine Ag/STO:Ag/SiO2 /p++ -Si device.
When the Ag TE is biased positively, the oxidation occurs on
the electromagnetically active Ag metal and generates Ag+ cations
(Ag → Ag+ +e− ), as shown in Fig. 4(B). These cations are accumu-
lated near the TE interface and subsequently drifted toward p++ -Si
BE through STO:Ag/SiO2 bilayers and then deoxidated to Ag atoms
(Ag+ +e− → Ag). The further increase in electrical bias could grow
the Ag-filaments, bridge the TE and the BE, and finally switch the
device to LRS from HRS abruptly. In this case, given a growth of
Ag-filaments near the interface between TE and STO:Ag film, the
porous nature of STO could facilitate the accumulation of more Ag
atoms and thus slow down the mobility of Ag cations. If the TE
is negatively biased, shown in Fig. 4(C), rapid dissolution of Ag-
filaments by Joule heating could switch the resistance state to LRS
again.
For experimental confirmation of the growth/dissolution of Ag
metallic filaments, the C-AFM observations of both pristine and
electroformed devices are performed, in which the size and po-
sition of the conductive filaments are well confirmed. For the C-
AFM mapping investigation, another device with SiO2 /STO:Ag/Ag/c-
Si structure was fabricated according to the above-mentioned ex-
perimental details. Fig. S3 shows the schematic diagram of the
testing process for C-AFM measurements. First, the C-AFM scan-
ning probe tip is grounded while a positive biased voltage is ap-
plied to Ag BE to realize the electroforming of the device. Fig. 4(D,
E) shows C-AFM images of an as-deposited device (HRS) and fully
electroformed device (LRS), respectively. Here, as in Fig. 4(E), the
electroforming voltage is about 8.0 V, which is higher than that
of 4.0 V (Fig. 3(A)), possibly due to the high energy barrier and
non-uniform electric field caused by the C-AFM scanning probe.
During the C-AFM measurements, the tip of the scanning probe
is biased positively with 0.5 V. The scanning area in the pristine

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Fig. 5. (A) Device response, (B) endurance test result and (C) retention property under a pulsed stimulation mode. The device is stimulated by a pulse bias of height +3.0 V
for set and −3.0 V for reset, and the response current is measured at +0.3 V.
device shows a uniformly low current of ~0.1 nA, as shown in
Fig. 4(D), owing to a uniform surface morphology of the amor-
phous film. When the device is fully electroformed with 8.0 V, the
C-AFM image in Fig. 4(E) shows a highly localized conductive re-
gion of 5.0 μA with many other small current spikes less than 0.5
nA, indicating the growth of high-volume Ag conductive filaments.
In contrast, when the tip of the scanning probe is negatively bi-
ased with 4.0 V, the size of conducting spot is decreased and the
scanning current is 0.1 μA, indicating the dissolution of conductive
Ag-filaments from the weakest part near to the p++ -Si BE shown
as in Fig. 4(F). The simultaneously current testing and microstruc-
tural mapping provide well the direct evidence of formation and
dissolution of the confined conduction path in STO:Ag/SiO2 layers.
As shown in Fig. 4(G, H), the charge transport behavior is al-
ways taken into account to confirm the physical mechanism by fit-
ting the positive and negative regions of the I-V curve as plotted in
the semilogarithmic scale. In the positive region (Fig. 4(G)), it can
be seen from the fitted results in HRS that the charge transport
behavior follows the trap-controlled space charge limited conduc-
tion (SCLC) mechanism, consisting of the Ohmic (slope ~1.1) region,
the Mott-Gurney law (slope ~2.2) region, and the steep current
(slope ~8.5) region [40]. The SCLC, Poole–Frenkel and Ohmic con-
duction will be realized sequentially in LRS if the trap-filled SCLC
dominates the HRS conduction mechanism. However, the fitted re-
sults show that the current decreases linearly with the decreas-
ing voltage, and no steep drop in current is observed, indicating
the Ohmic characteristics. Fitting results in Fig. 4(H) for the nega-
tive region demonstrate that the charge transport changes from the
Ohmic conduction to the trap-filled SCLC. The resistance in LRS is
measured as a function of temperature (300 to 400 K) when the
memristor is being electroformed with a Icc =10 mA, as in Fig. 4(I).
It is observed that the resistance of the device is increased lin-
early with temperature indicating a typical charge transport be-
havior of metals. The temperature coefficient (α ) is then calculated
as 0.9 × 10−3 K − 1 from the linearly fitted data, close to the α
value for Ag nanowire [50]. The above results confirm that the
Ag-filament is responsible for the switched LRS of electroformed
Ag/STO:Ag/SiO2 /p++ -Si device consistent with the ECM hypothesis
and the dissolution of the Ag-filament occurs at the weakest part
near the BE interface there then the HRS recovers back.
For the potential applications in data memory, the resistance
states of the Ag/STO:Ag/SiO2 /p++ -Si device should be examined by
applying a pulse programming mode. Herein, an alternate pulse
programming with a + 5 V (set) bias and a −3.5 V (reset) bias is
carried out on the device, and the corresponding current response
subjected to set and reset pulses is shown in Fig. 5(A). The resis-
tance of the device is measured by a read pulse of +0.3 V after the
stimulation process. Fig. 5(B) shows that the device presents a sta-
ble and good endurance behavior, keeping enough ratio of LRS/HRS
over more than 103 cycles under pulse programming biases. More-
over, the resistance states of the testing device are also measured
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Journal of Materials Science & Technology 97 (2022) 254–263
to ensure long-term data retention. It can be seen from Fig. 5(C)
that the LRS and HRS are stable and holding a good long-term data
retention ability (>104 s at room temperature) during the set and
reset pulse bias stimulation process with a continuous read voltage
of 0.3 V. Based on above results, it can be concluded that the de-
vice exhibits a large on/off ratio of about ~103 with a rapid forma-
tion of conducting filaments at a relatively high operating voltage,
showing out a potential for nonvolatile memory applications.
In addition to nonvolatile memory applications, our newly pro-
posed RRAM device structured as Ag/STO:Ag/SiO2 /p++ -Si can also
be used as an artificial synapse for neuromorphic computation,
and hence analog conductance modulation is needed to simulate
the incremental synaptic weight transfer in the biological synapse
[51]. In our device, the direct current (DC) switching properties
have been studied and optimized to implement bi-directional ana-
log resistance transition before evaluating synaptic characteristics
in detail. First, the gradual set and reset processes on the device
using non-identical consecutive sweeps are studied. Fig. 6(A, B)
shows a noticeable increase and decrease in current flow under
repeated positive (1st -9th ) and negative (10th -18th ) voltage sweeps,
respectively. Initially, the memristor device is gradually set to an
LRS when applied a sweep bias of 1.6 V. After that, a consecutive
set process is followed with a suitable sweep voltage ranging from
1.6 V to 2.8 V using an increment of 0.2 V. This set process in-
creases the response current gradually, leading to multiple resis-
tance states of LRS. The repeated negative sweep results in a grad-
ual increase in the effective gap between the Ag filament tip and
BE while decreasing the cross-sectional area of Ag filaments. Af-
ter that, a gradual reset process from predefined LRS is realized
using repeated negative sweep biases in the range of 1.0 V-2.6 V
using a step voltage of 0.2 V. This type of resistance modulation in
multiple intermediate states indicates the existence of analog-type
switching [52], distinguishing it from the digital-type of switch-
ing. As mentioned above, the abrupt change in resistance between
HRS and LRS similar to digital-type switching could be realized
by rapid formation/rupture of conductive Ag filament. However, to
bridge the TE and BE completely, a repeated sweep bias ranging
from 1.6 V to 2.6 V is not enough. The increasing voltage for each
sweep pushes more Ag atoms between the Ag/STO interface, led
to a decreased effective gap between TE and BE. Therefore, un-
der repeated biases with a 0.2 V increment, the filament gap be-
tween electrodes might be decreased, and the corresponding lat-
eral size of Ag filament might also be increased, finally leading to
an increase in current flow through the device. Based on these ex-
perimental results, the down-up and up-down conductance mod-
ulation of the memristor device has been demonstrated, which is
much similar to the transition of weight changes in a biological
synapse, simply by a limited but repeated DC voltage sweeping on
the device. Notably, the I-V curve traces the former left off slope,
showing a typical phenomenon in a memristor for analog resistive
switching [53].
N. Ilyas, J. Wang, C. Li et al.
Fig. 6. (A) Gradual set and (B) reset processes by repeated sweeping positive and negative voltage respectively, ranging from 1.6 V to 2.6 V with step voltage of 0.2 V. (C, D)
Response to the pulses with +2.0 V for potentiation and −2.0 V for depression of the Ag/STO:Ag/SiO2 /p++ -Si device.
In order to confirm the gradual change of conductance in our
device, the resistance is also tuned by pulse programming. Fig. 6(C)
shows the voltage applied as black and the corresponding current
response as a red line along with the pulse trains and numbers.
The pulse amplitude for the potentiation process is fixed to 2.0 V
and for the depression process, the pulse amplitude is fixed to
−2.0 V, and both the width and the delay time for the repeated
pulse are fixed at 5.0 ms. It can be seen that the resulting con-
ductance responds to either potentiating or depressive stimuli re-
gardless of pulse polarity, which is the same for weight modulation
as in biological synapses. Fig. 6(D) shows that the conductance of
our device is tunable gradually regardless of positive or negative
pulse bias. Therefore, the STO:Ag/SiO2 based RRAM device exhibit-
ing nonlinear I-V characteristics has the potential to emulate the
biological functions faithfully with suitable pulse-assisted stimuli.
Similar to bio-synapses, the selected synaptic features in
Ag/STO:Ag/SiO2 /p++ -Si memristor device are examined to mimic
the synaptic plasticity modulation the human brain. Fig. 7(A, B)
illustrates the synaptic weight change between the axon (presy-
naptic neuron) and the dendrite (postsynaptic neuron) and a corre-
sponding fabricated memristor. In the human brain, the hippocam-
pus is shown in Fig. 7(A), which controls memory [54]. In a bi-
ological synapse, the synaptic weight is adjusted between presy-
naptic and postsynaptic neurons via releasing Ca2+ or K+ influx
in synaptic cleft when the axon receives an action potential [55].
As in the biological synapse, the conductance of STO:Ag/SiO2 di-
electric layers can artificially be modulated by the migration of Ag
filaments (drift in or drift out) under DC pulse programming. In
the electronic synapse, the STO:Ag/SiO2 layers act as the synaptic
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Journal of Materials Science & Technology 97 (2022) 254–263
cleft between TE and BE terminals, where the applied pulse signal
is transmitted. As mentioned above, the incremental conductance
modulation of Ag/STO:Ag/SiO2 /p++ -Si device under pulse program-
ming is realized similar to the synaptic weight modulation in the
biological synapse. Again, in Fig. 6(D), the memristor device shows
potentiation and depression under repeated pulse biases, gener-
ally known as LTP and LTD phenomena in the electronic synapse,
where the synaptic weight changes and transfer efficiencies could
be determined by dynamical changes in connection strength be-
tween electrodes through continuous pulse stimulations. The per-
formance of electronic synapse could be determined by linearity in
synaptic weight change during LTP and LTD [56]. It can be found
that the gradual conductance change with better linearity dur-
ing potentiation and depression processes in Ag/STO:Ag/SiO2 /p++ -
Si device has demonstrated a potential for neuromorphic comput-
ing.
Besides essential long-term synaptic plasticity functions (i.e.,
LTP and LTD), SRDP, PPF, and PTP are common short-term plas-
ticity functions. It is known that frequency-dependent stimulation
influences synaptic weight control in biological synapses. Thus, the
STO:Ag/SiO2 based device is stimulated by different pulse pro-
gramming exhibiting the same pulse number and different fre-
quencies. The response of Ag/STO:Ag/SiO2 /p++ -Si device, when
stimulated with a pair of presynaptic and postsynaptic pulses,
is shown in Fig. 7(C). It can be found that the first stimulated
pulse increases the current response, and before recovery time,
the second pulse reinforces the current response. The interval be-
tween the stimulated pulses significantly affects the modulation
of synaptic weight depending on the recovery time of Ag+ ions
N. Ilyas, J. Wang, C. Li et al.
Fig. 7. (A) Schematic diagram of biological synapse and synaptic modulation between presynaptic and post-synapse with the migration of Ca2+ or K+ ions when an action
potential is received. (B) Schematic diagram of STO:Ag/SiO2 -based device and its conductance modulation at pulse bias stimulation. (C, D) PPF and fitting results of current
response with pulse intervals. (E, F) Illustration of programming for pulse interval of 5 ms, 10 ms, 15 ms and 20 ms, and the current responses.
in STO:Ag/SiO2 layers. This type of synaptic effect is known as
PPF [57]. It can also be found in Fig. 7(D) that decreasing the
pulse interval will increase the current response of the device,
i.e., the shortest interval induces the highest PPF (%) when com-
pared to the longest interval stimuli. Here, the relative change
in synaptic weight at consecutive pulses is calculated as PPF
(%)=100 × (I2 −I1 )/I1 . These results indicate the dependence on the
time difference between presynaptic and postsynaptic stimulation
processes, showing a resemblance to that in the biological synapse.
Similarly, in the biological synapse, the synaptic weight change can
be realized for a short interval as a result of Ca2+ ions released
upon the neural pulse. Simultaneously, another stimulation dur-
ing the recovery time of Ca2+ reinforces the synaptic change to be
more extensive than that of the first stimulus [57].
The influence of pulse rate on current change (I) is further
evaluated with pulse trains comprised of the same pulse numbers
but different frequencies by adjusting the pulse interval of consec-
utive pulses. Fig. 7(E) illustrates the four sets of pulse trains with
the same height (i.e., 1.5 V) and width (i.e., 0.5 ms) but different
pulse intervals. The current change (I) with the change in pulse
rate or frequency is shown in Fig. 7(F). The total change in cur-
rent after stimulation with different pulse frequencies is measured
as I=[(IN −I1 )/I1 ]. The gradual increase in synaptic strength upon
consecutive presynaptic stimulations for a longer time is termed
as post-tetanic potentiation (PTP) phenomenon. It can be seen
that the current response in the device shows an apparent depen-
dence on pulse frequency during the stimulation process. The con-
ductance changes faster with lowering pulse interval (higher fre-
quency). These results indicate that the pulse rate can influence
synaptic weight in our Ag/STO:Ag/SiO2 /p++ -Si device.
Interestingly, with the increase in pulse interval, the memristor
conductance reaches a saturated state rapidly at last. It is known
that the synaptic weight change could be increased and further
strengthened with continuous learning in a biological synapse and
that due to an intrinsic enforced restriction to modulate the Heb-
bian rule, the synaptic weight has a limited value so that the con-
ductance could be reached at saturation state [58]. As mentioned
above, in our Ag/STO:Ag/SiO2 /p++ -Si device, the gap between elec-
trodes might be decreased, and the cross-sectional size of Ag fila-
ments can be increased under repeated stimulations, leading to an
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Journal of Materials Science & Technology 97 (2022) 254–263
increase in current flow through the device. The high current re-
sponse at PTP can be attributed to the limited recovery time and
more robust Ag filament formation during high-frequency stimula-
tion (limited to pulse interval). In contrast, a longer recovery time
between the facilitating pulses forming a weaker Ag filament, re-
sulting in the lowest response of current enhancement.
Moreover, the synaptic weight change can be determined by the
temporal order of presynaptic and postsynaptic spikes, known as
spike-time-dependent-plasticity (STDP). STDP is one of the critical
Hebbian learning rules of biological synapses [59], and the success-
ful demonstration of STDP is essential to determine the plausibil-
ity of the fabricated electronic synapses for neuromorphic appli-
cations. Therefore, a suitable pulse scheme is designed to demon-
strate the STDP on our Ag/STO:Ag/SiO2 /p++ -Si device for stimula-
tion. Herein, Ag TE is considered for presynaptic stimulation, and
p++ -Si is considered for postsynaptic stimulation. If the presynap-
tic pulse precedes the postsynaptic pulse (t > 0), it will result
in LTP. However, if the postsynaptic pulse precedes the presynaptic
pulse (t < 0), it then will result in LTD. The difference between
presynaptic and postsynaptic pulse time is calculated as t=tpre -
tpost . A schematic illustration of both presynaptic and postsynap-
tic pulses can be seen in the inset of Fig. 8, and the correlated
pulse parameters are designed as follows. For a presynaptic pulse,
pulse height is 1.2 V with a width of 5 ms, but for a postsynap-
tic pulse, pulse high is −1.2 V with a width of 5 ms. The synaptic
weight change (W) after presynaptic and postsynaptic stimula-
tion for both t > 0 and t < 0 can be calculated as [60]:
W = A+ e−t/τ+ if t > 0 (1)
W = A− e−t/τ− if t < 0 (2)
In these equations Eqs. (1) and (2), A+ and A− refer to the scal-
ing factor, τ +, and τ − correspond to the decaying constant. In the
case of t > 0, the synaptic weight change (W) is increased with
decreasing timing difference (t)., indicating the presence of LTP
behavior. In contrast, when t < 0, W is decreased with an in-
crease t, again reflecting the existence of LTD behavior. Herein,
when shorter t between the stimulating spikes, a larger response
of the device conductance changes due to a larger change in synap-
tic weight. These results confirm that our Ag/STO:Ag/SiO2 /p++ -Si
N. Ilyas, J. Wang, C. Li et al.
Fig. 8. The synaptic weight change (W) of Ag/STO:Ag/SiO2 /p++ -Si memristor with
various time difference (t) of preceding or lagging pulses set on it.
memristor exhibits an STDP learning rule with the controllable
change in synaptic weight, similar to a biological synapse.
4. Conclusion
In conclusion, the STO:Ag/SiO2 based memristor has demon-
strated a stable switching performance, which likely originates
from the controlled rupture/rejuvenation of Ag filaments in a two-
layer structure due to different ion transport rates. The C-AFM
tests confirm the formation and dissolution of Ag filaments un-
der a relatively higher voltage, indicating a rapid digital type of
resistive switching. The gradual increase and decrease in current
could be explained by successive growth and contraction of Ag
filaments, promoted by a redox reaction. Based on the controlled
growth of Ag filaments, a memristive synapse is realized where the
long-term potentiation (LTP), long-term depression (LTD), spike-
rate-dependent plasticity (SRDP), pair-pulsed facilitation (PPF), and
post-tetanic potentiation (PTP) can be mimicked by applying a
suitable pulse bias. Moreover, for neuromorphic computing feasi-
bility, the synaptic weight changes with presynaptic and postsy-
naptic temporal order of pulses as the STDP can be mimicked in
the fabricated memristor.
Credit authorship contribution statement
Nasir Ilyas: Conceptualization, Methodology, Investigation,
Data curation, Visualization, Writing-original draft. Chunmei Li:
Methodology, Investigation, Visualization. Jingyong Wang: Inves-
tigation, Formal analysis. Hao Fu: Validation, Formal analysis.
Dongyang Li: Investigation, Visualization. Xiangdong Jiang: For-
mal analysis, Deen Gu: Formal analysis. Yadong Jiang: Validation,
Funding. Wei Li: Validation, Writing-review & editing, Formal anal-
ysis, Funding, and Supervision.
Declaration of Competing Interest
The authors declare that they have no competing financial in-
terests.
Acknowledgments
This work was financially supported by the National Science
Funds for Excellent Young Scholars of China (no. 61822106) and the
Natural Science Foundation of China (no. U19A2070).
262
Journal of Materials Science & Technology 97 (2022) 254–263
Supplementary materials
Supplementary material associated with this article can be
found, in the online version, at doi:10.1016/j.jmst.2021.04.071.
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