Chap 5 Memory Management

Memory Management
Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne ©2009
Outline
 Background
 Swapping
 Contiguous Memory Allocation
 Paging
 Structure of the Page Table
 Segmentation
 Examples on different topics
Operating System Concepts – 8th Edition 8.2 Silberschatz, Galvin and Gagne ©2009
Objectives
 To provide a detailed description of various ways of organizing memory

hardware
 To discuss various memory-management techniques, including paging and

segmentation
Memory
 Computer memory is any physical device capable of storing
information temporarily or permanently.
 1. Primary Memory
2. Secondary Memory
 Random Access Memory(RAM) ,is a volatile memory that
loses its contents when the computer or hardware device
losses power.
 Read Only Memory(ROM), is a non-volatile memory,
sometimes abbreviated as NVRAM, is a memory that keeps
its contents even if the power is lost.
 Computer uses special ROM called BIOS(Basic Input Output
System) which stores the software needed to access
computer hardware such as hard disk and then load an
operating system into RAM and start to execute it.
 PROM: In which you store a program. But once the PROM has
been used , you cannot wipe it clean and use it to store
something else. E.g. CD-R
 EPROM: that can be erased by exposing it to UV light.

E.g. CD-RW
 EEPROM: is a special type of ROM that can be erased by

exposing it to an electrical charge.
E.g. Pendrive
Background
 Program must be brought (from disk) into memory and placed within a
process for it to be run
 Main memory and registers are only storage CPU can access directly
 Memory unit only sees a stream of addresses + read requests, or address
+ data and write requests
 Register access in one CPU clock (or less)
 Main memory can take many cycles
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation
Need for Multi programming
 However, The CPU can directly access the main memory, Registers
and cache of the system.
 The program always executes in main memory.
 The size of main memory affects degree of Multi programming to
most of the extant.
 If the size of the main memory is larger than CPU can load more
processes in the main memory at the same time and therefore will
increase degree of Multi programming as well as CPU utilization.
Memory Allocation Preliminaries:
 Data structure used by Compiler and Operating System can be classified into the following
categories.
 Linear Data Structures
1. One-dimensional Array
2. Linked List
3. Stack
4. Queue
 Non-Linear data Structures
1. Tree
2. Graph
Swapping
 Swapping is the method of preventing an active process from
executing for a temporary time period in which another
process takes the address space that was allocated to the
former process.
 A process can be swapped temporarily out of memory to a

backing store, and then brought back into memory for
continued execution
 Total physical memory space of processes can exceed
physical memory
Contiguous Memory Allocation-
 Contiguous memory allocation is a memory allocation technique.

 It allows to store the process only in a contiguous fashion.
 Thus, entire process has to be stored as a single entity at one place inside
the memory.
Static Partitioning
 Static partitioning is a fixed size partitioning scheme.

 In this technique, main memory is pre-divided into fixed size partitions.
 The size of each partition is fixed and can not be changed.
 Each partition is allowed to store only one process.
 Under fixed size partitioning scheme, a memory of size 10
KB may be divided into fixed size partitions as-
 These partitions are allocated to the processes as they

arrive.
 The partition allocated to the arrived process depends on
the algorithm followed
Algorithms for Partition Allocation
 First Fit Algorithm

 This algorithm starts scanning the partitions serially from the starting.
 When an empty partition that is big enough to store the process is found,
it is allocated to the process.
 Obviously, the partition size has to be greater than or at least equal to
the process size.
 Best Fit Algorithm

 This algorithm first scans all the empty partitions.
 It then allocates the smallest size partition to the process.

 Worst Fit Algorithm
 This algorithm first scans all the empty partitions.
 It then allocates the largest size partition to the process.
 The idea is that splitting a large hole into two will leave a
large enough hole to be useful.
Important Points
 Point-01:
 For static partitioning,
 Best Fit Algorithm works best.
 This is because space left after the allocation inside the partition is of
very small size.
 Thus, internal fragmentation is least.
 Point-02:
 For static partitioning,
 Worst Fit Algorithm works worst.
 This is because space left after the allocation inside the partition is of
very large size.
 Thus, internal fragmentation is maximum.
Internal Fragmentation
 It occurs when the space is left inside the partition after allocating the
partition to a process.
 This space is called as internally fragmented space.
 This space can not be allocated to any other process.
 This is because only static partitioning allows to store only one process in
each partition.
 Internal Fragmentation occurs only in static partitioning.
External Fragmentation
 It occurs when the total amount of empty space required to store

the process is available in the main memory.
 But because the space is not contiguous, so the process can not
be stored.
Translating Logical Address into Physical
Address
 CPU always generates a logical address.

 A physical address is needed to access the main memory.
 Following steps are followed to translate logical address into physical
address-
Address
 Step-01:
 The translation scheme uses two registers that are under the
control of operating system.
 During context switching, the values corresponding to the process
being loaded are set in the registers.
 These two registers are-
 Relocation Register
 Limit Register
Address
 Relocation Register stores the base address or starting address

of the process in the main memory.
 Limit Register stores the size or length of the process.
 Step-02:
 CPU generates a logical address containing the address of the
instruction that it wants to read.
Address
 Step-03:
 The logical address generated by the CPU is compared with the limit of the
process.
 Now, two cases are possible-
 Case-01: Generated Address >= Limit
 If address is found to be greater than or equal to the limit, a trap is generated.
 This helps to prevent unauthorized access.
 Case-02: Generated Address < Limit
 The address must always lie in the range [0, limit-1].
 If address is found to be smaller than the limit, then the request is treated as a
valid request.
 Then, generated address is added with the base address of the process.
 The result obtained after addition is the address of the memory location storing
the required word.
Address
Advantages
 The advantages of static partitioning are-

 It is simple and easy to implement.
 It supports multiprogramming since multiple processes can be
stored inside the main memory.
 Only one memory access is required which reduces the access time.
Disadvantages
 The disadvantages of static partitioning are-

 It suffers from both internal fragmentation and external
fragmentation.
 It utilizes memory inefficiently.
 The degree of multiprogramming is limited equal to number of
partitions.
 There is a limitation on the size of process since processes with
size greater than the size of largest partition can‟t be stored
and executed.
Dynamic Partitioning
 Dynamic partitioning is a variable size partitioning scheme.

 It performs the allocation dynamically.
 When a process arrives, a partition of size equal to the size of process is
created.
 Then, that partition is allocated to the process.
 The processes arrive and leave the main memory.
 As a result, holes of different size are created in the main memory.
 These holes are allocated to the processes that arrive in future.
 Partition allocation algorithms are used to decide which hole should be
allocated to the arrived process.
Important Points-
 Point-01:
 For dynamic partitioning,
 Worst Fit Algorithm works best.
 This is because space left after allocation inside the partition is of large
size.
 There is a high probability that this space might suit the requirement of
arriving processes.
Important Points-
 Point-02:
 For dynamic partitioning,Best Fit Algorithm works worst.
 This is because space left after allocation inside the partition is of very
small size.
 There is a low probability that this space might suit the requirement of
arriving processes.
Address
Advantages
 The advantages of dynamic partitioning are-

 It does not suffer from internal fragmentation.
 Degree of multiprogramming is dynamic.
 There is no limitation on the size of processes.
Disadvantages
 The disadvantages of dynamic partitioning are-

 It suffers from external fragmentation.
 Allocation and de-allocation of memory is complex.
NOTE: Memory management unit (MMU)is a hardware device which is responsible for
the translation of virtual addresses used by software to physical addresses
used in the memory system.It handles all memory and caching operations
associated with the CPU.
Problems
 Problems on Contiguous Memory Allocation
Non-Contiguous Memory Allocation
Paging
 Paging is a fixed size partitioning scheme.
 In paging, secondary memory and main memory are divided into equal fixed size partitions.
 The partitions of secondary memory are called as pages.
 The partitions of main memory are called as frames.
 Each process is divided into parts where size of each part is same as page size.
 The size of the last part may be less than the page size.
 The pages of process are stored in the frames of main memory depending upon their availability.
Example
 Consider a process is divided into 4 pages P0, P1, P2 and P3.
 Depending upon the availability, these pages may be stored in the main
memory frames in a non-contiguous fashion as shown-
Translating Logical Address into Physical Address

 Following steps are followed to translate logical address into physical address-
 Step-01:
 CPU generates a logical address consisting of two parts-
 Page Number
 Page Offset
 Page Number specifies the specific page of the process from which CPU wants to read the
data.
 Page Offset specifies the specific word on the page that CPU wants to read.
 Step-02:
 For the page number generated by the CPU,
 Page Table provides the corresponding frame number (base address of the frame) where that
page is stored in the main memory.
 Step-03:
 The frame number combined with the page offset forms the required physical address.
 Frame number specifies the specific frame where the required page is stored.
 Page Offset specifies the specific word that has to be read from that page.
Page Table Base Register (PTBR)
Page table is stored in main memory at the time of process creation and its base address is stored
in process control block.
Paging
 Advantages of Paging-
 It allows to store parts of a single process in a non-contiguous fashion.
 It solves the problem of external fragmentation.
 Disadvantages of Paging-
 It suffers from internal fragmentation.
 There is an overhead of maintaining a page table for each process.
 The time taken to fetch the instruction increases since two memory accesses
are required (Page table and Frame).
Page Table
 Page table is a data structure.
 It maps the page number referenced by the CPU to the frame number where that
page is stored.
 Characteristics-
 Page table is stored in the main memory.
 Number of entries in a page table = Number of pages in which the process is
divided.
 Page Table Base Register (PTBR) contains the base address of page table.
 Each process has its own independent page table.
Page Table Working
 Page Table Base Register (PTBR) provides the base address of the page table.
 The base address of the page table is added with the page number referenced by the CPU.
 It gives the entry of the page table containing the frame number where the referenced page
is stored.
Page table Entry
 A page table entry contains several information about the page.
 The information contained in the page table entry varies from operating system to operating
system.
 The most important information in a page table entry is frame number
 In general, each entry of a page table contains the following information-
Frame Number-
 Frame number specifies the frame where the page is stored in the main memory.
 The number of bits in frame number depends on the number of frames in the main memory.
Page table Entry
Present / Absent Bit
 This bit is also sometimes called as valid / invalid bit.
 This bit specifies whether that page is present in the main memory or not.
 If the page is not present in the main memory, then this bit is set to 0 otherwise set to
1.
NOTE
 If the required page is not present in the main memory, then it is called as Page Fault.
 A page fault requires page initialization.
 The required page has to be initialized (fetched) from the secondary memory and brought
into the main memory.
Protection Bit-
 This bit is also sometimes called as “Read / Write bit“.
 This bit is concerned with the page protection.
 It specifies the permission to perform read and write operation on the page.
 If only read operation is allowed to be performed and no writing is allowed, then this bit
is set to 0.
 If both read and write operation are allowed to be performed, then this bit is set to 1.
Page table Entry
Reference Bit-
 Reference bit specifies whether that page has been referenced in the last
clock cycle or not.
 If the page has been referenced recently, then this bit is set to 1
otherwise set to 0.
NOTE
 Reference bit is useful for page replacement policy.
 A page that has not been referenced recently is considered a good candidate
for page replacement in LRU page replacement policy.
Caching Enabled / Disabled-
 This bit enables or disables the caching of page.
 Whenever freshness in the data is required, then caching is disabled using
this bit.
 If caching of the page is disabled, then this bit is set to 1 otherwise set
to 0.
Page table Entry
Dirty Bit
 This bit is also sometimes called as “Modified bit“.
 This bit specifies whether that page has been modified or not.
 If the page has been modified, then this bit is set to 1 otherwise set to 0.
NOTE
 In case the page is modified,before replacing the modified page with some
other page, it has to be written back in the secondary memory to avoid
losing the data.
 Dirty bit helps to avoid unnecessary writes.
 This is because if the page is not modified, then it can be directly
replaced by another page without any need of writing it back to the disk.
Important Formulas
For Main Memory-
 Physical Address Space = Size of main memory
 Size of main memory = Total number of frames x Page size
 Frame size = Page size
 If number of frames in main memory = 2X, then number of bits in frame number = X bits
 If Page size = 2X Bytes, then number of bits in page offset = X bits
 If size of main memory = 2X Bytes, then number of bits in physical address = X bits
For Process-
 Virtual Address Space = Size of process
 Number of pages the process is divided = Process size / Page size
 If process size = 2X bytes, then number of bits in virtual address space = X bits
For Page Table-
 Size of page table = Number of entries in page table x Page table entry size
 Number of entries in page table = Number of pages the process is divided
 Page table entry size = Number of bits in frame number + Number of bits used for optional
fields if any
Important Formulas
NOTE-
 In general, if the given address consists of „n‟ bits, then using „n‟
bits, 2n locations are possible.
 Then, size of memory = 2n x Size of one location.
 If the memory is byte-addressable, then size of one location = 1 byte.
 Thus, size of memory = 2n bytes.
 If the memory is word-addressable where 1 word = m bytes, then size of one
location = m bytes.
 Thus, size of memory = 2n x m bytes.
Problem-01
 Calculate the size of memory if its address consists of 22 bits and the
memory is 2-byte addressable.
Solution-
We have-
Number of locations possible with 22 bits = 222 locations
It is given that the size of one location = 2 bytes
Thus, Size of memory

= 222 x 2 bytes
= 223 bytes
= 8 MB
Problem 2
 Calculate the number of bits required in the address for memory having size
of 16 GB. Assume the memory is 4-byte adder
 Solution-
Let „n‟ number of bits are required. Then, Size of memory = 2n x 4 bytes.
Since, the given memory has size of 16 GB, so we have-
2n x 4 bytes = 16 GB
2n x 4 = 16 G
2n x 22 = 234
2n = 232
∴ n = 32 bits
Problem 3
 Consider a machine with 64 MB physical memory and a 32 bit virtual address space. If the page size is
4 KB, what is the approximate size of the page table?
Solution-
Given-
Size of main memory = 64 MB
Number of bits in virtual address space = 32 bits
Page size = 4 KB
We will consider that the memory is byte addressable.
Number of Bits in Physical Address-
Size of main memory
= 64 MB
= 226 B
Thus, Number of bits in physical address = 26 bits
Problem 3
Number of Frames in Main Memory-
Number of frames in main memory
= Size of main memory / Frame size
= 64 MB / 4 KB
= 226 B / 212 B
= 214
Thus, Number of bits in frame number = 14 bits
Number of Bits in Page Offset-
We have,
Page size
= 4 KB
= 212 B
Thus, Number of bits in page offset = 12 bits
So, Physical address is-
…Problem 3
Process Size-
Number of bits in virtual address space = 32 bits
Thus,
Process size
= 232 B
= 4 GB
Number of Entries in Page Table-
Number of pages the process is divided
= Process size / Page size
= 4 GB / 4 KB
= 220 pages
Thus, Number of entries in page table = 220 entries
…Problem 3
Page Table Size-
Page table size

= Number of entries in page table x Page table entry size
= Number of entries in page table x Number of bits in frame number
= 220 x 14 bits
≈ 220 x 16 bits (Approximating 14 bits ≈ 16 bits)
= 220 x 2 bytes
= 1 MB x 2 bytes
= 2 MB
Translation Lookaside Buffer
Disadvantage Of Paging-
 One major disadvantage of paging is-
 It increases the effective access time due to increased number of memory accesses.
 One memory access is required to get the frame number from the page table.
 Another memory access is required to get the word from the page.
Translation Lookaside Buffer-
 Translation Lookaside Buffer (TLB) is a solution that tries to reduce the effective access
time.
 Being a hardware, the access time of TLB is very less as compared to the main memory.
Structure-
 Translation Lookaside Buffer (TLB) consists of two columns-
 Page Number
 Frame Number
 In a paging scheme using TLB, the logical address generated by the CPU is translated into
the physical address using following steps-
 Step-01:
 Page Number
 Page Offset
 Step-02:
 TLB is checked to see if it contains an entry for the referenced page number.
 The referenced page number is compared with the TLB entries all at once.
 Case-01: If there is a TLB hit-
 If TLB contains an entry for the referenced page number, a TLB hit occurs.
 In this case, TLB entry is used to get the corresponding frame number for the referenced
page number.
 Case-02: If there is a TLB miss-

 If TLB does not contain an entry for the referenced page number, a TLB miss occurs.
 In this case, page table is used to get the corresponding frame number for the referenced
page number.
 Then, TLB is updated with the page number and frame number for future references.
 Step-03:
 After the frame number is obtained, it is combined with the page offset to generate the
physical address.
 Then, physical address is used to read the required word from the main memory.
 NOTE-
 In the above discussion, we have assumed that no Page Fault occurs.
 Diagram-
 The following diagram illustrates the above steps of translating logical address into physical
address-
 Flowchart-
 The following flowchart illustrates the above steps of translating logical address into physical
address-
 Important Points-
 Point-01:
 Unlike page table, there exists only one TLB in the system.
 So, whenever context switching occurs, the entire content of TLB is flushed and deleted.
 TLB is then again updated with the currently running process.
 Point-02:
 When a new process gets scheduled-
 Initially, TLB is empty. So, TLB misses are frequent.
 With every access from the page table, TLB is updated.
 After some time, TLB hits increases and TLB misses reduces.
 Point-03:
 The time taken to update TLB after getting the frame number from the page table is
negligible.
 Also, TLB is updated in parallel while fetching the word from the main memory.
 Advantages-
 The advantages of using TLB are-
 TLB reduces the effective access time.
 Only one memory access is required when TLB hit occurs.
 Disadvantages-
 A major disadvantage of using TLB is-
 When a context switching occurs, the entire content of the TLB is flushed.
 Then, TLB is again updated with the currently running process. This happens again and
again.
 Other disadvantages are-
 TLB can hold the data of only one process at a time.
 When context switches occur frequently, the performance of TLB degrades due to low hit
ratio.
 As it is a special hardware, it involves additional cost.
 Effective Access Time-

 In a single level paging using TLB, the effective access time is given as
Problem 1
 A paging scheme uses a Translation Lookaside buffer (TLB). A TLB access

takes 10 ns and a main memory access takes 50 ns. What is the effective
access time (in ns) if the TLB hit ratio is 90% and there is no page fault?
Solution-
Given-
TLB access time = 10 ns
Main memory access time = 50 ns
TLB Hit ratio = 90% = 0.9
Calculating TLB Miss Ratio-
TLB Miss ratio
= 1 – TLB Hit ratio
= 1 – 0.9
= 0.1
…Problem 1
Calculating Effective Access Time-
Substituting values in the above formula, we get-
Effective Access Time
= 0.9 x { 10 ns + 50 ns } + 0.1 x { 10 ns + 2 x 50 ns }
= 0.9 x 60 ns + 0.1 x 110 ns
= 54 ns + 11 ns
= 65 ns
Multilevel Paging
 Multilevel paging is a paging scheme where there exists a hierarchy of page tables.
 Need –
 The need for multilevel paging arises when-
 The size of page table is greater than the frame size.
 As a result, the page table can not be stored in a single frame in main memory.
 Working-
 In multilevel paging,
 The page table having size greater than the frame size is divided into several parts.
 The size of each part is same as frame size except possibly the last part.
 The pages of page table are then stored in different frames of the main memory.
 To keep track of the frames storing the pages of the divided page table, another page table
is maintained.
 As a result, the hierarchy of page tables get generated.
 Multilevel paging is done till the level is reached where the entire page table can be
stored in a single frame
Illustration of Multilevel Paging
 Consider a system using paging scheme where-
Logical Address Space = 4 GB
Physical Address Space = 16 TB
Page size = 4 KB
Now, let us find how many levels of page table will be required.
Size of main memory

= Physical Address Space
= 16 TB
= 244 B
Thus, Number of bits in physical address = 44 bits
…Illustration of Multilevel Paging
 Number of Frames in Main Memory-
Number of frames in main memory
= Size of main memory / Frame size
= 16 TB / 4 KB
= 232 frames
Thus, Number of bits in frame number = 32 bits
 Number of Bits in Page Offset-
We have,
Page size
= 4 KB
= 212 B
Thus, Number of bits in page offset = 12 bits
Alternatively,
Number of bits in page offset
Number of bits in physical address – Number of bits in frame number
= 44 bits – 32 bits
= 12 bits
So, Physical address is-
 Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 4 GB / 4 KB
= 220 pages
 Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Number of bits in frame number
= 220 x 32 bits
= 220 x 4 bytes
= 4 MB
Now, we can observe-
The size of inner page table is greater than the frame size (4 KB).
Thus, inner page table can not be stored in a single frame.
So, inner page table has to be divided into pages.
 Number of Pages of Inner Page Table-
Number of pages the inner page table is divided
= Inner page table size / Page size
= 4 MB / 4 KB
= 210 pages
Now, these 210 pages of inner page table are stored in different frames of the main memory.
Number of page table entries in one page of inner page table

= Page size / Page table entry size
= Page size / Number of bits in frame number
= 4 KB / 32 bits
= 4 KB / 4 B
= 210
 Number of Bits Required to Search an Entry in One Page of Inner Page Table-
One page of inner page table contains 210 entries.
Thus,
Number of bits required to search a particular entry in one page of inner page
table = 10 bits
Outer Page Table Size-
Outer page table is required to keep track of the frames storing the pages of
inner page table.
Outer Page table size
= Number of entries in outer page table x Page table entry size
= Number of pages the inner page table is divided x Number of bits in frame
number
= 210 x 32 bits
= 210 x 4 bytes
= 4 KB
Now, we can observe-
The size of outer page table is same as frame size (4 KB).
Thus, outer page table can be stored in a single frame.
So, for given system, we will have two levels of page table.
Page Table Base Register (PTBR) will store the base address of the outer page
table.
 Number of Bits Required to Search an Entry in Outer Page Table-
Outer page table contains 210 entries.
Thus,
Number of bits required to search a particular entry in outer page table = 10
bits
The paging system will look like as shown next slide--
Page Fault
 When a page referenced by the CPU is not found in the main memory, it is called as a page
fault.
 When a page fault occurs, the required page has to be fetched from the secondary memory
into the main memory.
 Translating Logical Address into Physical Address-
 In a paging scheme using TLB with possibility of page fault,
 The logical address generated by the CPU is translated into the physical address using the
following steps-
 Step-01:
 Page Number
 Page Offset
 Step-02:
 TLB is checked to see if it contains an entry for the referenced page number.
 The referenced page number is compared with the TLB entries all at once.
Page Fault
 Case-01: If there is a TLB hit-
• If TLB contains an entry for the referenced page number, a TLB hit occurs.
• In this case, TLB entry is used to get the frame number for the referenced page number.
 Case-02: If there is a TLB miss-
• If TLB does not contain an entry for the referenced page number, a TLB miss occurs.
• In this case, page table is used to get the frame number for the referenced page number.
• The valid / invalid bit of the page table entry indicates whether the referenced page is
present in the main memory or not.
• now, two cases are possible-
 Case-01: If Valid / Invalid Bit is Set to 1-

 If valid / invalid bit is set to 1, it indicates that the page is present in the main
memory.
 Then, page table is used to get the frame number for the referenced page number.
 Then, TLB is updated with the page number and its frame number for future references.
…Page Fault
 Case-02: If Valid / Invalid Bit is Set to 0-
 If valid / invalid bit is set to 0, it indicates that the page is not present in the main memory.
 A page fault occurs.
 The occurrence of page fault calls the page fault interrupt which executes the page fault handling
routine.
 Page Fault Handling Routine-
 The following sequence of events take place-
 The currently running process is stopped and context switching occurs.
 The referenced page is copied from the secondary memory to the main memory.
 If the main memory is already full, a page is replaced to create a room for the referenced page.
 After copying the referenced page successfully in the main memory, the page table is updated.
 When the execution of process is resumed, step-02 repeats.
 Step-03:
 After the frame number is obtained, it is combined with the page offset to generate the physical
address.
 Then, physical address is used to read the required word from the main memory.
… Page Fault
 Flowchart-
 The following flowchart illustrates the above steps of translating logical address into
physical address-
Yes
No
… Page Fault
 Page Fault Service Time-
 The time taken by the page fault handling routine to service the page fault
is called as page fault service time.
 Page fault service time is much greater than main memory access time.
 It increases the effective access time.
Page Replacement Algorithms
 Page Replacement
 Page replacement is a process of swapping out an existing page from the frame of a main memory and
replacing it with the required page.
 Page replacement is required when-
 All the frames of main memory are already occupied.
 Thus, a page has to be replaced to create a room for the required page.
 A good page replacement algorithm is one that minimizes the number of page faults.
 FIFO Page Replacement Algorithm-
 As the name suggests, this algorithm works on the principle of “First in First out“.
 It replaces the oldest page that has been present in the main memory for the longest time.
 It is implemented by keeping track of all the pages in a queue.
 LIFO Page Replacement Algorithm-

 As the name suggests, this algorithm works on the principle of “Last in First out“.
 It replaces the newest page that arrived at last in the main memory.
 It is implemented by keeping track of all the pages in a stack.
 LRU Page Replacement Algorithm-

 As the name suggests, this algorithm works on the principle of “Least Recently Used“.
 It replaces the page that has not been referred by the CPU for the longest time.
 Optimal Page Replacement Algorithm-

 This algorithm replaces the page that will not be referred by the CPU in future for the
longest time.
 It is practically impossible to implement this algorithm.
 This is because the pages that will not be used in future for the longest time can not be
predicted.
 However, it is the best known algorithm and gives the least number of page faults.
 Hence, it is used as a performance measure criterion for other algorithms.
Problem1
 A system uses 3 page frames for storing process pages in main memory. It uses the First in
First out (FIFO) page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
Also calculate the hit ratio and miss ratio.
Solution---Total number of references = 10
 From here,
 Total number of page faults occurred = 6
…Problem1
Calculating Hit ratio-
Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 6
= 4
Thus, Hit ratio

= Total number of page hits / Total number of references.
= 4 / 10
= 0.4 or 40%
Problem1
 Calculating Miss ratio-
Total number of page misses or page faults = 6
Thus, Miss ratio
= Total number of page misses / Total number of references
= 6 / 10
= 0.6 or 60%
Alternatively,
Miss ratio
= 1 – Hit ratio
= 1 – 0.4
= 0.6 or 60%
Problem 2
 A system uses 3 page frames for storing process pages in main memory. It uses the Least
Recently Used (LRU) page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
 Solution-
 Total number of references = 10
 From here,
 In the similar manner as above-
 Hit ratio = 0.4 or 40%
 Miss ratio = 0.6 or 60%
Problem 3
 A system uses 3 page frames for storing process pages in main memory. It
uses the Optimal page replacement policy.
From here,
Total number of page faults occurred = 5Assume that all the page frames
are initially empty. What is the total number of page faults that will
occur while processing the page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
Solution-
Total number of references = 10
6 came before 1
 From here,
 In the similar manner as above-
 Hit ratio = 0.5 or 50%
 Miss
Operating System ratio
Concepts = 0.5
– 8th Edition or 50% 8.90 Silberschatz, Galvin and Gagne ©2009
PRACTICE PROBLEMS BASED ON PAGE FAULTS IN OS
Effective Access Time
Problem 1
 Let the page fault service time be 10 ms in a computer with average memory access time
being 20 ns. If one page fault is generated for every 106 memory accesses, what is the
effective access time for the memory?
 Solution-
Given-
Page fault service time = 10 ms
Average memory access time = 20 ns
One page fault occurs for every 106 memory accesses
Page Fault Rate-
It is given that one page fault occurs for every 106 memory accesses.
Thus,
Page fault rate
= 1 / 106
= 10-6
Problem 1
Effective Access Time With Page Fault-
It is given that effective memory access time without page fault = 20 ns.
Now, substituting values in the above formula, we get-

Effective access time with page fault
= 10-6 x { 20 ns + 10 ms } + ( 1 – 10-6 ) x { 20 ns }
= 10-6 x 10 ms + 20 ns
= 10-5 ms + 20 ns
= 10 ns + 20 ns
= 30 ns
Belady’s Anomaly
 Effect of Increasing Number of Frames
 The number of page faults should either decrease or remain constant on
increasing the number of frames in main memory.
 But sometimes the unusual behavior is observed.
 Sometimes, on increasing the number of frames in main memory, the number of
page faults also increase.
…Belady’s Anomaly
 Belady‟s Anomaly is the phenomenon of increasing the number of page faults

on increasing the number of frames in main memory.
 Following page replacement algorithms suffer from Belady‟s Anomaly-
 FIFO Page Replacement Algorithm
 Random Page Replacement Algorithm
 Second Chance Algorithm
 NOTE-
 In the above discussion,
 “Algorithms suffer from Belady‟s Anomaly” does not mean that always the
number of page faults will increase on increasing the number of frames in
main memory.
 This unusual behavior is observed only sometimes.
Reason behind Belady’s Anomally
 An algorithm suffers from Belady‟s Anomaly if and only if it does not
follow stack property.
 Algorithms that follow stack property are called as stack based algorithms.
 Stack based algorithms do not suffer from Belady‟s Anomaly.
 This is because these algorithms assign priority to a page for replacement
that is independent of the number of frames in the main memory.
 Examples-
 Following page replacement algorithms are stack based algorithms-
 LRU Page Replacement Algorithm
 Optimal Page Replacement Algorithm
 Hence, they do not suffer from Belady‟s Anomaly.
 Stack Property-
 Consider-
 Initially, we had „m‟ number of frames in the main memory.
 Now, the number of frames in the main memory is increased to „m+1‟.
 According to stack property-
 At each stage, the set of pages that were present in the main memory when
number of frames is „m‟ will be compulsorily present in the corresponding
stages in main memory when the number of frames is increased to „m+1‟.
 Illustration-01: For Optimal Page Replacement Algorithm-
 Consider the reference string is-
 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4
 Now, observe the following two cases-
 Case-01: When frame size = 3
 Number of page faults = 7
 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4

 From here, we can observe-
 At all the stages in case-02, main memory compulsorily contains the set of pages that are present in
the corresponding stages in case-01.
 Thus, optimal page replacement algorithm follows the stack property.
 Hence, it does not suffer from Belady‟s Anomaly.
 As a proof, number of page faults decrease when the number of frames is increased from 3 to 4.
…Belady’s Anomally
 Illustration-02: For LRU Page Replacement Algorithm-
 Consider the reference string is-
 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4
Belady’s Anomally
 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4

 At all the stages in case-02, main memory compulsorily contains the set of pages that are present in
the corresponding stages in case-01.
 Thus, LRU page replacement algorithm follows the stack property.
 Hence, it does not suffer from Belady‟s Anomaly.
 As a proof, number of page faults decrease when the number of frames is increased from 3 to 4.
…Belady’s Anomally
 Illustration-03: For FIFO Page Replacement Algorithm-
 Consider the reference string is- 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4

 0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4

 At stage-07 and stage-08 in case-02, main memory does not contain the set of pages that are present
in the corresponding stages in case-01.
 Thus, FIFO page replacement algorithm does not follow the stack property.
 Hence, it suffers from Belady‟s Anomaly.
 As a proof, number of page faults increase when the number of frames is increased from 3 to 4.
Belady’s Anomally
 NOTE-
 FIFO Page Replacement Algorithm suffers from Belady‟s Anomaly.
 It would be wrong to say that “FIFO Page Replacement Algorithm always suffer from Belady‟s Anomaly”.
Inverted Page Table
 An inverted page table is one of the techniques to structure a page table, where
the page table is indexed by the actual frame number in the physical memory.
The entry in the table corresponds to the logical page number p and the process-
id (pid) of the process that owns that page. The tuple (pid,p) is extracted
whenever a memory reference happens and is forwarded to the memory subsystem that
contains the inverted page table.
Source: https://www.educative.io/answers/what-is-an-inverted-
page-table-in-operating-systems
…Inverted Page Table
 The memory subsystem searches through the inverted page table for a match. If a
match is found at an entry, such as i, then the corresponding physical address
consists of i and the offset (d). If no match is found, this means an address
was accessed illegally.
 Why inverted page table?
An inverted page table has exactly one entry for each physical frame in the real
memory, and therefore only one inverted page table exists in an operating system.
This is in contrast to the standard hierarchical page tables, which are indexed
by logical address pages, and each process has its own separate page table.
Through the inverted page table, the overhead of storing an individual page table
for every process gets eliminated and only a fixed portion of memory is required
to store the paging information of all the processes together, which eliminates
memory wastage.
 This technique is called inverted paging as the indexing is done with respect to
the frame number instead of the logical page number.
Segmentation
 Like Paging, Segmentation is another non-contiguous memory allocation technique.
 In segmentation, process is not divided blindly into fixed size pages.
 Rather, the process is divided into modules for better visualization.
Characteristics-
 Segmentation is a variable size partitioning scheme.
 In segmentation, secondary memory and main memory are divided into partitions of unequal
size.
 The size of partitions depend on the length of modules.
 The partitions of secondary memory are called as segments.
 Example-
 Consider a program is divided into 5 segments as-
Segment Table
 Segment table is a table that stores the information about each segment of the process.
 It has two columns.
 First column stores the size or length of the segment.
 Second column stores the base address or starting address of the segment in the main memory.
 Segment table is stored as a separate segment in the main memory.
 Segment table base register (STBR) stores the base address of the segment table.
 For the above illustration, consider the segment table is-
…Segment Table
 Here,
 Limit indicates the length or size of the segment.
 Base indicates the base address or starting address of the segment in the main memory.
 In accordance to the above segment table, the segments are stored in the main memory as-
Translating Logical Address to Physical Address

 Step-01:
 Segment Number
 Segment Offset
 Segment Number specifies the specific segment of the process from which CPU wants to read the data.
 Segment Offset specifies the specific word in the segment that CPU wants to read.
 Step-02:
 For the generated segment number, corresponding entry is located in the segment table.
 Then, segment offset is compared with the limit (size) of the segment.
 Case-01: Segment Offset >= Limit

 If segment offset is found to be greater than or equal to the limit, a trap is generated.
 Case-02: Segment Offset < Limit

 If segment offset is found to be smaller than the limit, then request is treated as a valid request.
 The segment offset must always lie in the range [0, limit-1],
 Then, segment offset is added with the base address of the segment.
 The result obtained after addition is the address of the memory location storing the required word.
address-
Segmentation
 Advantages-
 The advantages of segmentation are-
 It allows to divide the program into modules which provides better visualization.
 Segment table consumes less space as compared to Page Table in paging.
 It solves the problem of internal fragmentation.
 Disadvantages-
 The disadvantages of segmentation are-
 There is an overhead of maintaining a segment table for each process.
 The time taken to fetch the instruction increases since now two memory accesses are required.
 Segments of unequal size are not suited for swapping.
 It suffers from external fragmentation as the free space gets broken down into smaller pieces with
the processes being loaded and removed from the main memory.
Problem
 Consider the following segment table-
Segment No. Base Limit
0 1219 700
1 2300 14
2 90 100
3 1327 580
4 1952 96
 Which of the following logical address will produce trap addressing error?
a) 0, 430
b) 1, 11
c) 2, 100
d) 3, 425
e) 4, 95
Calculate the physical address if no trap is produced.
Problem
 Solution-
In a segmentation scheme, the generated logical address consists of two parts-
Segment Number
Segment Offset
We know-
Segment Offset must always lie in the range [0, limit-1].
If segment offset becomes greater than or equal to the limit of segment, then trap addressing error is
produced.
Option-A: 0, 430-
Here,
Segment Number = 0
Segment Offset = 430
We have,
In the segment table, limit of segment-0 is 700.
Thus, segment offset must always lie in the range = [0, 700-1] = [0, 699]
Now,
Since generated segment offset lies in the above range, so request generated is valid.
Therefore, no trap will be produced.
Physical Address = 1219 + 430 = 1649
…Problem
 Option-B: 1, 11-
Here,
Segment Number = 1
Segment Offset = 11
We have,
Now,
…Problem
 Option-C: 2, 100-
Here,
Segment Number = 2
We have,
Now,
Since generated segment offset does not lie in the above range, so request generated is invalid.
Therefore, trap will be produced.
…Problem
 Option-D: 3, 425-
Here,
Segment Number = 3
We have,
Now,
…Problem
 Option-E: 4, 95
Here,
Segment Number = 4
Segment Offset = 95
We have,
Now,
Thus, Option-(C) is correct.
Segmented Paging
 Segmented paging is a scheme that implements the combination of segmentation and paging.
Working-
 In segmented paging,
 Process is first divided into segments and then each segment is divided into pages.
 These pages are then stored in the frames of main memory.
 A page table exists for each segment that keeps track of the frames storing the pages of that
segment.
 Each page table occupies one frame in the main memory.
 Number of entries in the page table of a segment = Number of pages that segment is divided.
 A segment table exists that keeps track of the frames storing the page tables of segments.
 Number of entries in the segment table of a process = Number of segments that process is divided.
 The base address of the segment table is stored in the segment table base register.

 Step-01:
 CPU generates a logical address consisting of three parts-
 Segment Number
 Page Number
 Page Offset
 Segment Number specifies the specific segment from which CPU wants to reads the data.
 Page Number specifies the specific page of that segment from which CPU wants to read the data.
 Page Offset specifies the specific word on that page that CPU wants to read.

 Step-02:
 For the generated segment number, corresponding entry is located in the segment table.
 Segment table provides the frame number of the frame storing the page table of the referred segment.
 The frame containing the page table is located.
 Step-03:
 For the generated page number, corresponding entry is located in the page table.
 Page table provides the frame number of the frame storing the required page of the referred segment.
 The frame containing the required page is located.
 Step-04:
 The frame number combined with the page offset forms the required physical address.
 For the generated page offset, corresponding word is located in the page and read.
address-
Segmented Paging
Advantages-
 Segment table contains only one entry corresponding to each segment.
 It reduces memory wastage.
 The size of Page Table is limited by the segment size.
 It solves the problem of external fragmentation.
Disadvantages-
 Segmented paging suffers from internal fragmentation.
 The complexity level is much higher as compared to paging.

Chap 5 Memory Management

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Memory Management

 To provide a detailed description of various ways of organizing memory

 To discuss various memory-management techniques, including paging and

 Computer memory is any physical device capable of storing

information temporarily or permanently.

 EPROM: that can be erased by exposing it to UV light.

 EEPROM: is a special type of ROM that can be erased by

 Linear Data Structures

 Non-Linear data Structures

 A process can be swapped temporarily out of memory to a

 Contiguous memory allocation is a memory allocation technique.

 Static partitioning is a fixed size partitioning scheme.

 These partitions are allocated to the processes as they

 First Fit Algorithm

 Best Fit Algorithm

 It occurs when the total amount of empty space required to store

 CPU always generates a logical address.

 Relocation Register stores the base address or starting address

 The advantages of static partitioning are-

 The disadvantages of static partitioning are-

 Dynamic partitioning is a variable size partitioning scheme.

 The advantages of dynamic partitioning are-

 The disadvantages of dynamic partitioning are-

 CPU always generates a logical address.

Page Table Base Register (PTBR)

Thus, Size of memory

Page table size

 Case-02: If there is a TLB miss-

 Effective Access Time-

 A paging scheme uses a Translation Lookaside buffer (TLB). A TLB access

Size of main memory

Number of page table entries in one page of inner page table

 Case-01: If Valid / Invalid Bit is Set to 1-

 LIFO Page Replacement Algorithm-

 Optimal Page Replacement Algorithm-

Thus, Hit ratio

Now, substituting values in the above formula, we get-

 Belady‟s Anomaly is the phenomenon of increasing the number of page faults

 Number of page faults = 7

 Number of page faults = 6

 Number of page faults = 10

 Number of page faults = 8

 Number of page faults = 9

 Number of page faults = 10

 CPU always generates a logical address.

 Case-01: Segment Offset >= Limit

 Case-02: Segment Offset < Limit

Segment No. Base Limit

 CPU always generates a logical address.

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