Mcd2023 Chapter6 Design OP

Chapter 6 Feedback& Frequency
response, Circuit Design
➢ Feedback
➢ Frequency response and bode plot
➢ Miller Compensation and Stability
➢ An Example of Simple Amplifier Design
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2023/5/4 Microelectronics Circuit Design 2023 1
6.1 Feedback
➢ Types of Feedback
➢ Stability & Oscillation
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Technique of Negative Feedback
➢ Types of Feedback
Series-series Series-Shunt
Shunt-Series Shunt-Shunt
Justify classification, Loop gain, Closed-Loop gain,

Rin, Rout, Frequency response
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Classic Feedback System
• Above figure shows a negative feedback system

• H(s) and G(s) are called the feedforward and forward
networks respectively
• Feedback error is given by X(s) – G(s)Y(s)
• Thus
• H(s) is called the “open-loop” transfer function and

Y(s)/X(s) is called the “closed-loop” transfer function
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Classic Feedback System
• In most cases, H(s) represents an amplifier and G(s) is a

frequency-independent quantity
• In a well-designed negative feedback system, the error term
is minimized, making the output of G(s) an “accurate” copy
of the input and hence the output of the system a faithful
(scaled) replica of the input
• H(s) is a “virtual ground” since the signal amplitude is small
at this point
• In subsequent developments, G(s) is replaced by a
frequency-independent quantity β called the feedback factor
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Why Feedback?
Basic-amplifier Feedback-amplifier
Non-Linearity, Impedance, Noise, Gain Sensitivity

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General Considerations
• Four elements of a feedback system

• The feedforward amplifier
• A means of sensing the output
• The feedback network
• A means of generating the feedback error, i.e., a
subtractor (or an adder)
• These exist in every feedback system, though they
may not be obvious in some cases
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Calculation of Loop Gain
• To calculate the loop gain:

• Set the main input to (ac) zero
• Inject a test signal in the “right” direction
• Follow the signal around the loop and obtain the value
that returns to the break point
• Negative of the transfer function thus obtained is the
loop gain
• Loop gain is a dimensionless quantity
• In above figure, and hence
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Calculation of Loop Gain: Example
• Applying the given procedure to find the loop gain in

the circuit above, we can write
• That is,
• The current drawn by C2 from the output is neglected

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Types of Feedback
Series-shunt Shunt-shunt
Shunt-series Series-series
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Basic Feedback Category
Input variables Output variables Type of feedback

(Vi, Vf, Vs) Vo (input-output)
Voltage Voltage Series-Shunt
Current Voltage Shunt-Shunt
Current Current Shunt-Series
Voltage Current Series-Series
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Feedback Circuit Examples
Series-series Series-shunt
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Summary of Feedback Configurations
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Single/Multiple-Transistor Amplifiers
g-parameter------voltage amplifier;
h-parameter------current amplifier (hybrid);
y-parameter------feedback amplifier (admittance);
z-parameter------feedback amplifier (impedance).
i1 = g11v1 + g12i2
v2 = g 21v1 + g 22i2
v1 = h11i1 + h12v2 i1 = y11v1 + y12v2 v1 = z11i1 + z12i2

i2 = h21i1 + h22v2 i2 = y21v1 + y22v2 v2 = z 21i1 + z 22i2
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Voltage Amp.: Series-Shunt Feedback
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v1 = (h11A + h11F )i1 + (h12A + h12F )v2

i2 = (h21A + h21F )i1 + (h22A + h22F )v2
Define hijT = hijA + hijF
v1 = h11T i1 + h12T v2
i2 = h21
T
i1 + h22
T
v2 Input port : v1 = vS − i1RS
v2
Output port : i2 = − = −GL v2
RL
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vS = ( RS + h )i1 + h v
T
11
F
12 2
0 = h21A i1 + ( h22
T
+ GL ) v2
v2 h21A
AV = = A F
vS h21h12 − ( RS + h11T )(GL + h22
T
)
− h21A
v2 ( RS + h11T )(GL + h22
T
) A
AV = = =
vS − h21
A
1 + A
1+ F
h12
( RS + h11 )(GL + h22 )
T T
−h21A
where A=
( RS + h11T )(GL + h22
T
)
 = h12F
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− h21A
v2 ( RS + h11T )(GL + h22
T
) A
AV = = =
vS − h21
A
1 + A
1+ h F
( RS + h11T )(GL + h22

T 12
)
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−h21A
A=
( RS + h11T )(GL + h22
T
)
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Example of Series-Shunt Feedback
Find VO/VS using feedback Concept.
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Solution
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vS = ( RS + h11T )i1 + h12F v2
0 = h21A i1 + ( h22
T
+ GL ) v2
− A
vS = ( h11T + RS ) i1 + h12F T 21 i1
h
( h22 + GL )
 −h21A 
RIN = = ( h11 + RS ) 1 + h12 T ( + RS ) [1 + A ]
vS T F
 = hT
i1  ( h11 + RS )( h22 + GL ) 
T 11
RIN = RINA [1 + A ]
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Output Resistance
v1 = −i1 RS v2 = vx i2 = ix − GL v2
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Output Resistance
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Summary
The general approach to analyzing negative feedback ckts is:

1) Find hF11：input resistance of the fb. network with the output S.C..
2) Find hF22：output conductance of the fb. network with the input O.C..
3) Find hF12：β-voltage gain from output to input with input O.C..
4) Use the A-circuit (including hF11 & hF22) to find AAV=VO/VS
5) Calculate
Not for every opamp
6)
7)
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Summary
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Summary
For further information, plz refer to

8.5 Practical Configurations and the Effect of Loading
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6.2 Frequency response and
bode plot
➢ Frequency response
➢ Bode plot
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AMPILIFER FREQUENCY RESPONSE
The complex frequency analysis of amplifier will

yield the general transfer function
Transfer function
Vin(s) Vout(s)
Av(s)
a0 + a1s + a2 s 2 +  + am s m
Av( s ) = , where m  n
b0 + b1s + b2 s +  + bn s
2 n
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This expression can be written in terms of production of
roots as
Av ( s) = K
( s + z1 )( s + z2 )  ( s + zm )
( s + p1 )( s + p2 )  ( s + pn )
= K
( s / z1 + 1)( s / z2 + 1)  ( s / zm + 1)
( s / p1 + 1)( s / p2 + 1)  ( s / pn + 1)
where s=-z1,-z2,…,-zm are zeros and

s=-p1,-p2,…,-pn are poles of the transfer function.
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In particular, an amplifier performs three operation regions

➢Low frequency (gain is decreasing as frequency decreases)
➢Midband (gain is independent of frequency)
➢High frequency (gain is decreasing as frequency increases)
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Bode Plot
For A = a + jb
→| A |= a 2 + b2 , = tan −1 (b / a)
The frequency response of AV(s) can be found by replacing

s with jω
Av ( j ) = K 
( j / z1 + 1)( j / z2 + 1)  ( j / zm + 1)
( j / p1 + 1)( j / p2 + 1)  ( j / pn + 1)
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Bode Plot
The magnitude and phase shift of AV(s) is then given as
( / z1 ) + 1 ( / z2 ) + 1  ( / zm ) + 1
2 2 2
| Av ( j ) |= K 
(  1) + (  2) +  (  m ) +1
2 2 2
/ p 1 / p 1 / p
Arg  Av ( j )  = 180 + tan −1 ( / z1 ) + tan −1 ( / z2 ) + 

+ tan −1 ( / zm ) − tan −1 ( / p1 ) − tan −1 ( / p2 ) −  − tan −1 ( / pn )
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Bode Plot
Taking 20Log10(|AV(s)|)
20 log10 (| Av ( j ) |) = 20 log10 ( )
( / z1 ) + 1 + ... + 20 log10
2
( ( / zm ) + 1
2
)
−20 log10 ( ( / p1 )
2
)
+ 1 − ... − 20 log10 ( ( / pn )
2
+1 )
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Bode Plot
How to plot Bode plot by approximation?
Approximation
Note that 20log10(K’) !! line (constant value).
is simplified as straight
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Bode Plot
How to plot Bode plot by approximation?
Note that the location of poles/zeros can be found by 45O phase shift.
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Bode Plot of Zeros
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Bode Plot of Poles
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Bode Plot
Example of frequency response

R2 / / (1/ sC2 ) R2 sR1C1 1
AV ( s) = − =−
R1 + 1/ sC1 R1 sR1C1 + 1 sR2C2 + 1
 s /103   1 
AV ( s) = −10   
 s /10 + 1   s /10 + 1 
3 5 C2=1nF
= Amidband  FL ( s) FH ( s)
R1=1kΩ R2=10kΩ
VIN(s)
VOUT(s)
C1=1μF
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Bode Plot
where
Amidband = −10
 s /103 
FL ( s) =  
 s /10 + 1 
3
 1 
FH ( s) =  
 s /10 5
+ 1 
Consequently, there is one zero at s=0 and two poles at s=-1e3 and
s=-1e5 rad/ses.
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Bode Plot
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Frequency Response of Opamp
VOUT
VIN
VOUT
VIN
How the bandwidth will be changed ?
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A
A( s ) =
s
1+
VIN 
VOUT A
VIN − VOUT     s
= VOUT
1+

 
A  A 
VIN  = VOUT  1 +
s s
1+  1+ 
  
A
s
1+
A(0) = A, p =  V
T ( s ) = OUT =
VIN 1 + A
 = A( s ) = A 
1 + A( s )   1 + A   1 +
1
s
1+
s   A 
1 
A(0) = , p =   A 
 
1

1
 1+ s
  A 
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VOUT
A
A( s ) =
s
1+

R2  R1  − A
V
 IN − (V − V )   = VOUT
R1 + R 2  1 + s
IN OUT
R1

VOUT A  R2 1
T (s) = =− 
VIN VIN R1 + R 2 + A  R1 1 + s
 R1 
  1 + A
 R1 + R 2 
R2 1
− 
R1 1 + s
 R1 
  1 + A
 R1 + R 2 
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A0
dB AOL ( s ) =
1 + s 0
AOL ( s )
120 ω0 ACL ( s ) =
1 +   AOL ( s )
100 A0
1 + s 0
AOL (s) =
A0
80 1+  
AOL(0)β 1 + s 0
60 ω1 =
A0

1
ACL(s) 1 +  A0 1 + s (1 +  A0 ) 0
40
GBW
20 1/β
-20dB/dec Freq.
10 100 1k 10k 100k

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Circuit example – Common emitter Amp.
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Transition Frequency-BJT
C 0
C = g m F C =
VCB
1+
gm  jc
z =
C
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Transition Frequency-BJT
io = Vgs ( g m − sCgd ) = i1 
(g m − sCgd )
s ( Cgs + Cgb + Cgd )
io
 (s) = =
( g m − sCgd )

gm
i1 s ( Cgs + Cgb + Cgd ) s ( Cgs + Cgb + Cgd )
gm gm
z = T =
Cgd Cgs + Cgb + Cgd
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6.3 Miller Compensation and
Stability
➢ Miller Capacitance
➢ Stability of Circuit
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MILLER EFFECT
• If the circuit of Fig (a) can be converted to that of

Fig (b), then
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MILLER EFFECT
• Miller’s theorem does not stipulate the conditions

under which this conversion is valid.
• If the impedance Z forms the only signal path between
X and Y , then the conversion is often invalid.
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MILLER EFFECT
Vo (s ) = − AVs (s ) and I s (s ) = sCVs (s ) − Vo (s )
I s (s )
Y (s ) = = sC (1 + A)
Vs (s )
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MILLER EFFECT
Vo (s ) = − AVs (s ) and I s (s ) = sCVs (s ) − Vo (s )
Is ( s)  1
Yout ( s ) = = sC 1 + 
Vo ( s )  A
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Miller Effects in Frequency Response
vout = [(vin − vout )C1s − g m1vin ]rds1

C1
vout
sC1
(1 − ) g m1rds1 +
vout g m1 vin
AV = =−
vin ( sC1rds1 + 1) _ gm1vin rds1
There is a right-hand plane zero and a left-half plane pole.
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Stability of Circuit
Frequency-Dependent Hybrid-Pi Model for the Bipolar Transistor
ic(s)
I c (s ) = g mVbe (s ) − I  (s )
I  ( s ) = sCVbe ( s )
ib(s)
Ib ( s ) = Vbe ( s ) / (r ) + Vbe ( s ) sC + Vbe ( s ) sC )

g 1
z = m  =
C r (C + C )
o gm
 T =  o  = =
r (C + C  ) C + C 
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A(s ) =
2 1024
(s + 105 )(s + 3106 )(s + 108 )
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Stability Analysis with Bode Plots
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海因里希·巴克豪森 Heinrich Barkhausen
德累斯顿工业大学（TU Dresden，全称Technische Universitaet Dresden）

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A(s ) =
2 1024
(s + 105 )(s + 3106 )(s + 108 )
20 log A
1
= 20 log A − 20 log

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Gain and phase versus frequency with 3-Poles
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Objective: 1-Pole system frequency response
➢ Enough Phase Margin
➢ Easy for Compensation
➢ Predictable step response
➢ Without overshoot/undershoot
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Relative Gain for various phase margins
Acceptable
Best
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Compensation – Move dominant pole
➢ Decrease dominant pole
➢ Easy for implementation
➢ Large capacitance, large area
➢ GBW limited by non-dominant pole

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Compensation – Location
If PM=60O,
what’s the distance between GBW and p1?
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Case Study-Compensate a two stage Amp.
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Compensation – Move dominant pole
Difficult for integration!
➢ Decrease dominant pole
➢ Easy for implementation
➢ Large capacitance, large area
➢ GBW limited by non-dominant pole

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Compensation – Miller compensation
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Dominant-Pole Approximation
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by g m R2
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Compensation – Before compensation
Right Half Plane Zero
➢ Gain Extension
➢ Phase roll down
Worse PM!
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Eliminate RHP zero
1) No RHP zero;
2) Smaller compensation capacitor;
3) Better high-frequency negative PSRR than Miller compensation
Drawback: input offset

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Eliminate RHP zero
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Eliminate RHP zero
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3-stage Opamp. compensation
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Zero in Transfer Function
• The transfer function of exhibits a zero given by
• CGD provides a feedthrough path that conducts

the input signal to the output at very high
frequencies.
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79
Calculating zero in a CS stage
• The transfer function Vout(s)=Vin(s) must drop to

zero for s = sz.
• Therefore, the currents through CGD and M1 are
equal and opposite:
• That is
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80
Example
• Can this (the zero) occur if H1(s) and H2(s) are

first-order low-pass circuits?
• H1 = and H2=
• The overall transfer function contains a zero.

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81
Simple CMOS AMP
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82
P532-533:7.3.5
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fnd
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2 Stage Miller CMOS OTA
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85
Miller BiCMOS OTA
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86
Two-Stage Op Amps
• Voltage headroom in today’s design is constrained with
low supply voltage and large output swing
• Gain:
• Output Swing: Vdd-2Overdrive
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87
Two-Stage Op Amps with cascode devices
• Voltage headroom in today’s design is constrained with
low supply voltage and large output swing
• Gain:
• Can we have more stages? Feedback stability limits
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88
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6.4 Example of Simple Amplifier
Design
How ?
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DESIGN OF A DIFFERENTIAL AMPLIFIER
Design Considerations:
Constraints:
Power supply, Technology, Temperature, Power Dissipation,
Area …
Specifications:
Smaller-signal gain, Frequency response, ICMR, Slew rate,
Power dissipation, OCMR, Offsets …
Architecture:
Type of input, Type of output, Type of mirrors, Type of feedback,
Output driver, Number of stages…
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Example - Design of a MOS Differential Amp
with a Current Mirror Load
Design the current and W/L values of the MOS differential

amplifier using a current mirror load to satisfy: VDD = -VSS = 2.5V,
SR  10V / μs with a 5 pF load, f -3db  100kHz, a small signal gain
of 100 V / V , and power loss must be less than 1mW . Assume
1.5V  ICMR  2V, k' N = 110uA / V 2 , k' P = 50  A / V 2 ,Vtn = 0.7V,
Vtp = -0.7V,λN = 0.04V -1 , λP = 0.05V -1 .
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CMOS Differential Amp with a Current Mirror Load
Sample Design:
• Relationships:
Av = g m1 Rout  −3dB = 1 / RoutC L
VIC (max) = VDD − VSG 3 + Vtn1
VIC (min) = VSS + VDS 5( sat ) + VGS 1 = VSS + VDS 5( sat ) + VGS 2
SR = I SS / C L
Pdiss = VDD  (All dc current flowing from VDD )
+ | VSS | (All dc current flowing to VSS )

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Sample procedure for a simple 5-transistor CMOS
differential amplifier
• Pick ISS to satisfy the slew rate, knowing

CL or the power dissipation;
• Check to see if Rout will satisfy the
frequency response. If not, change ISS or
modify circuit;
• Design W3/L3 (W4/L4) to satisfy the
upper ICMR;
• Design W1/L1 (W2/L2) to satisfy the gain;
• Design W5/L5 to satisfy the lower ICMR;
• Check functionality of the circuit;
• Check all specifications;
• Iterate where necessary.
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Example-Design of a MOS Differential Amplifier with a
Current Mirror Load
VDD = -VSS = 2.5V, SR  10V / μs,CL = 5 pF ,

f -3db  100kHz, A V = 100 V / V , Pdiss  1mW .
1.5V  ICMR  2V, k' N = 110uA / V 2 ,
k' P = 50 A / V 2 ,Vtn = 0.7V,Vtp = -0.7V,
λN = 0.04V -1 , λP = 0.05V -1 .
Solution:
1.) To meet the slew rate, SR = I SS /C L , → I SS = SR  C L  I SS  50 A
For maximum, Pdiss = VDD(I DS 3 + I DS 4 ) + VSS  I SS  I SS  200 A
1
2.) f - 3db =  Rout  318 kΩ
2πRoutC L
2
Rout =  318 kΩ  I SS  70 A → choose I DD = 100 A
(λN + λP )I SS
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3) VIC (max) = VDD − VSG3 + Vtn1 → VSG3  1.2V
2 I SD3 W3 W4
VSG3 = VSD3 + | Vtp |= '
→ = 8
k pW3 / L3 L3 L4
vout gm1 2k N' (W 1/ L1) W1 W 2

4) = gm1Rout = = → = = 18.4
vin g ds 2 + g ds 4 ( gds 2 + gds 4 ) I DS1 L1 L2
W5 2 I SS
5) VIC (min) = VSS + VDS 5( sat ) + VGS 1  = ' 2
= 300
L5 k NVDS 5( sat )
6) Increase W1/L1 to reduce VGS1 and allow a smaller W5/L5. If
W1/L1=40, then W5/L5=9 or 10.
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Analog design octagon
Noise Linearity Intuition
Power Gain
Dissipation
Input/Output Supply
Impedance Voltage
Voltage Experience
Speed
Swing
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6.4 Two Stage Op-Amp Design
➢ Case Study: OP-Amp

→ Circuit
→ Library & Model
→ Source & Stimuli
→ Analysis Type
→ Output Files
→ Graphic Tools
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6.4.2 Design of a Two Stages AMP. OP.
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99
I5
Slew Rate : SR =
CC
− g m1 −2 g m1
First Stage : AV 1 = =
g ds 2 + g ds 4 I 5 ( 2 + 4 )
− gm6 − gm6
Second Stage : AV 2 = =
g ds 6 + g ds 7 I 6 ( 6 + 7 )
g m1
Gain Bandwidth : GBW =
CC
− gm6
Output Pole : p2 =
CL
g
RHP Zero : z1 = m 6
CC
I5
Positive CMR VIN ( max ) = VDD − − VT 03 ( max ) + VT 1 ( min )
3
I5
Negtive CMR VIN ( min ) = VSS + + VT 1 ( max ) + VDS 5 ( sat )
1
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100
For PM = 60, and the RHP zero is ten times
higher than GBW ,
       
−1 
 =180- tan −1   - tan −1
  - tan   = 60
 p1   p2   z

−1 GBW
 
−1 GBW
 
−1 GBW

p1 p2 tan   + tan   + tan   = 120
p
 1  p
 2   z 
GBW

−1 GBW

tan ( A0 ) + tan 
−1
 + tan ( 0.1) = 120= 2 3
−1
g m1
Gain Bandwidth : GBW =  p2 
CC
 GBW 
− gm6
tan −1   = 2 3-  2-0.0997=0.4239
Output Pole : p2 =  p2 
CL 1
= 2.216
gm6 0.4239
RHP Zero : z1 = p2 2.2  GBW
CC
_____________________________________________________________________________________
101
Step1: Choose CC CC = 0.22  CL
I5
Step2: Choose I5 Slew Rate : SR =
CC
Step3: Determine M3/M4 by CMR+
Step4: Determine M1 by GBW
Step5: Determine M5 by CMR-
Step6: M6: gm6 = 2.2 gm2CL / CC
Iteration
_____________________________________________________________________________________
102
6.5 Design of Folded Cascode Amp.
1 ： Do not need perfect

current balancing;
2: IM2, IM6, IM5, For large
signal response, make sure
the DC current never zero!
3: Normally IM6 is set
between IM2 to 2xIM2
_____________________________________________________________________________________
整体电路图
_____________________________________________________________________________________
差分输入对版图设计
NMOS
B A A B
A B B A
PMOS
_____________________________________________________________________________________
版图设计
PiP电容,将电容分块,
提高匹配精度
衬底PNP,一般采用1:8的比例结构
_____________________________________________________________________________________
整体版图
VDD
基准电流源
GND
_____________________________________________________________________________________
单位增益响应测试PCB
SR+测试结果 SR-测试结果
_____________________________________________________________________________________
Advise from P.E. Allen
DO NOT
use the computer
as a substitute for thinking!
Before you look at the result, be sure to think
about what we expect to see, then open the
AWAVES with self-confidence.
It’s dangerous to totally rely on the computer.

_____________________________________________________________________________________
Summary of Chapter 6
➢ Keystones
• How to design an integrated circuit
➢ Difficulties
• Feedback
• Bode plot
• Frequency Response and stability
_____________________________________________________________________________________

Mcd2023 Chapter6 Design OP

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Mcd2023 Chapter6 Design OP

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Chapter 6 Feedback& Frequency

response, Circuit Design

➢ Stability & Oscillation

Justify classification, Loop gain, Closed-Loop gain,

• Above figure shows a negative feedback system

• H(s) is called the “open-loop” transfer function and

• In most cases, H(s) represents an amplifier and G(s) is a

Non-Linearity, Impedance, Noise, Gain Sensitivity

• Four elements of a feedback system

• To calculate the loop gain:

• Applying the given procedure to find the loop gain in

• The current drawn by C2 from the output is neglected

Input variables Output variables Type of feedback

Voltage Voltage Series-Shunt

Current Voltage Shunt-Shunt

Current Current Shunt-Series

Voltage Current Series-Series

v1 = h11i1 + h12v2 i1 = y11v1 + y12v2 v1 = z11i1 + z12i2

v1 = (h11A + h11F )i1 + (h12A + h12F )v2

Define hijT = hijA + hijF

( RS + h11T )(GL + h22

Example of Series-Shunt Feedback

Find VO/VS using feedback Concept.

vS = ( RS + h11T )i1 + h12F v2

The general approach to analyzing negative feedback ckts is:

3) Find hF12：β-voltage gain from output to input with input O.C..

4) Use the A-circuit (including hF11 & hF22) to find AAV=VO/VS

For further information, plz refer to

The complex frequency analysis of amplifier will

where s=-z1,-z2,…,-zm are zeros and

In particular, an amplifier performs three operation regions

The frequency response of AV(s) can be found by replacing

The magnitude and phase shift of AV(s) is then given as

Arg  Av ( j )  = 180 + tan −1 ( / z1 ) + tan −1 ( / z2 ) + 

How to plot Bode plot by approximation?

How to plot Bode plot by approximation?

Example of frequency response

How the bandwidth will be changed ?

10 100 1k 10k 100k

• If the circuit of Fig (a) can be converted to that of

• Miller’s theorem does not stipulate the conditions

Vo (s ) = − AVs (s ) and I s (s ) = sCVs (s ) − Vo (s )

Vo (s ) = − AVs (s ) and I s (s ) = sCVs (s ) − Vo (s )

vout = [(vin − vout )C1s − g m1vin ]rds1

There is a right-hand plane zero and a left-half plane pole.

Ib ( s ) = Vbe ( s ) / (r ) + Vbe ( s ) sC + Vbe ( s ) sC )

德累斯顿工业大学（TU Dresden，全称Technische Universitaet Dresden）

➢ Enough Phase Margin

➢ Easy for Compensation

➢ Predictable step response

➢ Decrease dominant pole

➢ Easy for implementation

➢ Large capacitance, large area

➢ GBW limited by non-dominant pole

Difficult for integration!

➢ Decrease dominant pole

➢ Easy for implementation

➢ Large capacitance, large area

➢ GBW limited by non-dominant pole

Right Half Plane Zero

➢ Phase roll down

Drawback: input offset

• The transfer function of exhibits a zero given by