Programmable Logic Controllers Laboratory - ELEG 301L

Summer 2022
Assignment 1
Due Date: 4 – July – 2022

Student #1 Name: Student #1 ID:

Student #2 Name: Student #2 ID:

Student #3 Name: Student #3 ID:

Question 1 /10

Question 2 /10

Question 3 /10

Question 4 /10

Question 5 /10

Question 6 /10

Question 7 /10

Question 8 /10

Question 9 /20

Total / 100

Notes:

§ Solve the assignment in the same Word document, and submit it by the due date on Moodle.
§ If you have any questions, contact your instructor via email or during office hours.

Fatima Badreddine
Page 1 of 11
Question 1:

Answer the following questions for the given Ladder Diagram program.

1. How many inputs are used in the above program? What are their tags?
2. How many outputs are used in the above program? What are their addresses?
3. What is the logical value of “Motor” if “Start” is logic 1, and “Stop” is logic 0? Why?
4. What is the logical value of “LED” if “Start” is logic 1, and “Stop” is logic 0? Why?
5. What should the logical values of “Start”, “Stop”, and “Salem” be in order for “LED” to be logic 1?
Mention two different answers.
6. There are unprofessional programming practices in the above program, mention two.
1. 3 input are used, and the tags ( start, stop, Salem)
2. 2 output and there addresses (Q0.0 , Q0.2 )
3. Stop is normal close so it's mean closed
Start is normal open so it's mean closed
So, both series close then the value will be 1
4. Since we said in number 3 the motor value is 1, and Salem is 0, which mean it’s
directly given to LED so the value will be 0.
Start Stop Salem LED

6. 1- Salem is not professional name

2- also the address for Salem should be I0.2, and the address for LED should be Q0.1

Fatima Badreddine
Page 2 of 11
Question 2:
Based on the Ladder Diagram programming rules, mention a mistake in each of the following Ladder
Diagram programs.

a.

b.

Fatima Badreddine
Page 3 of 11
Question 3:
Given the status of the inputs of the following Ladder Diagram program, what are the status of “Output
1”?

A B C D E F G H Output 1
0 0 1 0 0 0 0 0
1 1 1 0 0 1 1 1
0 1 1 1 1 1 0 0

Fatima Badreddine
Page 4 of 11
Question 4:
Implement the following logical expression using Ladder Diagram programming language:
Note: the expression is read from left to right. The operation between the circular brackets is done first.
Note: the expression is read from left to right. The operation between the circular brackets is done first.
a. Include a picture of your program.
b. Write the truth table for the expression.

Fatima Badreddine
Page 5 of 11
Question 5:
Implement an AND gate from a NAND gate using two rungs only.
a. Include a picture of your program.

Fatima Badreddine
Page 6 of 11
Question 6:
Implement a 4-inputs EX-OR gate using Ladder Diagram programming language.
a. Include a picture of your program.
b. Draw the timing diagram of the implemented gate if the applied inputs are as follows:

Input 1 Input 2 Input 3 Input 4

1 0 1 0
1 1 0 1
1 1 1 1

Fatima Badreddine
Page 7 of 11
Question 7:
Choose one answer only for the following questions.

1. If the values of the timing diagrams 1 and (NOT 2) are inputs to a logic gate, what would be the logic
gate if the output is the timing diagram 4?
a. AND
b. OR
c. NOR
d. EXOR
e. None of the above

2. If the values of the timing diagrams 1 and (NOT 2) are inputs to a logic gate, what would be the logic
gate if the output is the timing diagram 5?
a. OR
b. NAND
c. NOR
d. EXNOR
e. None of the above

Fatima Badreddine
Page 8 of 11
3. If the values of the timing diagrams 1 and 2 are inputs to a logic gate, what would be the logic gate
if the output is the timing diagram 6?
a. OR
b. NOR
c. EXOR
d. EXNOR
e. None of the above

4. If the values of the timing diagrams 1 and 3 are inputs to a logic gate, what would be the logic gate
if the output is the timing diagram 5?
a. OR
b. NOR
c. EXOR
d. EXNOR
e. None of the above

5. The output of an EXOR gate will be always high if the inputs are:
a. Timing diagrams 5 and 6
b. Timing diagrams 4 and 5
c. Timing diagrams 1 and 6
d. Timing diagrams 2 and 7
e. None of the above

6. If the values of the timing diagrams 4 and 5 are inputs to a logic gate, what would be the logic gate
if the output is always low?
a. OR
b. AND
c. NAND
d. EXOR
e. None of the above

Fatima Badreddine
Page 9 of 11
Question 8:
Explain the testing scenario of the given timing diagram for the burglar alarm system.

Fatima Badreddine
Page 10 of 11
Question 9:
When input I0.0 (Switch 1) is high and either input I0.1 (Switch 2) or input I0.2 (Switch 3) is low, output
Q0.0 (Alarm) is turned on; otherwise, output Q0.0 (Alarm) is turned off. Write the Ladder Diagram
program for the described system and include a picture of it.

Fatima Badreddine
Page 11 of 11