CONFIDENTIAL TEST 1/NOV 2022/ELE558

UNIVERSITI TEKNOLOGI MARA

TEST 1

COURSE : DIGITAL DESIGN AND COMPUTER ARCHITECTURE

COURSE CODE : ELE558
DATE : NOV 2022
TIME : 1.5 HOURS
FACULTY : ELECTRICAL ENGINEERING
SEMESTER : OCT 2022 – FEB 2023

INSTRUCTION TO CANDIDATES

1. This question paper consists of three (3) questions. Answer all questions.
2. All answers must be written in Answer Booklet. Start each answer on a new page.

NAME : ______________________________________

STUDENT ID. : ______________________________________

GROUP/LECTURER : ______________________________________

Question 1a 1b 1c 2a 2b 2c 3a 3b 3c
(2M) (4M) (4M) (2M) (5M) (3M) (3M) (5M) (2M)
Total
Cognitive level C1 C4 C3 C4 C1 C5 C6 C4 C3 (30M)
CO CO1 CO1 CO1 CO1 CO1 CO1 CO1 CO1 CO1
PO PO2 PO2 PO2 PO2 PO2 PO2 PO2 PO2 PO2
Marks

BLOOM’S LEVEL FOR SEM 6 Level I (20-40%) Level II (55-60%) Level III (15-20%)
Q1b, Q1c, Q2a, Q3b,
BLOOM’S LEVEL QUESTION Q1a, Q2b Q2c, Q3a
Q3c
FOR TEST 1
DOMAIN COGNITIF C1,C2 C3, C4 C6
LEARNING OUTCOME LO2 LO2 LO2
7 17 6
ALLOCATED MARKS
7/30 17/30 6/30

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This test paper consists of 6 printed pages including the cover page

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CONFIDENTIAL 2 TEST 1/NOV 2022/ELE558

QUESTION 1

a) Logic simulation and synthesis are two major purposes of hardware description languages
(HDLs). Describe the task performed during the logic simulation and synthesis.

(2 marks)

b) Figure Q1b(i) and Figure Q1b(ii) show the Verilog codes for a design file test1b and
a testbench file tb_test1b. These two files are simulated using a simulator. Evaluate
the values of the output signals d, e,f and g after the simulation is completed (your
answer can be either in binary or hexadecimal number).
(4 marks)
module test1b ( module tb_test1b;
input [7:0] a, b, c, reg [7:0] a, b, c;
output reg [15:0] d, e, wire [15:0] d, e;
output reg [7:0] f, g); wire [7:0] f, g;

always @* test1b uut (a, b, c, d, e, f, g);

begin
d = {b,a}; initial begin
e = {4{1’b1}},{4{1’b0}},b}; a = 8'b0110_1110;
f = a | b; b = 8'hAD;
g = (c == A4)? a : b; c = 8'h4A;
end end
endmodule endmodule

Figure Q1b(i) Figure Q1b(ii)

c) Illustrate the Verilog codes for the 8 to 1 multiplexer shown in Figure Q1c. The Verilog
code for the multiplexer must be implemented using case statement.
(4 marks)
4
in0
4
in1
4
in2
4
in3 4
4 MUX8to1 out
in4
4
in5
4
in6
4
in7
3
sel

Figure Q1c
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QUESTION 2

a) The Verilog assign statement is typically used to continuously drive a signal of wire
datatype and gets synthesized as combinational logic. Figure Q2a shows the coding for
simple digital combinational logic that has an output wire Z that is driven continuously
with an assign statement to realize the digital equation. Evaluate the code to illustrate
the respective combinational logic gate diagrams.

(2 marks)

module combo ( input A, B, C, D, E, output reg Z);

assign Z = ( (A | B) & (C ^ D) | ~E);

endmodule

Figure Q2a

b) An 8-bit magnitude comparator compares the two 8-bit values and produces a 1-bit flag
as result, which indicates that the first value is either greater than or less than, or equal
to the second value. The block diagram of a comparator is shown in Figure Q2b(i). The
truth table of the magnitude comparator is shown in Figure Q2b(ii). A and B are the two
8-bit input signals to the comparator which compares the magnitude of these two signals.
The three 1-bit output signals are Eq (for A = B), Gt (for A > B) and Lt (for A < B). Write:

i) the RTL code for the comparator.

ii) the testbench for the comparator.

(5 marks)

magComp

Eq
A 8
Magnitude
Comparator Gt
B 8
Lt

Figure Q2b(i)

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CONFIDENTIAL 4 TEST 1/NOV 2022/ELE558

Inputs Outputs
A B Eq (A = B) Gt (A > B) Lt (A < B)
0000 1100 0000 1100 1 0 0
0000 1010 0001 0001 0 0 1
0000 1111 0000 0101 0 1 0
0001 1000 0001 1000 1 0 0

Figure Q2b(ii)

c) Figure Q2c shows a 3-bits counter. It starts incrementing from 3’b000 to 3’b111 and
then rolls over back to 3’b000. It will keep counting as long as it is provided with a running
clock and the reset is held low. The rollover happens when the most significant bit of the
final addition gets discarded. When the counter is at a maximum value of 3’b111 and
gets on more count requests, the counter tries to reach 4’b1000 but since the counter
can support only 3-bits, the MSB will be discarded resulting in 0. Write:

i) the RTL code for the counter.

ii) the testbench for the counter.

MyCounter

clock 3-bits 3 out

Counter

reset

Figure Q2c

(3 marks)

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QUESTION 3

A group of design engineers has attached the circuit as shown in Figure Q3. They need to
trace back the design until the state diagram. Therefore, they need your help to :

a) Construct respective Boolean Equations. [You might need help from Appendix 1]

(3 marks)

b) Determine a state table.

(5 marks)

c) Build a state diagram.

(2 marks)

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DA
D A
SET
Q
A

CLK

CLR Q

DB
D B
SET
Q
CLK

CLR Q

Figure Q3

END OF QUESTION PAPER

APPENDIX 1

Truth Table for XNOR

Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1

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