File 0 55592400 1472821077

LatticeMico32/DSP Development Board for LatticeECP2
User’s Guide
June 2009
Revision: EB26_02.6
LatticeMico32/DSP Development Board
Lattice Semiconductor for LatticeECP2 User’s Guide
Introduction
This document describes the features and functionality of the LatticeMico32™/DSP Development Board for
LatticeECP2™ devices. This board is designed as a hardware platform for design and development with the
LatticeMico32 microprocessor, as well as for the LatticeMico8™ microcontroller, and for various DSP functions.
Note: There are two versions of this board, named version 1 (v1) and version 2 (v2). Differences between the v1
and v2 boards are described in this document as required. The appendices of this document contain schematics of
both versions. In summary, v2 boards include the following changes:
• Copper plating indicates v2 in text (HPEminiv2)

• A pushbutton has been added for USB reset. This allows the FPGA to be reset independently from the USB
Cable circuitry.
• Boards are populated with a MachXO-2280 device (v1 boards were populated with a MachXO-640).
• Board color is blue, and board is fully RoHS compliant.
This document describes the numerous functional elements of the board. The schematics of the board can be
found in the appendices at the end of this document.
Features
• Lattice ECP2-50 FPGA with 48 kLUTs, 387 kbit of Embedded Block RAM, 18 sysDSP™ blocks, 72 18x18 multi-
pliers, 6 PLLs, and 500 user I/O pins
• Lattice MachXO™ with 640 LUTs and 6.1 kbit of RAM
• Serial Flash with at least 8 Mbit for non-volatile storage of FPGA configuration data.
• DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus)
• Parallel Flash 2x128 Mbit, organized as 8M 32-bit words
• SRAM 2x4 Mbit, organized as 256K 32-bit words
• USB 2.0 connector and integrated ispDOWNLOAD® cable for JTAG programming the FPGA
• Flywire connector for programming using an ispDOWNLOAD cable (available separately)
• 9-pin RS232 serial port (230 Kbps)
• 15-pin VGA (64 color encoding)
• Ethernet 10/100 M full/half duplex
• Two USB 2.0 compatible host connectors
• One USB 2.0 compatible target connector
• One USB OTG (On-the-Go) connector
• Expansion connector with 46 user I/Os
• 12x12 prototyping area for the integration of individual components (connections to the FPGA)
• Sigma Delta D/A converter
• Two SATA interfaces with four LVDS signal pairs for high-speed data transfer (Note: Full SATA implementation is
not supported)
• AC’97 Stereo Audio Codec with line input and output
• LCD connector for character displays, with contrast potentiometer
• 25 MHz oscillator with clock distribution buffer
2
• Eight LEDs with test points for each LED

• Two-character 7-segment display
• Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies
• Blue LED which shows the configuration status (“DONE”)
• Red LED to signal that the FPGA can be configured (“INIT”)
• Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”)
• 3x4 key matrix
• Four DIP switches
• Single step key
• Program key to initiate the configuration sequence of the FPGA from SPI Flash memory
• Reset key
• 5V power supply
• Switching regulator for the generation of the 3.3V I/O voltage, the 2.5V DDR and LVDS voltages and the 1.2V
core voltage
Getting Started
1. Unpack all components and compare them to the packaging list. All boards leave the factory fully tested.
Detailed information can be found in the Troubleshooting section of this document.
2. Place the board in front of you so that the keyboard is on the left side.
3. Take the regulated DC power supply which has been supplied with the package and connect it to the power
jack on the board. Two green power-on LEDs will illuminate to confirm that power is correctly applied to the
board (regulating 5V to 3.3V and 2.5V).
4. To check the basic functionality, please see the Troubleshooting section of this document.
A number of example and demonstration programs are available for the LatticeMico32/DSP Development Board for
LatticeECP2. Check the Lattice web site at: www.latticesemi.com/boards (and navigate to the correct board) to find
additional documentation, such as the LatticeMico32 Tutorial, which describes how to use the LatticeMico32 Sys-
tem software to develop microprocessor solutions for this board. Additional sample programs are included with the
LatticeMico32 System software. Check the software help to find these examples.
Note: Unless described otherwise, positional statements (left, right etc.) refer to the board positioned in front of you
so that the key pad is in the bottom left corner.
Related Literature
• LatticeMico32 Development Kit User’s Guide: This guide includes a tutorial for using the LatticeMico32 Sys-
tem software with the LatticeMico32/DSP Development Board. This document is written for the first generation
board (with LatticeECP-33 FPGA), which is similar to the board described in this document. While this document
may be useful, please remember there are differences in the designs of these boards.
Be sure to check the Lattice web site for updates to this document as well.
These documents can be downloaded from the Lattice web site at: www.latticesemi.com/boards. Select the
FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on the User Manu-
als link.
3
Overview
The following block diagram gives you an overview of the functionality of your LatticeMico32/DSP Development
Board. Subsequent pages illustrate the position of connectors, user interfaces, and modules.
Figure 1. LatticeMico32/DSP Development Board Block Diagram
AC97
Ethernet
10/100
RS232
LatticeECP2-50
To PC
PRG 672 fpBGA
3p LVDS
SATA
3p LVDS
SATA
Expansion
Connector
Table 1. Board Defaults

Default
Item Type Status Comments
The bitstream is based on Example PlatformA and the
LED7SegsTest_ecp2 project. The LED7SegsTest_ecp2.mem
and LED7SegsTest_ecp2.bit files are included in the
LED7SegsTest_ecp2 project.
LatticeECP2-50 FPGA Programmed
Visual indications of operation are:
• Left to Right and Right to Left scanning of the 8 LEDs.
• Upcount and roll over of the 7 segment displays from 0 to 99
decimal at ~1 second intervals.
LCD Backlight (X5) Jumper Open Backlight is off.
Configuration Switch TMS Switch Off (Down) LatticeECP2-50 FPGA can be programmed.
Sigma Delta DAC Converter Jumper Open
Contrast Control Reostat Variable Not set to any specific level.
4-place DIP - Logic 1 Switch Off Logic 0 on selected pins - see Table 18.
Shorts Pins
SODIMM DDR 400 Setting (X18) Jumper Set to below DDR400 memory use.
1 and 2
4
Peripheral Interfaces
This section describes all peripheral interfaces of the LatticeMico32/DSP Development Board for LatticeECP2 in
alphabetical order.
Figure 2 shows the position of peripheral interfaces available on the board.
Figure 2. Peripheral Interfaces (Version 1 Board Shown in this Figure)

Audio Mini USB
RS232 Ethernet VGA
Power Plug Line In
Connector 10/100M Connector OTG Connector
Line Out
USB Host
Connector
2.5V
Testpoint
3.3V
Testpoint
DDR SDRAM
Sockel
GND
Testpoint
1.2V
Testpoint SATA LVDS
Connectors
CLK
Testpoint
Flywire
Connector
High-Speed Expansion
USB for
Connector
Configuration
LCD Sigma Delta

Connector DAC Connector
In Version 2 of this board, the on-board USB cable circuit has been updated.
1. A USB RESET# pushbutton has USB Reset

been added. The Version 1 board Pushbutton
includes a single Reset pushbutton (v.2 board)
that resets both the LatticeECP2 MachXO-640
FPGA and the USB cable. The (v.1 board),
addition of the USB RESET# button MachXO-2280
allows the FPGA to be reset (v.2 board)
independent from the USB cable
circuit.
2. In the Version 2 board, the MachXO device has been changed from a
MachXO640 to a MachXO2280 device.
5
Audio Interface
The audio interface has two connectors for 3.5 mm stereo jacks. The upper one is for line-out, the lower for line-in.
They are connected to the audio codec LM4549B by National Semiconductor.
Table 2. Audio Codec U1001 Pin Definitions

Pin Signal Name FPGA Pin Pin Signal Name FPGA Pin
6 AC97_BITCLK B24 47 AC97_EAPD C23
2 AC97_EXT_CLK D25 11 AC97_RESET# B25
8 AC97_SDATA_IN C26 5 AC97_SDATA_OUT C25
10 AC97_SYNC D24
Detailed information on the audio codec can be found at the National Semiconductor website at www.national.com.
Clock Sources
A 25MHz oscillator supplies the FPGA (pin AD15), the CPLD (pin A8), the Ethernet controller and the Expansion
Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. To generate other clock frequencies
use the PLLs of the FPGA. You can find detailed information on the usage of the PLLs on the Lattice website and in
the LatticeECP2/M Family Data Sheet.
The USB controller requires a 24MHz quartz for configuration. Another 12MHz quartz supplies the USB
host/peripheral controller.
Note: Since the Ethernet controller demands a 25MHz clock, no other basic clock can be used. Use the PLLs of the
FPGA to generate custom frequencies.
DDR SODIMM Socket for DDR SDRAM Modules

The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included).
The upper four bytes of the data bus (D[63:32]) are not connected. Thus, only half of the capacity of the memory
module is available.
The DDR SODIMM socket is factory configured to provide a regulated 2.5V. DDR400 modules require a power
supply of 2.6V (±0.1V). Using a jumper on connector X21 (below the 5V power supply jack), the DDR power supply
can be changed to suit the needs of DDR400 modules.
Note: If you want to use the DDR SDRAM interface with a 16-bit data bus, provide your HDL design with an addi-
tional input port that is assigned to pin P9 of bank 6 (connected to schematic net DDR_VREF).
Do not use this signal in your design. Deactivate the internal pull-up of the pin in the ispLEVER software. It safe-
guards the DDR RAM memory from getting an incorrect supply voltage which will happen when the pin is unused
at a data bus width of 16 bits.
When using a 32-bit data bus, you do not have to assign this pin—ispLEVER will take care of it automatically.
6
Table 3. DDR SODIMM Socket (X4) - Data Bus

11 DDR_DQS0 AE6 47 DDR_DQS2 AB3
12 DDR_DM0 AF6 48 DDR_DM2 AB2
5 DDR_DQ0 AD9 41 DDR_DQ16 AE2
7 DDR_DQ1 AD4 43 DDR_DQ17 AD1
13 DDR_DQ2 Y5 49 DDR_DQ18 AD2
17 DDR_DQ3 AD8 53 DDR_DQ19 AD3
6 DDR_DQ4 AC8 42 DDR_DQ20 AC1
8 DDR_DQ5 AB8 44 DDR_DQ21 AC2
14 DDR_DQ6 AF7 50 DDR_DQ22 Y5
18 DDR_DQ7 AE7 54 DDR_DQ23 Y6
25 DDR_DQS1 AA6 61 DDR_DQS3 T1
26 DDR_DM1 AB6 62 DDR_DM3 T2
19 DDR_DQ8 AF5 55 DDR_DQ24 V1
23 DDR_DQ9 AE5 59 DDR_DQ25 U1
29 DDR_DQ10 AD5 65 DDR_DQ26 P4
31 DDR_DQ11 AC5 67 DDR_DQ27 P5
20 DDR_DQ12 AF4 56 DDR_DQ28 P6
24 DDR_DQ13 AE4 60 DDR_DQ29 N3
30 DDR_DQ14 AD4 66 DDR_DQ30 N4
32 DDR_DQ15 AC4 68 DDR_DQ31 N5
Table 4. DDR SODIMM Socket (X4) - Address Bus

112 DDR_A0 AD10 111 DDR_A1 AD14
110 DDR_A2 AB12 109 DDR_A3 AC12
108 DDR_A4 AD12 107 DDR_A5 AB13
106 DDR_A6 AC13 105 DDR_A7 AD13
102 DDR_A8 AB15 101 DDR_A9 AB14
115 DDR_A10 AC10 100 DDR_A11 AC14
99 DDR_A12 AD14 123 DDR_A13 AB10
117 DDR_BA0 AD7 116 DDR_BA1 AC7
Table 5. DDR SODIMM Socket (X4) - Other Signals

35 DDR_CK0+ AE12 37 DDR_CK0- AF12
160 DDR_CK1+ Y1 158 DDR_CK1- AA2
96 DDR_CKE0 AF11 95 DDR_CKE1 AF10
118 DDR_RAS# AE9 119 DDR_WE# AE10
120 DDR_CAS# AF9 121 DDR_S0# AF8
122 DDR_S1# AE8
7
Ethernet Interface
An Intel LXT971A is included for Ethernet PHY. This is an IEEE-compliant Fast Ethernet PHY Transceiver that
directly supports both 100BASE-TX and 10BASE-T applications, full and half duplex. For more information, please
refer to the data sheet of this component.
Each board has its own unique MAC address so that no conflicts with other components in the network will occur.
Specify this MAC address for synthesis of Ethernet designs. It can be found on the sticker at the bottom side of
your board.
Table 6. Ethernet Controller U0801 Pin Definition

4 HPE_RESOUT# AE24 42 ETH_MDIO N25
43 ETH_MDC M26 45 ETH_RXD3 W25
46 ETH_RXD2 W26 47 ETH_RXD1 Y26
48 ETH_RXD0 AA26 49 ETH_RXDV R25
52 ETH_RXCLK L26 53 ETH_RXER P26
54 ETH_TXER U26 55 ETH_TXEN R26
56 ETH_TXCLK L25 57 ETH_TXD0 V26
58 ETH_TXD1 V25 59 ETH_TXD2 V24
60 ETH_TXD3 V23 62 ETH_COL P25
63 ETH_CRS N26 64 ETH_MDINTR# W24
Expansion Connector
The expansion connector provides 46 user I/Os connected to the FPGA. The remaining pins serve as power and
clock supplies for expansion boards. The expansion connector is configured as two 2x20 100mil centered pin head-
ers (X12 and X13). Tables 7 and 8 describe the connections to the FPGA.
Table 7. Expansion Connector X13
1 GND — 2 NC (coding) —
3 VCC2V5 — 4 EXPCON_IO29 H4
5 EXPCON_IO30 H5 6 EXPCON_IO31 H6
7 EXPCON_IO32 H7 8 EXPCON_IO33 H8
9 EXPCON_IO34 G1 10 EXPCON_IO35 G2
11 EXPCON_IO36 G3 12 EXPCON_IO37 G4
13 EXPCON_IO38 F1 14 EXPCON_IO39 F2
15 EXPCON_IO40 F5 16 EXPCON_IO41 F6
17 EXPCON_IO42 E1 18 EXPCON_IO43 E2
19 EXPCON_IO44 E3 20 EXPCON_IO45 E4
21 VCC5V0 — 22 GND —
23 VCC2V5 — 24 GND —
25 VCC3V3 — 26 GND —
27 VCC3V3 — 28 GND —
29 EXPCON_OSC — 30 GND —
31 EXPCON_CLKIN — 32 GND —
33 EXPCON_CLKOUT — 34 GND —
35 VCC3V3 — 36 GND —
8
Table 7. Expansion Connector X13 (Continued)

37 VCC3V3 — 38 GND —
39 VCC3V3 — 40 GND —
Table 8. Expansion Connector X14

1 HPE_RESET# — 2 GND —
3 EXPCON_IO0 R1 4 EXPCON_IO1 R2
5 EXPCON_IO2 P1 6 EXPCON_IO3 P2
7 EXPCON_IO4 N1 8 EXPCON_IO5 M6
9 EXPCON_IO6 L2 10 EXPCON_IO7 L5
11 EXPCON_IO8 L6 12 EXPCON_IO9 L7
13 EXPCON_IO10 L8 14 EXPCON_IO11 K1
15 EXPCON_IO12 K2 16 EXPCON_IO13 K3
17 EXPCON_IO14 K4 18 EXPCON_IO15 K5
19 GND — 20 VCC3V3 —
21 EXPCON_IO16 K6 22 GND —
27 EXPCON_IO19 J1 28 EXPCON_IO20 J2
29 EXPCON_IO21 J3 30 GND —
31 EXPCON_IO22 J4 32 EXPCON_IO23 J5
33 EXPCON_IO24 J8 34 GND —
35 EXPCON_IO25 J9 36 EXPCON_IO26 H1
37 EXPCON_IO27 H2 38 CARDSEL# D1
39 EXPCON_IO28 H3 40 GND —
ispDOWNLOAD Cable Connector

There are two ways to configure the programmable Lattice devices on the board. The USB connector requires a
standard USB cable, and is described later in this document. Connector X3 is available to connect a Lattice isp-
DOWNLOAD cable. An ispDOWNLOAD cable is used to program IEEE 1532 compliant programmable devices.
Lattice provides either a parallel port or a USB port download cable. The FPGA and CPLD are programmed using
the cable and ispVM® programming software.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the
board inoperable.
DIP switch SW03021 controls the device to be configured: the FPGA or the MachXO. If it is on (in top position), the
MachXO is selected; if off, the FPGA is selected.
The ispVM System software can be downloaded from the Lattice web site at: www.latticesemi.com/ispvm.
Note: Do not change the switch when the configuration of a device is in progress!
1. Caption on the board: CONF.
9
Note: The board as configured from the factory, has a built-in USB ispDOWNLOAD cable. The built-in cable and an
external ispDOWNLOAD cable cannot be used at the same time. Doing so may damage the board.
Table 9. ispDOWNLOAD Connector X4 Pin Definition

Pin Signal Name Pin Signal Name
1 VCC3V3 2 JTAG_TDO
3 JTAG_TDI 4 JTAG_PROG
5 JTAG_TRST 6 JTAG_TMS
7 GND 8 JTAG_TCK
9 JTAG_DONE 10 JTAG_INIT
LCD Connector (Optional)

The LCD connector is a 16-pin header with a standard pinning for LCD modules with back-light (e.g. Truly MTC-
C202DPRN-1N). In order to use an LCD module, attach it to the connector via a 16-pin ribbon cable.
Note: The LCD module is tied to a 5V supply. The LatticeECP2-50 to LCD interface is 3.3V.
Put a jumper on connector X6 to turn on the backlight of the LCD. The contrast of the LCD module is adjustable
with the potentiometer R0526, because different LCD modules need different voltages for the best contrast.
Figure 3. LCD Panel (Not Included)
Table 10. LCD Connector X6 Pin Definition

1 GND — 2 VCC5V —
3 CONTRAST — 4 LCD_REGSEL K24
5 LCD_RW J24 6 LCD_ENABLE J22
7 SEG_A# M24 8 SEG_B# N23
9 SEG_C# M22 10 SEG_D# M21
11 SEG_E# M20 12 SEG_F# L22
13 SEG_G# L21 14 SEG_DP# K22
15 BACKLIGHT — 16 GND —
SATA Interfaces
Find the jacks X15 and X16 for connecting SATA cables on the right side of the board. This provides a convenient
method for evaluating or using LVDS signals with the FPGA. This board does not support implementation of a full
SATA solution. These SATA jacks have differential nets with high-speed signals connected to them. See Table 11
for SATA pinning information. The positive signal is connected with a plus (+), the negative with a minus (-). Every
differential signal pair can act as receiver or transmitter depending on the configuration of the FPGA.
10
Table 11. SATA Jacks X15 (Left Column) and X16 (Right Column) Pin Definition
2 SATA_X1D0+ M4 2 SATA_X2D0+ U3
3 SATA_X1D0- M5 3 SATA_X2D0- U4
5 SATA_X1D1+ P3 5 SATA_X2D1+ V2
6 SATA_X1D1- R3 6 SATA_X2D1- W2
Serial Interface
The board includes an RS232 serial interface port. The interface provides transmit (TX), receive (RX), and hard-
ware handshaking. The Maxim MAX3232 data sheet provides detailed information on the interface circuit. A 9-pin
female to 9-pin female null modem cable is required.
Table 12. Serial Interface X9 Pin Definition

Sub-D Pin Signal FPGA Pin Direction RS232 Function
3 RS_TXD_LVTTL K26 Out Transmit Data
7 RS_RTS_LVTTL K25 Out Request to Send
2 RS_RXD_LVTTL J25 In Receive Data
8 RS_CTS_LVTTL J26 In Clear to Send
Sigma Delta D/A Converter

The board includes a low-pass filter connected to a dedicated pin (C14) of the FPGA. With this, a sigma delta con-
verter can be realized. Great results can be achieved by using a resolution of 8 to 10 bits. Example VHDL code is
provided.
Power Supply
Four different voltages are needed: 3.3V I/O voltage, 2.5V DDR and LVDS voltages as well as 1.2V core voltage.
The 3.3V supply draws up to 1A, the 2.5V and 1.2V supplies up to 2A of current.
For more information, see the power supply information in the Components section of this document.
Test Points
In order to check the various voltage levels used, several test points are provided. There is one test point for 1.2V,
2.5V, 3.3V, one for ground, and one for accessing the 25MHz oscillator. The 25MHz clock signal can be checked
with another test point.
USB Host/Peripheral Interface

There are one mini USB OTG and two USB host connectors on board. These are connected to the Cypress
CY7C67300 USB Host/Peripheral Controller U0702. This controller is compliant with the Universal Serial Bus
Specification 2.0. You can transmit and receive serial data at both full-speed (12 Mbps) and low-speed (1.5 Mbps)
data rates. For more information, please refer to the data sheet of the USB controller. U0703 and U0704 are USB
power control switches, which must be enabled by the user via the USB PWEN signals. The USB OC signal pulls
low to indicate voltage, current and thermal issues.
Table 13. USB GPIO Connections (U0702)
94 USB_GPIO0 AE20 93 USB_GPIO1 AC18
92 USB_GPIO2 AE13 91 USB_GPIO3 AB20
90 USB_GPIO4 AA20 89 USB_GPIO5 AF19
87 USB_GPIO6 AE19 86 USB_GPIO7 AD19
11
Table 13. USB GPIO Connections (U0702) (Continued)

66 USB_GPIO8 AC19 65 USB_GPIO9 AB19
61 USB_GPIO10 AA19 60 USB_GPIO11 AF18
59 USB_GPIO12 AE18 58 USB_GPIO13 AD18
57 USB_GPIO14 AC18 56 USB_GPIO15 AB18
55 USB_GPIO16 AF17 54 USB_GPIO17 AE17
53 USB_GPIO18 AD17 52 USB_GPIO19 AC17
50 USB_GPIO20 AB17 49 USB_GPIO21 AF16
48 USB_GPIO22 AE16 47 USB_GPIO23 AF15
42 USB_GPIO28 AE13 41 USB_GPIO29 -
Table 14. Additional USB GPIO Connections (U0702, U0704, and U0704)
U0703:1 USB_PWEN0 Y17 U0703:2 USB_OC0# AA16
U0703:4 USB_PWEN1 Y16 U0703:3 USB_OC1# Y20
U0704:1 USB_PWEN2 AA21 U0704:2 USB_OC2# Y19
U0702:85 HPE_RESOUT# AE24
USB Configuration Connector

In addition to the ispDOWNLOAD connector, the FPGA and the MachXO can also be configured by a standard
USB connection. The USB target connector is wired to the Cypress CY7C68013A device (U0301).
This programming method requires the use of the ispVM System software. This can be downloaded from the Lat-
tice web site at: www.latticesemi.com/ispvm.
This connection will appear to the ispVM System software as if a regular USB-based ispDOWNLOAD cable is con-
nected to the PC.
The CY7C68013A in combination with the MachXO CPLD acts as a built-in ispDOWNLOAD cable. The MachXO is
connected to the ispDOWNLOAD Connector X3, and can program the LatticeECP2-50. The LatticeECP2-50 can
be programmed when DIP switch SW0302 is ‘off’ (pushed down).
Note: Like the ispDOWNLOAD connector, the MachXO drives the JTAG signals when it is programmed for USB
configuration. Only use the built-in ispDOWNLOAD cable or an external ispDOWNLOAD cable exclusively. It is not
recommended to switch between cables without first power cycling the board. Failure to follow this recommenda-
tion may cause unpredictable results and may possibly damage the board.
Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO
Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin
34 GP_D0 G14 35 GP_D1 N14
36 GP_D2 H14 37 GP_D3 H13
44 GP_D4 H12 45 GP_D5 J13
46 GP_D6 J12 47 GP_D7 K14
80 GP_D8 K13 81 GP_D9 K12
82 GP_D10 L14 83 GP_D11 M13
95 GP_D12 M14 96 GP_D13 M12
12
Table 15. Connections Between the USB Controller (CY7C68013A) and the MachXO (Continued)
Cypress Pin Signal Name MachXO Pin Cypress Pin Signal Name MachXO Pin
97 GP_D14 N14 98 GP_D15 N13
57 GP_ADR0 H1 58 GP_ADR1 H2
59 GP_ADR2 J1 60 GP_ADR3 J3
61 GP_ADR4 K1 62 GP_ADR5 K2
63 GP_ADR6 L1 64 GP_ADR7 L3
93 GP_ADR8 M1 69 GP_SLOE M3
67 GP_INT0 N7 68 GP_INT1 M6
71 GP_FIFOADR0 M4 72 GP_FIFOADR1 N4
70 GP_WU2 N3 73 GP_PKTEND P5
74 GP_SLCS# G3 79 USBCF_WAKE N9
3 GP_RDY0 D3 4 GP_RDY1 E2
5 GP_RDY2 F2 6 GP_RDY3 F3
7 GP_RDY4 G1 8 GP_RDY5 G2
54 GP_CTL0 D1 55 GP_CTL1 C3
56 GP_CTL2 C2 51 GP_CTL3 C1
52 GP_CTL4 B2 76 GP_CTL5 B1
23 GP_T0 M2 24 GP_T1 N1
25 GP_T2 P1 28 GP_BKPT F12
100 USB_CLK_O M7 26 GP_IFCLK M8
41 GP_RXD0 E13 40 GP_TXD0 E14
43 GP_RXD1 F13 42 GP_TXD1 F14
VGA Interface
The board includes a VGA connector for driving a VGA monitor. The VGA interface is connected to a 15-pin plug
socket. The pin definitions are listed in Table 16.
VGA RD0 and VGA RD1 are both connected to pin 1, but have different series resistors (see Figure 4). Thus, a 6-
bit VGA interface is realized. Figure 4 shows the connection of the RGB signals. The FPGA is responsible for gen-
erating correct HSYNC and VSYNC sweep frequencies. Understand the SYNC frequencies of the VGA monitor
being connected to the VGA plug and adjust the FPGA frequencies as required.
Table 16. VGA Connector X1B Pin Definition, n.c. ... Not Connected
1 VGA_RD0 AF24 1 VGA_RD1 AE23
2 VGA_GR0 AF23 2 VGA_GR1 AE22
3 VGA_BL0 AF22 3 VGA_BL1 AE21
4 n.c. — 5 n.c. —
6 GND — 7 GND —
8 GND — 9 n.c. —
10 GND — 11 n.c. —
12 n.c. — 13 VGA_HSYNC AF20
14 VGA_VSYNC AF21 15 n.c. —
13
Figure 4. VGA Connector
14
User Interface
Figure 5 shows the position of the user interface elements.
Figure 5. User Interface Features (Version 1 Board Shown in this Figure)

Audio Mini USB
RS232 Ethernet VGA
Power Plug Line In
Connector 10/100M Connector OTG Connector
Line Out
USB Host
Connector
2.5 V
Testpoint
3.3 V
Testpoint DDR SDRAM
Sockel
GND
Testpoint
1.2 V
Testpoint SATA LVDS
Connectors
CLK
Testpoint
Flywire
Connector
High-Speed Expansion
USB for Connector
Configuration
LCD Sigma Delta

Connector DAC Connector
15
7-Segment Display
The 7-segment display is wired as follows:
Table 17. 7-Segment Display U0502 Pin Definition
F G B
E C
A SEG_A# M24 E SEG_E# M20
B SEG_B# N23 F SEG_F# L22
C SEG_C# M22 G SEG_G# L21
D SEG_D# M21 DP SEG_DP# K22
right SEG_CA0# K21 left SEG_CA1# K20
The signals of the 7-segment display are low-active, which means that with a logic ‘0’, the segment is lit. SEG A# ...
SEG F# and SEG DP# drive not only the two 7-segment displays, but also the LCD. To write different data to these
three components, the user must drive the signals alternately to the components. This can be realized with the sig-
nals SEG CA0#, SEG CA1# and LCD ENABLE. They serve to activate the two 7-segment displays and the LCD,
respectively.
DIP Switches
There is a 4-bit DIP switch on the board. When the switch is turned to the on position, a logic ‘1’ will be seen. The
connections are in Table 18.
Table 18. DIP Switches SW0514 Connection

Switch Signal Name FPGA Pin Switch Signal Name FPGA Pin
SW315 SW316
1 DSW0 F26 2 DSW1 F25
3 DSW2 E26 4 DSW3 E25
LEDs
Eight LEDs can be used for custom status signaling. They are low-active; with a logic ‘0’ the LED is on. You can
control the LEDs via the signals below.
Table 19. LED LD0501 ... LD0508 Connection

1 LED0# R24 5 LED4# P23
2 LED1# R23 6 LED5# P22
3 LED2# R22 7 LED6# P21
4 LED3# R21 8 LED7# N22
Key Matrix
The board also features a key matrix with 12 push-buttons, which are not debounced. They must be driven with
three column lines and can be read with four rows. The following table shows the connections.
16
Table 20. Key Matrix with the Keys SW302 ... SW313 Definition
Signal Name TST_COL0 TST_COL1 TST_COL2
TST_ROW0 1 2 3
TST_ROW1 4 5 6
TST_ROW2 7 8 9
TST_ROW3 C 0 E
Table 21. Key Matrix with the Keys SW302 ... SW313 Connection
Signal Name FPGA Pin Signal Name FPGA Pin
TST_ROW0 H26 TST_COL0 G26
TST_ROW3 H23
To query all keys of the matrix, you must poll the column driver signals (TST COL0, TST COL1, and TST COL2). If
you press a key, a logic ‘1’ appears in the corresponding row. The following diagram explains the functionality:
Figure 6. Polling of the Key Matrix
Col0
Col1
Col2
1 pressed 3 pressed
Row0
6 pressed 6 pressed
Row1
You do not need the polling method if only four keys are used. Connect the column driver signals of one column to
VCC, the other two to GND and query the row data signals.
CPU Reset Key

The CPU reset key is a global reset. Please refer to the Reset Chip section of this document for detailed informa-
tion.
Single Step Key

The single step key is connected to a normal input of the FPGA and can be used by the application as required.
This key is connected to a Schmitt trigger, meaning it is debounced. This key can be used as a single clock for test-
ing your design.
17
Components
Figure 7 illustrates the position of major components.
Figure 7. Components (Version 1 board Shown in this Figure)

USB Host/
AC‘97 Audio
Target/OTG
Codec
Controller
Ethernet
PHY
CPLD
MachXO
FPGA
USB LFEC250
Configuration
Controller
Prototyping
Area
SPI Reset Asynchronous Parallel

Flash Controller SRAM Flash
18
12 x 12 FPGA Prototyping Area of The FPGA

A 12x12 prototyping area is available. The lead-wire spacing of the prototyping area is 100mil (2.54 mm). Figure 8
shows the prototyping area in top view. 14 plated-through-holes on its left side are connected to the FPGA. Eight
through-holes on the right side are wired to a 2.5V I/O bank. In the top row of the prototyping area there are six
connections to the 3.3V power supply as well as three to 2.5V. The bottom row has ten plated-through-holes con-
nected to GND.
Table 22. FPGA Connections for the 12x12 Prototyping Area

LRF Pin Signal Name FPGA Pin LRF Pin Signal Name FPGA Pin
TP0901 BB3V3_IO0 A15 TP0902 BB3V3_IO1 B15
TP0903 BB3V3_IO2 C15 TP0904 BB3V3_IO3 D15
TP0907 BB3V3_IO6 E16 TP0908 BB3V3_IO7 A17
TP0909 BB3V3_IO8 B17 TP0910 BB3V3_IO9 C17
TP0911 BB3V3_IO10 D17 TP0912 BB3V3_IO11 E17
TP09135 BB3V3_IO14 C18 TP09136 BB3V3_IO15 D18
TP09137 BB3V3_IO16 E18 TP09138 BB3V3_IO17 A19
TP09139 BB3V3_IO18 B19 TP09140 BB3V3_IO19 C19
TP09141 BB3V3_IO20 D19 TP09142 BB3V3_IO21 E19
TP09143 BB3V3_CLK0+ D14 TP09144 BB3V3_CLK0- F14
TP0913 VCC3V3 — TP0925 VCC3V3 —
TP0937 VCC3V3 — TP0949 VCC3V3 —
TP0961 VCC3V3 — TP0973 VCC3V3 —
TP0985 VCC3V3 — TP0997 VCC3V3 —
TP09109 VCC3V3 — TP09121 VCC3V3 —
TP0924 GND — TP0936 GND —
TP0996 GND — TP09108 GND —
TP09120 GND — TP09132 GND —
19
Figure 8. Schematic Illustration of the Prototyping Area

VCC3V3
BB3V3_IO[21:0]
BB3V3_IO[21:0]
TP0901 TP0913 TP0925 TP0937 TP0949 TP0961 TP0973 TP0985 TP0997 TP09109 TP09121 TP09133
BB3V3_IO0 BB3V3_IO12
BB3V3_IO10 BB3V3_CLK0+
DIFF
BB3V3_IO11 BB3V3_CLK0-
GND
Asynchronous SRAM
The board is populated with two asynchronous K6R4016V1D SRAMs from Samsung. Each is 4 Mbit in size with a
data bus width of 16 bits. They are wired as one memory with a 32-bit data bus and a depth of 256 k. The 18-bit
address bus, the data bus and the control signals are connected directly to the FPGA. The 18-bit address bus,
named MEMORY_A0 through MEMORY_A17, addresses word (4 bytes) locations.
Table 23. Address Signals of the Asynchronous SRAM Chips U0404 and U0405
SRAM Pin Signal Name FPGA Pin SRAM Pin Signal Name FPGA Pin
1 MEMORY_A0 C1 2 MEMORY_A1 B2
3 MEMORY_A2 C2 4 MEMORY_A3 A3
5 MEMORY_A4 B3 18 MEMORY_A5 C3
19 MEMORY_A6 D3 20 MEMORY_A7 A4
27 MEMORY_A14 D5 42 MEMORY_A15 E5
43 MEMORY_A16 A6 44 MEMORY_A17 B6
20
Table 24. Data Signals of the Asynchronous SRAM Chip U0404

7 MEMORY_DQ0 E7 8 MEMORY_DQ1 F7
9 MEMORY_DQ2 G7 10 MEMORY_DQ3 A8
13 MEMORY_DQ4 B8 14 MEMORY_DQ5 C8
15 MEMORY_DQ6 D8 16 MEMORY_DQ7 E8
29 MEMORY_DQ8 F8 30 MEMORY_DQ9 G8
31 MEMORY_DQ10 A9 32 MEMORY_DQ11 B9
35 MEMORY_DQ12 C9 36 MEMORY_DQ13 D9
37 MEMORY_DQ14 E9 38 MEMORY_DQ15 A10
Table 25. Data Signals of the Asynchronous SRAM Chip U0405

31 MEMORY_DQ26 G11 32 MEMORY_DQ27 C12
Table 26. Control Signals of the Asynchronous SRAM Chips U0404 and U0405
SRAM Pin Signal Name FPGA Pin
17 MEMORY_WE# C13 41 MEMORY_OE# D13
39 SRAM_BE0# F13 40 SRAM_BE1# G13
6 SRAM_CE# E13
MachXO
The LCMXO640 is a non-volatile, instant-on, reprogrammable logic device. It supports “background programming”
called TransFR™ (i.e., the device can be programmed while in operation).
The MachXO comes preprogrammed from the factory. The factory program permits the CY7C68013A/MachXO
combination to work as a built-in USB ispDOWNLOAD cable. Using ispVM software the built-in download cable
permits the FPGA, and SPI PROM, to be programmed. It is not recommended for the MachXO to be repro-
grammed. However, the MachXO does provide some connections to the LatticeECP2-50 FPGA, and to an 8x6 pro-
totyping area.
For further information, please consult the MachXO Family Data Sheet.
21
Table 27. Interface Between the MachXO and the FPGA

CPLD Pin Signal Name FPGA Pin CPLD Pin Signal Name FPGA Pin
A1 MACHXO_IO0 A20 A2 MACHXO_IO1 A23
A3 MACHXO_IO2 C20 B3 MACHXO_IO3 D20
A4 MACHXO_IO4 E20 C4 MACHXO_IO5 A21
A5 MACHXO_IO6 B21 B5 MACHXO_IO7 E21
A6 MACHXO_IO8 A22 B6 MACHXO_IO9 B22
B10 MACHXO_IO10 C22 A11 MACHXO_IO11 D22
A12 MACHXO_IO12 A23 B12 MACHXO_IO13 B23
A13 MACHXO_IO14 E23 A14 MACHXO_IO15 A24
C8 MACHXO_CLK0 H13 B8 MACHXO_CLK0 H13
FPGA
The LatticeECP2-50 FPGA represents the heart of the board. It has the following features:
• 48 k Look-Up Tables (LUTs)
• 96 kbit of distributed RAM
• 387 kbit of EBR SRAM
• 21 EBR SRAM blocks
• 18 sysDSP blocks
• 72 18 x 18 multipliers
• 6 PLLs: 2 GPLLs, 2 SPLLs, 2 GDLLs
• 500 user I/Os
• DDR memory support (DDR1-400, DDR2-400)
• Supported I/O standards: LVCMOS, LVTTL, SSTL, HSTL, LVDS, PCI, differential
• HSTL, differential SSTL, RSDS, Bus LVDS, MLVDS, LVPECL
The ispLEVER design software can be used to develop/modify programs for the FPGA using Verilog or VHDL
design entry methods. For more information on the ispLEVER software, see www.latticesemi.com/software.
Sample programs for the FPGA are available on-line as well. These can be found at www.latticesemi.com/boards.
Select FPGA/FPSC Boards -> LatticeMico32/DSP Development board for LatticeECP2 and click on the
Design Files link.
For further information please consult the LatticeECP2/M Family Data Sheet.
Parallel Flash
Two parallel MX29LV128MBTI-90Q Flash components from Macronics (or equivalents) are provided on the board
for program code and data. As with the SRAM, a 32-bit data bus is realized with these two devices. Thus, Flash can
be accessed as a 8Mx32 memory. The 23-bit address bus, the data bus and the control signals are connected
directly to the FPGA. The 23-bit address bus, named MEMORY_A0 through MEMORY_A22, addresses word (4
bytes) locations.
22
Note: The LatticeMico32/DSD Development Board generates byte enable outputs at the top-level HDL module. The
board does not use these outputs, which causes ispLEVER to generate some warning messages. The warnings
correctly tell the user that these pins are not connected or assigned to any location. The warnings can be avoided
by either commenting out these byte enable outputs, or assigning them to unused I/O.
Table 28. Address Signals of the Flash Chips U0402 and U0403
Flash Pin Signal Name FPGA Pin Flash Pin Signal Name FPGA Pin
31 MEMORY_A0 C1 26 MEMORY_A1 B2
25 MEMORY_A2 C2 24 MEMORY_A3 A3
4 MEMORY_A14 D5 3 MEMORY_A15 E5
54 MEMORY_A16 A6 19 MEMORY_A17 B6
18 MEMORY_A18 E6 11 MEMORY_A19 A7
2 MEMORY_A22 D7
Table 29. Data Signals of the Flash Chip U0402

35 MEMORY_DQ0 E7 37 MEMORY_DQ1 C9
39 MEMORY_DQ2 A11 41 MEMORY_DQ3 F12
45 MEMORY_DQ12 C9 47 MEMORY_DQ13 D9
49 MEMORY_DQ14 E9 51 MEMORY_DQ15 A10
Table 30. Data Signals of the Flash Chip U0403

40 MEMORY_DQ26 G11 42 MEMORY_DQ27 C12
23
Table 31. Control Signals of the Flash Chips U0402 and U0403
34 MEMORY_OE# D13 13 MEMORY_WE# C13
32 FLASH_CE# A13 16 FLASH_WP#/ACC A12
14 FLASH_RESET B14 17 FLASH_RY/BY#_A A14
53 FLASH_BYTE# B12
SPI Flash
The LatticeECP2-50 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to be
automatically configured upon power-up, a non-volatile 16 Mbit SPI Flash device is provided. The SPI Flash can be
programmed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWN-
LOAD connector or via the integrated USB configuration interface.
Table 32. FPGA to SPI Flash Connections

SPI Pin Signal Name FPGA Port Name FPGA Direction FPGA Pin
CS CSSPIN CEJ Output V22
CLK CCLK SCK Output NC/E191
Q SPIDO SO Input W23
DI SISPI SI Output Y25
WPn WP# WPJ Output AA25 (FPGA NC)
HOLDn HOLD# HOLDJ Output AB26 (FPGA NC)
Note: The SPI CLK pin can be connected to FPGA E19. This allows the LatticeMico32 to access the SPI PROM for
data retrieval/storage purposes. On revision B boards, CLK is E17.
To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. The
FPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices.
The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device.
Configure the SPI Flash as follows:
1. In the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box.
2. Click Select to open the Select Device dialog box. Select device family LatticeECP2, device LFE2-50E, and
package 672 fpBGA from the drop-down lists.
3. Change the Device Access Options to SPI Flash Programming.
4. Select Flash Device : STMicro SPI-M25P16 and click OK.
5. Browse Data File: Select the ECP2-50 bitstream to program into the SPI PROM, click OK.
6. Click OK to close the SPI Serial Flash Device dialog.
7. Click OK to close the Device Information dialog
8. Click GO. The ispVM System software programs the SPI Flash via the FPGA.
9. Disconnect and then reconnect the power supply. The FPGA will take about three seconds to be programmed
by the SPI Flash.
Power Supply
Power is supplied via a 2.1 mm DC power jack in the top left corner of the board. The board is protected against
reversed power supply. The input supply is 5V DC.
24
A two-phase synchronous step-down switching regulator generates the 3.3V (1A max.) I/O voltage and the 1.2V
(2A max.) core voltage.
Note: If you use a power supply other than the one included in the shipment, make sure it supplies regulated 5V.
Reset Chip
After power-up, a power surveillance chip (U0601) waits until the 5V supply and the 3.3V I/O voltage are stable.
Then, after 200 ms, it drives the signal HPE RESET# (pin M25 of the FPGA) high. If you press the reset button, the
supervisory circuit will generate a low on the HPE RESET# signal.
The surveillance chip has an I2C serial 2 kbit CMOS EEPROM. The four most significant bits of the 8-bit slave
address are programmable; the default being 1010. Detailed information on the reset circuit and the I2C interface
can be found in the data sheet of the Catalyst Semiconductor CAT1026.
Troubleshooting
If your board is not working properly, please follow these steps for diagnosis.
1. Check the 3.3V and 2.5V LEDs to ensure that the power supply is working correctly.
2. Make sure that the INIT LED is lit.

3. Load test program.
4. Make sure the FPGA has been configured properly (DONE LED must be lit).
5. Start test program 1.
Circuit diagrams for the localization of errors can be found in the appendix.
Electrical Specifications
Power requirement: regulated 5V DC
Input current: 2000 mA
Mechanical Specifications
Dimensions: 160 mm [L] x 160 mm [W] x 31 mm [H]
Net weight: 160 g
Temperature range: 0 to 50oC
25
FPGA Pin Information

Table 33. Pin Table
Pin Name Signal Name Area
M24 SEG_A# 7-Segment Display
N23 SEG_B# 7-Segment Display
M22 SEG_B# 7-Segment Display
K21 SEG_CA0# 7-Segment Display
K20 SEG_CA0# 7-Segment Display
M21 SEG_D# 7-Segment Display
K22 SEG_DP# 7-Segment Display
M20 SEG_E# 7-Segment Display
L22 SEG_F# 7-Segment Display
L21 SEG_G# 7-Segment Display
B24 AC97_BITCLK AC97 Audio Codec
C23 AC97_EAPD AC97 Audio Codec
D25 AC97_EXT CLK AC97 Audio Codec
B25 AC97_RESET# AC97 Audio Codec
C26 AC97_SDATA_IN AC97 Audio Codec
C25 AC97_SDATA_OUT AC97 Audio Codec
D24 AC97_SYNC AC97 Audio Codec
W4 ADC- Analog Digital Converter
W3 ADC+ Analog Digital Converter
Y3 ADCS Analog Digital Converter
AA22 CCLK Configuration
AC24 CFG0 Configuration
W20 CFG1 Configuration
AD24 CFG2 Configuration
V22 CSSPIN Configuration
Y24 DOUT Configuration
AC3 EC_TCK Configuration
AA8 EC_TDI Configuration
AA5 EC_TDO Configuration
AB4 EC_TMS Configuration
AD25 JTAG_DONE Configuration
AB24 JTAG_INIT Configuration
V19 PROGRAM# Configuration
Y25 SISPI Configuration
W23 SPIDO Configuration
AB25 SPIFASTN# Configuration
AD10 DDR_A0 DDR SDRAM
AB11 DDR_A1 DDR SDRAM
AC10 DDR_A10 DDR SDRAM
26
Table 33. Pin Table (Continued)

AD7 DDR_BA0 DDR SDRAM
AC7 DDR_BA1 DDR SDRAM
AF9 DDR_CAS# DDR SDRAM
AF12 DDR_CK0- DDR SDRAM
AE12 DDR_CK0+ DDR SDRAM
AA2 DDR_CK1- DDR SDRAM
Y1 DDR_CK1+ DDR SDRAM
AF11 DDR_CKE0 DDR SDRAM
AF10 DDR_CKE1 DDR SDRAM
AF6 DDR_DM0 DDR SDRAM
AB6 DDR_DM1 DDR SDRAM
AB2 DDR_DM2 DDR SDRAM
T2 DDR_DM3 DDR SDRAM
AD9 DDR_DQ0 DDR SDRAM
AC9 DDR_DQ1 DDR SDRAM
AF4 DDR_DQ12 DDR SDRAM
AE4 DDR_DQ13 DDR SDRAM
AB9 DDR_DQ2 DDR SDRAM
Y5 DDR_DQ22 DDR SDRAM
Y6 DDR_DQ23 DDR SDRAM
V1 DDR_DQ24 DDR SDRAM
U1 DDR_DQ25 DDR SDRAM
P4 DDR_DQ26 DDR SDRAM
N3 DDR_DQ29 DDR SDRAM
27

AB8 DDR_DQ5 DDR SDRAM
AE6 DDR_DQS0 DDR SDRAM
AA6 DDR_DQS1 DDR SDRAM
AB3 DDR_DQS2 DDR SDRAM
T1 DDR_DQS3 DDR SDRAM
AE9 DDR_RAS# DDR SDRAM
AF8 DDR_S0# DDR SDRAM
AE8 DDR_S1# DDR SDRAM
AF3 DDR_VREF DDR SDRAM
P9 DDR_VREF DDR SDRAM
AE10 DDR_WE# DDR SDRAM
C14 DAC_DIG Digital Analog Converter
F26 DSW0 DIP Switch
F25 DSW1 DIP Switch
E26 DSW2 DIP Switch
E25 DSW3 DIP Switch
P25 ETH_COL Ethernet
N26 ETH_CRS Ethernet
M26 ETH_MDC Ethernet
W24 ETH_MDINTR# Ethernet
N25 ETH_MDIO Ethernet
L26 ETH_RXCLK Ethernet
AA26 ETH_RXD0 Ethernet
Y26 ETH_RXD1 Ethernet
W26 ETH_RXD2 Ethernet
W25 ETH_RXD3 Ethernet
R25 ETH_RXDV Ethernet
P26 ETH_RXER Ethernet
L25 ETH_TXCLK Ethernet
V26 ETH_TXD0 Ethernet
R26 ETH_TXEN Ethernet
U26 ETH_TXER Ethernet
D1 CARDSEL# Expansion Connector
L1 EXPCON_CLKIN Expansion Connector
28

M1 EXPCON_CLKOUT Expansion Connector
R1 EXPCON_IO0 Expansion Connector
R2 EXPCON_IO1 Expansion Connector
L8 EXPCON_IO10 Expansion Connector
K1 EXPCON_IO11 Expansion Connector
J1 EXPCON_IO19 Expansion Connector
P1 EXPCON_IO2 Expansion Connector
H1 EXPCON_IO26 Expansion Connector
P2 EXPCON_IO3 Expansion Connector
G1 EXPCON_IO34 Expansion Connector
F1 EXPCON_IO38 Expansion Connector
N1 EXPCON_IO4 Expansion Connector
E1 EXPCON_IO42 Expansion Connector
M6 EXPCON_IO5 Expansion Connector
29

B12 FLASH_BYTE# Flash/SRAM
A13 FLASH_CE# Flash/SRAM
B14 FLASH_RESET# Flash/SRAM
A14 FLASH_RY/BY# A Flash/SRAM
B13 FLASH_RY/BY# B Flash/SRAM
A12 FLASH_WP#/ACC Flash/SRAM
C1 MEMORY_A0 Flash/SRAM
B2 MEMORY_A1 Flash/SRAM
D4 MEMORY_A10 Flash/SRAM
A5 MEMORY_A11 Flash/SRAM
E5 MEMORY_A15 Flash/SRAM
E6 MEMORY_A18 Flash/SRAM
E7 MEMORY_DQ0 Flash/SRAM
F7 MEMORY_DQ1 Flash/SRAM
A9 MEMORY_DQ10 Flash/SRAM
B9 MEMORY_DQ11 Flash/SRAM
C9 MEMORY_DQ12 Flash/SRAM
D9 MEMORY_DQ13 Flash/SRAM
30

G7 MEMORY_DQ2 Flash/SRAM
D13 MEMORY_OE# Flash/SRAM
C13 MEMORY_WE# Flash/SRAM
F13 SRAM_BE0# Flash/SRAM
G13 SRAM_BE1# Flash/SRAM
E14 SRAM_BE2# Flash/SRAM
E15 SRAM_BE3# Flash/SRAM
E13 SRAM_CE# Flash/SRAM
AD15 CLK_FPGA FPGA Clock
U25 CLK_FPGA FPGA Clock
F14 BB3V3_CLK0- FPGA Prototyping Area
D14 BB3V3_CLK0+ FPGA Prototyping Area
A15 BB3V3_IO0 FPGA Prototyping Area
B15 BB3V3_IO1 FPGA Prototyping Area
D17 BB3V3_IO10 FPGA Prototyping Area
E17 BB3V3_IO11 FPGA Prototyping Area
C18 BB3V3_IO14 FPGA Prototyping Area
31

T21 I2C_SCL1 I2C EEPROM
T22 I2C_SDA1 I2C EEPROM
G26 TST_COL0 Key Matrix
H26 TST_ROW0 Key Matrix
J22 LCD_ENABLE LCD
K24 LCD_REGSEL LCD
J24 LCD_RW LCD
R24 LED0# LED
R23 LED1# LED
R22 LED2# LED
R21 LED3# LED
P23 LED4# LED
P22 LED5# LED
P21 LED6# LED
N22 LED7# LED
H13 MACHXO_CLK0 MachXO
H14 MACHXO_CLK1 MachXO
A20 MACHXO_IO0 MachXO
B20 MACHXO_IO1 MachXO
C22 MACHXO_IO10 MachXO
D22 MACHXO_IO11 MachXO
E23 MACHXO_IO14 MachXO
C20 MACHXO_IO2 MachXO
D20 MACHXO_IO3 MachXO
32

M25 HPE_RESET# Reset
AE24 HPE_RESOUT# Reset
J26 RS CTS_LVTTL RS232
K25 RS RTS_LVTTL RS232
J25 RS RXD_LVTTL RS232
K26 RS TXD_LVTTL RS232
M5 SATA_X1D0- SATA
M4 SATA_X1D0+ SATA
R3 SATA_X1D1- SATA
P3 SATA_X1D1+ SATA
U4 SATA_X2D0- SATA
U3 SATA_X2D0+ SATA
W2 SATA_X2D1- SATA
V2 SATA_X2D1+ SATA
E24 TST_STEP Single Step Key
AB21 USB_CTS USB Interface
AE20 USB_GPIO0 USB Interface
AD20 USB_GPIO1 USB Interface
AA19 USB_GPIO10 USB Interface
AF18 USB_GPIO11 USB Interface
AC18 USB_GPIO14 USB Interface
AB18 USB_GPIO15 USB Interface
AA20 USB_GPIO4 USB Interface
33

AD23 USB_MISO USB Interface
AB16 USB_MOSI USB Interface
AA16 USB_OC0# USB Interface
Y20 USB_OC1# USB Interface
Y19 USB_OC2# USB Interface
Y17 USB_PWEN0 USB Interface
Y16 USB_PWEN1 USB Interface
AA21 USB_PWEN2 USB Interface
AB22 USB_RTS USB Interface
AC23 USB_RXD USB Interface
AC22 USB_SCK USB Interface
AD22 USB_SSI# USB Interface
AA17 USB_TXD USB Interface
AF22 VGA_BL0 VGA Interface
AE21 VGA_BL1 VGA Interface
AF23 VGA_GR0 VGA Interface
AE22 VGA_GR1 VGA Interface
AF20 VGA_HSYNC VGA Interface
AF24 VGA_RD0 VGA Interface
AE23 VGA_RD1 VGA Interface
AF21 VGA_VSYNC VGA Interface
Ordering Information
Ordering Part China RoHS Environment-
Description Number Friendly Use Period (EFUP)
LatticeMico32/DSP Development Board for LatticeECP2 LFE2-50E-D-EV

10
Technical Support Assistance

Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
34
Revision History
Date Version Change Summary
February 2007 01.0 Initial release.
March 2007 01.1 Added Ordering Information section.
April 2007 01.2 Updated SATA Interfaces information.
Reset Chip section - updated FPGA pin number for the the HPE RESET
signal.
April 2007 01.3 Ordering information (EFUP) updated.
April 2007 01.4 Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
July 2007 01.5 Various minor updates to improve readability, and correct typographical
errors.
August 2007 01.6 Updated information for pins 4-7 in the Expansion Connector X14 table.
Updated information for LRF pin TP0902 in the FPGA Connections for
the 12x12 Prototyping Area table.
September 2007 01.7 Updated Ascynchronous SRAM text section and corresponding table.
Updated Parallel Flash text section.
February 2008 01.8 Updated Ordering Information.
March 2008 01.9 Corrected Schematic Illustration of the Prototyping Area diagram.
April 2008 02.0 Updated 7-Segment Display U0502 Pin Definition table.
June 2008 02.1 Updated Schematic Illustration of the Prototyping Area.
October 2008 02.2 Updated Peripheral Interfaces diagram with Board Version 2
information.
Updated Data Signal of the Asynchronous SRAM Chip U0404 table.
SPI Flash text section - Updated SPI Flash density to 16 bits. Added
table. Updated steps for programing the SPI Flash memory.
Added note to Parallel Flash text section.
Added Appendix B. Board Version 2 Schematics.
October 2008 02.3 Address Signals of the Asynchronous SRAM Chips U0404 and
U0405 table - updated FPGA Pin information for MEMORY_A1 and
MEMORY_A2.
Address Signals of the Flash Chips U0402 and U0403 table -
updated FPGA Pin information for MEMORY_A1 and MEMORY_A2.
October 2008 02.4 Updated photo used in User Interface Features figure.
Updated photo used in Components figure.
February 2009 02.5 Updated Audio Interface text section.
June 2009 02.6 Updated FPGA to SPI Flash Connections table.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Portions copyright 2005 - 2008 Gleichmann and Company Electronics GmbH.
35
5 4 3 2 1
Figure 9.
Offpage Lattice ECP2-50 FPGA VCC1V2
U0201A U0201B U0201F
BANK 0 BANK 1 DIFF BANK 2 BANK 3 POWER SUPPLY
G5 D14 BB3V3_CLK0+ F21 L25 ETH_TXCLK L12 A2
Human Interface PT2A/VREF1_0 PCLKT1_0/PT48A BB3V3_CLK0- PR2A/VREF1_2 PCLKT3_0/PR46A ETH_RXCLK VCC GND
G6 PT2B/VREF2_0 PCLKC1_0/PT48B F14 E22 PR2B/VREF2_2 PCLKC3_0/PR46B L26 L13 VCC GND A25
MEMORY_A15 E5 B12 FLASH_BYTE# H20 N21 C0203 C0204 C0205 C0206 L14 AA18
SEG_CA0# TST_ROW0 MEMORY_A18 PT3A PT49A FLASH_WP#/ACC PR5A VREF1_3/PR47A 100n 100n 100n 100n VCC GND
5 SEG_CA0# 5 TST_ROW0 E6 PT3B PT49B A12 G21 PR5B VREF2_3/PR47B N18 L15 VCC GND AA24
SEG_CA1# TST_ROW1 MEMORY_DQ1 F7 E14 SRAM_BE2# AC97_EAPD C23 M25 HPE_RESET# M11 AA3
5 SEG_CA1# SEG_A# 5 TST_ROW1 TST_ROW2 MEMORY_DQ0 PT4A PT50A PR6A PR48A ETH_MDC VCC GND
5 SEG_A# 5 TST_ROW2 E7 PT4B PT50B G14 D23 PR6B PR48B M26 M12 VCC GND AA9
SEG_B# TST_ROW3 MEMORY_DQ2 G7 C14 DAC_DIG C24 N20 GND M15 AD11
5 SEG_B# SEG_C# 5 TST_ROW3 TST_COL0 MEMORY_DQ9 PT5A PT51A MEMORY_OE# AC97_BITCLK PR7A PR49A VCC GND
5 SEG_C# 5 TST_COL0 G8 PT5B PT51B D13 B24 PR7B PR49B N19 M16 VCC GND AD16
SEG_D# TST_COL1 MEMORY_A0 C1 H15 G22 N25 ETH_MDIO N11 AD21
5 SEG_D# SEG_E# 5 TST_COL1 TST_COL2 MEMORY_A2 PT6A PT52A PR8A/RDQS8 RDQS50/PR50A ETH_CRS C0207 C0208 C0209 C0210 VCC GND
5 SEG_E# 5 TST_COL2 C2 PT6B PT52B H17 H21 PR8B PR50B N26 N16 VCC GND AD6
SEG_F# MEMORY_A6 D3 B13 FLASH_RY/BY#_B AC97_RESET# B25 R21 LED3# 100n 100n 100n 100n P11 AE1
D 5 SEG_F# SEG_G# TST_STEP MEMORY_A10 PT7A PT53A FLASH_CE# AC97_SYNC PR9A PR51A LED7# VCC GND D
5 SEG_G# 5 TST_STEP D4 PT7B PT53B A13 D24 PR9B PR51B N22 P16 VCC GND AE26
SEG_DP# MEMORY_A1 B2 A15 BB3V3_IO0 AC97_SDATA_OUT C25 P22 LED5# R11 AF2
5 SEG_DP# MEMORY_A4 PT8A PT54A BB3V3_IO2 AC97_EXT_CLK PR10A PR52A LED4# GND VCC GND
B3 PT8B PT54B C15 D25 PR10B PR52B P23 R12 VCC GND AF25
DSW0 MEMORY_A3 A3 B14 FLASH_RESET# TST_STEP E24 P19 R15 B1
LED0# 5 DSW0 DSW1 MEMORY_A7 PT9A PT55A FLASH_RY/BY#_A PR11A PR53A LED6# VCC GND
5 LED0# 5 DSW1 A4 PT9B PT55B A14 F22 PR11B PR53B P21 R16 VCC GND B26
LED1# DSW2 MEMORY_A5 C3 F15 AC97_SDATA_IN C26 R19 C0211 C0212 T12 C11
5 LED1# LED2# 5 DSW2 DSW3 MEMORY_A9 PT10A PT56A BB3V3_IO3 PR12A PR54A 100n 100n VCC GND
5 LED2# 5 DSW3 C4 PT10B PT56B D15 D26 PR12B PR54B P20 T13 VCC GND C16
LED3# MEMORY_A8 B4 B15 BB3V3_IO1 J19 R23 LED1# T14 C21
5 LED3# LED4# MEMORY_A14 PT22B PT57A BB3V3_IO4 PR13A PR55A LED0# VCC3V3 VCC GND
5 LED4# D5 PT23A PT57B A16 K19 PR13B PR55B R24 T15 VCC GND C6
LED5# LCD_REGSEL MEMORY_A13 C5 G15 G23 P25 ETH_COL GND F18
5 LED5# 5 LCD_REGSEL PT23B PT58A PR14A PR56A GND
Lattice Semiconductor
LED6# LCD_RW H9 E15 SRAM_BE3# TST_COL2 G24 P26 ETH_RXER D11 F24
5 LED6# LED7# 5 LCD_RW LCD_ENABLE MEMORY_DQ8 PT24A PT58B BB3V3_IO10 PR14B PR56B I2C_SCL1 VCCIO0 GND
5 LED7# 5 LCD_ENABLE F8 PT24B PT59A D17 H22 PR15A PR57A T21 D6 VCCIO0 GND F3
MEMORY_DQ20 F10 C17 BB3V3_IO9 LCD_ENABLE J22 R22 LED2# C0213 C0214 C0215 G9 F9
MEMORY_DQ7 PT25A PT59B BB3V3_IO5 DSW3 PR15B PR57B ETH_RXDV 100n 100n 100n VCCIO0 GND
E8 PT25B PT60A B16 E25 PR16A/RDQS16 RDQS58/PR58A R25 J12 VCCIO0 GND J13
MEMORY_A22 D7 C18 BB3V3_IO14 DSW2 E26 R26 ETH_TXEN VCC3V3 K12 J14
Clock / Reset MEMORY_A21 PT26A PT60B BB3V3_IO8 PR16B PR58B I2C_SDA1 VCCIO0 GND
C7 PT26B PT61A B17 L19 PR17A PR59A T22 GND J21
MEMORY_A12 B5 A17 BB3V3_IO7 SEG_CA1# K20 T20 GND D16 J6
HPE_RESET# I2C_SDA1 MEMORY_A11 PT27A PT61B DSW1 PR17B PR59B VCCIO1 GND
3,6 HPE_RESET# 6 I2C_SDA1 A5 PT27B PT62A H18 F25 PR18A RLM0_GDLLC_IN_A/PR60A T26 D21 VCCIO1 GND K10
I2C_SCL1 H10 F16 DSW0 F26 T25 C0216 C0217 C0218 G18 K11
HPE_RESOUT# 6 I2C_SCL1 CLK_FPGA MEMORY_DQ21 PT28A PT62B TST_COL1 PR18B RLM0_GDLLC_IN_A/PR60B 100n 100n 100n VCCIO1 GND
6,7,8,9 HPE_RESOUT# 6 CLK_FPGA G10 PT28B PT63A G16 G25 PR19A RLM0_GDLLT_FB_A/PR61A U20 J15 VCCIO1 GND K13
MEMORY_DQ13 D9 E16 BB3V3_IO6 TST_COL0 G26 T19 VCC3V3 K15 K14
MEMORY_DQ14 PT29A PT63B BB3V3_IO12 TST_ROW3 PR19B RLM0_GDLLC_FB_A/PR61B CLK_FPGA VCCIO1 GND
E9 PT29B PT64A A18 H23 PR23A RLM0_GPLLT_IN_A/PR63A U25 GND K16
MEMORY_DQ19 E10 B18 BB3V3_IO13 TST_ROW2 H24 U24 GND F23 K17
RS232 MEMORY_DQ25 PT30A PT64B BB3V3_IO15 TST_ROW1 PR23B RLM0_GPLLC_IN_A/PR63B VCCIO2 GND
F11 PT30B PT65A D18 H25 PR24A/RDQS24 RLM0_GPLLT_FB_A/PR64A U23 J20 VCCIO2 GND L10
MEMORY_DQ5 C8 E17 BB3V3_IO11 TST_ROW0 H26 U22 C0219 C0220 C0221 L23 L11
RS_TXD_LVTTL RS_RXD_LVTTL MEMORY_DQ6 PT31A PT65B BB3V3_IO17 PR24B RLM0_GPLLC_FB_A/PR64B ETH_TXER 100n 100n 100n VCCIO2 GND
7 RS_TXD_LVTTL 7 RS_RXD_LVTTL D8 PT31B PT66A A19 K23 PR25A/RUM0_SPLLT_IN_A PR65A U26 M17 VCCIO2 GND L16
RS_RTS_LVTTL RS_CTS_LVTTL MEMORY_A17 B6 A20 MACHXO_IO0 J23 V26 ETH_TXD0 VCC3V3 M18 L17
7 RS_RTS_LVTTL 7 RS_CTS_LVTTL MEMORY_A16 PT32A PT66B RS_RXD_LVTTL PR25B/RUM0_SPLLC_IN_A PR65B ETH_TXD1 VCCIO2 GND
A6 PT32B PT67A F17 J25 PR26A/RUM0_SPLLT_FB_A PR66A V25 GND L24
MEMORY_DQ26 G11 G19 RS_CTS_LVTTL J26 V24 ETH_TXD2 GND AA23 L3
PT33A PT67B BB3V3_IO16 LCD_RW PR26B/RUM0_SPLLC_FB_A PR66B ETH_RXD2 VCCIO3 GND
H11 PT33B PT68A E18 J24 PR37A RDQS67/PR67A W26 R17 VCCIO3 GND M13
USB MEMORY_DQ18 D10 G17 LCD_REGSEL K24 W25 ETH_RXD3 C0222 C0223 C0224 R18 M14
MEMORY_DQ30 PT34A PT68B BB3V3_IO18 SEG_D# PR37B PR67B 100n 100n 100n VCCIO3 GND
F12 PT34B PT69A B19 M21 PR38A PR68A U19 T23 VCCIO3 GND N10
USB_GPIO[28:0] MEMORY_A20 B7 D19 BB3V3_IO20 SEG_CA0# K21 U21 VCC3V3 V20 N12
7 USB_GPIO[28:0] MEMORY_A19 PT35A PT69B MACHXO_IO1 SEG_C# PR38B PR68B ETH_RXD1 VCCIO3 GND
A7 PT35B PT70A B20 M22 PR39A PR69A Y26 GND N13
USB_MISO USB_PWEN0 MEMORY_DQ12 C9 B21 MACHXO_IO6 SEG_F# L22 AA26 ETH_RXD0 GND AC16 N14
7 USB_MISO USB_SSI# 7 USB_PWEN0 USB_OC0# MEMORY_DQ24 PT36A PT70B BB3V3_IO19 PR39B PR69B ETH_TXD3 VCCIO4 GND
7 USB_SSI# 7 USB_OC0# E11 PT36B PT71A C19 M19 PR40A PR70A V23 AC21 VCCIO4 GND N15
USB_SCK USB_PWEN1 MEMORY_DQ4 B8 E19 BB3V3_IO21 SEG_E# M20 W24 ETH_MDINTR# C0225 C0226 C0227 U15 N17
7 USB_SCK USB_MOSI 7 USB_PWEN1 USB_OC1# MEMORY_DQ3 PT37A PT71B MACHXO_IO5 RS_RTS_LVTTL PR40B PR70B 100n 100n 100n VCCIO4 GND
7 USB_MOSI 7 USB_OC1# A8 PT37B PT74A A21 K25 PR41A/RDQS41 V15 VCCIO4 GND P10
USB_TXD USB_PWEN2 MEMORY_DQ31 G12 A22 MACHXO_IO8 RS_TXD_LVTTL K26 VCC2V5 Y18 P12
7 USB_TXD USB_RXD 7 USB_PWEN2 USB_OC2# MEMORY_DQ29 PT38A PT74B MACHXO_IO3 SEG_B# PR41B VCCIO4 GND
7 USB_RXD 7 USB_OC2# E12 PT38B PT75A D20 N23 PR42A GND P13
USB_RTS MEMORY_DQ11 B9 C20 MACHXO_IO2 SEG_A# M24 GND AC11 P14
C 7 USB_RTS USB_CTS MEMORY_DQ10 PT39A PT75B MACHXO_IO13 SEG_DP# PR42B VCCIO5 GND C
7 USB_CTS A9 PT39B PT76A B23 K22 PR43A AC6 VCCIO5 GND P15
H12 B22 MACHXO_IO9 SEG_G# L21 C0228 C0229 C0230 U12 P17
SRAM_BE1# PT40A PT76B MACHXO_IO4 PR43B 100n 100n 100n VCCIO5 GND
G13 PT40B PT77A E20 M23 PR44A/PCLKT2_0 V12 VCCIO5 GND R13
MEMORY_DQ17 C10 C22 MACHXO_IO10 N24 VCC2V5 Y9 R14
Ethernet MEMORY_DQ27 PT41A PT77B PR44B/PCLKC2_0 VCCIO5 GND
C12 PT41B PT78A F19 GND T10
MEMORY_DQ16 B10 E21 MACHXO_IO7 ECP2-50-672BGA GND AA4 T11
ETH_TXER ETH_RXER MEMORY_DQ15 PT42A PT78B MACHXO_IO12 VCCIO6 GND
8 ETH_TXER 8 ETH_RXER A10 PT42B PT79A A23 R10 VCCIO6 GND T16
ETH_TXD3 ETH_RXD3 SRAM_BE0# F13 A24 MACHXO_IO15 C0231 C0232 C0233 R9 T17
8 ETH_TXD3 ETH_TXD2 8 ETH_RXD3 ETH_RXD2 MEMORY_DQ28 PT43A PT79B 100n 100n 100n VCCIO6 GND
8 ETH_TXD2 8 ETH_RXD2 D12 PT43B PT80A H19 T4 VCCIO6 GND T24
ETH_TXD1 ETH_RXD1 SRAM_CE# E13 F20 VCC3V3 V7 T3
8 ETH_TXD1 ETH_TXD0 8 ETH_RXD1 ETH_RXD0 MEMORY_WE# PT44A PT80B VCC1V2 VCC2V5 VCC3V3 VCCIO6 GND
8 ETH_TXD0 8 ETH_RXD0 C13 PT44B PT81A J18 GND U10
MEMORY_DQ23 B11 G20 GND F4 U11
ETH_TXEN MEMORY_DQ22 PT45A PT81B MACHXO_IO11 VCCIO7 GND
A11 D22 J7 U13
1
1
1
1
8 ETH_TXEN ETH_TXCLK MACHXO_CLK0 PT45B VREF1_1/PT82A MACHXO_IO14 C0234 C0235 C0236 VCCIO7 GND
8 ETH_TXCLK H13 PT46A/PCLKT0_0 VREF2_1/PT82B E23 L4 VCCIO7 GND U14
MACHXO_CLK1 H14 + C0238 C0239 + C0240 C0241 + C0242 + C0243 C0244 C0245 100n 100n 100n M10 U16
PT46B/PCLKC0_0 XRES 4u70 1n00 4u70 1n00 4u70 4u70 1n00 1n00 VCC3V3 VCCIO7 GND
XRES H16 M9 VCCIO7 GND U17
ETH_RXCLK ETH_MDINTR# V13
2
2
2
2
2
8 ETH_RXCLK ETH_RXDV 8 ETH_MDINTR# ECP2-50-672BGA GND GND
8 ETH_RXDV AE25 VCCIO8 GND V14
ETH_MDC R0202 GND GND GND V18 V21
ETH_CRS 8 ETH_MDC ETH_MDIO 10K0 C0237 VCCIO8 GND
8 ETH_CRS 8 ETH_MDIO GND V6
ETH_COL 1% 100n
8 ETH_COL ECP2-50-672BGA
36
GND GND
Expansion Connectors and Prototyping Area U0201C GND U0201D
Appendix A. Board Version 1 Schematic
BANK 4 BANK 5 LVDS BANK 6 BANK 7

EXPCON_IO[45:0] BB3V3_IO[21:0] CLK_FPGA AD15 AE3 SATA_X1D0+ M4 D2
9 EXPCON_IO[45:0] 9 BB3V3_IO[21:0] PB49A/PCLKT4_0 VREF2_5/PB2A DDR_VREF SATA_X1D0- PL46A/PCLKT6_0 VREF2_7/PL2A CARDSEL#
AC15 PB49B/PCLKC4_0 VREF1_5/PB2B AF3 M5 PL46B/PCLKC6_0 VREF1_7/PL2B D1
CARDSEL# BB3V3_CLK0+ USB_GPIO28 AE13 AC4 DDR_DQ15 N7 F6 EXPCON_IO41
1
9 CARDSEL# EXPCON_CLKIN 9 BB3V3_CLK0+ BB3V3_CLK0- USB_GPIO27 PB50A PB3A DDR_DQ14 C0201 DDR_VREF PL47A/VREF2_6 PL5A EXPCON_IO40
9 EXPCON_CLKIN 9 BB3V3_CLK0- AF13 PB50B PB3B AD4 P9 PL47B/VREF1_6 PL5B F5
EXPCON_CLKOUT R0201 USB_GPIO20 AB17 AE4 DDR_DQ13 100n DDR_DQ29 N3 E4 EXPCON_IO45
9 EXPCON_CLKOUT 0R00 PB51A/BDQS51 PB4A DDR_DQ12 C0202 DDR_DQ30 PL48A PL6A EXPCON_IO44
Y15 PB51B PB4B AF4 N4 PL48B PL6B E3
USB_GPIO26 AE14 V9 100n DDR_DQ31 N5 E2 EXPCON_IO43
SATA_X1D0+ SATA_X2D0+ USB_GPIO25 PB52A PB5A GND PL49A PL7A EXPCON_IO42
AF14 W9 P7 E1
2
9 SATA_X1D0+ SATA_X1D0- 9 SATA_X2D0+ SATA_X2D0- USB_OC0# PB52B PB5B DDR_DQS1 DDR_DQS3 PL49B PL7B EXPCON_IO31
9 SATA_X1D0- 9 SATA_X2D0- AA16 PB53A BDQS6/PB6A AA6 T1 PL50A/LDQS50 LDQS8/PL8A H6
SATA_X1D1+ SATA_X2D1+ W15 AB6 DDR_DM1 GND DDR_DM3 T2 H5 EXPCON_IO30
9 SATA_X1D1+ SATA_X1D1- 9 SATA_X2D1+ SATA_X2D1- GND USB_GPIO19 PB53B PB6B DDR_DQ11 PL50B PL8B EXPCON_IO39
9 SATA_X1D1- 9 SATA_X2D1- AC17 PB54A PB7A AC5 P8 PL51A PL9A F2 ADC
USB_MOSI AB16 AD5 DDR_DQ10 DDR_DQ28 P6 F1 EXPCON_IO38
USB_GPIO24 PB54B PB7B DDR_DQ27 PL51B PL9B EXPCON_IO33
AE15 PB55A PB8A AA7 P5 PL52A PL10A H8
USB_GPIO23 AF15 AB7 DDR_DQ26 P4 J9 EXPCON_IO25 X22
USB_GPIO22 PB55B PB8B DDR_DQ9 DDR_DQ25 PL52B PL10B EXPCON_IO37 VCC1V2 optional
AE16 PB56A PB9A AE5 U1 PL53A PL11A G4
B USB_GPIO21 AF16 AF5 DDR_DQ8 LVDS DDR_DQ24 V1 G3 EXPCON_IO36 A0201 B
Audio Codec USB_PWEN1 PB56B PB9B DDR_BA1 SATA_X1D1+ PL53B PL11B EXPCON_IO32 Jumper C0249 nb
Y16 AC7 P3 H7
2
1
USB_GPIO15 PB57A PB10A DDR_BA0 SATA_X1D1- PL54A PL12A EXPCON_IO24

AB18 PB57B PB10B AD7 R3 PL54B PL12B J8
AC97_BITCLK AC97_RESET# USB_GPIO18 AD17 W10 R4 G2 EXPCON_IO35
2
10 AC97_BITCLK AC97_SDATA_OUT 10 AC97_RESET# AC97_EXT_CLK USB_GPIO13 PB58A PB20A LVDS PL55A PL13A EXPCON_IO34 C0248 nb
10 AC97_SDATA_OUT 10 AC97_EXT_CLK AD18 PB58B PB20B Y10 U2 PL55B PL13B G1
AC97_SDATA_IN AC97_EAPD USB_GPIO14 AC18 W11 SATA_X2D1+ V2 H3 EXPCON_IO28 FB0201
10 AC97_SDATA_IN AC97_SYNC 10 AC97_EAPD USB_GPIO7 PB59A PB21A SATA_X2D1- PL56A PL14A EXPCON_IO29 BLM18BD601SN1
10 AC97_SYNC AD19 PB59B PB21B AA10 W2 PL56B PL14B H4
USB_GPIO8 AC19 AC8 DDR_DQ4 T6 J5 EXPCON_IO23 C0247 nb
1
USB_GPIO17 PB60A/BDQS60 PB22A DDR_DQ3 PL57A PL15A EXPCON_IO22 LVDS 1

AE17 PB60B PB22B AD8 R5 PL57B PL15B J4
USB_GPIO9 AB19 AB8 DDR_DQ5 R6 J3 EXPCON_IO21 ADC+
USB_GPIO6 PB61A PB23A DDR_A13 PL58A/LDQS58 LDQS16/PL16A EXPCON_IO14 ADC- C0246 3n30
AE19 PB61B PB23B AB10 R7 PL58B PL16B K4
VGA USB_GPIO16 AF17 AE6 DDR_DQS0 W1 H1 EXPCON_IO26 4
USB_GPIO12 PB62A BDQS24/PB24A DDR_DM0 PL59A PL17A EXPCON_IO27
AE18 PB62B PB24B AF6 Y2 PL59B PL17B H2
VGA_RD0 VGA_BL0 W16 AA11 DDR_CK1+ Y1 K6 EXPCON_IO16
10 VGA_RD0 VGA_RD1 10 VGA_BL0 VGA_BL1 USB_TXD PB63A PB25A DDR_DQ1 DDR_CK1- PL60A/LLM0_GDLLT_IN_A PL18A EXPCON_IO17 R0203 R0204 X1
10 VGA_RD1 10 VGA_BL1 AA17 PB63B PB25B AC9 AA2 PL60B/LLM0_GDLLC_IN_A PL18B K7
VGA_GR0 VGA_HSYNC USB_GPIO11 AF18 AB9 DDR_DQ2 T5 J1 EXPCON_IO19 ADCS 1 2 1 2 2
10 VGA_GR0 VGA_GR1 10 VGA_HSYNC VGA_VSYNC USB_GPIO5 PB64A PB26A DDR_DQ0 LVDS PL61A/LLM0_GDLLT_FB_A PL19A EXPCON_IO20
10 VGA_GR1 10 VGA_VSYNC AF19 PB64B PB26B AD9 T7 PL61B/LLM0_GDLLC_FB_D PL19B J2 1
USB_GPIO10 AA19 Y11 SATA_X2D0+ U3 K3 EXPCON_IO13 10k0 10k0
PB65A PB27A DDR_A1 SATA_X2D0- PL63A/LLM0_GPLLT_IN_A PL23A EXPCON_IO12 0,1% 0,1%
W17 PB65B PB27B AB11 U4 PL63B/LLM0_GPLLC_IN_A PL23B K2
USB_OC2# Y19 AE7 DDR_DQ7 V3 K1 EXPCON_IO11 3 2
Memory USB_PWEN0 PB66A PB28A DDR_DQ6 PL64A/LLM0_GPLLT_FB_A LDQS24/PL24A EXPCON_IO6 GND_ADC
Y17 PB66B PB28B AF7 U5 PL64B/LLM0_GPLLC_FB_A PL24B L2
VGA_HSYNC AF20 AC10 DDR_A10 V4 L1 EXPCON_CLKIN 0
MEMORY_A[22:0] MEMORY_DQ[31:0] USB_GPIO0 PB67A PB29A DDR_A0 PL65A LUM0_SPLLT_IN_A/PL25A
4 MEMORY_A[22:0] 4 MEMORY_DQ[31:0] AE20 PB67B PB29B AD10 V5 PL65B LUM0_SPLLC_IN_A/PL25B M2
USB_GPIO4 AA20 AA12 ADCS Y3 M1 EXPCON_CLKOUT
MEMORY_OE# PB68A PB30A LVDS PL66A LUM0_SPLLT_FB_A/PL26A Sternpunkt an X1
4 MEMORY_OE# W18 PB68B PB30B W12 Y4 PL66B LUM0_SPLLC_FB_A/PL26B N2
MEMORY_WE# USB_GPIO1 AD20 AB12 DDR_A2 ADC+ W3 N1 EXPCON_IO4 Place pins 0..4 near the balls of the FPGA.
4 MEMORY_WE# FLASH_CE# VGA_BL1 PB69A/BDQS69 PB31A ADC- PL67A/LDQS67 PL37A EXPCON_IO10 These pins must also be accessible for
4 FLASH_CE# AE21 PB69B PB31B Y12 W4 PL67B PL38A L8
SRAM_BE0# FLASH_RESET# VGA_VSYNC AF21 AD12 DDR_A4 AA1 K8 EXPCON_IO18 measurements instruments.
4 SRAM_BE0# SRAM_BE1# 4 FLASH_RESET# FLASH_RY/BY#_A VGA_BL0 PB70A PB32A DDR_A3 PL68A PL38B EXPCON_IO8
4 SRAM_BE1# 4 FLASH_RY/BY#_A AF22 PB70B PB32B AC12 AB1 PL68B PL39A L6
SRAM_BE2# FLASH_RY/BY#_B VGA_GR1 AE22 AC13 DDR_A6 U8 K5 EXPCON_IO15 GND_ADC GND
4 SRAM_BE2# SRAM_BE3# 4 FLASH_RY/BY#_B FLASH_WP#/ACC USB_SSI# PB74A BDQS33/PB33A PL69A PL39B EXPCON_IO9
4 SRAM_BE3# 4 FLASH_WP#/ACC AD22 PB74B PB33B AA13 U7 PL69B PL40A L7
SRAM_CE# FLASH_BYTE# VGA_GR0 AF23 AD13 DDR_A7 V8 L5 EXPCON_IO7
4 SRAM_CE# 4 FLASH_BYTE# VGA_RD1 PB75A PB34A DDR_A11 PL70A PL40B EXPCON_IO2
AE23 PB75B PB34B AC14 U6 PL70B LDQS41/PL41A P1
USB_MISO AD23 AE8 DDR_S1# W6 P2 EXPCON_IO3
DDR_DQ[31:0] DDR_DQS[3:0] USB_RXD PB76A PB35A DDR_S0# PL71A PL41B EXPCON_IO5
4 DDR_DQ[31:0] 4 DDR_DQS[3:0] AC23 PB76B PB35B AF8 W5 PL71B PL42A M6 DAC
USB_GPIO3 AB20 AB15 DDR_A8 DDR_DQ20 AC1 N8
DDR_DM[3:0] DDR_A[13:0] USB_GPIO2 PB77A PB36A DDR_DQ17 PL72A PL42B EXPCON_IO0 R0205 X2
4 DDR_DM[3:0] 4 DDR_A[13:0] AC20 PB77B PB36B Y13 AD1 PL72B PL43A R1
USB_CTS AB21 AE9 DDR_RAS# DDR_DQ23 Y6 R2 EXPCON_IO1 DAC_DIG 1 2 DAC_ANALOG 2
USB_SCK PB78A/BDQS78 PB37A DDR_CAS# DDR_DQ22 PL73A PL43B
AC22 PB78B PB37B AF9 Y5 PL73B PCLKT7_0/PL44A M7 1
DDR_CK0+ DDR_CK1+ W19 W13 DDR_DQ16 AE2 N9 33k2
4 DDR_CK0+ DDR_CK0- 4 DDR_CK1+ DDR_CK1- USB_PWEN2 PB79A PB38A DDR_DQ18 PL74A PCLKC7_0/PL44B HDR2
4 DDR_CK0- 4 DDR_CK1- AA21 PB79B PB38B AA14 AD2 PL74B
DDR_CKE0 DDR_CKE1 VGA_RD0 AF24 AE10 DDR_WE# DDR_DQS2 AB3 C0250 C0251 Sternpunkt an X2
A 4 DDR_CKE0 DDR_BA0 4 DDR_CKE1 DDR_BA1 HPE_RESOUT# PB80A PB39A DDR_CKE1 DDR_DM2 PL75A/LDQS75 4p70 nb_4p70
A
4 DDR_BA0 4 DDR_BA1 AE24 PB80B PB39B AF10 AB2 PL75B
USB_OC1# Y20 W14 W7
DDR_WE# DDR_S0# USB_RTS PB81A PB40A DDR_A5 PL76A
4 DDR_WE# 4 DDR_S0# AB22 PB81B PB40B AB13 W8 PL76B
DDR_RAS# DDR_S1# Y21 Y14 Y7
4 DDR_RAS# DDR_CAS# 4 DDR_S1# DDR_VREF PB82A/VREF2_4 PB41A DDR_A9 PL77A GND_DAC GND
4 DDR_CAS# 4 DDR_VREF AB23 PB82B/VREF1_4 PB41B AB14 Y8 PL77B
AE11 DDR_DQ21 AC2 GND_DAC
BDQS42/PB42A DDR_CKE0 DDR_DQ19 PL78A
PB42B AF11 AD3 PL78B
AD14 DDR_A12
MachXO PB43A ECP2-50-672BGA
PB43B AA15
AE12 DDR_CK0+
MACHXO_IO[15:0] MACHXO_CLK0 PCLKT5_0/PB44A DDR_CK0- P r o j e c t: Hpe_mini LEC2 S h e et: 02_FPGA
3 MACHXO_IO[15:0] 3 MACHXO_CLK0 PCLKC5_0/PB44B AF12
MACHXO_CLK1 Revision: R01 Last modified:
3 MACHXO_CLK1 ECP2-50-672BGA Authors: csam Monday, September 04, 2006
IF W : 17:15:04
Gleichmann Electronics
Research (Austria) GmbH & Co KG
Hauptstraße 119 Created: Saturday, April 29, 2006 10:35:32
A-4232 Hagenberg Page 2 o f 12
5 4 3 2 1
for LatticeECP2 User’s Guide
Figure 10.
5 4 3 2 1
Offpage Lattice ECP2-50 FPGA (Configuration) SPI Flash for Configuration Settings
Configuration VCC3V3 VCC3V3 VCC3V3 VCC3V3
MACHXO_IO[15:0] U0201E
2 MACHXO_IO[15:0] TP0301 BANK 8 BANK 9
2
2
1
2
CCLK JTAG_DONE AD25 AB5 VCC3V3
MACHXO_CLK0 JTAG_INIT DONE VCCJ EC_TDO R0305 R0306 R0307 R0308
2 MACHXO_CLK0 AB24 INITN TDO AA5
MACHXO_CLK1 CCLK AA22 AB4 EC_TMS 270R 270R 4k70 270R
2 MACHXO_CLK1 PROGRAM# CCLK TMS EC_TDI
V19 AA8
1
CFG0 PROGRAMN TDI EC_TCK
AC24 AC3
1
1
2
1
CLK_MACHXO R0301 CFG1 CFG0 TCK
W20
1
6 CLK_MACHXO 4k70 CFG2 CFG1 Place the 4k7 resistors LD0301 LD0302 LD0303
D AD24 CFG2 D
SISPI Y25 R0303 close to their clock VCC3V3 LED blue LED red LED yellow
DOUT BUSY/PR71A 4k70
Y24 line to keep the stub
2
EXPCON_IO[45:0] CSSPIN DOUT/CSON/PR71B
2,9 EXPCON_IO[45:0] V22 DI/PR72A
length as short as
GND TP0302 W21 PROGRAM# TP0310
2
possible.
1
DOUT WRITEN/PR77B PROGRAM#
Y22 CS1N/PR77A
AC25 R0304 T0301 1 3
HPE_RESET# SPIFASTN# CSN/PR76B GND 10K0 BSS138/SOT
2,6 HPE_RESET# AB25 PR76A/D0
AD26 SW0301
PR75B/D1 U0305 JTAG_DONE TP0308 B3FS-1012
AC26
2
USB_SCL PR75A/D2 WP# HOLD# CCLK DONE
7 USB_SCL Y23 PR74B/D3 1 HOLD CLK 16
USB_SDA SISPI 2 4
7 USB_SDA W22 PR74A/D4 2 VCC DI 15
AA25 3 14 GND T0302

PR73B/D5 NC NC BSS138/SOT GND
AB26 PR73A/D6 4 NC NC 13
SPIDO W23 5 12
PR72B/D7 FB0301 NC NC JTAG_INIT TP0309
6 NC NC 11
AUX & PLL POWER BLM18BD601SN1 CSSPIN 7 10 INIT# VCC3V3
VCCPLL SPIDO CS GND WP#
VCC3V3 J10 VCCAUX LUM0_VCCPLL M8 1 2 VCC1V2 8 Q WP 9 Drain
J11 R8 GND
VCCAUX LLM0_VCCPLL C0301 C0302 M25P16
J16 P18
1
1
1
1
VCCAUX RLM0_VCCPLL 1n00 100n M25P16-VMF6P 16Mb

J17 VCCAUX RUM0_VCCPLL L20
K18 GND SOT-23 RJ0301 RJ0303 RJ0305 RJ0307
VCCAUX nb_10K0 nb_10K0 nb_10K0 10K0
L18 VCCAUX
T18 T8 GND GND
VCCAUX LLM0_PLLCAP
U18 R20
2
2
2
2
VCCAUX RLM0_PLLCAP SPIFASTN#

V16 VCCAUX
Gate Source
V17 VCC3V3 CFG0
VCCAUX C0325 C0326 CFG1
V10 VCCAUX
V11 5n60 5n60 CFG2
VCCAUX Mode CFG2 CFG1 CFG0 SPIFAST#
T9
1
1
1
1
VCCAUX
U9 VCCAUX NC1 N6
K9 P24 GND GND C0303 C0304 SPI Normal 0 0 0 Pull-Up RJ0302 RJ0304 RJ0306 RJ0308
VCCAUX NC2 100n 100n SPI Fast 0 0 0 Pull-Down 0R00 0R00 0R00 nb_0R00
L9 VCCAUX NC3 M3
Reserved 0 0 1 X
ECP2-50-672BGA SPIm Normal 0 1 0 Pull-Up
2
2
2
2
SPIm Fast 0 1 0 Pull-Down

Reserved 0 1 1 X
GND Reserved 1 0 0 X
Slave Serial 1 0 1 X GND
Reserved 1 1 0 X
C C
rev 1.1
USB-JTAG Programmer Connector Test Adapter
Q0301 U0302
24MHz U0301 BANK 0/0,1 BANK 1/2,3
2 1 11 67 GP_INT0 MACHXO_IO0 A1 A14 MACHXO_IO15
USB Peripheral XTALIN PA0/INT0 GP_INT1 MACHXO_IO3 PT2A PR2A/PR2A
PA1/INT1 68 B3 PT2B/PT3A PR2B/PR3C C13
for Configuration 69 GP_SLOE MACHXO_IO1 A2 B14
C0339 C0340 PA2/SLOE GP_WU2 MACHXO_IO2 PT2C/PT2B PR2C/PR2B
PA3/WU2 70 A3 PT2D/PT3B PR2D/PR3D C14
12p0 12p0 71 GP_FIFOADR0 MACHXO_IO5 C4 D12
PA4/FIFOADR0 GP_FIFOADR1 MACHXO_IO4 PT2F/PT3C PR3C/PR4A
PA5/FIFOADR1 72 A4 PT3B/PT3D PR3D/PR4B D14
X3 73 GP_PKTEND MACHXO_IO6 A5 E14 GP_TXD0
GND GND PA6/PKTEND GP_SLCS# MACHXO_IO7 PT3D/PT4B PR4B/PR5A GP_RXD0
SHIELD 5 PA7/FLAGD/SLCS 74 B5 PT3E/PT5A PR4C/PR5B E13
PWR_IN 1 10 C6 F12 GP_BKPT
USBCF_M VCC XTALOUT GP_D0 MACHXO_IO9 PT3F/PT5B PR4D/PR6A GP_RXD1
2 DATA- PB0/FD0 34 B6 PT4C/PT5C PR5C/PR6B F13
TP0303 USBCF_P 3 35 GP_D1 MACHXO_IO8 A6 F14 GP_TXD1
DATA+ PB1/FD1 GP_D2 PT4D/PT5D PR5D/PR6C GP_D0 X23
4 GND PB2/FD2 36 B7 PT5A/PT6D PR6B/PR8A G14
6 37 GP_D3 MACHXO_CLK0 C8 G13 GP_D1 JTAG_TCK
37
SHIELD PB3/FD3 GP_D4 MACHXO_CLK1 PT5B/PT6F (PCLKT) PR6C/PR8B GP_D4 JTAG_TDO TP0 GND
PB4/FD4 44 B8 PT6A/PT7B PR6D/PR9A H12 TP1
USB Peripheral GP_RDY0 3 45 GP_D5 CLK_MACHXO A8 H13 GP_D3 JTAG_TMS VCC5V0
GP_RDY1 RDY0/SLRD PB5/FD5 GP_D6 USB_SDA PT6B/PT7D (PCLKT) PR7A/PR9B GP_D2 JTAG_TDI TP2 TVi0
4 RDY1/SLWR PB6/FD6 46 A9 PT7A/PT9A PR7B/PR10A H14 TP3
GP_RDY2 5 47 GP_D7 USB_SCL B9 J12 GP_D6
GNDA_CONF GNDP GP_RDY3 RDY2 PB7/FD7 PT7B/PT9B PR7C/PR10B GP_D5 TP4 TVi1
6 RDY3 C10 PT7E/PT9E PR8A/PR11A J13 TP5
GP_RDY4 7 80 GP_D8 MACHXO_IO10 B10 K12 GP_D9
GP_RDY5 RDY4 PD0/FD8 GP_D9 PT7F/PT9F PR8B/PR11B GP_D8 TP6 TVi2
8 RDY5 PD1/FD9 81 C11 PT8C/PT10C PR8C/PR12A K13 TP7
82 GP_D10 MACHXO_IO11 A11 K14 GP_D7
PD2/FD10 GP_D11 PT9A/PT10D PR8D/PR12B GP_D10 TP8 TVi3
PD3/FD11 83 C12 PT9B/PT11A PR10A/PR14A L14 TP9
95 GP_D12 MACHXO_IO13 B12 M13 GP_D11 VCC3V3_T
PD4/FD12 GP_D13 PT9C/PT10F PR10B/PR14B GP_D13 TP10 TVo0
13 NC PD5/FD13 96 B13 PT9D/PT11C PR11A/PR15A M12 TP11
14 97 GP_D14 MACHXO_IO12 A12 N13 GP_D15 VCC2V5_T
JTAG Connector NC PD6/FD14 GP_D15 MACHXO_IO14 PT9E/PT11B PR11B/PR16A GP_D12 TP12 TVo1
15 NC PD7/FD15 98 A13 PT9F/PT11D PR11C/PR15B M14 TP13
for Configuration 27 N14 GP_D14 VCC1V2_T
RESERVED GP_ADR0 PR11D/PR16B TP14 TVo2
PC0/GPIFADR0 57 A7 VCCAUX TP15
58 GP_ADR1
VCC3V3 GND PC1/GPIFADR1 GP_ADR2 TP16 TVo3
PC2/GPIFADR2 59 VCC3V3 C7 VCC VCC G12 VCC3V3
USBCF_P 17 60 GP_ADR3 B11 L12 TestContact
X4 USBCF_M DPLUS PC3/GPIFADR3 GP_ADR4 VCCIO0/VCCIO1 VCCIO1/VCCIO3
18 DMINUS PC4/GPIFADR4 61 C5 VCCIO0/VCCIO0 VCCIO1/VCCIO2 E12
B 1 62 GP_ADR5 A10 L13 GND B
JTAG_TDO PC5/GPIFADR5 GP_ADR6 GNDIO0/GNDIO1 GNDIO1/GNDIO3
2 PC6/GPIFADR6 63 B4 GNDIO0/GNDIO0 GNDIO1/GNDIO2 D13
3 JTAG_TDI 64 GP_ADR7 C9 J14
JTAG_PROG TP0304 GP_CTL0 PC7/GPIFADR7 GND GND
4 54 CTL0/FLAGA
5 JTAG_TRST GP_CTL1 55 86 GND GND
JTAG_TMS TP0305 GP_CTL2 CTL1/FLAGB PE0/T0OUT BANK 2/4,5 BANK 3/6,7
6 56 CTL2/FLAGC PE1/T1OUT 87
7 GP_CTL3 51 88 GP_SLOE M3 B1 GP_CTL5
JTAG_TCK GP_CTL4 CTL3 PE2/T2OUT GP_WU2 PB2C PL2A GP_CTL3
8 52 CTL4 PE3/RXD0OUT 89 N3 PB2D PL2B/PL3C C1
9 JTAG_DONE VCC3V3 VCC3V3 GP_CTL5 76 90 GP_FIFOADR0 M4 B2 GP_CTL4
JTAG_INIT CTL5 PE4/RXD1OUT GP_FIFOADR1 PB3B PL2C/PL2B GP_CTL2
10 PE5/INT6 91 N4 PB3C/PB4A PL2D/PL4A C2
TP0307 22 92 GP_PKTEND P5 C3 GP_CTL1
1
1
CON10 INT4 PE6/T2EX GP_ADR8 PB3D/PB4B PL3A/PL3D GP_CTL0
84 INT5 PE7/GPIFADR8 93 N6 PB4E/PB5C PL3B/PL4B D1
GND R0316 R0317 USBCF_WAKE 79 GP_INT1 M6 D3 GP_RDY0
10K0 10K0 WAKEUP GP_INT0 PB4F/PB6A PL3D/PL4C GP_RDY1
AVCC 9 VCC3V3_CONF N7 PB5A/PB6F PL5A/PL6A E2
16 USB_CLK_O M7 E3 HPE_RESET#
SW0302 GP_T0 AVCC USBCF_I2C_SDA PB5B/PB7B (PCLKT)(GSRN) PL5B/PL6B GP_RDY2 VCC3V3
23 N8 F2
2
2
EC_TMS GP_T1 T0 USBCF_I2C_SCL PB5D/PB7C PL5D/PL6D GP_RDY3
A 1 24 T1 AGND 12 P8 PB6A/PB7D PL6B/PL7C F3
JTAG_TMS GPIO_TMS 2 GP_T2 25 19 GP_IFCLK M8 G1 GP_RDY4
1
C MACHXO_TMS T2 AGND USBCF_WAKE PB6B/PB7F (PCLKT) PL6C/PL7D GP_RDY5

B 3 N9 PB7A/PB9A PL6D/PL8C G2
1 GNDA_CONF JTAG_INIT M9 G3 GP_SLCS# RJ0309
CAS-120A GP_RXD0 VCC JTAG_TRST PB7B/PB9B PL7A/PL8D GP_ADR1 nb_10K0
41 RXD0 VCC 20 N10 PB7E/PB9C PL7B/PL10A H2
GP_TXD0 40 33 VCC3V3 JTAG_DONE P10 H1 GP_ADR0
TXD0 VCC GPIO_TDI PB7F/PB9D PL7C/PL10B GP_ADR2
38 P11 J1
2
JTAG_TDI GPIO_TDO MACHXO_TDI E C _ TDI GP_RXD1 VCC JTAG_PROG PB8C/PB10A PL8A/PL11B MACHXO_TSALL TP0311
43 RXD1 VCC 49 M11 PB8D/PB10B (TSALL) PL8C/PL11C J2
GP_TXD1 42 53 R0314 GPIO_TDO P12 J3 GP_ADR3 TSALL
1
JTAG_TDO GPIO_TDI MACHXO_TDO E C _ T DO TXD1 VCC 10K0 GPIO_TMS PB9C/PB10C PL9A/PL11D GP_ADR5
VCC 66 P13 PB9D/PB11C PL9B/PL12A K2
USBCF_I2C_SCL 29 78 GPIO_TCK P14 K1 GP_ADR4 RJ0310
JTAG_TCK GPIO_TCK MACHXO_TCK E C _ T CK USBCF_I2C_SDA SCL VCC PB9F/PB11D PL9C/PL12B GP_ADR6 10K0
30 85 L1
2
SDA VCC VCC3V3 PL10A/PL14A

MACHXO_TMS P3 L3 GP_ADR7
GP_BKPT MACHXO_TCK TMS PL10B/PL14B GP_ADR8
28 2 P4 M1
2
USB_CLK_O BKPT GND MACHXO_TDO TCK PL11A/PL15A GP_T1

100 21 N5 N1
1
GP_IFCLK CLKOUT GND MACHXO_TDI TDO PL11B/PL16A GP_T0

26 IFCLK GND 39 M5 TDI PL11C/PL15B M2
31 48 R0315 P1 GP_T2 GND
RD GND 4k70 MACHXO_SLEEPN PL11D/PL16B
32 WR GND 50 N12 SLEEPN
GND 65 P7 VCCAUX
75
2
GND
GND 94 VCC3V3 P6 VCC VCC H3 VCC3V3
HPE_RESET# 77 99 GND N2 D2
RESET GND VCCIO2/VCCIO5 VCCIO3/VCCIO7
M10 VCCIO2/VCCIO4 VCCIO3/VCCIO6 K3
CY7C68013A_TQFP100 P2 E1
GND GNDIO2/GNDIO5 GNDIO3/GNDIO7
N11 GNDIO2/GNDIO4 GNDIO3/GNDIO6 L2
A P9 GND GND F1 A
GND MACHXO-640/1200-132csBGA GND
VCC3V3 FB0302 VCC3V3_CONF

BLM18PG600SN1 VCC3V3
1 2
1
1
+ C0307 C0308 C0309 C0310 C0311 C0312 C0313 C0314 C0315 C0316 C0317 C0318 C0319 C0320 C0321 C0322 C0323 + C0324
2u20 100n 100n 100n 100n 100n 100n 100n 1n00 100n 100n 100n 100n 100n 100n 100n 1n00 4u70
P r o j e c t: H p e _ mini LEC2 S h e e t: 0 3 _ F P G A _ C o n f
2
2
Revision: R01 Last modified:

GND GNDA_CONF Authors: csam Monday, September 04, 2006
GND GNDA_CONF GND IF W : 17:15:09
5 4 3 2 1
Figure 11.
5 4 3 2 1
Offpage DDR SDRAM socket (32 bit data bus) Parallel Flash SRAM
VCC2V5
Series Resistors (2 x 128 Mbit organized as 8M words of 32 bits) (2 x 4 Mbit organized as 256k words of 32 bits)
DDR_DQ[31:0] U0401 RN04011 CN1j 4 JTA 22R
2 DDR_DQ[31:0] DDR_VREF SODIMM_DQ0 DDR_DQ0
5 VDDQ VREF 4 5 4
DDR_DQS[3:0] 6 3 DDR_VTT SODIMM_DQ4 6 3 DDR_DQ4
2 DDR_DQS[3:0] AVIN VSENSE SODIMM_DQ1 DDR_DQ1
7 PVIN VTT 8 7 2
DDR_DM[3:0] 2 1 SODIMM_DQ5 8 1 DDR_DQ5
2 DDR_DM[3:0] GND NC VCC3V3
DDR_A[13:0] C0401 LP2995MR C0402 C0403 RN04012 CN1j 4 JTA 22R
Flash LOW
2 DDR_A[13:0] 47u 220u 100n SODIMM_DQ2 DDR_DQ2
D 5 4 Async. SRAM LOW D
SODIMM_DQ6 6 3 DDR_DQ6
DDR_CK0+ SODIMM_DQ3 7 2 DDR_DQ3 MEMORY_A[17:0] MEMORY_DQ[15:0]
2 DDR_CK0+ DDR_CK0- SODIMM_DQ7 DDR_DQ7 MEMORY_A[22:0] MEMORY_DQ[15:0] U0404
8 1
29
43
2 DDR_CK0- GND GND U0402 MEMORY_A0 MEMORY_DQ0
1 A0 IO1 7
DDR_CK1+ R0401 22R0 MEMORY_A0 31 35 MEMORY_DQ0 MEMORY_A1 2 8 MEMORY_DQ1
2 DDR_CK1+ A0 DQ0 A1 IO2
Vio
DDR_CK1- SODIMM_DQS0 DDR_DQS0 MEMORY_A1 MEMORY_DQ1 MEMORY_A2 MEMORY_DQ2
Vcc
2 DDR_CK1- 1 2 26 A1 DQ1 37 3 A2 IO3 9
VCC2V5 VCC2V5 MEMORY_A2 25 39 MEMORY_DQ2 MEMORY_A3 4 10 MEMORY_DQ3
DDR_CKE0 R0402 22R0 MEMORY_A3 A2 DQ2 MEMORY_DQ3 MEMORY_A4 A3 IO4 MEMORY_DQ4
2 DDR_CKE0 24 A3 DQ3 41 5 A4 IO5 13
DDR_CKE1 X5A SODIMM_DM0 1 2 DDR_DM0 MEMORY_A4 23 44 MEMORY_DQ4 MEMORY_A5 18 14 MEMORY_DQ5
2 DDR_CKE1 MEMORY_A5 A4 DQ4 MEMORY_DQ5 MEMORY_A6 A5 IO6 MEMORY_DQ6
22 A5 DQ5 46 19 A6 IO7 15
DDR_BA0 DDR_VREF 1 2 DDR_VREF RN04021 CN1j 4 JTA 22R MEMORY_A6 21 48 MEMORY_DQ6 MEMORY_A7 20 16 MEMORY_DQ7
2 DDR_BA0 Vref Vref A6 A7 IO8
DDR_BA1 3 4 SODIMM_DQ8 5 4 DDR_DQ8 MEMORY_A7 20 128 Megabit DQ6 50 MEMORY_DQ7 MEMORY_A8 21 29 MEMORY_DQ8
2 DDR_BA1 SODIMM_DQ0 Vss Vss SODIMM_DQ4 SODIMM_DQ12 DDR_DQ12 MEMORY_A8 A7 (x16) DQ7 MEMORY_DQ8 MEMORY_A9 A8 IO9 MEMORY_DQ9
5 DQ0 DQ4 6 6 3 10 A8 DQ8 36 22 A9 IO10 30
DDR_WE# SODIMM_DQ1 7 8 SODIMM_DQ5 SODIMM_DQ9 7 2 DDR_DQ9 MEMORY_A9 9 38 MEMORY_DQ9 MEMORY_A10 23 31 MEMORY_DQ10
2 DDR_WE# DDR_RAS# DQ1 DQ5 SODIMM_DQ13 DDR_DQ13 MEMORY_A10 A9 DQ9 MEMORY_DQ10 MEMORY_A11 A10 IO11 MEMORY_DQ11
2 DDR_RAS# 9 Vdd Vdd 10 8 1 8 A10 DQ10 40 24 A11 IO12 32
DDR_CAS# SODIMM_DQS0 11 12 SODIMM_DM0 MEMORY_A11 7 42 MEMORY_DQ11 MEMORY_A12 25 35 MEMORY_DQ12
2 DDR_CAS# SODIMM_DQ2 DQS0 DM0 SODIMM_DQ6 RN04022 CN1j 4 JTA 22R MEMORY_A12 A11 DQ11 MEMORY_DQ12 MEMORY_A13 A12 IO13 MEMORY_DQ13
13 DQ2 DQ6 14 6 A12 DQ12 45 26 A13 IO14 36
DDR_S0# 15 16 SODIMM_DQ10 5 4 DDR_DQ10 MEMORY_A13 5 47 MEMORY_DQ13 VCC3V3 MEMORY_A14 27 37 MEMORY_DQ14
2 DDR_S0# DDR_S1# SODIMM_DQ3 Vss Vss SODIMM_DQ7 SODIMM_DQ14 DDR_DQ14 MEMORY_A14 A13 DQ13 MEMORY_DQ14 MEMORY_A15 A14 IO15 MEMORY_DQ15
2 DDR_S1# 17 DQ3 DQ7 18 6 3 4 A14 DQ14 49 42 A15 IO16 38
SODIMM_DQ8 19 20 SODIMM_DQ12 SODIMM_DQ11 7 2 DDR_DQ11 MEMORY_A15 3 51 MEMORY_DQ15 MEMORY_A16 43
DQ8 DQ12 SODIMM_DQ15 DDR_DQ15 MEMORY_A16 A15 DQ15/A-1 MEMORY_A17 A16
21 Vdd Vdd 22 8 1 54 A16 44 A17
DDR_VREF SODIMM_DQ9 23 24 SODIMM_DQ13 MEMORY_A17 19 R0421
2 DDR_VREF SODIMM_DQS1 DQ9 DQ13 SODIMM_DM1 R0403 22R0 MEMORY_A18 A17 MACRONIX 10K0 SRAM_CE#
25 DQS1 DM1 26 18 6 CS#
27 28 SODIMM_DQS1 1 2 DDR_DQS1 MEMORY_A19 11
A18 MX29LV128MBTI-90Q SRAM_BE1# 40
SODIMM_DQ10 Vss Vss SODIMM_DQ14 MEMORY_A20 A19 SRAM_BE0# UB#
29 DQ10 DQ14 30 12 A20 39 LB#
SODIMM_DQ11 31 32 SODIMM_DQ15 R0404 22R0 MEMORY_A21 15 17 FLASH_RY/BY#_A
DQ11 DQ15 SODIMM_DM1 DDR_DM1 MEMORY_A22 A21 RY/BY# FLASH_BYTE# MEMORY_OE#
33 Vdd Vdd 34 1 2 2 A22 BYTE# 53 41 OE#
MEMORY_A[22:0] SODIMM_CK0+ 35 36
2 MEMORY_A[22:0] SODIMM_CK0- CK0+ Vdd R0405 22R0 VCC3V3 MEMORY_WE#
37 CK0- Vss 38 17 WE#
MEMORY_DQ[31:0] 39 40 SODIMM_CK0+ 1 2 DDR_CK0+ FLASH_CE# 32 30
2 MEMORY_DQ[31:0] Vss Vss MEMORY_OE# CE# NC
34 OE# NC 1 11 VCC GND 12
R0406 22R0 MEMORY_WE# 13 27 33 34
MEMORY_OE# DDR_SODIMM200 SODIMM_CK0- DDR_CK0- FLASH_WP#/ACC WE# NC VCC GND
2 MEMORY_OE# 1 2 16 WP#/ACC NC 28
MEMORY_WE# FLASH_RESET# 14 55 GND
2 MEMORY_WE# RN04031 CN1j 4 JTA 22R RESET# NC K6R4016V1D-UI10
56
Vss
Vss
X5B SODIMM_DQ16 DDR_DQ16 NC SAMSUNG
5 4
FLASH_CE# SODIMM_DQ20 6 3 DDR_DQ20
2 FLASH_CE#
33
52
FLASH_RESET# SODIMM_DQ16 41 42 SODIMM_DQ20 SODIMM_DQ17 7 2 DDR_DQ17
2 FLASH_RESET# FLASH_RY/BY#_A SODIMM_DQ17 DQ16 DQ20 SODIMM_DQ21 SODIMM_DQ21 DDR_DQ21
2 FLASH_RY/BY#_A 43 DQ17 DQ21 44 8 1
FLASH_RY/BY#_B 45 46
2 FLASH_RY/BY#_B FLASH_WP#/ACC SODIMM_DQS2 Vdd Vdd SODIMM_DM2 RN04032 CN1j 4 JTA 22R
2 FLASH_WP#/ACC 47 DQS2 DM2 48
C FLASH_BYTE# SODIMM_DQ18 49 50 SODIMM_DQ22 SODIMM_DQ18 5 4 DDR_DQ18 C
2 FLASH_BYTE# DQ18 DQ22 SODIMM_DQ22 DDR_DQ22 GND
51 Vss Vss 52 6 3
SODIMM_DQ19 53 54 SODIMM_DQ23 SODIMM_DQ19 7 2 DDR_DQ19
SRAM_BE0# SODIMM_DQ24 DQ19 DQ23 SODIMM_DQ28 SODIMM_DQ23 DDR_DQ23
2 SRAM_BE0# 55 DQ24 DQ28 56 8 1
SRAM_BE1# 57 58
2 SRAM_BE1# SRAM_BE2# SODIMM_DQ25 Vdd Vdd SODIMM_DQ29 R0407 22R0
2 SRAM_BE2# 59 DQ25 DQ29 60
SRAM_BE3# SODIMM_DQS3 61 62 SODIMM_DM3 SODIMM_DQS2 1 2 DDR_DQS2
2 SRAM_BE3# SRAM_CE# DQS3 DM3
2 SRAM_CE# 63 Vss Vss 64
SODIMM_DQ26 65 66 SODIMM_DQ30 R0408 22R0 VCC3V3
SODIMM_DQ27 DQ26 DQ30 SODIMM_DQ31 SODIMM_DM2 DDR_DM2
67 DQ27 DQ31 68 1 2 Flash HIGH
69 Vdd Vdd 70
71 72 RN04041 CN1j 4 JTA 22R Async. SRAM HIGH
- Place C0401 as close as possible to the PVIN CB0/NC CB4/NC SODIMM_DQ24 DDR_DQ24
73 CB1/NC CB5/NC 74 5 4
pin 75 76 SODIMM_DQ28 6 3 DDR_DQ28 MEMORY_A[22:0] MEMORY_DQ[31:16] MEMORY_A[17:0] MEMORY_DQ[31:16]
29
43
Vss Vss SODIMM_DQ25 DDR_DQ25 U0403 U0405
- Place C0403 as close as possible to the VREF 77 78 7 2
DQS8/NC DM8/NC SODIMM_DQ29 DDR_DQ29 MEMORY_A0 MEMORY_DQ16 MEMORY_A0 MEMORY_DQ16
pin 79 CB2/NC CB6/NC 80 8 1 31 A0 DQ0 35 1 A0 IO1 7
Vio
MEMORY_A1 MEMORY_DQ17 MEMORY_A1 MEMORY_DQ17
Vcc
- Place a bulk cap (100-220 µF) capacitor at 81 Vdd Vdd 82 26 A1 DQ1 37 2 A1 IO2 8
each end of the VTT island. (C04??, C04??) 83 84 RN04042 CN1j 4 JTA 22R MEMORY_A2 25 39 MEMORY_DQ18 MEMORY_A2 3 9 MEMORY_DQ18
CB3/NC CB7/NC SODIMM_DQ26 DDR_DQ26 MEMORY_A3 A2 DQ2 MEMORY_DQ19 MEMORY_A3 A2 IO3 MEMORY_DQ19
85 NC NC 86 5 4 24 A3 DQ3 41 4 A3 IO4 10
87 88 SODIMM_DQ30 6 3 DDR_DQ30 MEMORY_A4 23 44 MEMORY_DQ20 MEMORY_A4 5 13 MEMORY_DQ20
Vss Vss SODIMM_DQ27 DDR_DQ27 MEMORY_A5 A4 DQ4 MEMORY_DQ21 MEMORY_A5 A4 IO5 MEMORY_DQ21
89 CK2+/NC Vss 90 7 2 22 A5 DQ5 46 18 A5 IO6 14
38
CK2-/NC Vdd MEMORY_A7 A6 128 Megabit DQ6 MEMORY_DQ23 MEMORY_A7 A6 IO7 MEMORY_DQ23
Parallel Termination Resistors 93 Vdd Vdd 94 20 A7 DQ7 50 20 A7 IO8 16
SODIMM_CKE1 95 96 SODIMM_CKE0 R0409 22R0 MEMORY_A8 10 (x16) 36 MEMORY_DQ24 MEMORY_A8 21 29 MEMORY_DQ24
R0413 33R0 CKE1/NC CKE0 SODIMM_DQS3 DDR_DQS3 MEMORY_A9 A8 DQ8 MEMORY_DQ25 MEMORY_A9 A8 IO9 MEMORY_DQ25
97 NC NC 98 1 2 9 A9 DQ9 38 22 A9 IO10 30
SODIMM_DQS0 1 2 SODIMM_A12 99 100 SODIMM_A11 MEMORY_A10 8 40 MEMORY_DQ26 MEMORY_A10 23 31 MEMORY_DQ26
SODIMM_A9 A12/NC A11 SODIMM_A8 R0410 22R0 MEMORY_A11 A10 DQ10 MEMORY_DQ27 MEMORY_A11 A10 IO11 MEMORY_DQ27
101 A9 A8 102 7 A11 DQ11 42 24 A11 IO12 32
R0414 33R0 103 104 SODIMM_DM3 1 2 DDR_DM3 MEMORY_A12 6 45 MEMORY_DQ28 MEMORY_A12 25 35 MEMORY_DQ28
SODIMM_DM0 SODIMM_A7 Vss Vss SODIMM_A6 MEMORY_A13 A12 DQ12 MEMORY_DQ29 VCC3V3 MEMORY_A13 A12 IO13 MEMORY_DQ29
1 2 105 A7 A6 106 5 A13 DQ13 47 26 A13 IO14 36
SODIMM_A5 107 108 SODIMM_A4 RN04051 CN1j 4 JTA 22R MEMORY_A14 4 49 MEMORY_DQ30 MEMORY_A14 27 37 MEMORY_DQ30
RN0408 CND1J 10K JTA 33R SODIMM_A3 A5 A4 SODIMM_A2 SODIMM_CKE1 DDR_CKE1 MEMORY_A15 A14 DQ14 MEMORY_DQ31 MEMORY_A15 A14 IO15 MEMORY_DQ31
109 A3 A2 110 5 4 3 A15 DQ15/A-1 51 42 A15 IO16 38
SODIMM_DQ0 1 10 DDR_VTT SODIMM_A1 111 112 SODIMM_A0 SODIMM_CKE0 6 3 DDR_CKE0 MEMORY_A16 54 MEMORY_A16 43
SODIMM_DQ1 SODIMM_DQ4 A1 A0 SODIMM_A12 DDR_A12 MEMORY_A17 A16 R0422 MEMORY_A17 A16
2 9 113 Vdd Vdd 114 7 2 19 A17 MACRONIX 44 A17
SODIMM_DQ2 3 8 SODIMM_DQ5 SODIMM_A10 115 116 SODIMM_BA1 SODIMM_A11 8 1 DDR_A11 MEMORY_A18 18 10K0
SODIMM_DQ3 SODIMM_DQ6 SODIMM_BA0 A10/AP BA1 SODIMM_RAS# MEMORY_A19 A18 MX29LV128MBTI-90Q SRAM_CE#
4 7 117 BA0 RAS# 118 11 A19 6 CS#
DDR_VTT 5 6 SODIMM_DQ7 SODIMM_WE# 119 120 SODIMM_CAS# RN04052 CN1j 4 JTA 22R MEMORY_A20 12 SRAM_BE3# 40
SODIMM_S0# WE# CAS# SODIMM_S1# SODIMM_A9 DDR_A9 MEMORY_A21 A20 FLASH_RY/BY#_B SRAM_BE2# UB#
121 S0# S1#/NC 122 5 4 15 A21 RY/BY# 17 39 LB#
R0415 33R0 SODIMM_A13 123 124 SODIMM_A8 6 3 DDR_A8 MEMORY_A22 2 53 FLASH_BYTE#
SODIMM_DQS1 A13/NC NC SODIMM_A7 DDR_A7 A22 BYTE# MEMORY_OE#
1 2 125 Vss Vss 126 7 2 41 OE#
127 128 SODIMM_A6 8 1 DDR_A6
R0416 33R0 DQ32 DQ36 FLASH_CE# VCC3V3 MEMORY_WE#
129 DQ33 DQ37 130 32 CE# NC 30 17 WE#
B SODIMM_DM1 1 2 131 132 RN04061 CN1j 4 JTA 22R MEMORY_OE# 34 1 B
Vdd Vdd SODIMM_A5 DDR_A5 MEMORY_WE# OE# NC
133 DQS4 DM4 134 5 4 13 WE# NC 27 11 VCC GND 12
RN0409 CND1J 10K JTA 33R 135 136 SODIMM_A4 6 3 DDR_A4 FLASH_WP#/ACC 16 28 33 34
SODIMM_DQ8 DDR_VTT DQ34 DQ38 SODIMM_A3 DDR_A3 FLASH_RESET# WP#/ACC NC VCC GND
1 10 137 Vss Vss 138 7 2 14 RESET# NC 55
SODIMM_DQ9 2 9 SODIMM_DQ12 139 140 SODIMM_A2 8 1 DDR_A2 56 GND
Vss
Vss
SODIMM_DQ10 SODIMM_DQ13 DQ35 DQ39 NC K6R4016V1D-UI10

3 8 141 DQ40 DQ44 142
SODIMM_DQ11 4 7 SODIMM_DQ14 143 144 RN04062 CN1j 4 JTA 22R SAMSUNG
Vdd Vdd
33
52
DDR_VTT 5 6 SODIMM_DQ15 145 146 SODIMM_A1 5 4 DDR_A1

DQ41 DQ45 SODIMM_A0 DDR_A0
147 DQS5 DM5 148 6 3
R0417 33R0 149 150 SODIMM_A10 7 2 DDR_A10
SODIMM_DQS2 Vss Vss SODIMM_BA1 DDR_BA1
1 2 151 DQ42 DQ46 152 8 1
153 DQ43 DQ47 154
R0418 33R0 155 156 RN04071 CN1j 4 JTA 22R GND
SODIMM_DM2 Vdd Vdd SODIMM_CK1- SODIMM_BA0 DDR_BA0
1 2 157 Vdd CK1- 158 5 4
159 160 SODIMM_CK1+ SODIMM_RAS# 6 3 DDR_RAS#
RN0410 CND1J 10K JTA 33R Vss CK1+ SODIMM_WE# DDR_WE#
161 Vss Vss 162 7 2
SODIMM_DQ16 1 10 DDR_VTT 163 164 SODIMM_CAS# 8 1 DDR_CAS#
SODIMM_DQ17 SODIMM_DQ20 DQ48 DQ52
2 9 165 DQ49 DQ53 166
SODIMM_DQ18 3 8 SODIMM_DQ21 167 168 RN04072 CN1j 4 JTA 22R
SODIMM_DQ19 SODIMM_DQ22 Vdd Vdd SODIMM_S0# DDR_S0#
4 7 169 DQS6 DM6 170 5 4
DDR_VTT 5 6 SODIMM_DQ23 171 172 SODIMM_S1# 6 3 DDR_S1# VCC3V3 VCC3V3
173 Vss Vss 174 7 2
R0419 33R0 175 176 8 1
SODIMM_DQS3 DQ51 DQ55
1 2 177 DQ56 DQ60 178
179 180 R0411 22R0
R0420 33R0 Vdd Vdd SODIMM_CK1- DDR_CK1-
181 182 1 2
1
1
1
1
1
1
1
1
SODIMM_DM3 DQ57 DQ61

1 2 183 DQS7 DM7 184
185 186 R0412 22R0 C0404 C0405 C0406 C0407 C0408 C0409 C0410 C0411
RN0411 CND1J 10K JTA 33R Vss Vss SODIMM_CK1+ DDR_CK1+ 4u70 100n 4u70 100n 4u70 100n 4u70 100n
187 188 1 2
2
2
2
2
2
2
2
2
SODIMM_DQ24 DDR_VTT DQ58 DQ62

1 10 189 DQ59 DQ63 190
SODIMM_DQ25 2 9 SODIMM_DQ28 191 192
SODIMM_DQ26 SODIMM_DQ29 Vdd Vdd
3 8 193 SDA SA0 194
DDR_VTT SODIMM_DQ31 SCL SA1 GND GND
5 6 197 Vddspd SA2 198
199 Vddid NC 200
RN0412 CND1J 10K JTA 33R
SODIMM_CKE1 1 10 DDR_VTT
SODIMM_A12 2 9 SODIMM_CKE0 DDR_SODIMM200
SODIMM_A9 3 8 SODIMM_A11 GND GND
SODIMM_A7 4 7 SODIMM_A8
DDR_VTT 5 6 SODIMM_A6
A RN0413 CND1J 10K JTA 33R
A
SODIMM_A5 1 10 DDR_VTT DDR_VTT DDR_VTT DDR_VREF
SODIMM_A10 4 7 SODIMM_A0 C0416 C0417 C0418 C0419 C0420 C0421 C0422 C0414 C0415 C0412 C0413
DDR_VTT 5 6 SODIMM_BA1 220u 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

SODIMM_BA0 1 10 DDR_VTT
SODIMM_WE# 2 9 SODIMM_RAS# GND GND GND
SODIMM_S0# 3 8 SODIMM_CAS# P r o j e c t: H p e _ m in i L E C 2 S h e e t: 0 4 _ M e m o ry
SODIMM_A13 4 7 SODIMM_S1# Revision: R01 Last modified:
DDR_VTT 5 6 Authors: csam Monday, September 04, 2006
IF W : 17:15:10
Hauptstraße 119 Created: Friday, September 24, 2004 12:36:34
5 4 3 2 1
Figure 12.
5 4 3 2 1
VCC3V3
Offpage 8x LED Single Step VCC3V3
2
2
2
2
2
2
2
2
VCC3V3
R0501 R0502 R0503 R0504 R0505 R0506 R0507 R0508
SEG_CA0# Key R0509
2 SEG_CA0# SEG_CA1# 330R 330R 330R 330R 330R 330R 330R 330R SW0501 100K U0501
5
2 SEG_CA1# SEG_A# B3FS-1012
1
1
1
1
1
1
1
1
2 SEG_A# SEG_B#
2 SEG_B# 1 3 2
SEG_C# 4 TST_STEP
2 SEG_C# SEG_D# LD0501 LD0502 LD0503 LD0504 LD0505 LD0506 LD0507 LD0508 R0510
2 SEG_D# 1 nc
SEG_E# LED red LED red LED red LED red LED red LED red LED red LED red 100K C0501
2 SEG_E# SEG_F# 100n
3
2 SEG_F# SEG_G# 2 4 74AHC1G14_SOT353
D 2 SEG_G# SEG_DP#
D
2 SEG_DP#
GND GND GND
LED0# LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7#
2 LED0# LED1#
2 LED1# LED2#
2 LED2# LED3#
2 LED3# LED4#
2 LED4# LED5# TP0501
2 LED5# LED6# nb_TEST POINT
2 LED6# LED7#
1
1
1
1
1
1
1
1
2 LED7#
1
TST_ROW0 TP0502 TP0503 TP0504 TP0505 TP0506 TP0507 TP0508 TP0509
2 TST_ROW0 TST_ROW1 nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT Key Matrix
2 TST_ROW1 TST_ROW2 GND
2 TST_ROW2 TST_ROW3
2 TST_ROW3 TST_COL0
2 TST_COL0 TST_COL1
2 TST_COL1 TST_COL2
2 TST_COL2
TST_STEP
2 TST_STEP
TST_COL0
TST_COL1
TST_COL2
SW0502 SW0503 SW0504

B3FS-1012 B3FS-1012 B3FS-1012
DSW0 1 3 1 3 1 3
2 DSW0 DSW1 VCC3V3
2 DSW1 DSW2
2 DSW2 DSW3 7-Segment Display
2 DSW3
2
R0511 2 4 2 4 2 4
LCD_REGSEL SEG_CA0# 2 1 SEG_CA0#_B 1 BC807-25
2 LCD_REGSEL LCD_RW Q0501
2 LCD_RW LCD_ENABLE 1K00 D0501 D0502 D0503
3
2 LCD_ENABLE MMBD4148 MMBD4148 MMBD4148
2
R0513 TST_ROW0
1
SEG_CA1# 2 1 SEG_CA1#_B 1 BC807-25
Q0502 R0512
1K00 1K00 SW0505 SW0506 SW0507
B3FS-1012 B3FS-1012 B3FS-1012
C C
2
1 3 1 3 1 3
GND
R0514
2 4 2 4 2 4
SEG_CA1#_X 3
SEG_CA0#_X
SEG_A# 2 1 SEG_A#_X
R0515 120R
10
5
SEG_B# 2 1 SEG_B#_X U0502 D0504 D0505 D0506
MMBD4148 MMBD4148 MMBD4148
120R R0516 TST_ROW1
1
SEG_C# 2 1 SEG_C#_X
C.A. D1
C.A. D2
7 R0517
R0518 120R A SW0508 SW0509 SW0510
6 B D1 D2 1K00
SEG_D# 2 1 SEG_D#_X 4 B3FS-1012 B3FS-1012 B3FS-1012
C A
1
2
D 1 3 1 3 1 3
120R R0519 3
SEG_E# SEG_E#_X E
2 1 8 F F B
9 GND
R0520 120R G G
2 DP
SEG_F# SEG_F#_X 2 4 2 4 2 4
2 1
E C
39
120R R0521
SEG_G# 2 1 SEG_G#_X D0507 D0508 D0509
D DP
R0522 120R TST_ROW2
1
SEG_DP# 2 1 SEG_DP#_X
ELD-426SYGWA/S530-E2 R0523
120R 1K00 SW0511 SW0512 SW0513
B3FS-1012 B3FS-1012 B3FS-1012
2
1 3 1 3 1 3
GND
2 4 2 4 2 4
VCC5V0 D0510 D0511 D0512

LCD Connector TST_ROW3
1
1
B R0524 R0525
B
10K0 1K00
2
2
VCC5V0
X7 GND
R0526 GND 1 2
5K LCD_CONT 3 4 LCD_REGSEL
Display LCD_RW 5 6 LCD_ENABLE
Contrast SEG_A# 7 8 SEG_B#
SEG_C# 9 10 SEG_D#
SEG_E# 11 12 SEG_F#
GND VCC5V0 SEG_G# 13 14 SEG_DP#
15 16 VCC3V3
CON16A 4x DIP Switch SW0514
1
2
GND RP0501
DSW0 1 8
DSW1 2 7
DSW2 3 6
X6 DSW3 4 5
HDR2
LCD Backlight on/off RP0502 1K0
1 8 SW DIP-4
2 7
3 6
4 5
10K0
GND
A A
P r o j e c t: H p e _ mini LEC2 S h e e t: 0 5 _ L E D _ K E Y
Authors: csam Monday, September 04, 2006
IF W : 17:15:09
5 4 3 2 1
Figure 13.
5 4 3 2 1
Offpage VCC3V3
VCC3V3
Reset Control VCC3V3 VCC5V0
R0603
CLK_FPGA 10K0
2 CLK_FPGA
CLK_ETH U0602
5
8 CLK_ETH R0601 U0601
EXPCON_OSC 27K0 8 7 CAT_RESET 2
9 EXPCON_OSC VCC RESET HPE_RESET#
4
CLK_MACHXO CAT_I2C_SCL 6 2 CAT_RESET# 1 nc
3 CLK_MACHXO X8 CAT_I2C_SDA SCL RESET
5 SDA
Ext. Reset 1 C0601 CAT_VSENSE 3 1
3
D 100n 1.25 V VSENSE VLOW 74AHC1G14_SOT353
D
2
HPE_RESET# 4
2,3 HPE_RESET# nb_HDR2 GND R0604
D0601
HPE_RESOUT# CAT1026SI-30 100K
2,7,8,9 HPE_RESOUT# GND R0602 GND
1
10K7
SW0601 3
I2C_SDA1 B3FS-1012
2 I2C_SDA1 I2C_SCL1
2 I2C_SCL1 1 3 2
GND
Reset Vth = 1.25V x (R0601+R0602)/R0602 = 4.4V
BAT54A
Button GND
2 4
GND
VCC3V3 VCC3V3
VCC3V3
1
1
R0605 R0606 R0607 R0608 R0609
10K0 nb_10K0 nb_10K0 2K7 2K7 Rp of the I2C bus
R0610 22R0
2
2
HPE_RESOUT# CAT_I2C_SCL I2C_SCL1
R0611 22R0
CAT_I2C_SDA I2C_SDA1
Rs of the I2C bus

C C
Clock Sources
VCC3V3 FB0601 VCC3V3_OSC R0612
BLM21PG331SN1D VCC3V3_OSC CLK_FPGA
1 2
40
33R0
U0603 U0604
1 4 6 3 R0613
EN VCC VDD OUT1 CLK_ETH
2 OE OUT2 5
2 3 CLK 1 7
C0602 C0603 GND CLK BUF_IN OUT3 33R0
4 GND OUT4 8
1n00 100n OSC_SMT4_25MHz
CY2304NZ_TSSOP8 R0614
GND CLK_MACHXO
VCC3V3_OSC 33R0
GND GND
TP0601 R0615
TEST POINT 1 EXPCON_OSC
C0604 CLK
100n 33R0
B GND B
A A
P r o j e c t: H p e _ mini LEC2 S h e e t: 0 6 _ C l o c k _ R e s e t
IF W : 17:15:09
5 4 3 2 1
Figure 14.
5 4 3 2 1
Offpage RS232 Interface

GND X9
5 VCC3V3
9
RS_TXD_LVTTL U0701 RS_DTP_LVTTL_X 4
2 RS_TXD_LVTTL RS_RTS_LVTTL RS_TXD_LVTTL RS_CTS_LVTTL_X
2 RS_RTS_LVTTL 11 T1IN T1OUT 14 8
RS_RXD_LVTTL RS_RTS_LVTTL 10 7 RS_TXD_LVTTL_X 3 C0701 C0702
2 RS_RXD_LVTTL RS_CTS_LVTTL T2IN T2OUT RS_RTS_LVTTL_X 100n 10u0
2 RS_CTS_LVTTL 7
RS_RXD_LVTTL 12 13 RS_RXD_LVTTL_X 2
RS_CTS_LVTTL R1OUT R1IN
9 R2OUT R2IN 8 6
1
VCC3V3 R0702 0R00
USB_GPIO[28:0] 1 16 1 2 RS_DSP_LVTTL_X CON_DSUB_9M GND
D 2 USB_GPIO[28:0] C1+ VCC D
3 C1-
2 R0701 0R00
USB_MISO V+ RS_DCD_LVTTL_X
2 USB_MISO 4 C2+ GND 15 1 2
USB_SSI# 5 6
2 USB_SSI# USB_SCK C2- V-
2 USB_SCK USB_MOSI C0703 C0704 MAX3232/TSSOP C0705 C0706
2 USB_MOSI USB_TXD 100n 100n 100n 100n
2 USB_TXD USB_RXD
2 USB_RXD USB_RTS
2 USB_RTS USB_CTS
2 USB_CTS
USB_PWEN0 GND
2 USB_PWEN0 USB_OC0#
2 USB_OC0# USB_PWEN1
2 USB_OC2#
USB_SCL
3 USB_SCL USB_SDA
3 USB_SDA
USB Controller
HPE_RESOUT#
2,6,8,9 HPE_RESOUT# VCC5V0
U0702 USB_GPIO[28:0]
EXT MEMORY GPIO
FB0701
99 94 USB_GPIO0
A0/BEL GPIO0/D0 USB_GPIO1 VCC3V3 C0707 USB_VBUS0 USB_VBUS0_X
1 A1 GPIO1/D1 93 1 2
2 92 USB_GPIO2 1u00
A2 GPIO2/D2 USB_GPIO3 USB_OTG_VBUS
3 A3 GPIO3/D3 91 BLM21PG331SN1D
7 90 USB_GPIO4 + C0708 C0709
1
1
1
A4 GPIO4/D4 USB_GPIO5 U0703 100u 100n

8 A5 GPIO5/D5 89
VCC3V3 17 87 USB_GPIO6 R0704 R0705 GNDA_USB 7 C0726 FB0705 1500mA
A6 GPIO6/D6 USB_GPIO7 10K0 10K0 IN 4u70
20 A7 GPIO7/D7 86 BLM21PG331SN1D
24 66 USB_GPIO8 330 Ohm @ 100 MHz
2
2
A8 GPIO8/MISO/D8 USB_GPIO9 USB_PWEN0
25 65 1 8
2
2
R0703 A9 GPIO9/SSI/D9 USB_GPIO10 USB_OC0# ENA OUTA X10
27 A10 GPIO10/SCK/D10 61 2 FLGA
47K0 30 60 USB_GPIO11 GNDA_USB GND USB_OTG_VBUS_X 1 6
A11 GPIO11/MOSI/D11 FB0702 VBUS SH1
C 31 59 USB_GPIO12 USB_OC1# 3 USB_OTG_DM1A 2 7 C
A12 GPIO12/D12 USB_GPIO13 USB_PWEN1 FLGB USB_VBUS1 USB_VBUS1_X USB_OTG_DP1A D- SH2
32 58 4 5 1 2 3
1
A13 GPIO13/D13 USB_GPIO14 ENB OUTB USB_OTG_ID D+ USB OTG
33 A14 GPIO14/D14 57 4 ID SH3 8
USB_A15 38 56 USB_GPIO15 5 9
A15/CLKSEL GPIO15/SSI/D15 USB_GPIO16 + C0710 C0711 BLM21PG331SN1D GND SH4
97 A16 GPIO16/TXD/I_A0 55 6 GND
95 54 USB_GPIO17 100u 100n C0727 USB miniAB 440479-1
A17 GPIO17/RXD/I_A1 USB_GPIO18 SP2526-1EN nb_100n
96 A18 GPIO18/RTS/I_A2 53
52 USB_GPIO19 GNDA_USB
GPIO19/CS0/H_A0 USB_GPIO20
83 D0 GPIO20/CS1/H_A1 50
82 49 USB_GPIO21 VCC3V3
D1 GPIO21/nCS USB_GPIO22 VCC5V0 GND
81 D2 GPIO22/WR/IOW 48
80 47 USB_GPIO23 GNDA_USB X11A
1
D3 GPIO23/RD/IOR USB_GPIO24
79 D4 GPIO24/INT/IORDY 46 SHIELD 13
78 45 USB_GPIO25 R0706 USB_VBUS0_X 1A
D5 GPIO25 USB_GPIO26 15K0 USB_DM1B VCC
77 D6 GPIO26/CTS/PWM3 44 2A DATA- USB HOST
76 43 USB_GPIO27 VCC3V3 C0712 USB_DP1B 3A
USB_MISO D7 GPIO27/RX USB_GPIO28 1u00 DATA+
74 42 4A
2
USB_SSI# D8/MISO GPIO28/TX USB_OTG_ID GND
73 D9/SSI GPIO29/OTGID 41 SHIELD 14
USB_SCK 72 40 USB_SCL
1
USB_MOSI D10/SCK GPIO30/SCL USB_SDA U0704 USB_TypeA/Host
71 D11/MOSI GPIO31/SDA 39
USB_TXD 70 R0707 GNDA_USB 7
USB_RXD D12/TXD 10K0 IN
69 FB0703
41
USB_RTS D13/RXD X11B
68 D14/RTS
USB_CTS 67 USB_PWEN2 1 8 USB_VBUS2 1 2 USB_VBUS2_X 15
2
D15/CTS USB_OC2# ENA OUTA USB_VBUS1_X SHIELD
2 FLGA 1B VCC
EXT MEMORY CONTROL USB_DM2A 2B
+ C0713 C0714 BLM21PG331SN1D USB_DP2A DATA- USB HOST
98 BEH MEMSEL 34 3 FLGB 3B DATA+
64 35 4 5 100u 100n 4B
WR ROMSEL ENB OUTB GND
62 RD RAMSEL 36 SHIELD 16
USB PORTS 6 USB_TypeA/Host
USB_OTG_DM1A USB_DM2A GND
22 DM1A DM2A 9
USB_OTG_DP1A 23 10 USB_DP2A SP2526-1EN
USB_DM1B DP1A DP2A USB_DM2B GNDA_USB GNDA_USB X11C
18 DM1B DM2B 4
USB_DP1B 19 5 USB_DP2B
DP1B DP2B USB_VBUS2_X 1C VCC
VCC3V3_USB 21 6 USB_DM2B 2C
AVCC AGND USB_DP2B DATA- USB HOST
3C DATA+
D0701 CHARGE PUMP GNDA_USB VCC3V3 VCC3V3 4C
BAT54S USB_OTG_VBUS GND
11 OTGVBUS BOOSTVCC 16 VCC3V3
2 1 13 15
1
1
CSWITCHA BOOSTGND USB_TypeA/Host

B 12 CSWITCHB VSWITCH 14 B
GND RJ0701 RJ0703
3
2
2
RESET / CLOCK nb_10K0 nb_10K0 GNDA_USB GNDP
C0724 HPE_RESOUT# 85 29 USB_XTALIN Q0701 R0708
100n C0725 100n RESET XTALIN USB_XTALOUT nb_1M00
84 28 CRYSTAL_12MHz
2
2
RESERVED XTALOUT USB_SCL
1
GND POWER USB_SDA
1
37 26
1
1
VCC3V3 VCC GND

63 VCC GND 51
GNDA_USB 88 75 C0715 C0716 RJ0702 RJ0704
VCC GND 22p0 22p0 0R00 0R00
GND 100
CY7C67300_TQFP100
2
2
GND
GND GND GND
GND GNDA_USB
Boot Configuration Interface GPIO31 GPIO30
VCC3V3 FB0704 VCC3V3_USB SDA SCL
BLM18PG600SN1 Host Port Interface (HPI) 0 0
1 2 High-Speed Serial (HSS) 0 1
Serial Peripheral Interface (SPI) 1 0
I2C EEPROM (Standalone Mode) 1 1
C0717 C0718 C0719 C0720 C0721 C0722 C0723
10u0 100n 100n 100n 100n 100n 1n00
GND GNDA_USB
A A
P r o j e c t: Hpe_mini LEC2 S h e et: 07_Serial_USB

IF W : 17:15:10
5 4 3 2 1
Figure 15.
5 4 3 2 1
Offpage Ethernet
VCC3V3_LAN
8
7
6
5
GND
ETH_TXER RP0801
2 ETH_TXER ETH_TXD3 10k0
2
2 ETH_TXD3 ETH_TXD2
2 ETH_TXD2 ETH_TXD1 U0801 FB0801 VCC3V3
1
2
3
4
2 ETH_TXD1 ETH_TXD0
2 ETH_TXD0 BLM11B750S
ETH_TXER 54 19
1
ETH_TXEN ETH_TXD3 TX_ER TPFOP
60
2
2 ETH_TXEN ETH_TXCLK ETH_TXD2 TXD3 U0802
2 ETH_TXCLK 59 TXD2 TPFON 20
ETH_TXD1 58 LAN_TX+ 1 12 X12 R0801
D ETH_TXD0 TXD1 TD+ TX+ 220R
D
57 TXD0 3 CT_TD CT_TX 10 13 SHIELD
ETH_RXER LAN_TX- 2 11 ETH_TX+ 1
1
2 ETH_RXER R0802 TD- TX- TX+
ETH_RXD3 ETH_TXEN 56 ETH_TX- 2 9
2
2 ETH_RXD3 ETH_RXD2 ETH_TXCLK ETH_TXCLK0 TX_EN ETH_RX+ TX- LED2+ ETH_CFG1
2 ETH_RXD2 2 1 55 TX_CLK 3 RX+ LED2- 10
ETH_RXD1 LAN_RX+ 5 8 4 R0803
2 ETH_RXD1 ETH_RXD0 22R0 C0801 270p RD+ RX+ nc 220R
2 ETH_RXD0 4 CT_RD CT_RX 9 5 nc
ETH_RXER 53 23 1 2 LAN_RX- 6 7 ETH_RX- 6 11
1
ETH_RXD3 RX_ER TPFIP VCC3V3 RD- RX- RX- LED1+ ETH_CFG3

45 RXD3 7 nc LED1- 12
ETH_RXCLK ETH_RXD2 46 24 1 2 PULSE H1112 8
2 ETH_RXCLK ETH_RXDV ETH_RXD1 RXD2 TPFIN nc
2 ETH_RXDV 47 RXD1 14 SHIELD
ETH_RXD0 48 C0802 270p
1
1
RXD0
ETH_CRS GNDP RJ-45-LED VCC3V3
2
2
1
1
1
1
2 ETH_CRS R0806
ETH_COL R0804 R0805
2 ETH_COL ETH_RXCLK ETH_RXCLK0 nb_10K0 nb_10K0 R0807 R0808 R0809 R0810 R0811 R0812
2 1 52 RX_CLK SD/TP 26
ETH_RXDV 49 49R9 49R9 49R9 49R9 49R9 49R9
2
ETH_MDINTR# 22R0 RX_DV
2
2
2
2
2
2
2 ETH_MDINTR# ETH_CRS GND R0813
63 5
1
1
ETH_MDC ETH_COL CRS TxSLEW0 220R
62 6
1
1
1
1
2 ETH_MDC ETH_MDIO COL TxSLEW1 C0803 C0804
1
1
2 ETH_MDIO CLK_ETH R0816 22K1 C0805 100n 100n R0814 R0815 LED0801
1
2
2
REFCLK/XI 10n0 49R9 49R9 LED red
17 2 1
2
2
HPE_RESOUT# RBIAS R0817 R0818
2
2
2
2
2,6,7,9 HPE_RESOUT# XO 10K0 10K0
2
CLK_ETH 38 ETH_CFG1 GND
1
1
1
6 CLK_ETH ETH_MDINTR# LED/CFG1 ETH_CFG2 ETH_CFG2
64 37
1
1
MDINT# LED/CFG2 ETH_CFG3 C0806 C0807 C0808
LED/CFG3 36
ETH_MDC 43 1n00 1n00 1n00
2
2
2
ETH_MDIO MDC C0809 2kV 2kV 2kV
42 MDIO
3 27 GND 2 1
MDDIS TDI
TDO 28
HPE_RESOUT# 4 29 220n
VCC3V3 RESET# TMS GNDP
TCK 30
39 31 GND_LAN
8
7
6
5
PWRDWN TRST
RP0802 33
1
1
1
10k0 PAUSE TxSLEW0 TxSLEW1 Slew Rate
ADDR4 16
RJ0801 RJ0803 RJ0805 VCC3V3 32 15
nb_10K0 nb_10K0 nb_10K0 SLEEP ADDR3 0 0 2.5ns
14
1
2
3
4
ADDR2 0 1 3.1ns
ADDR1 13
9 12 1 0 3.7ns
2
2
2
GND nc ADDR0 1 1 4.3ns
10 nc
C 44 nc TEST0 34 C
TEST1 35
VCC3V3
2
2
2
51 VCCD DGND 61
RJ0802 RJ0804 RJ0806 50
10K0 10K0 10K0 DGND
8 VCCIO DGND 41
VCC3V3_LAN 40 25
VCCIO DGND
18
1
1
1
DGND
21 VCCA DGND 11
22 VCCA DGND 7
GND
LXT971A
GND
VCC3V3 VCC3V3_LAN
GND GND_LAN
FB0802 C0810 C0813
BLM18PG600SN1 220n 10n0
1 2
42
1
1
2
2
GND_LAN
B B
A A
P r o j e c t: Hpe_mini LEC2 S h e et: 08_Ethernet

IF W : 17:15:10
Hauptstraße 119 Created: Tuesday, December 14, 2004 14:10:51
5 4 3 2 1
Figure 16.
5 4 3 2 1
Offpage Expansion Connector Prototyping Area (RM2.54) of FPGA

EXPCON_IO[45:0]
2 EXPCON_IO[45:0]
CARDSEL# VCC3V3
2 CARDSEL#
EXPCON_CLKIN
2 EXPCON_CLKIN EXPCON_CLKOUT BB3V3_IO[21:0]
2 EXPCON_CLKOUT BB3V3_IO[21:0]
EXPCON_OSC VCC2V5 TP0901 TP0913 TP0925 TP0937 TP0949 TP0961 TP0973 TP0985 TP0997 TP09109 TP09121 TP09133
6 EXPCON_OSC BB3V3_IO0 BB3V3_IO12
1
D HPE_RESOUT#
D
2,6,7,8 HPE_RESOUT# R0901
0R00 TP0902 TP0914 TP0926 TP0938 TP0950 TP0962 TP0974 TP0986 TP0998 TP09110 TP09122 TP09134
Pin 2 removed for coding BB3V3_IO1 BB3V3_IO13
BB3V3_IO[21:0] of expansion board
2
2 BB3V3_IO[21:0] X13
BB3V3_CLK0+ 1 2 TP0903 TP0915 TP0927 TP0939 TP0951 TP0963 TP0975 TP0987 TP0999 TP09111 TP09123 TP09135
2 BB3V3_CLK0+ BB3V3_CLK0- EXPCON_2V5 EXPCON_IO29 BB3V3_IO2 BB3V3_IO14
2 BB3V3_CLK0- 3 4
EXPCON_IO30 5 6 EXPCON_IO31
GND EXPCON_IO32 7 8 EXPCON_IO33
EXPCON_IO34 9 10 EXPCON_IO35 TP0904 TP0916 TP0928 TP0940 TP0952 TP0964 TP0976 TP0988 TP09100 TP09112 TP09124 TP09136
SATA_X1D0+ EXPCON_IO36 11 12 EXPCON_IO37 BB3V3_IO3 BB3V3_IO15

2 SATA_X1D0+ SATA_X1D0- EXPCON_IO38 EXPCON_IO39
2 SATA_X1D0- 13 14
SATA_X1D1+ EXPCON_IO40 15 16 EXPCON_IO41
2 SATA_X1D1+ SATA_X1D1- EXPCON_IO42 EXPCON_IO43 TP0905 TP0917 TP0929 TP0941 TP0953 TP0965 TP0977 TP0989 TP09101 TP09113 TP09125 TP09137
2 SATA_X1D1- 17 18
EXPCON_IO44 19 20 EXPCON_IO45 BB3V3_IO4 BB3V3_IO16
SATA_X2D0+ VCC5V0 21 22
2 SATA_X2D0+ SATA_X2D0- EXPCON_2V5
2 SATA_X2D0- 23 24
SATA_X2D1+ VCC3V3 25 26 TP0906 TP0918 TP0930 TP0942 TP0954 TP0966 TP0978 TP0990 TP09102 TP09114 TP09126 TP09138
2 SATA_X2D1+ SATA_X2D1- BB3V3_IO5 BB3V3_IO17
2 SATA_X2D1- 27 28
EXPCON_OSC 29 30
1
EXPCON_CLKIN 31 32
R0902 EXPCON_CLKOUT 33 34 TP0907 TP0919 TP0931 TP0943 TP0955 TP0967 TP0979 TP0991 TP09103 TP09115 TP09127 TP09139
0R00 35 36 BB3V3_IO6 BB3V3_IO18
37 38
EXPCON_3V3 39 40
2
HDR40 BB3V3_IO7 BB3V3_IO19
GND
X14
HPE_RESOUT# 1 2 TP0911 TP0923 TP0935 TP0947 TP0959 TP0971 TP0983 TP0995 TP09107 TP09119 TP09131 TP09143
EXPCON_IO0 3 4 EXPCON_IO1 BB3V3_IO10 BB3V3_CLK0+
EXPCON_IO2 5 6 EXPCON_IO3 DIFF
C EXPCON_IO4 7 8 EXPCON_IO5 C
EXPCON_IO8 11 12 EXPCON_IO9 BB3V3_IO11 BB3V3_CLK0-
19 20 EXPCON_3V3
EXPCON_IO16 21 22 VCC3V3
EXPCON_IO17 23 24 GND
EXPCON_IO18 25 26
1
EXPCON_IO21 29 30 R0904
EXPCON_IO22 31 32 EXPCON_IO23 10K0
EXPCON_IO24 33 34
2
EXPCON_IO27 37 38 CARDSEL#
EXPCON_IO28 39 40
HDR40
GND GND
43
Place the 0402-resistors of the LVDS termination
SATA-Connector as close as possible to the FPGA.
R0905 0R00
B 1 2 B
LVDS LVDS
2
SATA_XT1D0+ SATA_X1D0+
SATA_XT1D0- R0906 SATA_X1D0-
X15 nb_100R
R0907 0R00
1
1 LVDS 1 2
GND SATA_XT1D0+
A+ 2
3 SATA_XT1D0- R0908 0R00
A-
GND 4 1 2
5 SATA_XT1D1- LVDS LVDS
2
B- SATA_XT1D1+ SATA_XT1D1+ SATA_X1D1+
B+ 6
7 SATA_XT1D1- R0909 SATA_X1D1-
GND LVDS nb_100R
R0910 0R00
1
CON_SATA 1 2
R0911 0R00
X16 1 2
LVDS LVDS
2
1 LVDS SATA_XT2D0+ SATA_X2D0+
GND SATA_XT2D0+ SATA_XT2D0- R0912 SATA_X2D0-
A+ 2
3 SATA_XT2D0- nb_100R
A- R0913 0R00
4
1
GND SATA_XT2D1-
B- 5 1 2
6 SATA_XT2D1+
B+ R0914 0R00
GND 7
LVDS 1 2
LVDS LVDS
2
CON_SATA SATA_XT2D1+ SATA_X2D1+
nb_100R
GND_HS R0916 0R00
1
1 2
Sternpunkt X16
A A
GND GND_HS
P r o j e c t: Hpe_mini LEC2 S h e et: 09_ExpCon_ProtoArea

IF W : 17:15:10
5 4 3 2 1
Figure 17.
5 4 3 2 1
Offpage Audio Codec

X17B LC1003
NFE31PT222Z1E9
NF_R 1U 2 1
AC97_BITCLK LC1004
2 AC97_BITCLK AC97_SDATA_OUT NFE31PT222Z1E9
3
2 AC97_SDATA_OUT AC97_SDATA_IN
2 AC97_SDATA_IN 3L 4U 2 1
AC97_SYNC NF_L
2 AC97_SYNC AC97_RESET# 5U
3
2 AC97_RESET# AC97_EXT_CLK LC1001 X17A
2 AC97_EXT_CLK AC97_EAPD NFE31PT222Z1E9 Shield
2 AC97_EAPD 4
2 1 1L NF_R ST-4235-3/3-N
LC1002 Headphone / Line-out GNDA_AC
D NFE31PT222Z1E9
D
3
2 1 4L 2L
NF_L
5L
3
VGA_RD0 FB1005
2 VGA_RD0 C1005
VGA_RD1 1 Shield BLM21PG331SN1D
2 VGA_RD1
+
VGA_GR0 ST-4235-3/3-N LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND 1 2 1 2 AC97_AOUT_L
2 VGA_GR0 VGA_GR1 GNDA_AC LINE-IN PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT
2 VGA_GR1 VGA_BL0 OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE
2 VGA_BL0 VGA_BL1 ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG 1u00 R1008 C1009
2 VGA_BL1 VGA_HSYNC GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE. 47k0 1n00
2 VGA_HSYNC
VGA_VSYNC
2 VGA_VSYNC
R1002 FB1003 U1001 GNDA_AC

C1003 ANALOG
0R00 BLM21PG331SN1D FB1006
C1002
AC97_AIN_L 1 2 2 1 AC97_LINEIN_L 23 35 AC97_LINEOUT_L BLM21PG331SN1D
LINE_IN_L LINE_OUT_L
+
AC97_LINEIN_R 24 36 AC97_LINEOUT_R 1 2 1 2 AC97_AOUT_R
R1003 LINE_IN_R LINE_OUT_R
C1007 1k00 C1004 R1004 1u00 R1024
1n00 47k0 AC97_HP_OUT_L nb_0R00 1u00 R1009 C1010
100p 18 CD_L HP_OUT_L 39
19 40 AC97_HP_OUT_C TP1001 47k0 1n00
CD_GND HP_OUT_C/NC AC97_HP_OUT_R
20 CD_R HP_OUT_R 41
TP1002 VDDA5V0_AC97
GNDA_AC 21 37
MIC1 MONO_OUT GNDA_AC GNDA_AC
22 MIC2
R1005 FB1004 R1019
C1001
0R00 BLM21PG331SN1D 28 AC97_VREFOUT 10k0
AC97_AIN_R VREFOUT nb_10k0
1 2 2 1 16 VIDEO_L
+
17 27 AC97_VREF (VT1612A)
R1006 VIDEO_R REFFLT
C1006 1k00 C1008 R1007 1u00
100p 1n00 47k0 C1014 14 29 AC97_AFILT1
100n AUX_L AFILT1/NC AC97_AFILT2
15 AUX_R AFILT2/NC 30
31 AC97_AFILT3
AFILT3/NC
12 C1011
GNDA_AC GNDA_AC PC_BEEP AC97_3DFLT 22n0
3DFLT/NC 32
33 AC97_3DN
C 3DN AC97_3DP C
13 PHONE 3DP 34
R1021 100n C0603 C0603 C0805 C0805 C0603 C0603 C0603 C0603 C1206
33R0 DIGITAL INTERFACE (AD1881)
R1026 <--- AC97_BITCLK 6 48 1n00 C1021 C1022 C1023 C1024 C1025 C1026 C1027 C1012 C1013
PLL ---> AC97_EXT_CLK ---> AC97_SDATA_OUT BIT_CLK SPDIF/NC (CS4299) nb_22n0 nb_100n nb_10u0 nb_1n00 nb_1n00 nb_1n00 nb_1u00 100n 10u0
1 2 5 SDATA_OUT EAPD/NC 47
<--- AC97_SDATA_IN 8 46 47n0 100n 10u0 1u00 270p 270p 270p 10u0 (VT1612A)
0R00 ---> AC97_SYNC SDATA_IN ID1 (AD1881) (VT1612A) (VT1612A) (AD1881) (VT1612A) (VT1612A) (VT1612A) 3u30 (LM4480)
10 SYNC ID0 45
44 10n0 1u00 1u00 (CS4299)
---> AC97_RESET# HPP/NC (CS4299) (AD1881)
11 RESET NC 43
GNDA_AC
C1028 CLOCK R1025
AC97_XTL_IN 2 nb_0R00
GND GNDA_AUD XTL_IN AC97_PIN48 AC97_SPDIF_OUT
2
2
Locate under CODEC AC97_PIN47 AC97_EAPD TP1003
use 60 mil wide trace between 33p0 R1027 Q1001 AC97_XTL_OUT 3 XTL_OUT
digital and analog GND planes 1M00 nb_24.576MHz R1028 R1020
VCC3V3 0R0 POWER nb_0R00
1
VDD3V3_AC97 C1029
FB1001 1 4
1
VDD3V3_AC97 DVDD1 DVSS1
BLM18PG600SN1 9 7
DVDD2 DVSS2
1 2
R1023 GND
33p0 nb_0R00
VDDA5V0_AC97 25 26
44
C1017 C1018 C1019 GND AVDD AVSS
38 NC/AVDD AVSS/NC 42
1u00 100n 100n
AC'97 CODEC R1022
C1020 nb_0R00
nb_100n PB-Free Part:
LM4549BVHX
GND
VCC5V0
FB1002 VDDA5V0_AC97 GNDA_AC GNDA_AC
BLM18PG600SN1
1 2 Connect ANALOG GND to
GND on Plane
realized in CAMTASTIC
C1015 C1016
1u00 100n
B GNDA_AC GND B
GNDA_AC
VGA Interface
R1010 270R
VGA_RD0
R1011 270R R1012 270R X19

VGA_RD1 6
VGA_RD_X 1 11
R1013 270R 7
VGA_GR0 VGA_GR_X 2 12
8
R1014 270R R1015 270R VGA_BL_X 3 13
VGA_GR1 9
4 14
R1016 270R 10
VGA_BL0 5 15
GND
R1017 270R R1018 270R CON_DSUB_15F
VGA_BL1
VGA_VSYNC
VGA_HSYNC
A A
P r o j e c t: Hpe_mini LEC2 S h e et: 10_Audio_VGA

IF W : 17:15:09
5 4 3 2 1
Figure 18.
5 4 3 2 1
Offpage 3.3V (1A) / 1.2V (2A) DC/DC-Converter

Place the parts C1103, C1105 and C1124 VCC5V0
as close as possible to the pins of the U1101
1
C1101 C1102
10u0 100n
1
T1101A
D1101 PW_T1A_GATE 4 SI6966DQ
MBR0540LT1 max 2A VCC1V2_T VCC1V2
X20 VCC5V0
2
2
3
D D1102 C1103 GND_PWR R1102 PH1101 TP1101
D
3 VCC_KLD 1 2 100n L1101 0R025 PlaceHolder
CENTER PW_BOOST1 PW_SW1 TEST POINT
1 2 1 2 1
2 10MQ040N 1.2V
2
OPENER C1104 C1105 33u0
8
1
1 + C1106 + C1107 R1103 10u0 100n C1108 C1112
OUTSIDE 47u0 47u0 4k70 1n00 1n00 C1109 R1104 C1110 + C1111
Connect ANALOG GND to KLD-0202-A 20V 20V T1101B 180p 5K10 10u0 220u
2
GND on Plane C7343 C7343 PW_T1B_GATE 5 SI6966DQ 1% 10V 10V
1
2
GND D1103 C7343H
2
GND_PWR GND extra ANALOG GND plane GND_PWR GND_PWR GND_PWR GND R1105 10MQ040N LESR40
7
6
connected with 6Vias to C1113 5R10
1
1
GND on plane nb_10n0 GND_PWR
U1101 R1106
1
24 25 10K0
VIN BOOST1 1%
22 27 GND_PWR
2
Ext_Vcc TG1 GND_PWR
21 26 PW_SW1_L
INTVcc SW1 GND_PWR TP1102
C1114 5 23
10u0 FREQSET BG1 TEST POINT
1
28 2 VOS1 GND
FLTCPL SENSE1+
7 FCB SENSE1- 3
GND
10 4 VCC5V0 GND
3V3Out Vos1
6 18 PW_BOOST2
STBYMD BOOST2
1 RUN/SS1 TG2 16
1
15 17 C1115 C1116
1
RUN/SS2 SW2 10u0 100n
8 19 D1104 T1102A
ITH1 BG2 MBR0540LT1 PW_T2A_GATE SI6966DQ
4
11 14 max 1A VCC3V3_T VCC3V3
2
ITH2 SENSE2+
2
3
9 13 C1124 GND_PWR R1111 PH1102 TP1103
C1117 C1118 SGND SENSE2- 100n L1102 0R05 PlaceHolder
220p 220p 20 12 PW_SW2 1 2 1 2 1 TEST POINT
C PGND Vos2 3.3V C
LTC1628-SSOP28 100u0
8
2
2
C1126 C1127
2
2
GND_PWR 1n00 1n00 C1128 R1112 C1129 + C1130 R1114
R1107 R1108 T1102B 180p 47K0 10u0 220u 330R
2
C1119 C1120 C1121 C1122 15K0 C1123 15K0 PW_T2B_GATE 5 SI6966DQ 1% 10V
2
10n0 100n 100n 33p0 33p0 D1105 C7343H
1
1
R1110 10MQ040N LESR40
1
1
7
6
C1125 5R10
1
2
nb_10n0 GND_PWR
R1113
1
15K0 LD1101
GND 1% LED green
GND_PWR 3.3V PG
1
GND_PWR
PW_SW2_L
GND_PWR
GND
PW_VOS2
45
2.5V/2.6V (2A) Drill
GNDP
DRILL1101 DRILL1102
DRILL DRILL
VCC5V0 GNDP
R1115 0R033
B 1 2 B
C1131
10u0 GND
4
U1102 R1116 10R0 T1103 VCC2V5 DRILL1103 DRILL1104
1 6 1 2 3 S Si3445DV DRILL DRILL
EN SW VCC2V5_T
2 GND VIN 5 G
3 4 D max 2.4A PH1103
FB ISENSE PlaceHolder
TPS64203DBVT L1103 TP1104
1
2
5
6
1 2 1 TEST POINT
2.5V
1
2
GND 10u0
2
R1117 C1132 + C1133 C1134 R1120
D1106 42K2 4p70 100u 1u00 100R
10MQ040N 1%
1
2
1
GND GND
LD1102
LED green Miscellaneous
2.5V PG
1
3
2
1
1
R1118 R1119 optional optional optional optional optional
36k0 39k0 GND Pad1101 Pad1102 Pad1103 Pad1104 Pad1105
1% X21 HDR3 1% ArtNr05281 ArtNr05281 ArtNr05281 ArtNr05281 ArtNr05281
2
2
optional optional
GND A1101 GND Label01
Jumper LABEL
Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V
(This is important for the DDR SDRAM module)
A A
P r o j e c t: Hpe_mini LEC2 S h e et: 11_PowerSupply

IF W : 17:14:07
5 4 3 2 1
5 4 3 2 1
Figure 19.
D D
Hpe_mini_LEC2 V1.2
Copyright © Gleichmann Electronics Research (Austria) GmbH & Co KG 2005, All Rights Reserved
Copying of this document, and giving it to others and the use or communication of the contents thereof, are
forbidden without express authority. Offenders are liable to the payment of damages. All rights are reserved
in the event of the grant of a patent or the registration of a utility model or design.
PAGE LOCATOR REVISIONS REVISIONS

SHEET PAGE DESCRIPTION DATE VERSION AUTHOR CHANGE DESCRIPTION DATE VERSION AUTHOR CHANGE DESCRIPTION
C 1/12 PROJECT OVERVIEW 05-05-2006 1.0 CSAM new release ... ... ... ...
C
2/12 FPGA I/O & POWER 19-07-2006 1.1 CSAM position of U0601 must be changed away from
3/12 FPGA CONFIGURATION the DDR
test adapter added (X23)
4/12 MEMORY
04-09-2006 1.2 CSAM final version
5/12 HUMAN INTERFACE
6/12 CLOCK & RESET
7/12 USB & RS232
46
8/12 ETHERNET
Appendix B. Board Version 2 Schematic
9/12 EXPANSION CONNECTOR & SATA

10/12 AUDIO & VGA
11/12 POWER SUPPLY
12/12 DESIGN NOTES
B B
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 1 _ O ve r vie w

IFW: 10:13:29
Hauptstraße 119 Created: Monday, September 13, 2004 05:56:22
A-4232 Hagenberg Page 1 of 12
5 4 3 2 1
5 4 3 2 1 Figure 20.
Offpage Lattice ECP2-50 FPGA VCC1V2
U0201A U0201B U0201F
BANK 0 BANK 1 DIFF BANK 2 BANK 3 POWER SUPPLY
G5 D14 BB3V3_CLK0+ F21 L25 ETH_TXCLK L12 A2
Human Interface PT2A/VREF1_0 PCLKT1_0/PT48A BB3V3_CLK0- PR2A/VREF1_2 PCLKT3_0/PR46A ETH_RXCLK VCC GND
G6 F14 E22 L26 L13 A25
PT2B/VREF2_0 PCLKC1_0/PT48B PR2B/VREF2_2 PCLKC3_0/PR46B VCC GND
MEMORY_A15 E5 B12 FLASH_BYTE# H20 N21 C0203 C0204 C0205 C0206 L14 AA18
PT3A PT49A PR5A VREF1_3/PR47A VCC GND
SEG_CA0# TST_ROW0 MEMORY_A18 E6 A12 FLASH_WP#/ACC G21 N18 100n 100n 100n 100n L15 AA24
5 SEG_CA0# SEG_CA1# 5 TST_ROW0 TST_ROW1 MEMORY_DQ1 PT3B PT49B SRAM_BE2# AC97_EAPD PR5B VREF2_3/PR47B HPE_RESET# VCC GND
F7 E14 C23 M25 M11 AA3
5 SEG_CA1#
SEG_A#
5 TST_ROW1
TST_ROW2 MEMORY_DQ0 PT4A PT50A PR6A PR48A ETH_MDC VCC GND
E7 G14 D23 M26 M12 AA9
5 SEG_A# 5 TST_ROW2 PT4B PT50B PR6B PR48B VCC GND
SEG_B# TST_ROW3 MEMORY_DQ2 G7 C14 DAC_DIG C24 N20 GND M15 AD11
5 SEG_B# 5 TST_ROW3 PT5A PT51A PR7A PR49A VCC GND
SEG_C# TST_COL0 MEMORY_DQ9 G8 D13 MEMORY_OE# AC97_BITCLK B24 N19 M16 AD16
5 SEG_C# 5 TST_COL0 PT5B PT51B PR7B PR49B VCC GND
SEG_D# TST_COL1 MEMORY_A0 C1 H15 G22 N25 ETH_MDIO N11 AD21
5 SEG_D# 5 TST_COL1 PT6A PT52A PR8A/RDQS8 RDQS50/PR50A VCC GND
SEG_E# TST_COL2 MEMORY_A2 C2 H17 H21 N26 ETH_CRS C0207 C0208 C0209 C0210 N16 AD6
5 SEG_E# SEG_F# 5 TST_COL2 MEMORY_A6 PT6B PT52B FLASH_RY/BY#_B AC97_RESET# PR8B PR50B LED3# 100n 100n 100n 100n VCC GND
D3 B13 B25 R21 P11 AE1
5 SEG_F# SEG_G# TST_STEP MEMORY_A10 D4 PT7A PT53A A13 FLASH_CE# AC97_SYNC D24 PR9A PR51A N22 LED7# P16 VCC GND AE26
D 5 SEG_G# SEG_DP# 5 TST_STEP MEMORY_A1 PT7B PT53B BB3V3_IO0 AC97_SDATA_OUT PR9B PR51B LED5# VCC GND D
B2 A15 C25 P22 R11 AF2
5 SEG_DP# MEMORY_A4 PT8A PT54A BB3V3_IO2 AC97_EXT_CLK PR10A PR52A LED4# GND VCC GND
B3 C15 D25 P23 R12 AF25
DSW0 MEMORY_A3 PT8B PT54B FLASH_RESET# TST_STEP PR10B PR52B VCC GND
A3 B14 E24 P19 R15 B1
LED0#
5 DSW0
DSW1 MEMORY_A7 PT9A PT55A FLASH_RY/BY#_A PR11A PR53A LED6# VCC GND
A4 A14 F22 P21 R16 B26
5 LED0# LED1# 5 DSW1 DSW2 MEMORY_A5 C3 PT9B PT55B F15 AC97_SDATA_IN C26 PR11B PR53B R19 C0211 C0212 T12 VCC GND C11
5 LED1# LED2# 5 DSW2 DSW3 MEMORY_A9 PT10A PT56A BB3V3_IO3 PR12A PR54A 100n 100n VCC GND
C4 D15 D26 P20 T13 C16
5 LED2# LED3# 5 DSW3 MEMORY_A8 PT10B PT56B BB3V3_IO1 PR12B PR54B LED1# VCC GND
B4 B15 J19 R23 T14 C21
5 LED3# LED4# MEMORY_A14 PT22B PT57A BB3V3_IO4 PR13A PR55A LED0# VCC3V3 VCC GND
D5 A16 K19 R24 T15 C6
5 LED4# LED5# LCD_REGSEL MEMORY_A13 PT23A PT57B PR13B PR55B ETH_COL GND VCC GND
5 LED5# 5 LCD_REGSEL C5 G15 G23 P25 F18
LED6# LCD_RW H9 PT23B PT58A E15 SRAM_BE3# TST_COL2 G24
PR14A PR56A P26 ETH_RXER D11 GND F24
5 LED6# LED7# 5 LCD_RW LCD_ENABLE MEMORY_DQ8 PT24A PT58B BB3V3_IO10 PR14B PR56B I2C_SCL1 VCCIO0 GND
F8 D17 H22 T21 D6 F3
5 LED7# 5 LCD_ENABLE MEMORY_DQ20 PT24B PT59A BB3V3_IO9 LCD_ENABLE PR15A PR57A LED2# C0213 C0214 C0215 VCCIO0 GND
F10 C17 J22 R22 G9 F9
MEMORY_DQ7 PT25A PT59B BB3V3_IO5 DSW3 PR15B PR57B ETH_RXDV 100n 100n 100n VCCIO0 GND
E8 B16 E25 R25 J12 J13
MEMORY_A22 PT25B PT60A BB3V3_IO14 DSW2 PR16A/RDQS16 RDQS58/PR58A ETH_TXEN VCC3V3 VCCIO0 GND
D7 C18 E26 R26 K12 J14
Clock / Reset MEMORY_A21 PT26A PT60B BB3V3_IO8 PR16B PR58B I2C_SDA1 VCCIO0 GND
C7 B17 L19 T22 J21

MEMORY_A12 PT26B PT61A BB3V3_IO7 SEG_CA1# PR17A PR59A GND GND
B5 A17 K20 T20 D16 J6
HPE_RESET# I2C_SDA1 MEMORY_A11 PT27A PT61B DSW1 PR17B PR59B VCCIO1 GND
A5 H18 F25 T26 D21 K10
3,6 HPE_RESET# 6 I2C_SDA1 I2C_SCL1 PT27B PT62A DSW0 PR18A RLM0_GDLLC_IN_A/PR60A C0216 C0217 C0218 VCCIO1 GND
H10 F16 F26 T25 G18 K11
HPE_RESOUT# 6 I2C_SCL1 CLK_FPGA MEMORY_DQ21 PT28A PT62B TST_COL1 PR18B RLM0_GDLLC_IN_A/PR60B 100n 100n 100n VCCIO1 GND
G10 G16 G25 U20 J15 K13
6,7,8,9 HPE_RESOUT# 6 CLK_FPGA MEMORY_DQ13 PT28B PT63A BB3V3_IO6 TST_COL0 PR19A RLM0_GDLLT_FB_A/PR61A VCC3V3 VCCIO1 GND
D9 E16 G26 T19 K15 K14
MEMORY_DQ14 PT29A PT63B BB3V3_IO12 TST_ROW3 PR19B RLM0_GDLLC_FB_A/PR61B CLK_FPGA VCCIO1 GND
E9 A18 H23 U25 K16
MEMORY_DQ19 PT29B PT64A BB3V3_IO13 TST_ROW2 PR23A RLM0_GPLLT_IN_A/PR63A GND GND
E10 B18 H24 U24 F23 K17
RS232 MEMORY_DQ25 PT30A PT64B BB3V3_IO15 TST_ROW1 PR23B RLM0_GPLLC_IN_A/PR63B VCCIO2 GND
F11 D18 H25 U23 J20 L10
MEMORY_DQ5 PT30B PT65A BB3V3_IO11 TST_ROW0 PR24A/RDQS24 RLM0_GPLLT_FB_A/PR64A C0219 C0220 C0221 VCCIO2 GND
C8 E17 H26 U22 L23 L11
RS_TXD_LVTTL RS_RXD_LVTTL MEMORY_DQ6 D8 PT31A PT65B A19 BB3V3_IO17 K23 PR24B RLM0_GPLLC_FB_A/PR64B U26 ETH_TXER 100n 100n 100n M17 VCCIO2 GND L16
7 RS_TXD_LVTTL 7 RS_RXD_LVTTL PT31B PT66A PR25A/RUM0_SPLLT_IN_A PR65A VCC3V3 VCCIO2 GND
RS_RTS_LVTTL RS_CTS_LVTTL MEMORY_A17 B6 A20 MACHXO_IO0 J23 V26 ETH_TXD0 M18 L17
7 RS_RTS_LVTTL 7 RS_CTS_LVTTL PT32A PT66B PR25B/RUM0_SPLLC_IN_A PR65B VCCIO2 GND
MEMORY_A16 A6 F17 RS_RXD_LVTTL J25 V25 ETH_TXD1 L24
PT32B PT67A PR26A/RUM0_SPLLT_FB_A PR66A GND
MEMORY_DQ26 G11 G19 RS_CTS_LVTTL J26 V24 ETH_TXD2 GND AA23 L3
PT33A PT67B PR26B/RUM0_SPLLC_FB_A PR66B VCCIO3 GND
H11 E18 BB3V3_IO16 LCD_RW J24 W26 ETH_RXD2 R17 M13
USB MEMORY_DQ18 D10 PT33B PT68A G17 LCD_REGSEL K24 PR37A RDQS67/PR67A W25 ETH_RXD3 C0222 C0223 C0224 R18 VCCIO3 GND M14
PT34A PT68B PR37B PR67B VCCIO3 GND
MEMORY_DQ30 F12 B19 BB3V3_IO18 SEG_D# M21 U19 100n 100n 100n T23 N10
USB_GPIO[28:0] PT34B PT69A PR38A PR68A VCC3V3 VCCIO3 GND
MEMORY_A20 B7 D19 BB3V3_IO20 SEG_CA0# K21 U21 V20 N12
7 USB_GPIO[28:0] PT35A PT69B PR38B PR68B VCCIO3 GND
MEMORY_A19 A7 B20 MACHXO_IO1 SEG_C# M22 Y26 ETH_RXD1 N13
PT35B PT70A PR39A PR69A GND
USB_MISO USB_PWEN0 MEMORY_DQ12 C9 B21 MACHXO_IO6 SEG_F# L22 AA26 ETH_RXD0 GND AC16 N14
7 USB_MISO 7 USB_PWEN0 PT36A PT70B PR39B PR69B VCCIO4 GND
USB_SSI# USB_OC0# MEMORY_DQ24 E11 C19 BB3V3_IO19 M19 V23 ETH_TXD3 AC21 N15
7 USB_SSI# 7 USB_OC0# PT36B PT71A PR40A PR70A VCCIO4 GND
USB_SCK USB_PWEN1 MEMORY_DQ4 B8 E19 BB3V3_IO21 SEG_E# M20 W24 ETH_MDINTR# C0225 C0226 C0227 U15 N17
7 USB_SCK 7 USB_PWEN1 PT37A PT71B PR40B PR70B VCCIO4 GND
USB_MOSI USB_OC1# MEMORY_DQ3 A8 A21 MACHXO_IO5 RS_RTS_LVTTL K25 100n 100n 100n V15 P10
7 USB_MOSI USB_TXD 7 USB_OC1# USB_PWEN2 MEMORY_DQ31 PT37B PT74A MACHXO_IO8 RS_TXD_LVTTL PR41A/RDQS41 VCC2V5 VCCIO4 GND
G12 A22 K26 Y18 P12
7 USB_TXD 7 USB_PWEN2 PT38A PT74B PR41B VCCIO4 GND
7 USB_RXD
USB_RXD
7 USB_OC2#
USB_OC2# MEMORY_DQ29 E12 D20 MACHXO_IO3 SEG_B# N23 P13
USB_RTS MEMORY_DQ11 B9 PT38B PT75A C20 MACHXO_IO2 SEG_A# M24 PR42A GND AC11 GND P14
7 USB_RTS USB_CTS MEMORY_DQ10 PT39A PT75B MACHXO_IO13 SEG_DP# PR42B VCCIO5 GND
A9 B23 K22 AC6 P15
C 7 USB_CTS PT39B PT76A MACHXO_IO9 SEG_G# PR43A C0228 C0229 C0230 VCCIO5 GND C
H12 B22 L21 U12 P17
PT40A PT76B PR43B VCCIO5 GND
SRAM_BE1# G13 E20 MACHXO_IO4 M23 100n 100n 100n V12 R13
PT40B PT77A PR44A/PCLKT2_0 VCC2V5 VCCIO5 GND
MEMORY_DQ17 C10 C22 MACHXO_IO10 N24 Y9 R14
Ethernet MEMORY_DQ27 PT41A PT77B PR44B/PCLKC2_0 VCCIO5 GND
C12 F19 T10
MEMORY_DQ16 PT41B PT78A MACHXO_IO7 ECP2-50-672BGA GND GND
B10 E21 AA4 T11
ETH_TXER ETH_RXER MEMORY_DQ15 PT42A PT78B MACHXO_IO12 VCCIO6 GND
A10 A23 R10 T16
8 ETH_TXER ETH_TXD3 8 ETH_RXER ETH_RXD3 SRAM_BE0# PT42B PT79A MACHXO_IO15 C0231 C0232 C0233 VCCIO6 GND
F13 A24 R9 T17
8 ETH_TXD3 ETH_TXD2
8 ETH_RXD3
ETH_RXD2 MEMORY_DQ28 PT43A PT79B 100n 100n 100n VCCIO6 GND
D12 H19 T4 T24
8 ETH_TXD2 ETH_TXD1 8 ETH_RXD2 ETH_RXD1 SRAM_CE# E13 PT43B PT80A F20 VCC3V3 V7 VCCIO6 GND T3
8 ETH_TXD1 ETH_TXD0 8 ETH_RXD1 ETH_RXD0 MEMORY_WE# PT44A PT80B VCC1V2 VCC2V5 VCC3V3 VCCIO6 GND
C13 J18 U10
8 ETH_TXD0 8 ETH_RXD0 MEMORY_DQ23 PT44B PT81A GND GND
B11 G20 F4 U11
ETH_TXEN MEMORY_DQ22 PT45A PT81B MACHXO_IO11 VCCIO7 GND
A11 D22 J7 U13
1
1
1
1
8 ETH_TXEN ETH_TXCLK MACHXO_CLK0 PT45B VREF1_1/PT82A MACHXO_IO14 C0234 C0235 C0236 VCCIO7 GND
H13 E23 L4 U14
8 ETH_TXCLK MACHXO_CLK1 H14 PT46A/PCLKT0_0 VREF2_1/PT82B + C0238 C0239 + C0240 C0241 + C0242 + C0243 C0244 C0245 100n 100n 100n M10 VCCIO7 GND U16
PT46B/PCLKC0_0 XRES 4u70 1n00 4u70 1n00 4u70 4u70 1n00 1n00 VCC3V3 VCCIO7 GND
H16 M9 U17
XRES VCCIO7 GND
ETH_RXCLK ETH_MDINTR# V13
2
2
2
2
2
8 ETH_RXCLK 8 ETH_MDINTR# GND
ETH_RXDV ECP2-50-672BGA GND AE25 V14
8 ETH_RXDV VCCIO8 GND
ETH_MDC R0202 GND GND GND V18 V21
8 ETH_MDC VCCIO8 GND
ETH_CRS ETH_MDIO 10K0 C0237 V6
8 ETH_CRS ETH_COL 8 ETH_MDIO 1% 100n GND
8 ETH_COL ECP2-50-672BGA
47
GND GND
Expansion Connectors and Prototyping Area U0201C GND U0201D
BANK 4 BANK 5 LVDS BANK 6 BANK 7
EXPCON_IO[45:0] BB3V3_IO[21:0] CLK_FPGA AD15 AE3 SATA_X1D0+ M4 D2
9 EXPCON_IO[45:0] 9 BB3V3_IO[21:0] PB49A/PCLKT4_0 VREF2_5/PB2A DDR_VREF SATA_X1D0- PL46A/PCLKT6_0 VREF2_7/PL2A CARDSEL#
AC15 AF3 M5 D1
PB49B/PCLKC4_0 VREF1_5/PB2B PL46B/PCLKC6_0 VREF1_7/PL2B
CARDSEL# BB3V3_CLK0+ USB_GPIO28 AE13 AC4 DDR_DQ15 N7 F6 EXPCON_IO41
1
9 CARDSEL# EXPCON_CLKIN 9 BB3V3_CLK0+ BB3V3_CLK0- USB_GPIO27 PB50A PB3A DDR_DQ14 C0201 DDR_VREF PL47A/VREF2_6 PL5A EXPCON_IO40
AF13 AD4 P9 F5
9 EXPCON_CLKIN 9 BB3V3_CLK0- PB50B PB3B PL47B/VREF1_6 PL5B
EXPCON_CLKOUT R0201 USB_GPIO20 AB17 AE4 DDR_DQ13 100n DDR_DQ29 N3 E4 EXPCON_IO45
9 EXPCON_CLKOUT PB51A/BDQS51 PB4A PL48A PL6A
0R00 Y15 AF4 DDR_DQ12 C0202 DDR_DQ30 N4 E3 EXPCON_IO44
PB51B PB4B PL48B PL6B
USB_GPIO26 AE14 V9 100n DDR_DQ31 N5 E2 EXPCON_IO43
PB52A PB5A PL49A PL7A
SATA_X1D0+ SATA_X2D0+ USB_GPIO25 AF14 W9 GND P7 E1 EXPCON_IO42
2
9 SATA_X1D0+ SATA_X1D0- 9 SATA_X2D0+ SATA_X2D0- USB_OC0# PB52B PB5B DDR_DQS1 DDR_DQS3 PL49B PL7B EXPCON_IO31
AA16 AA6 T1 H6
9 SATA_X1D0- 9 SATA_X2D0- PB53A BDQS6/PB6A PL50A/LDQS50 LDQS8/PL8A
SATA_X1D1+ SATA_X2D1+ W15 AB6 DDR_DM1 GND DDR_DM3 T2 H5 EXPCON_IO30
9 SATA_X1D1+ SATA_X1D1- 9 SATA_X2D1+ SATA_X2D1- GND USB_GPIO19 PB53B PB6B DDR_DQ11 PL50B PL8B EXPCON_IO39
AC17 AC5 P8 F2
9 SATA_X1D1- 9 SATA_X2D1- USB_MOSI PB54A PB7A DDR_DQ10 DDR_DQ28 PL51A PL9A EXPCON_IO38
ADC
AB16 AD5 P6 F1
USB_GPIO24 PB54B PB7B DDR_DQ27 PL51B PL9B EXPCON_IO33
AE15 AA7 P5 H8
USB_GPIO23 PB55A PB8A DDR_DQ26 PL52A PL10A EXPCON_IO25 X22
AF15 AB7 P4 J9
USB_GPIO22 PB55B PB8B DDR_DQ9 DDR_DQ25 PL52B PL10B EXPCON_IO37 VCC1V2 optional
AE16 AE5 U1 G4
PB56A PB9A PL53A PL11A
USB_GPIO21 AF16 AF5 DDR_DQ8 LVDS DDR_DQ24 V1 G3 EXPCON_IO36 A0201
Audio Codec USB_PWEN1 PB56B PB9B DDR_BA1 SATA_X1D1+ PL53B PL11B EXPCON_IO32 Jumper C0249 nb
Y16 AC7 P3 H7
2
1
B USB_GPIO15 AB18
PB57A PB10A
AD7 DDR_BA0 SATA_X1D1- R3
PL54A PL12A
J8 EXPCON_IO24
B
PB57B PB10B PL54B PL12B
AC97_BITCLK AC97_RESET# USB_GPIO18 AD17 W10 R4 G2 EXPCON_IO35
2
10 AC97_BITCLK AC97_SDATA_OUT 10 AC97_RESET# AC97_EXT_CLK USB_GPIO13 PB58A PB20A LVDS PL55A PL13A EXPCON_IO34 C0248 nb
AD18 Y10 U2 G1
10 AC97_SDATA_OUT 10 AC97_EXT_CLK PB58B PB20B PL55B PL13B
AC97_SDATA_IN AC97_EAPD USB_GPIO14 AC18 W11 SATA_X2D1+ V2 H3 EXPCON_IO28 FB0201
10 AC97_SDATA_IN 10 AC97_EAPD PB59A PB21A PL56A PL14A
10 AC97_SYNC
AC97_SYNC USB_GPIO7 AD19 AA10 SATA_X2D1- W2 H4 EXPCON_IO29 BLM18BD601SN1
USB_GPIO8 PB59B PB21B DDR_DQ4 PL56B PL14B EXPCON_IO23 C0247 nb
AC19 AC8 T6 J5
1
USB_GPIO17 AE17 PB60A/BDQS60 PB22A AD8 DDR_DQ3 R5 PL57A PL15A J4 EXPCON_IO22 LVDS 1
USB_GPIO9 PB60B PB22B DDR_DQ5 PL57B PL15B EXPCON_IO21 ADC+
AB19 AB8 R6 J3
USB_GPIO6 PB61A PB23A DDR_A13 PL58A/LDQS58 LDQS16/PL16A EXPCON_IO14 ADC- C0246 3n30
AE19 AB10 R7 K4
VGA USB_GPIO16 AF17
PB61B PB23B
AE6 DDR_DQS0 W1
PL58B PL16B
H1 EXPCON_IO26 4
USB_GPIO12 PB62A BDQS24/PB24A DDR_DM0 PL59A PL17A EXPCON_IO27
AE18 AF6 Y2 H2
VGA_RD0 VGA_BL0 W16 PB62B PB24B AA11 DDR_CK1+ Y1 PL59B PL17B K6 EXPCON_IO16
10 VGA_RD0 VGA_RD1 10 VGA_BL0 VGA_BL1 USB_TXD PB63A PB25A DDR_DQ1 DDR_CK1- PL60A/LLM0_GDLLT_IN_A PL18A EXPCON_IO17 R0203 R0204 X1
AA17 AC9 AA2 K7
10 VGA_RD1 VGA_GR0 10 VGA_BL1 VGA_HSYNC USB_GPIO11 PB63B PB25B DDR_DQ2 PL60B/LLM0_GDLLC_IN_A PL18B EXPCON_IO19 ADCS
AF18 AB9 T5 J1 1 2 1 2 2
10 VGA_GR0 VGA_GR1 10 VGA_HSYNC VGA_VSYNC USB_GPIO5 PB64A PB26A DDR_DQ0 LVDS PL61A/LLM0_GDLLT_FB_A PL19A EXPCON_IO20
AF19 AD9 T7 J2 1
10 VGA_GR1 10 VGA_VSYNC USB_GPIO10 PB64B PB26B PL61B/LLM0_GDLLC_FB_D PL19B
AA19 Y11 SATA_X2D0+ U3 K3 EXPCON_IO13 10k0 10k0
W17 PB65A PB27A AB11 DDR_A1 SATA_X2D0- U4
PL63A/LLM0_GPLLT_IN_A PL23A
K2 EXPCON_IO12 0,1% 0,1%
PB65B PB27B PL63B/LLM0_GPLLC_IN_A PL23B 3 2
USB_OC2# Y19 AE7 DDR_DQ7 V3 K1 EXPCON_IO11
Memory USB_PWEN0 PB66A PB28A DDR_DQ6 PL64A/LLM0_GPLLT_FB_A LDQS24/PL24A EXPCON_IO6 GND_ADC
Y17 AF7 U5 L2
VGA_HSYNC PB66B PB28B PL64B/LLM0_GPLLC_FB_A PL24B 0
AF20 AC10 DDR_A10 V4 L1 EXPCON_CLKIN
MEMORY_A[22:0] MEMORY_DQ[31:0] PB67A PB29A PL65A LUM0_SPLLT_IN_A/PL25A
4 MEMORY_A[22:0] 4 MEMORY_DQ[31:0]
USB_GPIO0 AE20 AD10 DDR_A0 V5 M2
USB_GPIO4 AA20 PB67B PB29B
AA12 ADCS PL65B LUM0_SPLLC_IN_A/PL25B EXPCON_CLKOUT
Y3 M1
PB68A PB30A PL66A LUM0_SPLLT_FB_A/PL26A
MEMORY_OE# W18 W12 LVDS Y4 N2 Sternpunkt an X1
4 MEMORY_OE# PB68B PB30B PL66B LUM0_SPLLC_FB_A/PL26B
MEMORY_WE# USB_GPIO1 AD20 AB12 DDR_A2 ADC+ W3 N1 EXPCON_IO4 Place pins 0..4 near the balls of the FPGA.
4 MEMORY_WE# VGA_BL1 PB69A/BDQS69 PB31A PL67A/LDQS67 PL37A
FLASH_CE# AE21 Y12 ADC- W4 L8 EXPCON_IO10 These pins must also be accessible for
SRAM_BE0# 4 FLASH_CE# FLASH_RESET# VGA_VSYNC PB69B PB31B DDR_A4 PL67B PL38A EXPCON_IO18
AF21 AD12 AA1 K8 measurements instruments.
4 SRAM_BE0# SRAM_BE1# 4 FLASH_RESET# FLASH_RY/BY#_A VGA_BL0 PB70A PB32A DDR_A3 PL68A PL38B EXPCON_IO8
AF22 AC12 AB1 L6
4 SRAM_BE1# SRAM_BE2# 4 FLASH_RY/BY#_A FLASH_RY/BY#_B VGA_GR1 PB70B PB32B DDR_A6 PL68B PL39A EXPCON_IO15 GND_ADC GND
AE22 AC13 U8 K5
4 SRAM_BE2# SRAM_BE3# 4 FLASH_RY/BY#_B FLASH_WP#/ACC USB_SSI# PB74A BDQS33/PB33A PL69A PL39B EXPCON_IO9
AD22 AA13 U7 L7
4 SRAM_BE3# 4 FLASH_WP#/ACC VGA_GR0 PB74B PB33B PL69B PL40A
SRAM_CE# FLASH_BYTE# AF23 AD13 DDR_A7 V8 L5 EXPCON_IO7
4 SRAM_CE# 4 FLASH_BYTE# VGA_RD1 PB75A PB34A DDR_A11 PL70A PL40B EXPCON_IO2
AE23 AC14 U6 P1
PB75B PB34B PL70B LDQS41/PL41A
USB_MISO AD23 AE8 DDR_S1# W6 P2 EXPCON_IO3
DDR_DQ[31:0] DDR_DQS[3:0] PB76A PB35A PL71A PL41B
USB_RXD AC23 AF8 DDR_S0# W5 M6 EXPCON_IO5
4 DDR_DQ[31:0] 4 DDR_DQS[3:0] PB76B PB35B PL71B PL42A
USB_GPIO3 DDR_A8 DDR_DQ20 N8
DDR_DM[3:0] DDR_A[13:0]
AB20
PB77A PB36A
AB15 AC1
PL72A PL42B
DAC X2
USB_GPIO2 AC20 Y13 DDR_DQ17 AD1 R1 EXPCON_IO0 R0205
4 DDR_DM[3:0] 4 DDR_A[13:0] USB_CTS PB77B PB36B DDR_RAS# DDR_DQ23 PL72B PL43A EXPCON_IO1 DAC_DIG DAC_ANALOG
AB21 AE9 Y6 R2 1 2 2
USB_SCK AC22 PB78A/BDQS78 PB37A AF9 DDR_CAS# DDR_DQ22 Y5 PL73A PL43B M7 1
PB78B PB37B PL73B PCLKT7_0/PL44A
DDR_CK0+ DDR_CK1+ W19 W13 DDR_DQ16 AE2 N9 33k2
4 DDR_CK0+ DDR_CK0- 4 DDR_CK1+ DDR_CK1- USB_PWEN2 PB79A PB38A DDR_DQ18 PL74A PCLKC7_0/PL44B HDR2
AA21 AA14 AD2
4 DDR_CK0- DDR_CKE0 4 DDR_CK1- DDR_CKE1 VGA_RD0 PB79B PB38B DDR_WE# DDR_DQS2 PL74B C0250 C0251 Sternpunkt an X2
4 DDR_CKE0 4 DDR_CKE1 AF24 AE10 AB3
DDR_BA0 DDR_BA1 HPE_RESOUT# PB80A PB39A DDR_CKE1 DDR_DM2 PL75A/LDQS75 4p70 nb_4p70
4 DDR_BA0 4 DDR_BA1 AE24 AF10 AB2
A USB_OC1# Y20 PB80B PB39B W14 W7 PL75B A
PB81A PB40A PL76A
DDR_WE# DDR_S0# USB_RTS AB22 AB13 DDR_A5 W8
4 DDR_WE# DDR_RAS# 4 DDR_S0# DDR_S1# PB81B PB40B PL76B
Y21 Y14 Y7
4 DDR_RAS# DDR_CAS# 4 DDR_S1# DDR_VREF PB82A/VREF2_4 PB41A DDR_A9 PL77A GND_DAC GND
AB23 AB14 Y8
4 DDR_CAS# 4 DDR_VREF PB82B/VREF1_4 PB41B DDR_DQ21 PL77B GND_DAC
AE11 AC2
BDQS42/PB42A AF11 DDR_CKE0 DDR_DQ19 AD3 PL78A
PB42B DDR_A12 PL78B
AD14
MachXO PB43A ECP2-50-672BGA
AA15
PB43B DDR_CK0+
AE12
MACHXO_IO[15:0] MACHXO_CLK0 PCLKT5_0/PB44A DDR_CK0- Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 2 _ F PG A
3 MACHXO_IO[15:0] 3 MACHXO_CLK0 AF12
MACHXO_CLK1 PCLKC5_0/PB44B Revision: R01 Last modified:
3 MACHXO_CLK1 ECP2-50-672BGA Authors: csam Monday, September 04, 2006
IFW: 10:15:04
5 4 3 2 1
5 4 3 2 1 Figure 21.
Offpage Lattice ECP2-50 FPGA (Configuration) SPI Flash for Configuration Settings
Configuration VCC3V3 VCC3V3 VCC3V3 VCC3V3
MACHXO_IO[15:0] U0201E
2 MACHXO_IO[15:0] TP0301 BANK 8 BANK 9
2
2
1
2
CCLK JTAG_DONE AD25 AB5 VCC3V3
MACHXO_CLK0 JTAG_INIT DONE VCCJ EC_TDO R0305 R0306 R0307 R0308
AB24 AA5
2 MACHXO_CLK0 MACHXO_CLK1 CCLK INITN TDO EC_TMS 270R
AA22 AB4 270R 4k70 270R
2 MACHXO_CLK1 CCLK TMS
PROGRAM# V19 AA8 EC_TDI
1
CFG0 PROGRAMN TDI EC_TCK
AC24 AC3
1
1
2
1
CFG0 TCK
CLK_MACHXO R0301 CFG1 W20
1
6 CLK_MACHXO CFG1
4k70 CFG2 AD24 Place the 4k7 resistors LD0301 LD0302 LD0303
SISPI Y25
CFG2 R0303 close to their clock VCC3V3 LED blue LED red LED yellow
D DOUT BUSY/PR71A 4k70
D
Y24
2
DOUT/CSON/PR71B
line to keep the stub
EXPCON_IO[45:0] CSSPIN V22 length as short as
2,9 EXPCON_IO[45:0] DI/PR72A
GND TP0302 W21 PROGRAM# TP0310
2
1
WRITEN/PR77B possible.
DOUT Y22 PROGRAM#
AC25 CS1N/PR77A R0304 T0301
CSN/PR76B 1 3
HPE_RESET# SPIFASTN# AB25 GND 10K0 BSS138/SOT
2,6 HPE_RESET# PR76A/D0 BBV3_IO11 SW0301
AD26
PR75B/D1 U0305 JTAG_DONE TP0308 B3FS-1012
AC26
2
USB_SCL PR75A/D2 WP# HOLD# CCLK DONE
7 USB_SCL Y23 1 16
USB_SDA W22 PR74B/D3 2 HOLD CLK
15 SISPI 2 4
7 USB_SDA PR74A/D4 VCC DI GND T0302
AA25 3 14
PR73B/D5 NC NC BSS138/SOT GND
AB26 4 13
PR73A/D6 NC NC
SPIDO W23 5 12
BB3V3_IO[21:0] PR72B/D7 FB0301 NC NC JTAG_INIT TP0309
6 11
2 BB3V3_IO[21:0] AUX & PLL POWER BLM18BD601SN1 CSSPIN NC NC INIT# VCC3V3
7 10
VCCPLL CS GND WP#
VCC3V3 J10 M8 1 2 VCC1V2 SPIDO 8 9 Drain
VCCAUX LUM0_VCCPLL Q WP GND
J11 R8
VCCAUX LLM0_VCCPLL C0301 C0302 M25P16
J16 P18
1
1
1
1
VCCAUX RLM0_VCCPLL 1n00 100n M25P16-VMF6P 16Mb

J17 L20
VCCAUX RUM0_VCCPLL GND SOT-23 RJ0301 RJ0303 RJ0305 RJ0307
K18
VCCAUX nb_10K0 nb_10K0 nb_10K0 10K0
L18
VCCAUX GND GND
T18 T8
VCCAUX LLM0_PLLCAP
U18 R20
2
2
2
2
VCCAUX RLM0_PLLCAP
V16 Gate Source SPIFASTN#
V17 VCCAUX VCC3V3 CFG0
VCCAUX
V10 C0325 C0326 CFG1
VCCAUX
V11 5n60 5n60 CFG2
VCCAUX Mode CFG2 CFG1 CFG0 SPIFAST#
T9
1
1
1
1
VCCAUX
U9 N6
K9 VCCAUX NC1 P24 GND GND C0303 C0304 SPI Normal 0 0 0 Pull-Up RJ0302 RJ0304 RJ0306 RJ0308
VCCAUX NC2 100n 100n SPI Fast 0 0 0 Pull-Down 0R00 0R00 0R00 nb_0R00
L9 M3
VCCAUX NC3 Reserved 0 0 1 X
ECP2-50-672BGA SPIm Normal 0 1 0 Pull-Up
2
2
2
2
SPIm Fast 0 1 0 Pull-Down

Reserved 0 1 1 X
GND Reserved 1 0 0 X
Slave Serial 1 0 1 X GND
Reserved 1 1 0 X
C C
rev 1.1
USB-JTAG Programmer Connector Test Adapter
Q0301 U0302
24MHz U0301 BANK 0/0,1 BANK 1/2,3
2 1 11 67 GP_INT0 MACHXO_IO0 A1 A14 MACHXO_IO15
USB Peripheral XTALIN PA0/INT0 GP_INT1 MACHXO_IO3 PT2A PR2A/PR2A
68 B3 C13
PA1/INT1 GP_SLOE MACHXO_IO1 PT2B/PT3A PR2B/PR3C
for Configuration 69 A2 B14
C0339 C0340 PA2/SLOE GP_WU2 MACHXO_IO2 PT2C/PT2B PR2C/PR2B
70 A3 C14
12p0 12p0 PA3/WU2 GP_FIFOADR0 MACHXO_IO5 PT2D/PT3B PR2D/PR3D
71 C4 D12
PA4/FIFOADR0 72 GP_FIFOADR1 MACHXO_IO4 A4 PT2F/PT3C PR3C/PR4A D14
X3 PA5/FIFOADR1 GP_PKTEND MACHXO_IO6 PT3B/PT3D PR3D/PR4B GP_TXD0
73 A5 E14
GND GND PA6/PKTEND GP_SLCS# MACHXO_IO7 PT3D/PT4B PR4B/PR5A GP_RXD0
5 74 B5 E13
PWR_IN SHIELD PA7/FLAGD/SLCS PT3E/PT5A PR4C/PR5B GP_BKPT
1 10 C6 F12
USBCF_M VCC XTALOUT GP_D0 MACHXO_IO9 PT3F/PT5B PR4D/PR6A GP_RXD1
2 34 B6 F13
TP0303 USBCF_P DATA- PB0/FD0 GP_D1 MACHXO_IO8 PT4C/PT5C PR5C/PR6B GP_TXD1
3 35 A6 F14
DATA+ PB1/FD1 GP_D2 PT4D/PT5D PR5D/PR6C GP_D0 X23
4 36 B7 G14
GND PB2/FD2 GP_D3 MACHXO_CLK0 PT5A/PT6D PR6B/PR8A GP_D1 JTAG_TCK
6 37 C8 G13
SHIELD PB3/FD3 GP_D4 MACHXO_CLK1 PT5B/PT6F (PCLKT) PR6C/PR8B GP_D4 JTAG_TDO TP0 GND
44 B8 H12
48
USB Peripheral GP_RDY0 PB4/FD4 GP_D5 CLK_MACHXO PT6A/PT7B PR6D/PR9A GP_D3 JTAG_TMS TP1
3 45 A8 H13 VCC5V0
GP_RDY1 4 RDY0/SLRD PB5/FD5 46 GP_D6 USB_SDA A9 PT6B/PT7D (PCLKT) PR7A/PR9B H14 GP_D2 JTAG_TDI TP2 TVi0
GP_RDY2 RDY1/SLWR PB6/FD6 GP_D7 USB_SCL PT7A/PT9A PR7B/PR10A GP_D6 TP3
5 47 B9 J12
GNDA_CONF GNDP GP_RDY3 RDY2 PB7/FD7 PT7B/PT9B PR7C/PR10B GP_D5 TP4 TVi1
6 C10 J13
RDY3 PT7E/PT9E PR8A/PR11A TP5
GP_RDY4 7 80 GP_D8 MACHXO_IO10 B10 K12 GP_D9
RDY4 PD0/FD8 PT7F/PT9F PR8B/PR11B TP6 TVi2
GP_RDY5 8 81 GP_D9 C11 K13 GP_D8
RDY5 PD1/FD9 PT8C/PT10C PR8C/PR12A TP7
82 GP_D10 MACHXO_IO11 A11 K14 GP_D7
PD2/FD10 PT9A/PT10D PR8D/PR12B TP8 TVi3
83 GP_D11 C12 L14 GP_D10
PD3/FD11 GP_D12 MACHXO_IO13 PT9B/PT11A PR10A/PR14A GP_D11 TP9
95 B12 M13 VCC3V3_T
PD4/FD12 GP_D13 PT9C/PT10F PR10B/PR14B GP_D13 TP10 TVo0
13 96 B13 M12
NC PD5/FD13 PT9D/PT11C PR11A/PR15A TP11
14 97 GP_D14 MACHXO_IO12 A12 N13 GP_D15 VCC2V5_T
JTAG Connector 15 NC PD6/FD14 GP_D15 MACHXO_IO14 PT9E/PT11B PR11B/PR16A GP_D12 TP12 TVo1
98 A13 M14
NC PD7/FD15 PT9F/PT11D PR11C/PR15B TP13
for Configuration 27 N14 GP_D14
VCC1V2_T
RESERVED GP_ADR0 PR11D/PR16B TP14 TVo2
57 A7
PC0/GPIFADR0 GP_ADR1 VCCAUX TP15
58
VCC3V3 GND PC1/GPIFADR1 GP_ADR2 TP16 TVo3
59 VCC3V3 C7 G12 VCC3V3
USBCF_P PC2/GPIFADR2 GP_ADR3 VCC VCC TestContact
17 60 B11 L12
X4 USBCF_M DPLUS PC3/GPIFADR3 GP_ADR4 VCCIO0/VCCIO1 VCCIO1/VCCIO3
18 61 C5 E12
DMINUS PC4/GPIFADR4 GP_ADR5 VCCIO0/VCCIO0 VCCIO1/VCCIO2 GND
1 62 A10 L13
JTAG_TDO PC5/GPIFADR5 GP_ADR6 GNDIO0/GNDIO1 GNDIO1/GNDIO3
B 2 63 B4 D13 B
JTAG_TDI PC6/GPIFADR6 GP_ADR7 GNDIO0/GNDIO0 GNDIO1/GNDIO2
3 64 C9 J14
JTAG_PROG TP0304 GP_CTL0 PC7/GPIFADR7 GND GND
4 54
CTL0/FLAGA
5 JTAG_TRST GP_CTL1 55 86 GND GND
CTL1/FLAGB PE0/T0OUT
6 JTAG_TMS TP0305 GP_CTL2 56 87 BANK 2/4,5 BANK 3/6,7
CTL2/FLAGC PE1/T1OUT
7 GP_CTL3 51 88 GP_SLOE M3 B1 GP_CTL5
CTL3 PE2/T2OUT PB2C PL2A
8 JTAG_TCK GP_CTL4 52 89 GP_WU2 N3 C1 GP_CTL3
9 JTAG_DONE VCC3V3 VCC3V3 GP_CTL5 76
CTL4 PE3/RXD0OUT 90 GP_FIFOADR0 M4 PB2D PL2B/PL3C B2 GP_CTL4
CTL5 PE4/RXD1OUT PB3B PL2C/PL2B
10 JTAG_INIT 91 GP_FIFOADR1 N4 C2 GP_CTL2
TP0307 PE5/INT6 GP_PKTEND PB3C/PB4A PL2D/PL4A GP_CTL1
22 92 P5 C3
1
1
INT4 PE6/T2EX PB3D/PB4B PL3A/PL3D
CON10 84 93 GP_ADR8 N6 D1 GP_CTL0
GND R0316 R0317 USBCF_WAKE INT5 PE7/GPIFADR8 GP_INT1 PB4E/PB5C PL3B/PL4B GP_RDY0
79 M6 D3
10K0 10K0 WAKEUP 9 GP_INT0 N7 PB4F/PB6A PL3D/PL4C E2 GP_RDY1
AVCC VCC3V3_CONF PB5A/PB6F PL5A/PL6A
16 USB_CLK_O M7 E3 USB_RESET_n
AVCC PB5B/PB7B (PCLKT) (GSRN) PL5B/PL6B VCC3V3
SW0302 GP_T0 23 USBCF_I2C_SDA N8 F2 GP_RDY2
2
2
EC_TMS GP_T1 T0 USBCF_I2C_SCL PB5D/PB7C PL5D/PL6D GP_RDY3
1 24 12 P8 F3
JTAG_TMS GPIO_TMS A GP_T2 T1 AGND GP_IFCLK PB6A/PB7D PL6B/PL7C GP_RDY4
2 25 19 M8 G1
1
C T2 AGND PB6B/PB7F (PCLKT) PL6C/PL7D

3 MACHXO_TMS USBCF_WAKE N9 G2 GP_RDY5
B GNDA_CONF JTAG_INIT PB7A/PB9A PL6D/PL8C GP_SLCS# RJ0309
1 M9 G3
VCC PB7B/PB9B PL7A/PL8D
CAS-120A GP_RXD0 41 20 JTAG_TRST N10 H2 GP_ADR1 nb_10K0
GP_TXD0 RXD0 VCC VCC3V3 JTAG_DONE PB7E/PB9C PL7B/PL10A GP_ADR0
40 33 P10 H1
TXD0 VCC GPIO_TDI PB7F/PB9D PL7C/PL10B GP_ADR2
38 P11 J1
2
JT AG _ T DI GPIO_TDO MACHXO _ T DI EC_ T DI GP_RXD1 VCC JTAG_PROG PB8C/PB10A PL8A/PL11B MACHXO_TSALL TP0311
43 49 M11 J2
GP_TXD1 RXD1 VCC R0314 GPIO_TDO PB8D/PB10B (TSALL) PL8C/PL11C GP_ADR3 TSALL
42 53 P12 J3
1
JT AG _ T DO GPIO_TDI MACHXO _ T DO EC_ T DO TXD1 VCC 10K0 GPIO_TMS PB9C/PB10C PL9A/PL11D GP_ADR5
66 P13 K2
USBCF_I2C_SCL VCC GPIO_TCK PB9D/PB11C PL9B/PL12A GP_ADR4 RJ0310
29 78 P14 K1
SCL VCC PB9F/PB11D PL9C/PL12B
JT AG _ T CK GPIO_TCK MACHXO _ T CK EC_ T CK USBCF_I2C_SDA 30 85 L1 GP_ADR6 10K0
2
SDA VCC VCC3V3 PL10A/PL14A

MACHXO_TMS P3 L3 GP_ADR7
VCC3V3 GP_BKPT MACHXO_TCK TMS PL10B/PL14B GP_ADR8
28 2 P4 M1
2
BKPT GND TCK PL11A/PL15A

USB_CLK_O 100 21 MACHXO_TDO N5 N1 GP_T1
1
GP_IFCLK CLKOUT GND MACHXO_TDI TDO PL11B/PL16A GP_T0

26 39 M5 M2
1
IFCLK GND R0315 TDI PL11C/PL15B GP_T2 GND
31 48 P1
R318 32 RD GND
50 4k70 MACHXO_SLEEPN N12
PL11D/PL16B
300K WR GND SLEEPN
65 P7
SW602 GND VCCAUX
75
2
B3FS-1012 GND
94 P6 H3
2
GND VCC3V3 VCC VCC VCC3V3
1 3 USB_RESET_n 77 99 GND N2 D2
RESET GND M10 VCCIO2/VCCIO5 VCCIO3/VCCIO7 K3
CY7C68013A_TQFP100 VCCIO2/VCCIO4 VCCIO3/VCCIO6
P2 E1
GNDIO2/GNDIO5 GNDIO3/GNDIO7
GND N11 L2
GNDIO2/GNDIO4 GNDIO3/GNDIO6
P9 F1
2 4 GND GND
A GND MACHXO-640/1200-132csBGA GND
A
C340
1uF VCC3V3 FB0302 VCC3V3_CONF
BLM18PG600SN1 VCC3V3
1 2
1
1
+ C0307 C0308 C0309 C0310 C0311 C0312 C0313 C0314 C0315 C0316 C0317 C0318 C0319 C0320 C0321 C0322 C0323 + C0324
2u20 100n 100n 100n 100n 100n 100n 100n 1n00 100n 100n 100n 100n 100n 100n 100n 1n00 4u70
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 3 _ F PG A_ Co n f
2
2

GND GNDA_CONF Authors: csam Thursday, July 10, 2008
GND GNDA_CONF GND IFW: 13:36:54
5 4 3 2 1
5 4 3 2 1 Figure 22.
Offpage DDR SDRAM socket (32 bit data bus) Parallel Flash SRAM
VCC2V5
Series Resistors (2 x 128 Mbit organized as 8M words of 32 bits) (2 x 4 Mbit organized as 256k words of 32 bits)
DDR_DQ[31:0] U0401 RN04011 CN1j 4 JTA 22R
2 DDR_DQ[31:0] DDR_VREF SODIMM_DQ0 DDR_DQ0
5 4 5 4
DDR_DQS[3:0] VDDQ VREF DDR_VTT SODIMM_DQ4 DDR_DQ4
6 3 6 3
2 DDR_DQS[3:0] AVIN VSENSE
7 8 SODIMM_DQ1 7 2 DDR_DQ1
DDR_DM[3:0] PVIN VTT
2 1 SODIMM_DQ5 8 1 DDR_DQ5
2 DDR_DM[3:0] GND NC VCC3V3
DDR_A[13:0] C0401 LP2995MR C0402 C0403
Flash LOW
RN04012 CN1j 4 JTA 22R
2 DDR_A[13:0] 47u 220u 100n SODIMM_DQ2 DDR_DQ2
5 4 Async. SRAM LOW
D SODIMM_DQ6 6 3 DDR_DQ6 D
DDR_CK0+ SODIMM_DQ3 7 2 DDR_DQ3 MEMORY_A[17:0] MEMORY_DQ[15:0]
2 DDR_CK0+ MEMORY_A[22:0] MEMORY_DQ[15:0]
DDR_CK0- SODIMM_DQ7 8 1 DDR_DQ7 U0404
29
43
2 DDR_CK0- GND GND U0402 MEMORY_A0 MEMORY_DQ0
1 7
A0 IO1
2 DDR_CK1+
DDR_CK1+ R0401 22R0 MEMORY_A0 31 35 MEMORY_DQ0 MEMORY_A1 2 8 MEMORY_DQ1
A0 DQ0 A1 IO2
Vio
Vcc
DDR_CK1- SODIMM_DQS0 1 2 DDR_DQS0 MEMORY_A1 26 37 MEMORY_DQ1 MEMORY_A2 3 9 MEMORY_DQ2
2 DDR_CK1- VCC2V5 VCC2V5 MEMORY_A2 A1 DQ1 MEMORY_DQ2 MEMORY_A3 A2 IO3 MEMORY_DQ3
25 39 4 10
DDR_CKE0 R0402 22R0 MEMORY_A3 A2 DQ2 MEMORY_DQ3 MEMORY_A4 A3 IO4 MEMORY_DQ4
24 41 5 13
2 DDR_CKE0 DDR_CKE1 X5A SODIMM_DM0 DDR_DM0 MEMORY_A4 A3 DQ3 MEMORY_DQ4 MEMORY_A5 A4 IO5 MEMORY_DQ5
1 2 23 44 18 14
2 DDR_CKE1 MEMORY_A5 A4 DQ4 MEMORY_DQ5 MEMORY_A6 A5 IO6 MEMORY_DQ6
22 46 19 15
DDR_BA0 DDR_VREF DDR_VREF RN04021 CN1j 4 JTA 22R MEMORY_A6 A5 DQ5 MEMORY_DQ6 MEMORY_A7 A6 IO7 MEMORY_DQ7
1 2 21 48 20 16
2 DDR_BA0 DDR_BA1 Vref Vref SODIMM_DQ8 DDR_DQ8 MEMORY_A7 A6 128 Megabit DQ6 MEMORY_DQ7 MEMORY_A8 A7 IO8 MEMORY_DQ8
3 4 5 4 20 50 21 29
2 DDR_BA1 SODIMM_DQ0 Vss Vss SODIMM_DQ4 SODIMM_DQ12 DDR_DQ12 MEMORY_A8 A7 (x16) DQ7 MEMORY_DQ8 MEMORY_A9 A8 IO9 MEMORY_DQ9
5 6 6 3 10 36 22 30
DQ0 DQ4 A8 DQ8 A9 IO10
DDR_WE# SODIMM_DQ1 7 8 SODIMM_DQ5 SODIMM_DQ9 7 2 DDR_DQ9 MEMORY_A9 9 38 MEMORY_DQ9 MEMORY_A10 23 31 MEMORY_DQ10
2 DDR_WE# DQ1 DQ5 A9 DQ9 A10 IO11
DDR_RAS# 9 10 SODIMM_DQ13 8 1 DDR_DQ13 MEMORY_A10 8 40 MEMORY_DQ10 MEMORY_A11 24 32 MEMORY_DQ11
2 DDR_RAS# DDR_CAS# SODIMM_DQS0 Vdd Vdd SODIMM_DM0 MEMORY_A11 A10 DQ10 MEMORY_DQ11 MEMORY_A12 A11 IO12 MEMORY_DQ12
11 12 7 42 25 35
2 DDR_CAS# SODIMM_DQ2 DQS0 DM0 SODIMM_DQ6 RN04022 CN1j 4 JTA 22R MEMORY_A12 A11 DQ11 MEMORY_DQ12 MEMORY_A13 A12 IO13 MEMORY_DQ13
13 14 6 45 26 36
DDR_S0# DQ2 DQ6 SODIMM_DQ10 DDR_DQ10 MEMORY_A13 A12 DQ12 MEMORY_DQ13 VCC3V3 MEMORY_A14 A13 IO14 MEMORY_DQ14
15 16 5 4 5 47 27 37
2 DDR_S0# DDR_S1# SODIMM_DQ3 Vss Vss SODIMM_DQ7 SODIMM_DQ14 DDR_DQ14 MEMORY_A14 A13 DQ13 MEMORY_DQ14 MEMORY_A15 A14 IO15 MEMORY_DQ15
2 DDR_S1# 17 18 6 3 4 49 42 38
SODIMM_DQ8 DQ3 DQ7 SODIMM_DQ12 SODIMM_DQ11 DDR_DQ11 MEMORY_A15 A14 DQ14 MEMORY_DQ15 MEMORY_A16 A15 IO16
19 20 7 2 3 51 43
DQ8 DQ12 A15 DQ15/A-1 A16
21 22 SODIMM_DQ15 8 1 DDR_DQ15 MEMORY_A16 54 MEMORY_A17 44
DDR_VREF SODIMM_DQ9 Vdd Vdd SODIMM_DQ13 MEMORY_A17 A16 R0421 A17
23 24 19
2 DDR_VREF SODIMM_DQS1 DQ9 DQ13 SODIMM_DM1 R0403 22R0 MEMORY_A18 A17 MACRONIX 10K0 SRAM_CE#
25 26 18 6
DQS1 DM1 SODIMM_DQS1 DDR_DQS1 MEMORY_A19 A18 MX29LV128MBTI-90Q SRAM_BE1# CS#
27 28 1 2 11 40
SODIMM_DQ10 Vss Vss SODIMM_DQ14 MEMORY_A20 A19 SRAM_BE0# UB#
29 30 12 39
SODIMM_DQ11 31 DQ10 DQ14 32 SODIMM_DQ15 R0404 22R0 MEMORY_A21 15 A20 17 FLASH_RY/BY#_A LB#
DQ11 DQ15 SODIMM_DM1 DDR_DM1 MEMORY_A22 A21 RY/BY# FLASH_BYTE# MEMORY_OE#
33 34 1 2 2 53 41
MEMORY_A[22:0] SODIMM_CK0+ Vdd Vdd A22 BYTE# OE#
35 36
2 MEMORY_A[22:0] SODIMM_CK0- CK0+ Vdd R0405 22R0 VCC3V3 MEMORY_WE#
37 38 17
MEMORY_DQ[31:0] CK0- Vss SODIMM_CK0+ DDR_CK0+ FLASH_CE# WE#
39 40 1 2 32 30
2 MEMORY_DQ[31:0] Vss Vss MEMORY_OE# 34 CE# NC 1 11 12
R0406 22R0 MEMORY_WE# OE# NC VCC GND
13 27 33 34
MEMORY_OE# DDR_SODIMM200 SODIMM_CK0- DDR_CK0- FLASH_WP#/ACC WE# NC VCC GND
1 2 16 28
2 MEMORY_OE# MEMORY_WE# FLASH_RESET# WP#/ACC NC GND
14 55
2 MEMORY_WE#
RN04031 CN1j 4 JTA 22R RESET# NC K6R4016V1D-UI10
56
Vss
Vss
X5B SODIMM_DQ16 DDR_DQ16 NC SAMSUNG
5 4
FLASH_CE# SODIMM_DQ20 6 3 DDR_DQ20
2 FLASH_CE#
33
52
FLASH_RESET# SODIMM_DQ16 41 42 SODIMM_DQ20 SODIMM_DQ17 7 2 DDR_DQ17
2 FLASH_RESET# DQ16 DQ20
2 FLASH_RY/BY#_A
FLASH_RY/BY#_A SODIMM_DQ17 43 44 SODIMM_DQ21 SODIMM_DQ21 8 1 DDR_DQ21
FLASH_RY/BY#_B DQ17 DQ21
45 46
2 FLASH_RY/BY#_B FLASH_WP#/ACC SODIMM_DQS2 47 Vdd Vdd 48 SODIMM_DM2 RN04032 CN1j 4 JTA 22R
2 FLASH_WP#/ACC FLASH_BYTE# SODIMM_DQ18 DQS2 DM2 SODIMM_DQ22 SODIMM_DQ18 DDR_DQ18
49 50 5 4
C 2 FLASH_BYTE# DQ18 DQ22 SODIMM_DQ22 DDR_DQ22 GND C
51 52 6 3
SODIMM_DQ19 Vss Vss SODIMM_DQ23 SODIMM_DQ19 DDR_DQ19
53 54 7 2
DQ19 DQ23
SRAM_BE0# SODIMM_DQ24 55 56 SODIMM_DQ28 SODIMM_DQ23 8 1 DDR_DQ23
2 SRAM_BE0# SRAM_BE1# DQ24 DQ28
57 58
2 SRAM_BE1# SRAM_BE2# SODIMM_DQ25 Vdd Vdd SODIMM_DQ29 R0407 22R0
59 60
2 SRAM_BE2# SRAM_BE3# SODIMM_DQS3 DQ25 DQ29 SODIMM_DM3 SODIMM_DQS2 DDR_DQS2
61 62 1 2
2 SRAM_BE3# SRAM_CE# DQS3 DM3
63 64
2 SRAM_CE# SODIMM_DQ26 Vss Vss SODIMM_DQ30 R0408 22R0 VCC3V3
65 66
SODIMM_DQ27 67 DQ26 DQ30 68 SODIMM_DQ31 SODIMM_DM2 1 2 DDR_DM2
DQ27 DQ31 Flash HIGH
69 70
Vdd Vdd RN04041 CN1j 4 JTA 22R
71 72 Async. SRAM HIGH
- Place C0401 as close as possible to the PVIN CB0/NC CB4/NC SODIMM_DQ24 DDR_DQ24
73 74 5 4
CB1/NC CB5/NC SODIMM_DQ28 DDR_DQ28 MEMORY_A[22:0] MEMORY_DQ[31:16] MEMORY_A[17:0] MEMORY_DQ[31:16]
pin 75 76 6 3
29
43
77 Vss Vss 78 SODIMM_DQ25 7 2 DDR_DQ25 U0403 U0405
- Place C0403 as close as possible to the VREF DQS8/NC DM8/NC
pin 79 80 SODIMM_DQ29 8 1 DDR_DQ29 MEMORY_A0 31 35 MEMORY_DQ16 MEMORY_A0 1 7 MEMORY_DQ16
CB2/NC CB6/NC A0 DQ0 A0 IO1
Vio
Vcc
- Place a bulk cap (100-220 µF) capacitor at 81 82 MEMORY_A1 26 37 MEMORY_DQ17 MEMORY_A1 2 8 MEMORY_DQ17
Vdd Vdd A1 DQ1 A1 IO2
each end of the VTT island. (C04??, C04??) 83 84 RN04042 CN1j 4 JTA 22R MEMORY_A2 25 39 MEMORY_DQ18 MEMORY_A2 3 9 MEMORY_DQ18
CB3/NC CB7/NC A2 DQ2 A2 IO3
NC NC A3 DQ3 A3 IO4
Vss Vss A4 DQ4 A4 IO5
CK2+/NC Vss A5 DQ5 A5 IO6
CK2-/NC Vdd MEMORY_A7 A6 128 Megabit DQ6 MEMORY_DQ23 MEMORY_A7 A6 IO7 MEMORY_DQ23
93 94 20 50 20 16
49
Parallel Termination Resistors SODIMM_CKE1 Vdd Vdd SODIMM_CKE0 R0409 22R0 MEMORY_A8 A7 (x16) DQ7 MEMORY_DQ24 MEMORY_A8 A7 IO8 MEMORY_DQ24
95 96 10 36 21 29
R0413 33R0 97 CKE1/NC CKE0 98 SODIMM_DQS3 1 2 DDR_DQS3 MEMORY_A9 9 A8 DQ8 38 MEMORY_DQ25 MEMORY_A9 22 A8 IO9 30 MEMORY_DQ25
NC NC A9 DQ9 A9 IO10
SODIMM_DQS0 1 2 SODIMM_A12 99 100 SODIMM_A11 MEMORY_A10 8 40 MEMORY_DQ26 MEMORY_A10 23 31 MEMORY_DQ26
SODIMM_A9 A12/NC A11 SODIMM_A8 R0410 22R0 MEMORY_A11 A10 DQ10 MEMORY_DQ27 MEMORY_A11 A10 IO11 MEMORY_DQ27
101 102 7 42 24 32
R0414 33R0 A9 A8 SODIMM_DM3 DDR_DM3 MEMORY_A12 A11 DQ11 MEMORY_DQ28 MEMORY_A12 A11 IO12 MEMORY_DQ28
103 104 1 2 6 45 25 35
SODIMM_DM0 SODIMM_A7 Vss Vss SODIMM_A6 MEMORY_A13 A12 DQ12 MEMORY_DQ29 VCC3V3 MEMORY_A13 A12 IO13 MEMORY_DQ29
1 2 105 106 5 47 26 36
SODIMM_A5 A7 A6 SODIMM_A4 RN04051 CN1j 4 JTA 22R MEMORY_A14 A13 DQ13 MEMORY_DQ30 MEMORY_A14 A13 IO14 MEMORY_DQ30
107 108 4 49 27 37
RN0408 CND1J 10K JTA 33R SODIMM_A3 A5 A4 SODIMM_A2 SODIMM_CKE1 DDR_CKE1 MEMORY_A15 A14 DQ14 MEMORY_DQ31 MEMORY_A15 A14 IO15 MEMORY_DQ31
109 110 5 4 3 51 42 38
SODIMM_DQ0 DDR_VTT SODIMM_A1 A3 A2 SODIMM_A0 SODIMM_CKE0 DDR_CKE0 MEMORY_A16 A15 DQ15/A-1 MEMORY_A16 A15 IO16
1 10 111 112 6 3 54 43
SODIMM_DQ1 SODIMM_DQ4 A1 A0 SODIMM_A12 DDR_A12 MEMORY_A17 A16 R0422 MEMORY_A17 A16
2 9 113 114 7 2 19 44
Vdd Vdd A17 MACRONIX A17
SODIMM_DQ2 3 8 SODIMM_DQ5 SODIMM_A10 115 116 SODIMM_BA1 SODIMM_A11 8 1 DDR_A11 MEMORY_A18 18 10K0
SODIMM_DQ3 4 7 SODIMM_DQ6 SODIMM_BA0 117 A10/AP BA1 118 SODIMM_RAS# MEMORY_A19 A18 MX29LV128MBTI-90Q SRAM_CE#
11 6
DDR_VTT SODIMM_DQ7 SODIMM_WE# BA0 RAS# SODIMM_CAS# RN04052 CN1j 4 JTA 22R MEMORY_A20 A19 SRAM_BE3# CS#
5 6 119 120 12 40
SODIMM_S0# WE# CAS# SODIMM_S1# SODIMM_A9 DDR_A9 MEMORY_A21 A20 FLASH_RY/BY#_B SRAM_BE2# UB#
121 122 5 4 15 17 39
R0415 33R0 SODIMM_A13 S0# S1#/NC SODIMM_A8 DDR_A8 MEMORY_A22 A21 RY/BY# FLASH_BYTE# LB#
123 124 6 3 2 53
SODIMM_DQS1 A13/NC NC SODIMM_A7 DDR_A7 A22 BYTE# MEMORY_OE#
1 2 125 126 7 2 41
Vss Vss OE#
127 128 SODIMM_A6 8 1 DDR_A6
R0416 33R0 DQ32 DQ36 FLASH_CE# VCC3V3 MEMORY_WE#
129 130 32 30 17
SODIMM_DM1 DQ33 DQ37 RN04061 CN1j 4 JTA 22R MEMORY_OE# CE# NC WE#
1 2 131 132 34 1
Vdd Vdd SODIMM_A5 DDR_A5 MEMORY_WE# OE# NC
B 133 134 5 4 13 27 11 12 B
RN0409 CND1J 10K JTA 33R DQS4 DM4 SODIMM_A4 DDR_A4 FLASH_WP#/ACC WE# NC VCC GND
135 136 6 3 16 28 33 34
SODIMM_DQ8 1 DDR_VTT DQ34 DQ38 SODIMM_A3 DDR_A3 FLASH_RESET# WP#/ACC NC VCC GND
10 137 138 7 2 14 55
Vss Vss RESET# NC
SODIMM_DQ9 2 9 SODIMM_DQ12 139 140 SODIMM_A2 8 1 DDR_A2 56 GND
NC
Vss
Vss
DQ35 DQ39
SODIMM_DQ10 3 8 SODIMM_DQ13 141 142 K6R4016V1D-UI10
SODIMM_DQ11 SODIMM_DQ14 DQ40 DQ44 RN04062 CN1j 4 JTA 22R SAMSUNG
4 7 143 144
Vdd Vdd
33
52
DDR_VTT 5 6 SODIMM_DQ15 145 146 SODIMM_A1 5 4 DDR_A1

147 DQ41 DQ45 148 SODIMM_A0 6 3 DDR_A0
R0417 33R0 DQS5 DM5 SODIMM_A10 DDR_A10
149 150 7 2
Vss Vss
SODIMM_DQS2 1 2 151 152 SODIMM_BA1 8 1 DDR_BA1
DQ42 DQ46
153 154
R0418 33R0 DQ43 DQ47 RN04071 CN1j 4 JTA 22R GND
155 156
SODIMM_DM2 1 2 157 Vdd Vdd 158 SODIMM_CK1- SODIMM_BA0 5 4 DDR_BA0
Vdd CK1- SODIMM_CK1+ SODIMM_RAS# DDR_RAS#
159 160 6 3
RN0410 CND1J 10K JTA 33R Vss CK1+ SODIMM_WE# DDR_WE#
161 162 7 2
Vss Vss
SODIMM_DQ16 1 10 DDR_VTT 163 164 SODIMM_CAS# 8 1 DDR_CAS#
2 9 165 166
DQ49 DQ53
SODIMM_DQ18 3 8 SODIMM_DQ21 167 168 RN04072 CN1j 4 JTA 22R
SODIMM_DQ19 SODIMM_DQ22 Vdd Vdd SODIMM_S0# DDR_S0#
4 7 169 170 5 4
DDR_VTT SODIMM_DQ23 DQS6 DM6 SODIMM_S1# DDR_S1# VCC3V3 VCC3V3
5 6 171 172 6 3
173 174 7 2
Vss Vss
R0419 33R0 175 176 8 1
SODIMM_DQS3 1 2 177 DQ51 DQ55
178
DQ56 DQ60 R0411 22R0
179 180
R0420 33R0 Vdd Vdd SODIMM_CK1- DDR_CK1-
181 182 1 2
1
1
1
1
1
1
1
1
SODIMM_DM3 DQ57 DQ61

1 2 183 184
DQS7 DM7 R0412 22R0 C0404 C0405 C0406 C0407 C0408 C0409 C0410 C0411
185 186
RN0411 CND1J 10K JTA 33R Vss Vss SODIMM_CK1+ DDR_CK1+ 4u70 100n 4u70 100n 4u70 100n 4u70 100n
187 188 1 2
2
2
2
2
2
2
2
2
SODIMM_DQ24 DDR_VTT DQ58 DQ62

1 10 189 190
2 9 191 192
Vdd Vdd
SODIMM_DQ27 SODIMM_DQ30 SDA SA0
4 7 195 196
DDR_VTT 5 6 SODIMM_DQ31 197 SCL SA1
198 GND GND
Vddspd SA2
199 200
RN0412 CND1J 10K JTA 33R Vddid NC
SODIMM_CKE1 1 10 DDR_VTT
SODIMM_A12 2 9 SODIMM_CKE0 DDR_SODIMM200
SODIMM_A9 3 8 SODIMM_A11 GND GND
DDR_VTT 5 6 SODIMM_A6
A RN0413 CND1J 10K JTA 33R A

SODIMM_A5 1 10 DDR_VTT DDR_VTT DDR_VTT DDR_VREF
SODIMM_A10 4 7 SODIMM_A0 C0416 C0417 C0418 C0419 C0420 C0421 C0422 C0414 C0415 C0412 C0413
DDR_VTT 5 6 SODIMM_BA1 220u 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

SODIMM_BA0 1 10 DDR_VTT
SODIMM_WE# 2 9 SODIMM_RAS# GND GND GND
SODIMM_S0# 3 8 SODIMM_CAS# Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 4 _ Me mo r y
SODIMM_A13 4 7 SODIMM_S1# Revision: R01 Last modified:
DDR_VTT 5 6 Authors: csam Monday, September 04, 2006
IFW: 10:15:10
5 4 3 2 1
5 4 3 2 1
VCC3V3
Figure 23.
Offpage 8x LED Single Step VCC3V3
2
2
2
2
2
2
2
2
VCC3V3
R0501 R0502 R0503 R0504 R0505 R0506 R0507 R0508
SEG_CA0# Key R0509
2 SEG_CA0# SEG_CA1# 330R 330R 330R 330R 330R 330R 330R 330R SW0501 100K U0501
5
2 SEG_CA1# SEG_A# B3FS-1012
1
1
1
1
1
1
1
1
2 SEG_A#
SEG_B# 1 3 2
2 SEG_B# SEG_C# TST_STEP
4
2 SEG_C# SEG_D# LD0501 LD0502 LD0503 LD0504 LD0505 LD0506 LD0507 LD0508 R0510 1 nc
2 SEG_D# SEG_E# LED red LED red LED red LED red LED red LED red LED red LED red 100K C0501
2 SEG_E# SEG_F# 100n
3
2 SEG_F# SEG_G# 2 4 74AHC1G14_SOT353
2 SEG_G# SEG_DP#
D 2 SEG_DP# D
GND GND GND
LED0# LED0# LED1# LED2# LED3# LED4# LED5# LED6# LED7#
2 LED0#
LED1#
2 LED1# LED2#
2 LED2# LED3#
2 LED3# LED4#
2 LED4# LED5# TP0501
2 LED5# LED6# nb_TEST POINT
2 LED6# LED7#
1
1
1
1
1
1
1
1
2 LED7#
1
TST_ROW0 TP0502 TP0503 TP0504 TP0505 TP0506 TP0507 TP0508 TP0509
2 TST_ROW0 TST_ROW1 nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT nb_TEST POINT Key Matrix
2 TST_ROW1 TST_ROW2 GND

2 TST_ROW2 TST_ROW3
2 TST_ROW3 TST_COL0
2 TST_COL0 TST_COL1
2 TST_COL1 TST_COL2
2 TST_COL2
TST_STEP
2 TST_STEP
TST_COL0
TST_COL1
TST_COL2
SW0502 SW0503 SW0504
B3FS-1012 B3FS-1012 B3FS-1012
DSW0 1 3 1 3 1 3
2 DSW0 DSW1 VCC3V3
2 DSW1 DSW2
2 DSW2 7-Segment Display
DSW3
2 DSW3
2
R0511 2 4 2 4 2 4
LCD_REGSEL SEG_CA0# 2 1 SEG_CA0#_B 1 BC807-25
2 LCD_REGSEL LCD_RW Q0501
2 LCD_RW LCD_ENABLE 1K00 D0501 D0502 D0503
3
2 LCD_ENABLE MMBD4148 MMBD4148 MMBD4148
2
R0513 TST_ROW0
1
SEG_CA1# 2 1 SEG_CA1#_B 1 BC807-25
Q0502 R0512
1K00 1K00 SW0505 SW0506 SW0507
3
B3FS-1012 B3FS-1012 B3FS-1012
2
C 1 3 1 3 1 3 C
GND
R0514
2 4 2 4 2 4
SEG_CA1#_X
SEG_CA0#_X
SEG_A# 2 1 SEG_A#_X
R0515 120R
10
5
SEG_B# 2 1 SEG_B#_X U0502 D0504 D0505 D0506
120R R0516 TST_ROW1
1
SEG_C# 2 1 SEG_C#_X
C.A. D1
C.A. D2
7 R0517
R0518 120R A SW0508 SW0509 SW0510
6 D1 D2 1K00
SEG_D# 2 1 SEG_D#_X 4 B B3FS-1012 B3FS-1012 B3FS-1012
C A
1
2
D 1 3 1 3 1 3
120R R0519 3
E
SEG_E# 2 1 SEG_E#_X 8 F B
F GND
9
R0520 120R G G
2
SEG_F# SEG_F#_X DP 2 4 2 4 2 4
2 1
E C
120R R0521
50
SEG_G# 2 1 SEG_G#_X D0507 D0508 D0509
D DP
R0522 120R TST_ROW2
1
SEG_DP# 2 1 SEG_DP#_X
ELD-426SYGWA/S530-E2 R0523
120R 1K00 SW0511 SW0512 SW0513
B3FS-1012 B3FS-1012 B3FS-1012
2
1 3 1 3 1 3
GND
2 4 2 4 2 4
VCC5V0 D0510 D0511 D0512

LCD Connector TST_ROW3
1
1
B R0524 R0525 B
10K0 1K00
2
2
VCC5V0
X7 GND
R0526 GND 1 2
5K LCD_CONT 3 4 LCD_REGSEL
Display LCD_RW 5 6 LCD_ENABLE
Contrast SEG_A# 7 8 SEG_B#
SEG_C# 9 10 SEG_D#
SEG_E# 11 12 SEG_F#
GND VCC5V0 SEG_G# 13 14 SEG_DP#
15 16 VCC3V3
CON16A 4x DIP Switch SW0514
1
2
GND RP0501
DSW0 1 8
DSW1 2 7
DSW2 3 6
X6 DSW3 4 5
HDR2
LCD Backlight on/off RP0502 1K0
1 8 SW DIP-4
2 7
3 6
4 5
10K0
GND
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 5 _ L ED_ KEY

IFW: 10:15:09
5 4 3 2 1
5 4 3 2 1 Figure 24.
Offpage VCC3V3
VCC3V3
Reset Control VCC3V3 VCC5V0
R0603
CLK_FPGA 10K0
2 CLK_FPGA
CLK_ETH U0602
5
8 CLK_ETH
R0601 U0601
EXPCON_OSC 27K0 8 7 CAT_RESET 2
9 EXPCON_OSC VCC RESET HPE_RESET#
4
CLK_MACHXO CAT_I2C_SCL 6 2 CAT_RESET# 1
3 CLK_MACHXO SCL RESET nc
X8 CAT_I2C_SDA 5
Ext. Reset C0601 CAT_VSENSE SDA
1 3 1
3
2 100n 1.25 V VSENSE VLOW 74AHC1G14_SOT353
D 2,3 HPE_RESET#
HPE_RESET# 4
GND
D
nb_HDR2 R0604
D0601
HPE_RESOUT# CAT1026SI-30 100K
2,7,8,9 HPE_RESOUT# GND 1 R0602 GND
10K7
SW0601 3
I2C_SDA1 B3FS-1012
2 I2C_SDA1 I2C_SCL1 1 3 2
2 I2C_SCL1 GND
Reset Vth = 1.25V x (R0601+R0602)/R0602 = 4.4V
Button BAT54A GND
2 4
GND
VCC3V3 VCC3V3
VCC3V3
1
1
R0605 R0606 R0607 R0608 R0609
10K0 nb_10K0 nb_10K0 2K7 2K7 Rp of the I2C bus
R0610 22R0
2
2
HPE_RESOUT# CAT_I2C_SCL I2C_SCL1
R0611 22R0
CAT_I2C_SDA I2C_SDA1
Rs of the I2C bus

C C
Clock Sources
VCC3V3 FB0601 VCC3V3_OSC R0612
BLM21PG331SN1D VCC3V3_OSC CLK_FPGA
1 2
33R0
51
U0603 U0604
1 4 6 3 R0613
EN VCC VDD OUT1 CLK_ETH
2 5
CLK OE OUT2
2 3 1 7
GND CLK BUF_IN OUT3
C0602 C0603 4 8 33R0
1n00 100n OSC_SMT4_25MHz GND OUT4
CY2304NZ_TSSOP8 R0614
GND CLK_MACHXO
VCC3V3_OSC 33R0
GND GND
TP0601 R0615
TEST POINT 1 EXPCON_OSC
C0604 CLK
100n 33R0
GND
B B
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 6 _ Clo ck_ Re se t

IFW: 10:15:09
5 4 3 2 1
5 4 3 2 1 Figure 25.
Offpage RS232 Interface
GND X9
5 VCC3V3
9
RS_TXD_LVTTL U0701 RS_DTP_LVTTL_X 4
2 RS_TXD_LVTTL RS_RTS_LVTTL RS_TXD_LVTTL 11 14 RS_CTS_LVTTL_X 8
2 RS_RTS_LVTTL RS_RXD_LVTTL RS_RTS_LVTTL T1IN T1OUT RS_TXD_LVTTL_X C0701 C0702
2 RS_RXD_LVTTL 10 7 3
RS_CTS_LVTTL T2IN T2OUT RS_RTS_LVTTL_X 100n 10u0
7
2 RS_CTS_LVTTL RS_RXD_LVTTL RS_RXD_LVTTL_X
12 13 2
R1OUT R1IN
RS_CTS_LVTTL 9 8 6
R2OUT R2IN
1
VCC3V3 R0702 0R00
USB_GPIO[28:0] 1 16 1 2 RS_DSP_LVTTL_X CON_DSUB_9M GND
2 USB_GPIO[28:0]
3 C1+ VCC
D C1- R0701 0R00
D
2
USB_MISO V+ RS_DCD_LVTTL_X
4 15 1 2
2 USB_MISO USB_SSI# C2+ GND
5 6
2 USB_SSI#
USB_SCK C2- V-
2 USB_SCK USB_MOSI C0703 C0704 MAX3232/TSSOP C0705 C0706
2 USB_MOSI USB_TXD 100n 100n 100n 100n
2 USB_TXD USB_RXD
2 USB_RXD USB_RTS
2 USB_RTS USB_CTS
2 USB_CTS
USB_PWEN0 GND
2 USB_OC2#
USB_SCL
3 USB_SCL USB_SDA
3 USB_SDA
USB Controller
HPE_RESOUT#
2,6,8,9 HPE_RESOUT# VCC5V0
U0702 USB_GPIO[28:0]
EXT MEMORY GPIO
FB0701
99 94 USB_GPIO0
1 A0/BEL GPIO0/D0 93 USB_GPIO1 VCC3V3 C0707 USB_VBUS0 1 2 USB_VBUS0_X
A1 GPIO1/D1 USB_GPIO2 1u00
2 92
A2 GPIO2/D2 USB_GPIO3 USB_OTG_VBUS
3 91
A3 GPIO3/D3 USB_GPIO4 + C0708 C0709 BLM21PG331SN1D
7 90
1
1
1
A4 GPIO4/D4
8 89 USB_GPIO5 U0703 100u 100n
VCC3V3 17
A5 GPIO5/D5
87 USB_GPIO6 R0704 R0705 GNDA_USB 7 C0726 FB0705 1500mA
A6 GPIO6/D6 IN
20 86 USB_GPIO7 10K0 10K0 4u70 BLM21PG331SN1D
A7 GPIO7/D7 USB_GPIO8 330 Ohm @ 100 MHz
24 66
2
2
A8 GPIO8/MISO/D8
25 65 USB_GPIO9 USB_PWEN0 1 8
2
2
R0703 A9 GPIO9/SSI/D9 USB_GPIO10 USB_OC0# ENA OUTA X10
27 61 2
47K0 30 A10 GPIO10/SCK/D10 60 USB_GPIO11 FLGA GNDA_USB GND USB_OTG_VBUS_X 1 6
A11 GPIO11/MOSI/D11 FB0702 VBUS SH1
31 59 USB_GPIO12 USB_OC1# 3 USB_OTG_DM1A 2 7
C A12 GPIO12/D12 USB_GPIO13 USB_PWEN1 FLGB USB_VBUS1 USB_VBUS1_X USB_OTG_DP1A D- SH2 C
32 58 4 5 1 2 3
1
A13 GPIO13/D13 ENB OUTB D+ USB OTG
33 57 USB_GPIO14 USB_OTG_ID 4 8
USB_A15 A14 GPIO14/D14 USB_GPIO15 ID SH3
38 56 5 9
A15/CLKSEL GPIO15/SSI/D15 USB_GPIO16 + C0710 C0711 BLM21PG331SN1D GND SH4
97 55 6
A16 GPIO16/TXD/I_A0 USB_GPIO17 GND 100u 100n C0727 USB miniAB 440479-1
95 54
A17 GPIO17/RXD/I_A1 USB_GPIO18 SP2526-1EN nb_100n
96 53
A18 GPIO18/RTS/I_A2 USB_GPIO19 GNDA_USB
52
GPIO19/CS0/H_A0
83 50 USB_GPIO20
82 D0 GPIO20/CS1/H_A1 49 USB_GPIO21 VCC3V3
D1 GPIO21/nCS VCC5V0
81 48 USB_GPIO22 GND
D2 GPIO22/WR/IOW
80 47 USB_GPIO23 GNDA_USB X11A
1
D3 GPIO23/RD/IOR USB_GPIO24
79 46 13
D4 GPIO24/INT/IORDY USB_GPIO25 R0706 USB_VBUS0_X SHIELD
78 45 1A
77 D5 GPIO25 44 USB_GPIO26 15K0 USB_DM1B 2A VCC
D6 GPIO26/CTS/PWM3 USB_GPIO27 VCC3V3 C0712 USB_DP1B DATA- USB HOST
76 43 3A
USB_MISO D7 GPIO27/RX USB_GPIO28 1u00 DATA+
74 42 4A
2
USB_SSI# D8/MISO GPIO28/TX USB_OTG_ID GND
73 41 14
USB_SCK D9/SSI GPIO29/OTGID USB_SCL SHIELD
72 40
1
USB_MOSI 71 D10/SCK GPIO30/SCL 39 USB_SDA U0704 USB_TypeA/Host
USB_TXD D11/MOSI GPIO31/SDA R0707 GNDA_USB
70 7
USB_RXD D12/TXD 10K0 IN
69 FB0703
USB_RTS D13/RXD X11B
68
52
D14/RTS
USB_CTS 67 USB_PWEN2 1 8 USB_VBUS2 1 2 USB_VBUS2_X 15
2
D15/CTS USB_OC2# 2 ENA OUTA USB_VBUS1_X 1B SHIELD
EXT MEMORY CONTROL FLGA USB_DM2A VCC
2B
+ C0713 C0714 BLM21PG331SN1D USB_DP2A DATA- USB HOST
98 34 3 3B
BEH MEMSEL FLGB 100u 100n DATA+
64 35 4 5 4B
WR ROMSEL ENB OUTB GND
62 36 16
RD RAMSEL SHIELD
USB PORTS 6 USB_TypeA/Host
USB_OTG_DM1A USB_DM2A GND
22 9
USB_OTG_DP1A DM1A DM2A USB_DP2A SP2526-1EN
23 10
USB_DM1B DP1A DP2A USB_DM2B GNDA_USB GNDA_USB X11C
18 4
USB_DP1B DM1B DM2B USB_DP2B
19 5
DP1B DP2B USB_VBUS2_X 1C
USB_DM2B VCC
VCC3V3_USB 21 6 2C
AVCC AGND USB_DP2B DATA- USB HOST
3C
D0701 CHARGE PUMP GNDA_USB VCC3V3 VCC3V3 DATA+
4C
BAT54S USB_OTG_VBUS GND
11 16 VCC3V3
OTGVBUS BOOSTVCC
2 1 13 15
1
1
CSWITCHA BOOSTGND USB_TypeA/Host

12 14
CSWITCHB VSWITCH GND RJ0701 RJ0703
3
2
2
B RESET / CLOCK nb_10K0 nb_10K0 GNDA_USB GNDP
B
C0724 HPE_RESOUT# 85 29 USB_XTALIN Q0701 R0708
RESET XTALIN
100n C0725 100n 84 28 USB_XTALOUT nb_1M00
2
2
RESERVED XTALOUT CRYSTAL_12MHz

USB_SCL
1
GND POWER USB_SDA
1
VCC3V3 37 26
1
1
VCC GND
63 51
VCC GND
GNDA_USB 88 75 C0715 C0716 RJ0702 RJ0704
VCC GND 22p0 22p0 0R00 0R00
100
GND
CY7C67300_TQFP100
2
2
GND
GND GND GND
GND GNDA_USB
Boot Configuration Interface GPIO31 GPIO30
VCC3V3 FB0704 VCC3V3_USB SDA SCL
BLM18PG600SN1 Host Port Interface (HPI) 0 0
1 2 High-Speed Serial (HSS) 0 1
Serial Peripheral Interface (SPI) 1 0
I2C EEPROM (Standalone Mode) 1 1
C0717 C0718 C0719 C0720 C0721 C0722 C0723
10u0 100n 100n 100n 100n 100n 1n00
GND GNDA_USB
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 7 _ Se r ia l_ USB

IFW: 10:15:10
5 4 3 2 1
5 4 3 2 1 Figure 26.
Offpage Ethernet
VCC3V3_LAN
8
7
6
5
GND
ETH_TXER RP0801
2 ETH_TXER ETH_TXD3 10k0
2
2 ETH_TXD3 ETH_TXD2
2 ETH_TXD2
ETH_TXD1 U0801 FB0801 VCC3V3
1
2
3
4
2 ETH_TXD1 ETH_TXD0
2 ETH_TXD0 BLM11B750S
ETH_TXER 54 19
1
ETH_TXEN ETH_TXD3 TX_ER TPFOP
60
2
2 ETH_TXEN ETH_TXCLK ETH_TXD2 TXD3 U0802
2 ETH_TXCLK 59 20
ETH_TXD1 TXD2 TPFON LAN_TX+ X12 R0801
58 1 12
ETH_TXD0 TXD1 TD+ TX+ 220R
57 3 10 13
D ETH_RXER TXD0 LAN_TX- CT_TD CT_TX ETH_TX+ SHIELD D
2 11 1
1
2 ETH_RXER R0802 TD- TX- TX+
ETH_RXD3 ETH_TXEN 56 ETH_TX- 2 9
2
2 ETH_RXD3 ETH_RXD2 ETH_TXCLK ETH_TXCLK0 TX_EN ETH_RX+ TX- LED2+ ETH_CFG1
2 ETH_RXD2 2 1 55 3 10
TX_CLK RX+ LED2-
2 ETH_RXD1
ETH_RXD1 LAN_RX+ 5 8 4 R0803
ETH_RXD0 22R0 C0801 270p 4 RD+ RX+ 9 5 nc 220R
2 ETH_RXD0 ETH_RXER LAN_RX- CT_RD CT_RX ETH_RX- nc
53 23 1 2 6 7 6 11
1
ETH_RXD3 RX_ER TPFIP VCC3V3 RD- RX- RX- LED1+ ETH_CFG3
45 7 12
RXD3 nc LED1-
ETH_RXCLK ETH_RXD2 46 24 1 2 PULSE H1112 8
2 ETH_RXCLK ETH_RXDV ETH_RXD1 RXD2 TPFIN nc
2 ETH_RXDV 47 14
ETH_RXD0 RXD1 C0802 270p SHIELD
48
1
1
ETH_CRS RXD0 GNDP RJ-45-LED VCC3V3
2
2
1
1
1
1
2 ETH_CRS R0806
ETH_COL R0804 R0805
2 ETH_COL ETH_RXCLK ETH_RXCLK0 nb_10K0 nb_10K0 R0807 R0808 R0809 R0810 R0811 R0812
2 1 52 26
ETH_RXDV RX_CLK SD/TP 49R9 49R9 49R9 49R9 49R9 49R9
49 2
ETH_MDINTR# 22R0 RX_DV
2
2
2
2
2
2
2 ETH_MDINTR# ETH_CRS GND R0813
63 5
1
1
ETH_MDC ETH_COL CRS TxSLEW0 220R
62 6
1
1
1
1
2 ETH_MDC ETH_MDIO COL TxSLEW1 C0803 C0804
1
11
2 ETH_MDIO CLK_ETH R0816 22K1 C0805 100n 100n R0814 R0815 LED0801
1
2
2
REFCLK/XI 10n0 49R9 49R9 LED red
17 2 1
2
2
HPE_RESOUT# RBIAS R0817 R0818
2
2
2
2
2,6,7,9 HPE_RESOUT# XO 10K0 10K0
2
CLK_ETH 38 ETH_CFG1 GND
1
1
1
6 CLK_ETH LED/CFG1
ETH_MDINTR# 64 37 ETH_CFG2 ETH_CFG2
1
1
MDINT# LED/CFG2 36 ETH_CFG3 C0806 C0807 C0808
ETH_MDC LED/CFG3 1n00 1n00 1n00
43
2
2
2
ETH_MDIO MDC C0809 2kV 2kV 2kV
42
MDIO GND
3 27 2 1
MDDIS TDI
28
HPE_RESOUT# 4 TDO 29 220n
VCC3V3 RESET# TMS GNDP
30
TCK GND_LAN
39 31
8
7
6
5
PWRDWN TRST
RP0802 33
1
1
1
10k0 PAUSE TxSLEW0 TxSLEW1 Slew Rate
16
RJ0801 RJ0803 RJ0805 VCC3V3 ADDR4
32 15
nb_10K0 nb_10K0 nb_10K0 SLEEP ADDR3 0 0 2.5ns
14
1
2
3
4
ADDR2 0 1 3.1ns
13
ADDR1 1 0 3.7ns
9 12
2
2
2
GND nc ADDR0 1 1 4.3ns
10
nc
44 34
C nc TEST0 C
35
VCC3V3 TEST1
2
2
2
51 61
RJ0802 RJ0804 RJ0806 VCCD DGND
50
DGND
10K0 10K0 10K0 8 41
VCC3V3_LAN VCCIO DGND
40 25
VCCIO DGND
18
1
1
1
21 DGND 11
VCCA DGND
22 7
VCCA DGND
GND
LXT971A
GND
VCC3V3 VCC3V3_LAN
GND GND_LAN
FB0802 C0810 C0813
BLM18PG600SN1 220n 10n0
1 2
1
1
53
2
2
GND_LAN
B B
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 8 _ Eth e r n e t

IFW: 10:15:10
5 4 3 2 1
5 4 3 2 1 Figure 27.
Offpage Expansion Connector Prototyping Area (RM2.54) of FPGA
EXPCON_IO[45:0]
2 EXPCON_IO[45:0]
CARDSEL# VCC3V3
2 CARDSEL#
EXPCON_CLKIN
2 EXPCON_CLKIN EXPCON_CLKOUT BB3V3_IO[21:0]
2 EXPCON_CLKOUT BB3V3_IO[21:0]
EXPCON_OSC VCC2V5 TP0901 TP0913 TP0925 TP0937 TP0949 TP0961 TP0973 TP0985 TP0997 TP09109 TP09121 TP09133
6 EXPCON_OSC BB3V3_IO0 BB3V3_IO12
1
HPE_RESOUT#
D 2,6,7,8 HPE_RESOUT# R0901
D
0R00 TP0902 TP0914 TP0926 TP0938 TP0950 TP0962 TP0974 TP0986 TP0998 TP09110 TP09122 TP09134
Pin 2 removed for coding BB3V3_IO1 BB3V3_IO13
BB3V3_IO[21:0] of expansion board
2
2 BB3V3_IO[21:0]
X13
BB3V3_CLK0+ 1 2 TP0903 TP0915 TP0927 TP0939 TP0951 TP0963 TP0975 TP0987 TP0999 TP09111 TP09123 TP09135
2 BB3V3_CLK0+ BB3V3_CLK0- EXPCON_2V5 EXPCON_IO29 BB3V3_IO2 BB3V3_IO14
3 4
2 BB3V3_CLK0- EXPCON_IO30 EXPCON_IO31
5 6
GND EXPCON_IO32 7 8 EXPCON_IO33
SATA_X1D0+ EXPCON_IO36 11 12 EXPCON_IO37 BB3V3_IO3 BB3V3_IO15
2 SATA_X1D0+ SATA_X1D0- EXPCON_IO38 EXPCON_IO39
13 14
2 SATA_X1D0- SATA_X1D1+ EXPCON_IO40 EXPCON_IO41
15 16
2 SATA_X1D1+ SATA_X1D1- EXPCON_IO42 EXPCON_IO43 TP0905 TP0917 TP0929 TP0941 TP0953 TP0965 TP0977 TP0989 TP09101 TP09113 TP09125 TP09137
2 SATA_X1D1- 17 18
EXPCON_IO44 EXPCON_IO45 BB3V3_IO4 BB3V3_IO16
19 20
SATA_X2D0+ VCC5V0 21 22
2 SATA_X2D0+ SATA_X2D0- EXPCON_2V5 23 24
2 SATA_X2D0- SATA_X2D1+ TP0906 TP0918 TP0930 TP0942 TP0954 TP0966 TP0978 TP0990 TP09102 TP09114 TP09126 TP09138
2 SATA_X2D1+ VCC3V3 25 26
SATA_X2D1- 27 28 BB3V3_IO5 BB3V3_IO17
2 SATA_X2D1- EXPCON_OSC 29 30
1
EXPCON_CLKIN 31 32
R0902 EXPCON_CLKOUT 33 34 TP0907 TP0919 TP0931 TP0943 TP0955 TP0967 TP0979 TP0991 TP09103 TP09115 TP09127 TP09139
0R00 35 36 BB3V3_IO6 BB3V3_IO18
37 38
EXPCON_3V3 39 40
2
HDR40 BB3V3_IO7 BB3V3_IO19
GND
X14
HPE_RESOUT# 1 2 TP0911 TP0923 TP0935 TP0947 TP0959 TP0971 TP0983 TP0995 TP09107 TP09119 TP09131 TP09143
EXPCON_IO0 3 4 EXPCON_IO1 BB3V3_IO10 BB3V3_CLK0+
EXPCON_IO2 5 6 EXPCON_IO3 DIFF
C EXPCON_IO6 9 10 EXPCON_IO7 TP0912 TP0924 TP0936 TP0948 TP0960 TP0972 TP0984 TP0996 TP09108 TP09120 TP09132 TP09144 C
EXPCON_IO8 11 12 EXPCON_IO9 BB3V3_IO11 BB3V3_CLK0-
EXPCON_IO10 13 14 EXPCON_IO11 SPI_CCLK
19 20 EXPCON_3V3
EXPCON_IO16 21 22 VCC3V3
EXPCON_IO17 23 24 GND
EXPCON_IO18 25 26
1
EXPCON_IO21 29 30 R0904
EXPCON_IO22 31 32 EXPCON_IO23 10K0
EXPCON_IO24 33 34
2
EXPCON_IO27 37 38 CARDSEL#
EXPCON_IO28 39 40
HDR40
GND GND
54
Place the 0402-resistors of the LVDS termination
SATA-Connector as close as possible to the FPGA.
R0905 0R00
1 2
LVDS LVDS
2
B SATA_XT1D0+ SATA_X1D0+
B
X15 nb_100R
R0907 0R00
1
1 LVDS 1 2
GND SATA_XT1D0+
2
A+ 3 SATA_XT1D0- R0908 0R00
A-
4 1 2
GND SATA_XT1D1- LVDS LVDS
5
2
B- SATA_XT1D1+ SATA_XT1D1+ SATA_X1D1+
6
B+ SATA_XT1D1- R0909 SATA_X1D1-
7
GND LVDS nb_100R
R0910 0R00
1
CON_SATA 1 2
R0911 0R00
X16 1 2
LVDS LVDS
2
1 LVDS SATA_XT2D0+ SATA_X2D0+
GND SATA_XT2D0+ SATA_XT2D0- R0912 SATA_X2D0-
2
A+ SATA_XT2D0- nb_100R
3
A- 4 R0913 0R00
1
GND SATA_XT2D1-
5 1 2
B- SATA_XT2D1+
6
B+ R0914 0R00
7
GND LVDS 1 2
LVDS LVDS
2
CON_SATA SATA_XT2D1+ SATA_X2D1+
nb_100R
GND_HS R0916 0R00
1
1 2
Sternpunkt X16
A A
GND GND_HS
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 0 9 _ Exp Co n _ Pr o to Ar e a

Authors: csam Monday, February 23, 2009
IFW: 10:17:01
5 4 3 2 1
5 4 3 2 1 Figure 28.
Offpage Audio Codec
X17B LC1003
NFE31PT222Z1E9
NF_R 1U 2 1
AC97_BITCLK LC1004
2 AC97_BITCLK AC97_SDATA_OUT NFE31PT222Z1E9
3
2 AC97_SDATA_OUT AC97_SDATA_IN
2 AC97_SDATA_IN 3L 4U 2 1
AC97_SYNC NF_L
2 AC97_SYNC AC97_RESET# 5U
3
2 AC97_RESET# AC97_EXT_CLK LC1001 X17A
2 AC97_EXT_CLK AC97_EAPD NFE31PT222Z1E9 Shield 4
2 AC97_EAPD NF_R ST-4235-3/3-N
2 1 1L
LC1002 Headphone / Line-out GNDA_AC
NFE31PT222Z1E9
3
D 2 1 4L 2L
D
NF_L
5L
3
VGA_RD0 FB1005
2 VGA_RD0 VGA_RD1 C1005
1 Shield BLM21PG331SN1D
2 VGA_RD1
+
VGA_GR0 ST-4235-3/3-N LOCATE SEPERATE ANALOG POWER AND ANALOG GROUND 1 2 1 2 AC97_AOUT_L
2 VGA_GR0 VGA_GR1 GNDA_AC LINE-IN PLANES DIRECTLY ON TOP OF ONE ANOTHER WITHOUT
2 VGA_GR1 VGA_BL0 OVERLAPPING DIGITAL POWER OR GROUND PLANES. A SINGLE
2 VGA_BL0 VGA_BL1 ZERO OHM RESISTOR SHOULD LINK THE DIGITAL AND ANALOG 1u00
R1008 C1009
2 VGA_BL1 VGA_HSYNC GROUND PLANES AS CLOSE TO THE CODEC AS POSSIBLE. 47k0 1n00
2 VGA_HSYNC VGA_VSYNC
2 VGA_VSYNC
R1002 FB1003 U1001 GNDA_AC

0R00 BLM21PG331SN1D C1003 ANALOG FB1006

C1002
AC97_AIN_L 1 2 2 1 AC97_LINEIN_L 23 35 AC97_LINEOUT_L BLM21PG331SN1D
LINE_IN_L LINE_OUT_L
+
AC97_LINEIN_R 24 36 AC97_LINEOUT_R 1 2 1 2 AC97_AOUT_R
R1003 LINE_IN_R LINE_OUT_R
C1007 1k00 1u00
C1004 R1004 R1024
1n00 47k0 AC97_HP_OUT_L nb_0R00 1u00 R1009 C1010
100p 18 39
CD_L HP_OUT_L AC97_HP_OUT_C TP1001 47k0 1n00
19 40
CD_GND HP_OUT_C/NC AC97_HP_OUT_R
20 41
CD_R HP_OUT_R TP1002 VDDA5V0_AC97
GNDA_AC 21 37
MIC1 MONO_OUT GNDA_AC GNDA_AC
22
R1005 FB1004 MIC2 R1019
C1001
0R00 BLM21PG331SN1D 28 AC97_VREFOUT 10k0
AC97_AIN_R 1 2 2 1 16 VREFOUT nb_10k0
VIDEO_L
+
17 27 AC97_VREF (VT1612A)
R1006 VIDEO_R REFFLT
C1006 1k00 C1008 R1007 1u00
100p 1n00 47k0 C1014 14 29 AC97_AFILT1
100n AUX_L AFILT1/NC AC97_AFILT2
15 30
AUX_R AFILT2/NC AC97_AFILT3
31
AFILT3/NC
12 C1011
GNDA_AC GNDA_AC PC_BEEP AC97_3DFLT 22n0
32
3DFLT/NC 33 AC97_3DN
3DN AC97_3DP
13 34
C R1021 PHONE 3DP 100n C0603 C0603 C0805 C0805 C0603 C0603 C0603 C0603 C1206 C
33R0 DIGITAL INTERFACE (AD1881)
R1026 <--- AC97_BITCLK 6 48 1n00 C1021 C1022 C1023 C1024 C1025 C1026 C1027 C1012 C1013
PLL ---> AC97_EXT_CLK ---> AC97_SDATA_OUT BIT_CLK SPDIF/NC nb_22n0 nb_100n nb_10u0 nb_1n00 nb_1n00 nb_1n00 nb_1u00 100n 10u0
1 2 5 47 (CS4299)
SDATA_OUT EAPD/NC
<--- AC97_SDATA_IN 8 46 47n0 100n 10u0 1u00 270p 270p 270p 10u0 (VT1612A)
0R00 ---> AC97_SYNC SDATA_IN ID1 (AD1881) 3u30 (LM4480)
10 45 (VT1612A) (VT1612A) (AD1881) (VT1612A) (VT1612A) (VT1612A)
SYNC ID0 10n0 1u00 1u00 (CS4299)
44
---> AC97_RESET# HPP/NC (CS4299) (AD1881)
11 43
RESET NC GNDA_AC
C1028 R1025
CLOCK
AC97_XTL_IN 2 nb_0R00
GND GNDA_AUD XTL_IN AC97_PIN48 AC97_SPDIF_OUT
2
2
Locate under CODEC AC97_PIN47 AC97_EAPD TP1003
33p0 AC97_XTL_OUT
use 60 mil wide trace between R1027 Q1001 3
1M00 R1028 XTL_OUT R1020
digital and analog GND planes nb_24.576MHz
VCC3V3 0R0 POWER nb_0R00
1
VDD3V3_AC97 C1029
FB1001 1 4
1
VDD3V3_AC97 DVDD1 DVSS1
BLM18PG600SN1 9 7
1 2 DVDD2 DVSS2
R1023 GND
33p0 nb_0R00
VDDA5V0_AC97 25 26
C1017 C1018 C1019 GND AVDD AVSS
38 42
55
1u00 100n 100n NC/AVDD AVSS/NC
AC'97 CODEC R1022
C1020 nb_0R00
nb_100n PB-Free Part:
LM4549BVHX
GND
VCC5V0
FB1002 VDDA5V0_AC97 GNDA_AC GNDA_AC
BLM18PG600SN1
1 2 Connect ANALOG GND to
GND on Plane
realized in CAMTASTIC
C1015 C1016
1u00 100n
GNDA_AC GND
B GNDA_AC B
VGA Interface
R1010 270R
VGA_RD0
R1011 270R R1012 270R X19

VGA_RD1 6
VGA_RD_X 1 11
R1013 270R 7
VGA_GR0 VGA_GR_X 2 12
8
R1014 270R R1015 270R VGA_BL_X 3 13
VGA_GR1 9
4 14
R1016 270R 10
VGA_BL0 5 15
GND
R1017 270R R1018 270R CON_DSUB_15F
VGA_BL1
VGA_VSYNC
VGA_HSYNC
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 1 0 _ Au d io _ VG A

IFW: 10:15:09
5 4 3 2 1
5 4 3 2 1
Offpage
Figure 29.
3.3V (1A) / 1.2V (2A) DC/DC-Converter
Place the parts C1103, C1105 and C1124 VCC5V0
as close as possible to the pins of the U1101
1
C1101 C1102
10u0 100n
1
T1101A
D1101 PW_T1A_GATE 4 SI6966DQ
MBR0540LT1 max 2A VCC1V2_T VCC1V2
X20 VCC5V0
2
2
3
D D1102 C1103 GND_PWR R1102 PH1101 TP1101 D
3 VCC_KLD 1 2 100n L1101 0R025 PlaceHolder
CENTER PW_BOOST1 PW_SW1 TEST POINT
1 2 1 2 1
2 10MQ040N 1.2V
2
OPENER C1104 C1105 33u0
8
1
1 + C1106 + C1107 R1103 10u0 100n C1108 C1112
OUTSIDE 47u0 47u0 4k70 1n00 1n00 C1109 R1104 C1110 + C1111
Connect ANALOG GND to KLD-0202-A 20V 20V T1101B 180p 5K10 10u0 220u
2
GND on Plane C7343 C7343 PW_T1B_GATE 5 SI6966DQ 1% 10V 10V
1
2
GND D1103 C7343H
2
GND_PWR GND extra ANALOG GND plane GND_PWR GND_PWR GND_PWR GND R1105 LESR40
7
6
10MQ040N
connected with 6Vias to C1113 5R10
1
1
GND on plane nb_10n0 GND_PWR
U1101 R1106
1
24 25 10K0
VIN BOOST1 1%
22 27 GND_PWR
2
Ext_Vcc TG1 GND_PWR
21 26 PW_SW1_L
INTVcc SW1 GND_PWR TP1102
C1114 5 23
10u0 FREQSET BG1 TEST POINT
1
28 2 VOS1 GND
FLTCPL SENSE1+
7 3
GND FCB SENSE1-
10 4 VCC5V0 GND
3V3Out Vos1
6 18 PW_BOOST2
STBYMD BOOST2
1 16
RUN/SS1 TG2
1
15 17 C1115 C1116
1
RUN/SS2 SW2 10u0 100n
8 19 D1104 T1102A
ITH1 BG2 MBR0540LT1 PW_T2A_GATE SI6966DQ
4
11 14 max 1A VCC3V3_T VCC3V3
2
ITH2 SENSE2+
2
3
9 13 C1124 GND_PWR R1111 PH1102 TP1103
C1117 C1118 SGND SENSE2- 100n L1102 0R05 PlaceHolder
220p 220p 20 12 PW_SW2 1 2 1 2 1 TEST POINT
PGND Vos2 3.3V
C LTC1628-SSOP28 100u0 C
8
2
2
C1126 C1127
2
2
GND_PWR 1n00 1n00 C1128 R1112 C1129 + C1130 R1114
R1107 R1108 T1102B 180p 47K0 10u0 220u 330R
2
C1119 C1120 C1121 C1122 15K0 C1123 15K0 PW_T2B_GATE 5 SI6966DQ 1% 10V
2
10n0 100n 100n 33p0 33p0 D1105 C7343H
1
1
R1110 LESR40
1
1
7
6
10MQ040N
C1125 5R10
1
2
nb_10n0 GND_PWR
R1113
1
15K0 LD1101
GND 1% LED green
GND_PWR 3.3V PG
1
GND_PWR
PW_SW2_L
GND_PWR
GND
PW_VOS2
56
2.5V/2.6V (2A) Drill
GNDP
DRILL1101 DRILL1102
DRILL DRILL
VCC5V0 GNDP
R1115 0R033
1 2
B B
C1131
10u0 GND
4
U1102 R1116 10R0 T1103 VCC2V5 DRILL1103 DRILL1104
1 6 1 2 3 S Si3445DV DRILL DRILL
EN SW VCC2V5_T
2 5
3
GND VIN 4
G
D max 2.4A PH1103
FB ISENSE PlaceHolder
TPS64203DBVT L1103 TP1104
1
2
5
6
1 2 1 TEST POINT
2.5V
1
2
GND 10u0
2
R1117 C1132 + C1133 C1134 R1120
D1106 42K2 4p70 100u 1u00 100R
10MQ040N 1%
1
2
1
GND GND
LD1102
LED green
Miscellaneous
2.5V PG
1
3
2
1
1
R1118 R1119 optional optional optional optional optional
36k0 39k0 GND Pad1101 Pad1102 Pad1103 Pad1104 Pad1105
1% X21 HDR3 1% ArtNr05281 ArtNr05281 ArtNr05281 ArtNr05281 ArtNr05281
2
2
optional optional
GND A1101 GND Label01
Jumper LABEL
Set the jumper to 1-2 for 2.5V and to 3-2 for 2.6V
(This is important for the DDR SDRAM module)
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 1 1 _ Po we r Su p p ly

IFW: 10:14:07
5 4 3 2 1
5 4 3 2 1 Figure 30.
Netclasses:
Clocks: max. 120mm, daisy chain routing
Memory: Signals: max 150mm, length matching +/- 10mm
D Differential: routing as differential signals, length matching +/- 20 mils D
length max. 100mm, route as daisy chain
General routing requirements:
C C
57
B B
A A
Pr o je ct: Hp e _ min i L EC2 Sh e e t: 1 2 _ De sig n No te s

Authors: csam Wednesday, July 19, 2006
IFW: 00:17:49
5 4 3 2 1

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LatticeMico32/DSP Development Board for LatticeECP2

• Copper plating indicates v2 in text (HPEminiv2)

• Eight LEDs with test points for each LED

Figure 1. LatticeMico32/DSP Development Board Block Diagram

Table 1. Board Defaults

Figure 2 shows the position of peripheral interfaces available on the board.

Figure 2. Peripheral Interfaces (Version 1 Board Shown in this Figure)

LCD Sigma Delta

1. A USB RESET# pushbutton has USB Reset

Table 2. Audio Codec U1001 Pin Definitions

DDR SODIMM Socket for DDR SDRAM Modules

Table 3. DDR SODIMM Socket (X4) - Data Bus

Table 4. DDR SODIMM Socket (X4) - Address Bus

Table 5. DDR SODIMM Socket (X4) - Other Signals

Table 6. Ethernet Controller U0801 Pin Definition

Table 7. Expansion Connector X13 (Continued)

Table 8. Expansion Connector X14

ispDOWNLOAD Cable Connector

1. Caption on the board: CONF.

Table 9. ispDOWNLOAD Connector X4 Pin Definition

LCD Connector (Optional)

Figure 3. LCD Panel (Not Included)

Table 10. LCD Connector X6 Pin Definition

Table 12. Serial Interface X9 Pin Definition

Sigma Delta D/A Converter

USB Host/Peripheral Interface

Table 13. USB GPIO Connections (U0702) (Continued)

USB Configuration Connector

Figure 4. VGA Connector

Figure 5. User Interface Features (Version 1 Board Shown in this Figure)

LCD Sigma Delta

Table 17. 7-Segment Display U0502 Pin Definition

Table 18. DIP Switches SW0514 Connection

Table 19. LED LD0501 ... LD0508 Connection

Figure 6. Polling of the Key Matrix

CPU Reset Key

Single Step Key

Figure 7. Components (Version 1 board Shown in this Figure)

SPI Reset Asynchronous Parallel

12 x 12 FPGA Prototyping Area of The FPGA

Table 22. FPGA Connections for the 12x12 Prototyping Area

Figure 8. Schematic Illustration of the Prototyping Area

Table 24. Data Signals of the Asynchronous SRAM Chip U0404

Table 25. Data Signals of the Asynchronous SRAM Chip U0405

Table 27. Interface Between the MachXO and the FPGA

• 48 k Look-Up Tables (LUTs)

• 96 kbit of distributed RAM

• 387 kbit of EBR SRAM

• 21 EBR SRAM blocks

• 6 PLLs: 2 GPLLs, 2 SPLLs, 2 GDLLs

• 500 user I/Os

• DDR memory support (DDR1-400, DDR2-400)

• HSTL, differential SSTL, RSDS, Bus LVDS, MLVDS, LVPECL

Table 29. Data Signals of the Flash Chip U0402

Table 30. Data Signals of the Flash Chip U0403

Table 32. FPGA to SPI Flash Connections

Configure the SPI Flash as follows:

3. Change the Device Access Options to SPI Flash Programming.

4. Select Flash Device : STMicro SPI-M25P16 and click OK.

6. Click OK to close the SPI Serial Flash Device dialog.

7. Click OK to close the Device Information dialog

2. Make sure that the INIT LED is lit.

5. Start test program 1.