S. Y. B.

Tech
Microprocessors and Computer Architecture CSE – II

HANDOUT

Assignment No: 11

Instruction Level Parallelism

Problem Statement: Study and compare different types of hazards in

InstructionLevel Parallelism.
Input:
Output:
Description:

➢ Write down the following in journal:

• What is Instruction Level Parallelism?
Instruction Level Parallelism (ILP) refers to the ability of a computer
architecture to execute multiple instructions in parallel, thereby improving
performance and increasing throughput. It is a concept in computer
architecture and design that focuses on exploiting the inherent parallelism
present within a program's instructions.
Traditionally, computers execute instructions sequentially, one after another,
following the sequential order specified by the program. However, many
modern processors employ techniques to extract parallelism from the
instruction stream, thereby executing multiple instructions simultaneously.
ILP is achieved through various techniques, including:

1. Pipelining: Instructions are divided into smaller stages, and multiple

instructions are executed simultaneously in different stages of the
pipeline. This allows for the overlapping of different instruction
executions and increases the overall throughput.

2. Superscalar Execution: Superscalar processors have multiple functional

units, such as multiple arithmetic logic units (ALUs) and floating-point units
(FPUs). They can execute multiple instructions concurrently by dispatching
them to different functional units, as long as there are no dependencies
between the instructions.

WALCHAND INSTITUTE OF TECHNOLOGY, SOLAPUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINE

Ms. Pratibha A. Domal Year 2022-23 Sem-II

ERING
 S. Y. B. Tech
Microprocessors and Computer Architecture CSE – II

3. Out-of-order Execution: In this technique, instructions are dynamically

reordered to execute independent instructions as soon as their operands
become available, rather than waiting for their original sequential order. This
helps in exploiting more parallelism and improving performance.

4. Speculative Execution: Speculative execution allows the processor to

execute instructions ahead of time, even before it is certain that those
instructions will be needed. If the speculation is correct, it can improve
performance by overlapping the execution of independent instructions.

5. Branch Prediction: Branch instructions, such as if-else statements or loops,

introduce a challenge to ILP since the program flow becomes conditional.
Branch prediction techniques are employed to predict the outcome of branch
instructions, enabling the processor to speculatively execute instructions in the
predicted direction, improving ILP.

These techniques work together to identify and exploit instruction-level

parallelism within a program, making use of available hardware resources and
maximizing the utilization of the processor's execution units. By leveraging ILP,
modern processors can achieve higher performance and execute more
instructions per clock cycle, ultimately enhancing the overall efficiency of
computing systems.
• Compare different types of hazards in ILP.
In Instruction Level Parallelism (ILP), hazards refer to dependencies or conflicts
between instructions that prevent them from executing in parallel. Hazards
can limit the exploitation of parallelism and negatively impact performance.
There are several types of hazards in ILP, including:

1. Data Hazards: Data hazards occur when there is a dependency between

instructions that prevents them from executing concurrently. There are three
subtypes of data hazards:

a. Read-after-Write (RAW) Hazard: A RAW hazard arises when an instruction

depends on the result of a previous instruction that writes to the same data
location. The dependent instruction must wait for the previous instruction to
complete its write before it can fetch the data.

b. Write-after-Read (WAR) Hazard: A WAR hazard occurs when a later

WALCHAND INSTITUTE OF TECHNOLOGY, SOLAPUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINE

Ms. Pratibha A. Domal Year 2022-23 Sem-II

ERING
 S. Y. B. Tech
Microprocessors and Computer Architecture CSE – II

instruction writes to a data location that a previous instruction reads from. The
later instruction must wait for the previous instruction to complete its read
before it can write to the same location.

c. Write-after-Write (WAW) Hazard: A WAW hazard arises when two

instructions attempt to write to the same data location. The second instruction
must wait for the first instruction to complete its write before it can perform
its write operation.

2. Control Hazards: Control hazards occur due to changes in the program flow
caused by branch instructions (e.g., conditional branches, jumps). They can
disrupt the sequential execution of instructions and impact ILP. There are two
common types of control hazards:

a. Branch Hazards: Branch hazards occur when the outcome of a branch

instruction is not known at the time of instruction fetch. The processor must
stall or flush instructions in the pipeline until the branch outcome is
determined.

b. Indirect Branch Hazards: Indirect branch hazards occur when the target of
a branch instruction is determined dynamically at runtime. The target address
is not known until the instruction executes, making it challenging to predict
and resolve the hazard efficiently.

3. Structural Hazards: Structural hazards arise when the hardware resources

required to execute multiple instructions concurrently are limited or not
available. They can occur due to resource conflicts, such as multiple
instructions trying to access the same functional unit simultaneously.

For example, if two instructions require the same floating-point unit, a

structural hazard occurs, and one instruction may need to wait until the unit
becomes available.

These hazards impact ILP by introducing stalls or pipeline bubbles, where the
processor has to delay instruction execution or insert idle cycles. Techniques
such as forwarding, data forwarding, branch prediction, and instruction
scheduling are employed to mitigate these hazards and improve ILP by
allowing instructions to execute in parallel whenever possible.

WALCHAND INSTITUTE OF TECHNOLOGY, SOLAPUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINE

Ms. Pratibha A. Domal Year 2022-23 Sem-II

ERING
 S. Y. B. Tech
Microprocessors and Computer Architecture CSE – II

Conclusion

➢ What are the possible overcoming methods for data hazard?

Data hazards can be mitigated or overcome through various methods in order
to enable parallel execution of instructions. The following are some commonly
used techniques to address data hazards:
1. Forwarding (also known as data forwarding or bypassing): Forwarding
allows the result of a previous instruction to be forwarded directly to a
dependent instruction without going through memory. By avoiding the need to
wait for the result to be written to memory and then read back, forwarding
reduces the latency caused by data hazards.
For example, if an instruction requires the result of a previous instruction
that is still in the execution stage, forwarding allows the result to be directly
forwarded to the dependent instruction, eliminating the need for stalling.

2. Register Renaming: Register renaming is a technique used to eliminate

WAW and WAR hazards. It involves assigning multiple physical registers to the
same logical register (architectural register), allowing independent instructions
to write their results to different physical registers. This eliminates the hazards
by ensuring that there are no conflicts between write and read operations on
the same logical register.
By renaming registers dynamically, the processor can maintain a larger
number of independent instructions in flight and execute them in parallel
without dependencies.

3. Compiler Techniques: Compiler optimizations can be employed to minimize

data hazards. Techniques like loop unrolling, software pipelining, and code
scheduling aim to rearrange instructions or eliminate dependencies to
maximize instruction-level parallelism.
The compiler can analyze the dependencies between instructions and
reorganize the code to reduce or eliminate data hazards, allowing the
processor to exploit more parallelism.

WALCHAND INSTITUTE OF TECHNOLOGY, SOLAPUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINE

Ms. Pratibha A. Domal Year 2022-23 Sem-II

ERING
 S. Y. B. Tech
Microprocessors and Computer Architecture CSE – II

4. Software Prefetching: Data hazards can also be reduced by using software

prefetching techniques. Prefetching involves fetching data from memory into
caches or registers in advance, anticipating its future use. By bringing data into
closer proximity to the processor, software prefetching can help alleviate data
hazards caused by memory accesses.
Predicting data accesses and fetching them ahead of time can reduce the
latency associated with data hazards and improve ILP.
It's worth noting that these techniques are often used in combination and are
implemented at different levels, including hardware and software. The specific
approach depends on the architecture, design goals, and the trade-offs
between performance, complexity, and power consumption. By applying these
methods, the processor can effectively handle data hazards and exploit
instruction-level parallelism for improved performance.

WALCHAND INSTITUTE OF TECHNOLOGY, SOLAPUR

DEPARTMENT OF COMPUTER SCIENCE AND ENGINE

Ms. Pratibha A. Domal Year 2022-23 Sem-II

ERING