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Reticle Design for Minimizing Multiproject Wafer Production Cost

Article  in  IEEE Transactions on Automation Science and Engineering · November 2007

DOI: 10.1109/TASE.2007.904239 · Source: IEEE Xplore

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WANG et al.: LEE et al.: LIN et al.: RETICLE DESIGN FOR MINIMIZING MULTIPROJECT WAFER PRODUCTION COST 589

Reticle Design for Minimizing Multiproject

Wafer Production Cost
Rung-Bin Lin, Meng-Chiou Wu, and Shih-Cheng Tsai

Abstract—Multiproject wafer (MPW) production cost are sensitive to

how the chips are arranged in a reticle. In this paper, we propose a method-
ology for exploring the reticle floorplan design space to minimize MPW
production cost. Experimental results show that our methodology often
achieves double-digit cost savings. A study using MPW for volume produc-
tion shows that the volume cutoff points range from a few thousand dice to
tens of thousands of dice.

Note to Practitioners—This paper proposes a methodology for mini-

mizing MPW production cost via better chip placement in a reticle (called
reticle floorplanning). Our methodology consists of an effective reticle
floorplanning method, two simulated wafer dicing methods, two cost esti-
mation models, and a procedure for calculating the cost assumed by each
project. A design service company or a foundry can use our methodology
to reduce MPW production cost and, thus, provides a more affordable and
expedient service to its customers. The reticle floorplanning method and
simulated wafer dicing methods employed here are the state-of-the-art.
A practitioner should adapt these methods to other MPW problems such Fig. 1. An MPW fabrication flow. The shaded area consists of the major tasks
as dealing with multitechnology process, placing multiple instances of implemented in our methodology.
the same design in a reticle, etc. The cost models should also be revised
accordingly. The cost data given in this paper should be used only for
reference as mask tooling and wafer fabrication costs constantly change.
The cost model proposed for calculating the production cost assumed by
each project can serve as a basis for developing a fairer pricing model.
The study of using MPW for low to medium-volume production is also
very useful. It may help a customer deliver its product earlier to market
using a low-cost fabrication program. The problem addressed in this
paper becomes much simpler if the side-to-side wafer dicing constraint is
removed.

Index Terms—Design automation, masks, optimization methods, semi-

conductor device fabrication.

I. INTRODUCTION
Multiproject wafer (MPW) or shuttle run has long been used for
fabricating educational chips [1] or prototyping innovative designs so
that the soaring mask cost [2] can be shared among the projects. This
has become increasingly important for the foundry business because
a low-cost MPW prototyping often plants a seed for potential volume
production. It is especially crucial to small companies that would like to
realize innovative ideas via silicon. Fig. 1 shows a simple flow for MPW
fabrication. In a shuttle run, designs (projects) are collected from cus-
tomers and placed into a reticle (called reticle floorplanning [3]–[5]).
This is followed by some data preparation tasks and simulated wafer
dicing. Simulated wafer dicing is a kind of sawing simulation per-
formed before wafer fabrication. It determines which wafers are used
to produce which dice, thereby determining the wafer dicing plan for
each yet to be fabricated wafer. This process determines the number of
wafers that need to be fabricated for the shuttle run. The total produc-
tion cost of the shuttle run and the cost shared by each project are then
Manuscript received July 1, 2006; revised February 5, 2007. This paper
was recommended for publication by Associate Editor J. Fowler and Editor
N. Viswanadham upon evaluation of the reviewers’ comments.
The authors are with the Department of Computer Science and Engineering,
Yuan Ze University, Chung-Li 320, Taiwan (e-mail: csrlin@cs.yzu.edu.tw;
mcwu@vlsi.cse.yzu.edu.tw; hamdo@vlsi.cse.yzu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TASE.2007.904239
Fig. 2. An MPW. On the left is one of the reticles used to fabricate the MPW
on the right. Ten chips are placed in the reticle.
calculated. Once the wafers are fabricated, wafer dicing plans are em-
ployed to obtain bare dice. Fig. 2 shows an MPW and the reticle used
for fabricating the wafer. Since the MPW fabrication service is very
important to the foundry business, it must provide affordable prices
to its customers. Such a service can be provided through an optimized
MPW fabrication flow, where reticle floorplanning and simulated wafer
dicing play an important role.
Besides being used for prototyping, MPW can be used for low
volume production [1], [6]. According to the 2003 annual report of
IMEC [6], IMEC carried out 91 low-volume projects that produced 4.1
million components. This amounts to 45 000 components per project.
With ever increasing mask tooling cost for more advanced technology,
MPW is becoming more viable for medium-volume production [7].
Reticle floorplanning for cost minimization is a multiple objective
optimization problem where the mask tooling and wafer fabrication
costs are two conflicting goals. The mask tooling cost favors a smaller
reticle size, but this would pack chips closely within a reticle and hence
create excessive sawing conflicts. As a consequence, more wafers must
be fabricated. On the other hand, an attempt to align chips in a reticle
to reduce sawing conflicts often requires a larger reticle and, hence,
increases the mask tooling cost. In the past, several metrics such as
an upper bound on the number of wafers [8]–[11], wafer dicing yield
[4], reticle area [3], compatibility (in contrast to sawing conflict), and
a combination of the above metrics [7], [12]–[14] have been used to

1545-5955/$25.00 © 2007 IEEE

590 IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, VOL. 4, NO. 4, OCTOBER 2007

evaluate the quality of a reticle floorplan. Metrics other than the reticle
area were all designed to minimize the number of wafers used. How-
ever, none of these metrics corresponds exactly to the MPW production
cost due to the dependency of the production cost on more than one of
these metrics.
Ideally, a floorplanner can directly employ the production cost as
an objective. The problem is that the floorplanner needs a very fast
and effective simulated wafer dicing method to compute the number of
wafers for a floorplan. Such a simulated wafer dicing method is virtu-
ally nonexistent [15].
In this paper, we propose a methodology for exploring the reticle Fig. 3. Reticle size versus sawing conflicts in reticle floorplans.
floorplan design space to minimize MPW production cost. We em-
ploy an efficient reticle floorplanning method to generate as many good
floorplans as possible using an objective function that can balance ret-
B. Reticle Floorplanning
icle area and sawing conflicts [13], [14]. We then select from them a
reticle floorplan that incurs the least production cost. We devise two A reticle floorplan sets a lower bound on the number of wafers
cost models for production cost calculation and a procedure for com- needed to be fabricated for a shuttle run and, hence, determines the
puting the cost shared by each project. We present an approach for MPW production cost. The reticle floorplanning problem is formulated
determining to what extent a shuttle run can be used for volume pro- as follows.
duction. We study the relationship between production cost and some Given a set of N chips and the required production volume Vp for
reticle floorplanning objectives such as reticle area, total number of ex- chip p = 1; . . . ; N , determine the coordinates of the chips such that
posures, number of wafers, and wafer dicing yield. The experimental the number of wafers used to attain the required production volume
results show that our methodology often achieves double-digit savings is minimized on the condition that no chips overlap and all chips are
in the MPW production cost. This can be done within half an hour on a inside the reticle with dimensions not larger than maximally allowable
PC. We will use project, chip, and design interchangeably in this work. values.
The usage of these words is based on how well they fit into the under- The difficulty in the above problem arises from the necessity for a
lying context. reticle floorplanning method to deal with two competing factors: reticle
The rest of this paper is organized as follows. Section II reviews size and compatibility. This is especially true for the cases where many
simulated wafer dicing and reticle floorplanning problems. Section III chips in a reticle have different widths and heights. Given any two chips
elaborates on the cost involved in a shuttle run. Section IV proposes a of this sort, they are compatible only when they are placed diagonally
reticle design space exploration methodology. Section V describes how in a reticle. This results in a larger reticle despite no sawing conflicts
to determine whether a project should be fabricated using a shuttle run. between them. Conversely, the two chips can be abutted together to
Section VI presents the experimental studies. Section VII draws some achieve a smaller reticle size. This enables more reticle images to be
conclusions. printed on a wafer but creates more sawing conflicts. Fig. 3 shows such
an example where the two reticle floorplans each contain the same two
II. SIMULATED MPW DICING AND RETICLE FLOORPLANNING chips. Which reticle floorplan would result in fewer wafers used? The
answer is not immediately clear. If both chips have the same produc-
A. Simulated Wafer Dicing tion volume, these two reticle floorplans would incur the same number
of wafers if the wafer dicing plans given in the figure are employed.
Simulated wafer dicing is a kind of sawing simulation performed
If their required production volumes are not the same, said a ratio 1/3
before wafer fabrication to determine the wafer dicing plans for yet to
of chip A’s volume to chip B’s volume, the reticle floorplan for the
be fabricated wafers. It can be formulated as follows.
wafer on the right would incur fewer wafers if the wafer dicing plan
Given a reticle floorplan of N chips and the required production
that did not include the third horizontal scribing line (counting from
volume Vp for chip p = 1; . . . ; N , find the wafer dicing plan for each
top to bottom) is used. It is clear that the two competing objectives,
yet to be fabricated wafer such that the number of wafers used to attain
sawing conflicts and reticle area, make the reticle floorplanning dif-
the production volumes of all chips is minimized.
ficult to solve. Furthermore, which reticle floorplan would incur less
Dicing yield zk is defined as, at least zk Vp good dice for each chip p
cost? The answer is not immediately clear, even if the two floorplans
must be obtained from dicing k wafers. The number of wafers needed
incur the same number of wafers used. The wafer on the left uses fewer
to meet the production volumes of all the projects is the smallest k such
that zk  1. Several wafer dicing methods can be found in [8] and [15].
exposures than the wafer on the right and, thus, has less exposure cost
(part of wafer fabrication cost), but the underlying reticle is larger and,
The difficulty in simulated wafer dicing arises from having to deal
thus, incurs greater mask tooling cost. Clearly, to answer the above
with the side-to-side dicing constraint. This constraint prescribes that
questions in general, a reticle floorplanning method should simultane-
a scribing line must start from one side of a wafer and stop at the other
ously minimize the two competing objectives: mask tooling cost and
side. With such a constraint, we cannot normally obtain all the bare dice
wafer fabrication cost. Hence, a floorplanner should be able to trade ret-
printed on a wafer. For the reticle floorplan in Fig. 2, the dice for chips
icle area for sawing conflicts and vice versa to perform a reticle design
6 and 7 will be destroyed and the die for chip 1 will be discarded when
space exploration. The floorplanner [13], [14] described in Section IV
scribing lines h2, h3, v1, and v2 are used to obtain the die for chip 8. A
possesses such characteristics.
good bare die considered in this paper is a die with four scribing lines
located at its four borders and without any other scribing lines going
across it. Two dice are in sawing conflict if sawing out one die would III. MPW FABRICATION COST
damage the other die. Otherwise, they are compatible. For example, the The total production cost of a shuttle run includes the mask tooling
dice for chips 2, 4, 5, and 8 are compatible, whereas the dice for chips and wafer fabrication costs. The wafer fabrication cost is further di-
1 and 8 are not compatible. The scribing lines used to obtain good bare vided into the wafer exposure and field-size independent wafer costs
dice from a wafer form a wafer dicing plan. [7], [12]. Given a reticle floorplan F (A; V ) for a shuttle run with a
WANG et al.: LEE et al.: LIN et al.: RETICLE DESIGN FOR MINIMIZING MULTIPROJECT WAFER PRODUCTION COST
TABLE I
MASK SET COSTS FOR DIFFERENT FIELD SIZES (US$)
vector A = (A1 ; A2 ; . . . ; AN ) denoting the chip areas and V =
(V1 ; V2 ; . . . ; VN ) denoting the required volumes, the total MPW pro-
duction cost is
Tmpw (F ) = C m (F ) + Q(F )(C e (F ) + Cw ) (1)
where F is short for F (A; V ). Cm (F ), Ce (F ), and Cw are the mask
cost, exposure cost per wafer, and field-size independent wafer cost
per wafer, respectively; Q(F ) is the number of wafers fabricated.
Q(F )(Ce (F ) + Cw ) is the total wafer fabrication cost. Very few
MPW cost models are found in the open literature [1], [7], [12], [16],
[17]. We are among the first to study the cost models for a shuttle run
[7], [12].
A. Mask Tooling Cost
Mask cost is incurred mainly by data preparation, mask write, mask
inspection, mask repair, mask blank, etc. [18]. Mask yield depends
highly on the number of critical layers used in a chip and the total area
of the chips in a reticle. It is basically a nonlinear function of the field
(reticle) size, as shown in Table I. The data in Table I are calculated
for a 90 nm technology node assuming that a chip has 8 very critical
layers, 8 critical layers, and 12 noncritical layers [18].
One issue that complicates mask cost calculation is how dead space
in a reticle is handled. Dead space is normally filled with dummy pat-
terns to achieve better chemical mechanical polishing (CMP) and does
not contribute to mask defects. Thus, it should cost less than an equiva-
lent area used by a chip. A customer would view this as a more rea-
sonable model. We call this model the customer oriented model or
C -model for short. However, a prevailing cost model adopted by a mask
shop is to treat dead space no different than an area occupied by a chip.
This would certainly increase the mask tooling cost if a reticle has a
large dead space. We call this model the mask shop oriented model or
M -model for short. The M -model was first mentioned in [7].
B. Wafer Fabrication Cost
The main contributors to wafer fabrication cost include exposure,
hot process, etch, sputter, polish, wafer blank, etc. [19]. Among them,
exposure cost depends highly on the type of layers employed in a chip.
The cost per exposure for a very critical layer can be five times that for
a noncritical layer [18]. The exposure cost per wafer also depends on
the number of reticles printed on a wafer, which depends on the field
size. This part of the cost is also called the field-size dependent wafer
cost [7], [12]. The other part of the wafer fabrication cost is called the
field-size independent wafer cost. This includes the costs for hot pro-
cessing, etching, sputtering, etc. Once we know the number of wafers
fabricated, we can calculate the total wafer fabrication cost.
C. Cost Sharing Model
Here, we present a procedure to compute the cost shared by each
project. Given a reticle floorplan F for a shuttle run with area vector A
and production volume vector V , the cost assumed by chip p is
C m (F )A p
Cmpw (p) = + Q (F )C e (F )
Ai
i=1;...;N
591
Fig. 4. Shared cost increase with respect to the shared cost for 1X volume due
to scaling chip 1’s volume for the test case I6 given in Table II. Floorplanning
was redone for chip 1’s volume scaling using the methodology presented in
Section IV. The shared cost of a chip was calculated using (2).
Fig. 5. Calculating the cost shared by each project. At step 2, (2) is used to
compute the shared cost based on production volumes of 120, 200, 200, and
p p p p
200 for , , , and , respectively. Step 3 is done twice. The first time
Q 0Q
distributes the cost of fabricating wafers to p p
and . The second
Q 0Q
time distributes the cost of fabricating wafers to . p
2 Vp
Vi
+
Q (F )C w A p V p
Ai Vi
: (2)
i=1;...;N i=1;...;N
This formula was first presented in [12]. The first term is the share
of the mask cost. It is proportional to the chip area. The second term
is the share of the exposure cost. It is proportional to the production
volume but independent of the chip area. A reticle exposure will print
a die on a wafer regardless of the chip size. The third term is the share
of the field-size independent wafer cost. It is proportional to the total
wafer area used to produce enough dice for a project.
When all chips have the same production volumes, the share of the
field-size independent wafer cost is proportional to the chip area and
the exposure cost is evenly shared. As the production volume varies, (2)
tends to favor projects with larger production volumes. The reason for
this is that it gives the projects with smaller production volumes a share
of the fabrication cost for wafers used solely for projects with larger
production volumes. As shown in Fig. 4, scaling up chip 1’s volume
incurs an increase in the costs shared by the other chips. This is espe-
cially significant for 100X volume scaling. Below is a cost calculation
procedure that does not have this drawback.
1) Sort the chips in ascending order in terms of their production vol-
umes. Place a demarcation line between any two chips that have
a large difference (determined by the value of di given later) in
production volume. Put the chips between any two consecutive
demarcation lines into a group so that the chips are divided into
s groups, G1 ; G2 ; . . . ; Gs . It is required that 0  ni 0 mi  di
for i = 1; 2; . . . ; s, where mi and ni are the smallest and largest
volumes found in Gi , respectively.
2) Determine the number of wafers required to meet the production
volumes for all of the projects in G1 and the production volume
592 IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, VOL. 4, NO. 4, OCTOBER 2007
n1 for each of the projects in the other groups. Suppose we need
Q1 wafers. Use (2) to calculate the cost shared by each project
based on the production volumes given in the first statement of
this step.
3) Repeat the following tasks for i = 2; 3; . . . ; s. Determine the
number Qi of wafers required to meet the production volumes for
all of the projects in Gj for j  i and the production volume ni for
the projects in Gk for all k > i. This is equivalent to saying that
we will use extra Qi 0Qi01 wafers to meet the remaining volumes
for the projects in Gi and the production volume ni 0 ni01 for
each of the projects in Gk for all k > i. Use the last two terms
in (2) to distribute the fabrication cost of Qi 0 Qi01 wafers to
the projects in Gk for all k  i based on the production volumes
given in the previous statement. Add this part of the shared cost
to each of the underlying projects.
Fig. 5 shows an example for the above procedure given the four
projects p1 , p2 , p3 , and p4 with production volumes 120, 200, 20 000,
and 50 000 dice, respectively, and di = 200 for all i. The value of di
plays a crucial role in the cost sharing fairness. Basically, di should
be set to the values so that the number of groups obtained in Step 1 is
maximized and Qi < Qi+1 . This cannot be done without simulated
wafer dicing. In our study, we set di = 0 for all i, and then merge any
two adjacent groups if Qi = Qi+1 .
IV. RETICLE DESIGN SPACE EXPLORATION
Here, we propose a methodology for obtaining a floorplan that would
minimize the total MPW production cost. This methodology requires
an effective reticle floorplanner and dicing method. We employ B 3 -tree
[20] to perform reticle floorplanning using an important concept called
volume-driven compatibility optimization (VOCO) [13], [14]. VOCO
tries to maximize the compatibility score among chips with large pro-
duction volumes, while minimizing reticle area. Our study shows that
B 3 -tree with VOCO on average attains 16%–26% fewer wafers than
the hierarchical quadrisection method [8]. For convenience, the objec-
tive function used for VOCO is given below
N01 N Our study is made on 300 mm wafers. We use the mask cost data given
V. MPW FOR VOLUME PRODUCTION
Here, we present an approach to studying whether MPW is viable
for volume production, i.e., whether a project fabricated with MPW is
cheaper than it is fabricated alone [7]. A project fabricated alone using
its own mask set is said to go with a single-project wafer (SPW) pro-
gram [7], [18]. SPW is, in fact, a special case of MPW. The question
is at what production volume does a project using MPW become more
expensive than using SPW. To answer this question, we need to deter-
mine a minimal cost SPW for the underlying project. If a project uses
SPW, the number of required wafers can be easily calculated. However,
there is still a reticle floorplanning problem for SPW. The question is
how many copies of the same design should be replicated in a reticle
for SPW and where should these copies be placed in a reticle. This
problem was investigated in [18], but not comprehensively. Here, we
introduce an approach to exploring all possible chip placements within
a SPW reticle. Our approach is as follows. Given a design with width w
and height h and maximal reticle width wmax and height hmax , align
i 2 j copies of the given design in a reticle into an i 2 j matrix, where
i = 1; 2; . . . ; bwmax =wc and j = 1; 2; . . . ; bhmax =hc. We calculate
the production cost for each i 2 j configuration to determine a config-
uration with the least production cost. A project p should be fabricated
with SPW if
Cspw (p) < Cmpw (p) (4)
where Cspw (p) is the production cost for project p going with SPW.
The cost Cmpw (p) assumed by each project should be computed using
the approach presented in Section III-C
VI. EXPERIMENTAL RESULTS
We carry out some experimental studies of reticle design space ex-
ploration. Our experiments consist of three parts. The first part shows
how much variation in production cost a shuttle run can have and how
the three parts of the production cost can vary with production volumes.
The second part studies how good a floorplanning objective would cor-
respond to the production cost. The third part studies to what produc-
tion volume a project can still use a shuttle run for chip fabrication. All
experiments are done on a 2.4 GHz AMD K8 CPU with 2 GB memory.
max  Epq (Vp + Vq ) 0 (1 0 )W H (3) in Table I. For simplicity, we assume that the mask cost for SPW and
p=1 q=p+1 MPW is the same if they have the same reticle area. We use the cost
per exposure data in [18] to compute the exposure cost per wafer. The
Epq = 1 if two chips p and q are compatible. W and H are reticle width cost per exposure is $2.5 for very critical layer, $1.5 for critical layer,
and height, respectively.  is a normalizing factor. Varying  ’s value,
we can trade compatibility for reticle size to perform a design space
exploration. As for simulated wafer dicing, we implement an integer
linear programming (ILP) model using the maximal independent sets
in a reticle conflict graph as it was done in [8]. This kind of method was
first used in [15]. Since it does not work well for low-volume produc-
tion, as suggested in [15], we will use HVMIS-SA-Z for low-volume
production and the ILP model for higher volume production.
In summary, our methodology has the following three steps.
1) Use B 3 -tree with VOCO to perform design space exploration by
varying  ’s value in (3). This step will generate a number of reticle
floorplans for each  ’s value.
2) Employ the simulated wafer dicing method HVMIS-SA-Z [15] for
low-volume production and the ILP model [8] for higher volume
production to determine the number of wafers that need to be fab-
ricated.
3) Use the cost models to calculate the total fabrication costs. The
reticle floorplan incurring the least production cost is selected as
the final solution. The cost assumed by each project is computed
using the approach presented in Section III-C.
and $0.5 for noncritical layer.
A. Production Cost Versus Production Volumes
We used the method proposed in Section IV to determine a floorplan
with minimal MPW production cost. What we did was vary the coeffi-
cient  in (3) from 0 to 1 by a step of 0.1. We generated 5 floorplans for
each  value and obtained 55 floorplans. Fig. 6 shows the MPW pro-
duction costs for the reticle floorplans for I7 using M -model for mask
cost calculation. It takes less than 20 min to generate these floorplans
and perform simulated wafer dicing. As one can see, mask cost is the
lion share of the total production cost for 1X volume. The floorplans on
the left of the X axis have smaller reticle areas and, thus, have smaller
mask costs. The cost variation for 1X volume is mainly due to the dif-
ference in reticle size. As the production volume increases, the expo-
sure cost gradually dominates the total production cost and contributes
most to the cost fluctuation. Most of the floorplans with small reticle
size pay much more exposure cost and, thus, have higher total produc-
tion costs. The reason for this is that the chips packed in a small reticle
create more sawing conflicts than in a larger reticle. This requires more
exposures to print enough dice on wafers to meet the volume require-
WANG et al.: LEE et al.: LIN et al.: RETICLE DESIGN FOR MINIMIZING MULTIPROJECT WAFER PRODUCTION COST
Fig. 6. MPW production cost.
Fig. 7. MPW production cost versus reticle area for I7.
Fig. 8. MPW production cost versus number of exposures for I7. X axis is
scaled by 100, 1000, and 10000 times for 1X, 10X, and 100X, respectively.
X axis is
Fig. 9. MPW production cost versus number of wafers used for I7.
scaled by 9.5 and 95 times for 10X and 100X, respectively.
ments. The ratio of the largest cost to the smallest cost is 1.23 for 1X
volume, 1.76 for 10X volume, and 2.83 for 100X volume. The need
for reticle design space exploration is evidenced by this example. Al-
though we only present the data for I7, the scenarios for the other test
cases are similar to this one. We obtained similar results except that
the mask cost variation is much smaller if the C-model is used for cost
calculation. For the sake of saving space, hereafter we will only show
M
the cost data calculated using the -model.
593
TABLE II
TEST CASES USED FOR OUR EXPERIMENTS. THE FIRST SIX TEST CASES WERE
ORIGINALLY GIVEN IN [13]. IN OUR STUDY, THE REQUIRED PRODUCTION
VOLUMES ARE SCALED BY 10X AND 100X TO SIMULATE LOW TO MEDIUM
VOLUME PRODUCTION. NOTE THAT THE RETICLE SIZE PRESENTED BELOW IS
SET EQUAL TO THE FIELD SIZE FOR EASE OF EXPLANATION
X
Fig. 10. MPW production cost versus 1-wafer dicing yield for I7. axis is
scaled by 0.1, 0.01, and 0.001 times for 1X, 10X, and 100X, respectively.
The ratio of the largest cost to the smallest cost depends highly on
the methods used to generate reticle floorplans. However, most impor-
tantly, we need a floorplanner that can achieve the lowest cost solu-
tion. Compared with the hierarchical quadrisection floorplanner [8],
our floorplanner achieves on average 9% less production cost for all of
the test cases studied in this paper and up to 25% less cost for some test
cases.
594 IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, VOL. 4, NO. 4, OCTOBER 2007
TABLE III
RATIOS OF PRODUCTION COST OBTAINED USING SOME METRICS TO THE SMALLEST PRODUCTION COST
Fig. 11. Cutoff volumes for some chips in I6. The volumes of chips 2, 7, and 13 are scaled one at a time (left). The volumes of chips 6, 7, and 9 are scaled all at
once (right).
B. Production Cost Versus Floorplanning Objectives
Here, we study how MPW production cost varies with some metrics
used in a floorplanning method. Fig. 7 shows how the total produc-
tion cost varies with the reticle area for I7. Smaller reticle area often
corresponds to lower production cost for 1X volume, but not for 10X
and 100X volumes. From Figs. 8–10, we observe that fewer exposures,
fewer wafers, and larger 1-wafer dicing yield normally correspond to
less cost for 10X and 100X volumes. However, if we look into the
figures, several cases exist where the smallest number of exposures,
smallest number of wafers, and largest 1-wafer dicing yield do not
achieve the lowest production cost. Note that the floorplans incurring
the minimal number of wafers for 1X volume production in Fig. 9 are
X
those points whose -coordinates are between 4 and 5. The above phe-
nomenon can be better observed in Table III. Fifty five floorplans are
generated for each test case. We single out the one with the smallest
fabrication cost, the one with the smallest reticle area, the one with
the smallest number of exposures, the one with the smallest number
of wafers, and the one with the largest 1-wafer dicing yield. If there is
a tie, we randomly select one floorplan. As a consequence, four floor-
plans are selected. We calculate the production cost for each of the last
three floorplans. We then compute the ratio of the production cost for
the one with the smallest reticle area to the smallest production cost
(achieved by the first floorplan). This ratio is given in the column de-
noted by “reticle area.” The ratios for “# of exposures,” “# of wafers,”
and “wafer dicing yield” are formed in the same manner. A smaller
ratio means that the underlying metric can have a higher probability of
producing a floorplan that achieves the lowest production cost. Reticle
area is clearly a good metric for 1X volume, but is not a good metric
for the 10X and 100X volumes. As mentioned before, the number of
wafers is the most commonly used metric in a floorplanner. In general,
it corresponds well to the production cost. However, in cases like I5,
the minimal number of wafers does not lead to the lowest production
cost. Therefore, we suggest that a reticle design space exploration be
performed to determine the lowest cost solution.
Our method can still be used when no cost information is available.
We should find a solution that has a small reticle size and incurs the
minimal number of wafers. This solution often corresponds to lower
cost production as can be seen from the data in Table III.
C. MPW for Volume Production
Here, we study to what extent MPW can be used for volume pro-
duction. We first deal with the case where only one project has a larger
volume requirement and the rest of the projects have small volume re-
quirements. We choose a chip with the largest chip area, i.e., chip 7
from I6 to increase its volume until the cost assumed by chip 7 ex-
ceeds the cost of fabricating chip 7 using SPW. The point formed by
intersecting the curve for chip 7’s MPW production cost with the curve
for chip 7’s SPW production cost is called a cutoff point, as shown on
the left of Fig. 11. We do the same thing for chips 2 and 13 (with the
smallest chip area). As one can see, MPW is only viable for a volume
up to a few thousand dice for this case. However, if more chips such
as 6, 7, and 9 have larger production volumes all at once, their cutoff
WANG et al.: LEE et al.: LIN et al.: RETICLE DESIGN FOR MINIMIZING MULTIPROJECT WAFER PRODUCTION COST
points can be up to about 45 000 dice, as shown on the right of Fig. 11.
Note that the same study can also be performed for the case where the
reticles are reused for volume production after prototyping.
VII. CONCLUSION
We proposed a reticle design space exploration methodology for
minimizing MPW production cost. The proposed methodology con-
sists of a reticle floorplanning method, two simulated dicing methods:
HVMIS-SA-Z for 1X volume production and ILP method for 10X and
100X volume production, two production cost calculation models, and
a shared cost calculation procedure. Our methodology often achieves
double-digit cost savings, superior to a method that simply minimizes
the number of wafers used. Our methodology can still be used to find a
solution with small reticle size and the minimal number of wafers when
no cost information is available. Our study also shows that MPW can
still be used for chip fabrication with a production volume up to several
ten thousand dice.
REFERENCES
[1] C. A. Pina, “MOSIS: IC prototyping and low volume production ser-
vice,” in Proc. Int. Conf. Microelectronic Syst. Education, 2001, pp.
4–5.
[2] M. LaPedus, “Is IC Industry Heading to the $10 Million Pho-
tomask?,” Semiconductor Business News, 2002. [Online]. Available:
http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=Z3
KSWRBF50NZEQSNDLOSKH0CJUNN2JVN?articleID=10805993
[3] S. Chen and E. C. Lynn, “Effective placement of chips on a shuttle
mask,” Proc. SPIE, vol. 5130, pp. 681–688, 2003.
[4] A. B. Kahng, I. Mandoiu, Q. Wang, X. Xu, and A. Z. Zelikovsky,
“Multi-project reticle floorplanning and wafer dicing,” in Proc. Int.
Symp. Phys. Design, 2004, pp. 70–77.
[5] G. Xu, R. Tian, D. Z. Pan, and D. F. Wong, “A multi-objective floor-
planner for shuttle mask,” Proc. SPIE, vol. 5567, pp. 340–350, 2004.
[6] IMEC, Annual Report 2003, p. 73.
View publication stats
595
[7] M. C. Wu and R. B. Lin, “Multiple project wafers for medium-volume
IC production,” in Proc. Int. Symp. Circuits Syst., 2005, pp. 4725–4728.
[8] A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, “Yield-driven
multi-project reticle design and wafer dicing,” in Proc. Annu. BACUS
Symp. Photomask Technol., 2005, pp. 1247–1257.
[9] C. C. Chen and W. K. Mak, “A multi-technology-process reticle floor-
planner and wafer dicing planner for multi-project wafers,” in Proc.
Asia and South Pacific Design Autom. Conf., 2006, pp. 777–782.
[10] A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, “Multi-Project
reticle design and wafer dicing under uncertain demand,” in Proc. Eur.
Mask Lithography Conf., Jan. 2006, pp. 45–54.
[11] R. L. S. Ching and E. F. Y. Young, “Shuttle mask floorplanning with
modified alpha-restricted grid,” in Proc. Great Lakes Symp. VLSI, Apr.
2006, pp. 85–90.
[12] R. B. Lin, M. C. Wu, W. C. Tseng, M. H. Kuo, T. Y. Lin, and S. C. Tsai,
“Design space exploration for minimizing multi-project wafer produc-
tion cost,” in Proc. Asia and South Pacific Design Autom. Conf., 2006,
pp. 783–788.
[13] M. C. Wu and R. B. Lin, “Reticle floorplanning and wafer dicing for
multiple project wafers,” in Proc. Int. Symp. Quality Electron. Design,
2005, pp. 610–615.
[14] M. C. Wu, S. C. Tsai, and R. B. Lin, “Floorplanning multiple reticles for
multi-project wafers,” in Proc. Int. Symp. VLSI Design, Autom., Test,
Apr. 2006, pp. 1–4.
[15] M. C. Wu and R. B. Lin, “A comparative study on dicing of multiple
project wafers,” in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2005,
pp. 314–315.
[16] J. Bonn, S. Sisler, and P. Tivnan, “Balancing mask and lithography
cost,” in Proc. Adv. Semiconductor Manuf. Conf., 2001, pp. 25–27.
[17] T. Y. Yang, L. I. Tong, and B. J. C. Yuan, “An innovative model of
multi-project wafer service in the foundry industry,” Int. J. Technol.
Manage., vol. 30, no. 1/2, pp. 172–187, 2005.
[18] D. Pramanik, H. Kamberian, C. Progler, M. Sanie, and D. Pinto,
“Cost effective strategies for ASIC masks,” Proc. SPIE, vol. 5043, pp.
142–152, 2003.
[19] S. Miraglia, C. Blouin, G. Boldman, S. Judd, T. Richardson, and D.
Yao, “ABC modeling: advanced features,” in Proc. Adv. Semiconductor
Manuf. Conf., 2002, pp. 336–339.
[20] Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu, “B -trees: A new
representation for non-slicing floorplans,” in Proc. ACM/IEEE Design
Autom. Conf., Jun. 2000, pp. 458–463.