Lecture 18

Microprogramming and Exceptions

Microcode storage Outputs Datapath control outputs

Input 1 Microprogram counter Adder Address select logic Sequencing control

Inputs from instruction register opcode field

Microinstruction Format
ALU Control
What is done

ALU SRC1

ALU SRC2

Register Control
R or W Source for W

Memory

PCWrite Control
When to write

Sequencing

Operand sources

R or W Source for W

What comes next

Microprogramming
Label: any string, direct targets for sequencing, or dispatch to jump tables. ALU Control: Add, Subt, or Func Code. SRC1: PC, register A.

. SRC2: B, 4, Extend, Extshft.

Register Control: Write ALU, Write MDR. Memory: Read PC, Read ALU, Write ALU. PCWrite Control: ALU, ALUOut-cond, Jump address. Sequencing: Seq, Fetch, Dispatch i.

Figure 5.33: Complete Datapath for a Multicycle Machine

PCWriteCond PCSource PCWrite ALUOp IorD Outputs ALUSrcB MemRead ALUSrcA MemWrite Control RegWrite MemtoReg IRWrite Op [50] RegDst 0

Instruction [250] Instruction [31-26]

26

Shift left 2

28

Jump address [31-0]

1 u
x 2

PC

0 M u x 1

Address
Memory MemData Write data

Instruction [2521] Instruction [2016] Instruction [150] Instruction register Instruction [150] Memory data register

Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 Write data A

0 M Instruction u x [1511] 1 0 M u x 1

0 M u x 1 0 4 1 M u 2 x 3

PC [31-28]

Zero ALU ALU result

ALUOut

16

Sign extend

32

Shift left 2

ALU control

Instruction [50]

Question: What is dispatch i? Dispatch is an operation similar to a switch or case statement. There can be two dispatch tables, indicated by the i value, which can be either 1 or 2.
Address select logic

opcode, i

Dispatch ROM 1 Mem1, Rformat1, BEQ1, JUMP1

Dispatch ROM 2 LW2, SW2

PC

to ROM

An Example in Microprogramming Instruction Fetching

Label Fetch ALU Control Add Add ALU SRC1 PC PC ALU SRC2 4 Extshft Read Register Control Memory ReadPC PCWrite Control ALU Sequencing Seq Dispatch 1

1) ALU Control, SRC1, SRC2: ALU = PC+4 Memory: IR = instruction PCWrite Control: PC = ALU Sequencing: next microinstruction 2) ALU Control, SRC1, SRC2: ALUOut = PC + sign extension (IR[15-0]) << 2 (just in case next instruction is a branch) Register control: A = rs, B = rt Sequencing: use opcode and dispatch table 1 to choose what comes next (will go to one of these labels Mem1, RFormat1, BEQ1, JUMP1)

Another Example in Microprogramming Memory instructions

Label Mem1 LW2 Write MDR SW2 WriteALU ALU Control Add ALU SRC1 A ALU SRC2 Extend ReadALU Register Control Memory PCWrite Control Sequencing Dispatch 2 Seq Fetch Fetch

1) Whether its lw or sw, I must compute the address referenced: addr = A + Extend lw: read from memory the data addressed by the output of the ALU and then write it to the MDR

3) sw: take the contents of register B and write the data to the memory position addressed by the output of the ALU Note: the microcode for every instruction ends with a jump to Fetch.

From Microprogram to Machine Code

Each value in the fields of a microinstruction has associated values for the control lines. Register control ALU control Read Add ALUOp=00 Write RegWrite=1, Subt ALUOp=01 ALU RegDst=1, Funct ALUOp=10 MemtoReg=0 code Write RegWrite=1, MDR RegDst=0, MemtoReg=1

Dont write the microprogram bit by bit: use a microprogram assembler.

Read Appendix C for more details.

Exceptions and Interrupts (must read: A.7) d-oh! or --it happens

Undefined instruction Arithmetic overflow Hardware malfunction Debugger breakpoint Call the OS
Unexpected change in control flow (int. or ext.)

wake up calls
I/O device request Bus error Hardware malfunction

Something outside the CPU requires attention: control flow also changes unexpectedly

When an exception or an interrupt happens, the normal instruction flow is disrupted so that this unexpected event can be dealt with. User code is stopped, perhaps temporarily, and a branch happens to an interrupt handler. We must know what caused the interruption so we know what course of action it demands.
EPC
register

Cause
register

Stores the address of the offending instruction

Bits in this register indicate what triggered the exception

We need control and data signals for these registers.

10

Question: how do we determine where to branch? a) We always branch to the same address (MIPS): 0xC0000000. b) The address of the branch is determined by the cause of the exception (vectored interrupts). Question: how do we put the address of this branch in the PC? Change the MUX to 4-way and add another control value to the selection control => PCSource =11. Complication: the PC has already been incremented by the fetch datapath. Hook up the data input of the EPC to the ALU, which is used to subtract 4 from the current value of the PC.

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Modifying Control to Deal with Exceptions Basic types of exceptions in MIPS: 1) Undefined Instruction: no next state when inspecting opcode. 2) Arithmetic Overflow: information comes from the ALU. Modifications to the FSM for the Control Unit
(see Figure 5.50 for complete FSM)
11 IntCause = 1 CauseWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 01 EPCWrite PCWrite PCSource = 11 PCSource = 11

10

IntCause = 0 CauseWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 01 EPCWrite PCWrite PC++Source = 11

To state 0 to begin next instruction

12

PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Control Op Outputs

CauseWrite IntCause EPCWrite PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst 0

PC

Address
Memory MemData Write data

Instruction Instruction Instruction register Instruction

Memory data register

% $ #  !    " 

0 M u x 1

Instruction [31-26] Instruction Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 Write data A

0 M Instruction u x 1 0 M u x 1

   
16

26

Shift left 2

28

Jump address [31-0]

1M
2 3 u x

% $ #  !    " 
0 M u x 1 0 4 1M u 2 x 3 B Sign extend
32

CO 00 00 00
PC [31-28]

Zero ALU ALU result

ALUOut

EPC

1 Shift left 2 ALU control

0 M u x 1

Cause

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