Lecture 21

Detecting and Handling Hazards

Pipeline Hazards
What if the next instruction cannot execute in the following clock cycle?
Structural hazard: Bad hardware support. We cant execute a combo of instructions in the same clock cycle. Example: memory. Solution: stall, design. Data hazard : An instruction depends on the result result of a previous instruction that is still in the pipeline.. add $s0, $t0, $t1 Example:
sub $t2, $s0, $t3

Control hazard: The result of one instruction determines what happens to other instructions.. Example: branch. Solutions: stall, reorder, predict.

Solution: stall, reorder, forwarding (or bypassing).

Data Hazards and Forwarding

sub and or add sw

$2, $12, $13, $14, $15,

$1, $3 $2, $5 $6, $2 $2, $2 100($2)

Time (in clock cycles) CC 1 Value of register $2: 10 Program execution order (in instructions) sub $2, $1, $3 IM Reg DM Reg CC 2 10 CC 3 10 CC 4 10 CC 5 10/20 CC 6 20 CC 7 20 CC 8 20 CC 9 20

and $12, $2, $5

IM

Reg

DM

Reg

or $13, $6, $2

IM

Reg

DM

Reg

add $14, $2, $2

IM

Reg

DM

Reg

sw $15, 100($2)

IM

Reg

DM

Reg

Possible solution: Let the compiler resolve the hazard sub

Hardware design: Register writes always happen at the first half of the clock cycle. Register reads always happen at the second half the clock cycle. No hazard for data that is written and read in the same clock cycle.

$2,

$1,

$3

nop

bubble

nop

bubble

and or add sw

$12, $13, $14, $15,

$2, $5 $6, $2 $2, $2 100($2)

Question: What is the drawback of this solution?

sub

$2,

$1,

$3

sub and or add sw

$2, $12, $13, $14, $15,

$1, $3 $2, $5 $6, $2 $2, $2 100($2)

nop

bubble

nop bubble and or add sw $12, $13, $14, $15, $2, $5 $6, $2 $2, $2 100($2)

nop = sll $0,$0,0

Time (in clock cycles) 10 10 10

Program execution order (in instructions) sub $2, $1, $3 IM Reg DM Reg

and $12, $2, $5

IM

Reg

DM

Reg

or $13, $6, $2

IM

Reg

DM

Reg

add $14, $2, $2

IM

Reg

DM

Reg

sw $15, 100($2)

IM

Reg

DM

Hardware design: * Register writes always happen at the first half of the clock cycle. * Register reads always happen at the second half the clock cycle. * No hazard for data that is written and read in the same clock cycle.

Reg

CC 1 Value of register $2: 10

CC 2

CC 3

CC 4

CC 5

CC 6

CC 7

CC 8

CC 9

IF/ID ID/EX EX/MEM MEM/WB

Question: How can one spot a hazard is in progress? 1a. EX/MEM.Rd = ID/EX.Rs 1b. EX/MEM.Rd = ID/EX.Rt 2a. MEM/WB.Rd = ID/EX.Rs 2b. MEM/WB.Rd = ID/EX.Rt
(*) Detectable when sub is in MEM.

Example:

sub and or

$2, $1, $3 $12, $2, $5 * $13, $6, $2 **

(**) Detectable when sub is in WB.

Constraints: 1) Not all instructions write to registers: need to forward data which is written to and then read from a register => look at RegWrite in WB field of EX and MEM. 2) $0 must always have 0; must be careful not to forward anything if foolish programmer used $0 as destination. This way programmers are protected from their own mistakes. 3) The register file takes care of internally forwarding data that is written to and read from in the same clock cycle.

DM DM DM Reg Reg Reg IM IM IM Reg Reg Reg IM IM IM

Reg Reg Reg DM DM DM Reg Reg Reg DM DM DM Reg Reg Reg IM IM IM Reg Reg Reg Reg Reg Reg DM DM DM Reg Reg Reg DM DM DM Reg Reg Reg

and $12, $2, $5 and $12, $2, $5 and $12, $2, $5 or $13, $6, $2 or $13, $6, $2 or $13, $6, $2 add $14, $2, $2 add $14, $2, $2 add $14, $2, $2 sw $15, 100($2) sw $15, 100($2) sw $15, 100($2)

IM IM IM

Notice how data is now forwarded from pipeline registers to the ALU.

     

     

     

     

               

     

Time (in clock cycles) Time (in clock cycles) Time CC clock cycles) (in 1 CC 22 CC 1 CC CC 2 Value of register $2 :CC 1 10 Value of register $2 : 10 10 10 Value register $2 10 X Value of of EX/MEM: : : X 10 Value of EX/MEM X X Value of MEM/WB : : X X Value of EX/MEM : X X X MEM/WB X X Value of MEM/WB : X Program Program execution order Program order execution (in instructions) execution order (in instructions) (in sub $2, $1, $3 instructions) Reg IM Reg sub $2, $1, $3 IM IM Reg sub $2, $1, $3

CC 33 CC CC 3 10 10 X 10 X X X X X

CC 44 CC CC 4 10 10 10 X X X

CC 55 CC CC 5 X X X

CC 66 CC CC 6 X X X X X X

CC 77 CC CC 7 X X X X X X

CC 88 CC CC 8 X X X X X X

CC 99 CC CC 9 X X X X X X

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Question: The forwarding scheme adds alternative sources to the inputs of the ALU. How does this change the datapath?
ID/EX
WB Control M EX

EX/MEM
WB M

MEM/WB
WB

IF/ID

Instruction

M u x Registers
ALU

PC

Instruction memory

Data memory

M u x IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd Rs Rt Rt Rd M u x Forwarding unit EX/MEM.RegisterRd

M u x

MEM/WB.RegisterRd

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Controlling the Forwarding Unit

1) EX hazard:
if ((EX/MEM.RegWrite) and (!EX/MEM.RegisterRd) and (EX/MEM.RegisterRd=ID/EX.RegisterRs)) then ForwardA=10 if ((EX/MEM.RegWrite) and (!EX/MEM.RegisterRd) and (EX/MEM.RegisterRd=ID/EX.RegisterRt)) then ForwardB=10

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Controlling the Forwarding Unit

2) MEM hazard:
if ((MEM/WB.RegWrite) and (!MEM/WB.RegisterRd) and (MEM/WB.RegisterRd=ID/EX.RegisterRs)) then ForwardA=01 if ((MEM/WB.RegWrite) and (!MEM/WB.RegisterRd) and (MEM/WB.RegisterRd=ID/EX.RegisterRt)) then ForwardB=01

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MUX control
ForwardA=00 ForwardA=10 ForwardA=01 ForwardB=00 ForwardB=10 ForwardB=01

Source
ID/EX EX/MEM MEM/WB ID/EX EX/MEM MEM/WB

Explanation
1st ALU from RegFile 1st ALU forwarded from ALU result 1st ALU from data memory or earlier ALU result 2nd ALU from RegFile 2nd ALU forwarded from ALU result 2nd ALU from data memory or earlier ALU result
ID/EX
WB

EX/MEM
WB M

Control

M EX

MEM/WB
WB

IF/ID

Instruction

M u x Registers

A
ALU

PC

Instruction memory

M u x IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd Rs Rt Rt Rd M u x

Data memory

M u x

EX/MEM.RegisterRd

Forwarding unit

MEM/WB.RegisterRd

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Work through the example of the execution of four instructions starting in page 485!

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Question: does this datapath now cover for all cases of hazard resolution by forwarding?
ID/EX EX/MEM MEM/WB

M u x Registers ALUSrc

ALU
Data memory

M u x

M u x

M u x

M u x Forwarding unit

ALU source selection to deal with signed immediates.

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Question: again, does this datapath now cover for all cases of hazard resolution by forwarding?
Time (in clock cycles) Program CC 1 execution order (in instructions) lw $2, 20($1) IM CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9

Reg

DM

Reg

and $4, $2, $5

IM

Reg

DM

Reg

or $8, $2, $6

IM

Reg

DM

Reg

add $9, $4, $2

IM

Reg

DM

Reg

slt $1, $6, $7

IM

Reg

DM

Reg

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Hazard Detection Unit

if ((ID/EX.MemRead) and ((ID/EX.RegisterRt=IF/ID.RegisterRs) or (ID/EX.RegisterRt=IF/ID.RegisterRt))) then

stall the pipeline

stall the pipeline: deassert all control lines in stages EX, MEM and WB to accomplish a do nothing effect (bubble). The bubble floats on through the pipeline. This happens at the ID stage. We must also guarantee that during the stalled cycle, PC and IF/ID dont change.

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Time (in clock cycles) Program execution CC 1 CC 2 order (in instructions) lw $2, 20($1) IM Reg

CC 3

CC 4

CC 5

CC 6

CC 7

CC 8

CC 9

CC 10

DM

Reg

and $4, $2, $5

IM

Reg

Reg

DM

Reg

or $8, $2, $6

IM

IM bubble

Reg

DM

Reg

add $9, $4, $2

IM

Reg

DM

Reg

slt $1, $6, $7

IM

Reg

DM

Reg

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Hazard detection unit

ID/EX.MemRead ID/EX
WB Control 0 M u x M EX

IF/IDWrite

EX/MEM
WB M

MEM/WB
WB

IF/ID

PCWrite

Instruction

M u x Registers
ALU

PC

Instruction memory

Data memory

M u x IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd Rt Rd Rs Rt M u x Forwarding unit EX/MEM.RegisterRd

M u x

ID/EX.RegisterRt

MEM/WB.RegisterRd

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Work through the example of the execution of five instructions starting in page 491!

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