Digital Computers

➢ A Digital computer can be considered as a digital system that performs various

computational tasks.
➢ The Central Processing Unit (CPU) contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data, and a control circuit
for fetching and executing instructions.
➢ The memory unit of a digital computer contains storage for instructions and
data.
➢ The Random Access Memory (RAM) for real-time processing of the data.
➢ The Input-Output devices for generating inputs from the user and displaying
the final results to the user.
➢ The Input-Output devices connected to the computer include the keyboard,
mouse, terminals, magnetic disk drives, and other communication devices.
Explanation of Different layers present
•Hardware : Hardware of a computer system consists of CPU, Main
memory, I/O Devices, Secondary Storage etc.

• BIOS : BIOS (basic input/output system) is the program (Firmware) a

personal computer's microprocessor uses to get the computer system
started after you turn it on. It also manages data flow between the
computer's operating system and attached devices such as the hard disk,
video adapter, keyboard, mouse and printer.

• Operating System: A set of programs that acts as the interface between

user programs and computer hardware.

• Application Program: High level instructions

1. Unsigned Numbers:
Unsigned numbers don’t have any sign, these can contain only magnitude of the
number. So, representation of unsigned binary numbers are all positive numbers
only. For example, representation of positive decimal numbers are positive by
default. We always assume that there is a positive sign symbol in front of every
number.
Representation of Unsigned Binary Numbers:
Since there is no sign bit in this unsigned binary number, so N bit binary number
represent its magnitude only. Zero (0) is also unsigned number. This
representation has only one zero (0), which is always positive. Every number in
unsigned number representation has only one unique binary equivalent form, so
this is unambiguous representation technique. The range of unsigned binary
number is from 0 to (2n-1).

Example-1: Represent decimal number 92 in unsigned binary number.

Simply convert it into Binary number, it contains only magnitude of the given
number.
= (92)10
= (1x26+0x25+1x24+1x23+1x22+0x21+0x20)10
= (1011100)2
It’s 7 bit binary magnitude of the decimal number 92.
Example-2: Find range of 5 bit unsigned binary numbers. Also, find minimum
and maximum value in this range.
Since, range of unsigned binary number is from 0 to (2n-1). Therefore, range of
5 bit unsigned binary number is from 0 to (25-1) which is equal from minimum
value 0 (i.e., 00000) to maximum value 31 (i.e., 11111).

2. Signed Numbers:
Signed numbers contain sign flag, this representation distinguish positive and
negative numbers. This technique contains both sign bit and magnitude of a
number. For example, in representation of negative decimal numbers, we need to
put negative symbol in front of given decimal number.
Representation of Signed Binary Numbers:
There are three types of representations for signed binary numbers. Because of
extra signed bit, binary number zero has two representation, either positive (0) or
negative (1), so ambiguous representation. But 2’s complementation
representation is unambiguous representation because of there is no double
representation of number 0. These are: Sign-Magnitude form, 1’s complement
form, and 2’s complement form which are explained as following below.
Sign-Magnitude form:
For n bit binary number, 1 bit is reserved for sign symbol. If the value of sign bit
is 0, then the given number will be positive, else if the value of sign bit is 1, then
the given number will be negative. Remaining (n-1) bits represent magnitude of
the number. Since magnitude of number zero (0) is always 0, so there can be two
representation of number zero (0), positive (+0) and negative (-0), which depends
on value of sign bit. Hence these representations are ambiguous generally because
of two representation of number zero (0). Generally sign bit is a most significant
bit (MSB) of representation. The range of Sign-Magnitude form is from (2(n-1)-
1) to (2(n-1)-1).
For example, range of 6 bit Sign-Magnitude form binary number is from (25-
1) to (25-1) which is equal from minimum value -31 (i.e., 1 11111) to maximum
value +31 (i.e., 0 11111). And zero (0) has two representation, -0 (i.e., 1
00000) and +0 (i.e., 0 00000).
1’s complement form:
Since, 1’s complement of a number is obtained by inverting each bit of given
number. So, we represent positive numbers in binary form and negative numbers
in 1’s complement form. There is extra bit for sign representation. If value of sign
bit is 0, then number is positive and you can directly represent it in simple binary
form, but if value of sign bit 1, then number is negative and you have to take 1’s
complement of given binary number. You can get negative number by 1’s
complement of a positive number and positive number by using 1’s complement
of a negative number. Therefore, in this representation, zero (0) can have two
representation, that’s why 1’s complement form is also ambiguous form. The
range of 1’s complement form is from (2(n-1)-1) to (2(n-1)-1) .
For example, range of 6 bit 1’s complement form binary number is from (25-
1) to (25-1) which is equal from minimum value -31 (i.e., 1 00000) to maximum
value +31 (i.e., 0 11111). And zero (0) has two representation, -0 (i.e., 1
11111) and +0 (i.e., 0 00000).
2’s complement form:
Since, 2’s complement of a number is obtained by inverting each bit of given
number plus 1 to least significant bit (LSB). So, we represent positive numbers
in binary form and negative numbers in 2’s complement form. There is extra bit
for sign representation. If value of sign bit is 0, then number is positive and you
can directly represent it in simple binary form, but if value of sign bit 1, then
number is negative and you have to take 2’s complement of given binary number.
You can get negative number by 2’s complement of a positive number and
positive number by directly using simple binary representation. If value of most
significant bit (MSB) is 1, then take 2’s complement from, else not. Therefore, in
this representation, zero (0) has only one (unique) representation which is always
positive. The range of 2’s complement form is from (2(n-1)) to (2(n-1)-1).
For example, range of 6 bit 2’s complement form binary number is from (25) to
(25-1) which is equal from minimum value -32 (i.e., 1 00000) to maximum value
+31 (i.e., 0 11111). And zero (0) has two representation, -0 (i.e., 1 11111) and
+0 (i.e., 0 00000).
Fixed point arithmatic operation
•Addition

•Subtraction

•Multiplication

•Division

Fixed-point representation has a radix point known as decimal point. Fixed-point

numbers having decimal points at the right end of the number are treated as
integers because the fixed-point numbers having decimal points at the left end of
the number are treated as fractions. In this method, the decimal point position is
settled because the number saved in the memory is considered as an integer or as
a fraction.

The binary numbers that are unsigned are continually considered as positive
integers and are defined as 0s in the MSB. The binary numbers that are registered
contrast for negative numbers and are defined as 1s in the MSB.

Float Point Number System

• All numbers are represented as an integer or fraction.

• Fractions are frequently used in computer system.

• Floating point representation of number keeps track of the position of the

radix(binary) point.

• In floating point representation, a number has two parts, first part is mantissa
or fraction and the second part is exponent.

• EX. 711.2233------- +.7112233 +03

Overflow and Underflow

Simply put, overflow and underflow happen when we assign a value that is out of
range of the declared data type of the variable.
If the (absolute) value is too big, we call it overflow, if the value is too small,
we call it underflow.
Let's look at an example where we attempt to assign the
value 101000 (a 1 with 1000 zeros) to a variable of type int or double. The value is
too big for an int or double variable in Java, and there will be an overflow.
As a second example, let's say we attempt to assign the value 10-1000 (which is very
close to 0) to a variable of type double. This value is too small for
a double variable in Java, and there will be an underflow.

Overflow
As for the integer data types, we might expect that:
assertTrue(Double.MAX_VALUE + 1 == Double.MIN_VALUE);
However, that is not the case for floating-point variables. The following is true:
assertTrue(Double.MAX_VALUE + 1 == Double.MAX_VALUE);
This is because a double value has only a limited number of significant bits. If
we increase the value of a large double value by only one, we do not change
any of the significant bits. Therefore, the value stays the same.
If we increase the value of our variable such that we increase one of the significant
bits of the variable, the variable will have the value INFINITY:
assertTrue(Double.MAX_VALUE * 2 == Double.POSITIVE_INFINITY);
and NEGATIVE_INFINITY for negative values:
assertTrue(Double.MAX_VALUE * -2 == Double.NEGATIVE_INFINITY);
We can see that, unlike for integers, there's no wraparound, but two different
possible outcomes of the overflow: the value stays the same, or we get one of
the special values, POSITIVE_INFINITY or NEGATIVE_INFINITY.

Underflow
There are two constants defined for the minimum values of
a double value: MIN_VALUE (4.9e-324)
and MIN_NORMAL (2.2250738585072014E-308).
IEEE Standard for Floating-Point Arithmetic (IEEE 754) explains the details for
the difference between those in more detail.
Let's focus on why we need a minimum value for floating-point numbers at all.
A double value cannot be arbitrarily small as we only have a limited number
of bits to represent the value.
The chapter about Types, Values, and Variables in the Java SE language
specification describes how floating-point types are represented. The minimum
exponent for the binary representation of a double is given as -1074. That means
the smallest positive value a double can have is Math.pow(2, -1074), which is
equal to 4.9e-324.
As a consequence, the precision of a double in Java does not support values
between 0 and 4.9e-324, or between -4.9e-324 and 0 for negative values.
So what happens if we attempt to assign a too-small value to a variable of
type double? Let's look at an example:
for(int i = 1073; i <= 1076; i++) {
System.out.println("2^" + i + " = " + Math.pow(2, -i));
}
With output:
2^1073 = 1.0E-323
2^1074 = 4.9E-324
2^1075 = 0.0
2^1076 = 0.0
We see that if we assign a value that's too small, we get an underflow, and the
resulting value is 0.0 (positive zero).
Similarly, for negative values, an underflow will result in a value of -0.0 (negative
zero).

Detecting Underflow and Overflow of Floating-

Point Data Types
As overflow will result in either positive or negative infinity, and underflow in
a positive or negative zero, we do not need exact arithmetic methods like for
the integer data types. Instead, we can check for these special constants to detect
over- and underflow.
If we want to throw an exception in this situation, we can implement a helper
method. Let's look at how that can look for the exponentiation:
public static double powExact(double base, double exponent) {
if(base == 0.0) {
return 0.0;
}

double result = Math.pow(base, exponent);

if(result == Double.POSITIVE_INFINITY ) {
throw new ArithmeticException("Double overflow resulting in POSITIVE_INFINITY");
} else if(result == Double.NEGATIVE_INFINITY) {
throw new ArithmeticException("Double overflow resulting in NEGATIVE_INFINITY");
} else if(Double.compare(-0.0f, result) == 0) {
throw new ArithmeticException("Double overflow resulting in negative zero");
} else if(Double.compare(+0.0f, result) == 0) {
throw new ArithmeticException("Double overflow resulting in positive zero");
}

return result;
}
 COA
Topic
Binary ADDER

• Presented By
• Dr. Sudipta Basu Pal
 What is an Adder?
• An adder is a kind of calculator that is used to
add two binary numbers. In many computers
and other types of processors, adders are
used to calculate addresses, similar operations
and table indices in the ALU and also in other
parts of the processors.
 Two kinds of Adder
• 1.Half adder
• 2. Full adder
 Half Adder Operations
• With the help of half adder, we can design circuits that
are capable of performing simple addition with the
help of logic gates.
• Let us first take a look at the addition of single bits.
• 0+0 = 0
• 0+1 = 1
• 1+0 = 1
• 1+1 = 10
• These are the least possible single-bit combinations.
But the result for 1+1 is 10
 Rewrite the equations
• 0+0 = 00
• 0+1 = 01
• 1+0 = 01
• 1+1 = 10
So, here the output ‘1’of ‘10’ becomes the carry-
out.
Sum is the normal output and ‘CARRY’ is the
normal carry-out.
Truth Table and Circuit Diagram
Full ADDER
Full Adder truth table
Multi Bit Addition
Definition of Adder
Types of Binary Adder
DIFFERENT TYPES OF ADDER
Parallel Adder
Circuit of Parallel Adder
Working of Parallel Adder
Ripple Carry Adder
Ripple Carry Adder
Circuit For Ripple Carry Order
Ripple Carry Adder Truth Table
Maximum Propagation Delay of Ripple
Carry Adder
Uses of Ripple Carry Adder
Carry Look Ahead Adder (CLA)
Basic Structure of CLA
 Steps to CLA
Curse of the Carry
Full Adder: What is carry Propagation
Full Adder with Propagate and
Generate
Full Adder Circuit to Carry Generation
And Propagation
Circuit of Propagate and Delay
Truth Table for Carry Generation And
Propagation
Expression
Boolean Expression Received
Boolean Expression of the carry
Outputs After nth Stage
Carry look Ahead Structure Can be
divided in three parts
Propagate / Generate Generator
Figure 1
Sum Generator
Fast Adder Architectures
 MULTIPLIER
• ARRAY MULTIPLIER

Presented By
Dr. Sudipta Basu Pal

1
 MULTIPLICATION OF UNSIGNED
NUMBERS
• Two unsigned number can be multiplied the
same way as two decimal number by manual
method, presented in following table.

2
Hardware Realization of the method
4x4 Array multiplier

3
• This method can be implemented by using AND
gate and full adder.
• The hardware realization of this method for 4 bit
multiplier, Q& 4 bit multiplicand, M is shown in
following figure.

4
 MULTIPLIER
Sequential Multiplier

5
 SEQUENTIAL MULTIPLICATION
METHOD FOR UNSIGNED NUMBER
• An n x n unsigned multiplier has three n bit
registers, A, M, Q.
• Register, A is called accumulator, initialized with ‘n’
number of ‘0’s.
• When the algorithm terminates, the register A
holds higher n bits &register Q holds lower order n
bits of the product.
• Beside that, there is a one bit register, F which
holds intermediate carry value.
• The multiplication method is described in
following flowchart.
6
FLOWCHART

7
 Multiplier, Q = 14 = 11102
Multiplicand, M = 6 = 01102
FINAL PRODUCT: AQ = 0101 01002= 8410

8
 Multiplier, Q = 11 = 10112
Multiplicand, M = 5 = 01012
FINAL PRODUCT: AQ = 0011 01112= 5510

9
 MULTIPLIER
Booth's multiplication algorithm for
Signed Number
• Booth's multiplication algorithm for Signed
Number
• Booth's multiplication algorithm is an
algorithm which multiplies 2 signed or
unsigned integers in 2's complement.
• This approach uses fewer additions and
subtractions than more straightforward
algorithms.
10
PROCEDURE

11
CONDITIONS

12
 Booth's multiplication algorithm for
Signed Number
• Booth's multiplication algorithm is an
algorithm which multiplies 2 signed in 2's
complement.
• This approach uses fewer additions and
subtractions than more straightforward
algorithms.

13
 Right Shift
• Right Shift of one position moves each bit to
the right by one.
• The least significant bit is discarded
•The vacant MSB is filled with zero.

14
 Arithmetic Right Shift
• A Arithmetic Right Shift of one position moves
each bit to the right by one.
• The least significant bit is discarded
• The vacant MSB is filled with the value of the
previous (now shifted one position to the
right) MSB.

15
Flow Chart Booth's multiplication
algorithm

16
Restoring Division Algorithm For Unsigned Integer
A division algorithm provides a quotient and a remainder when we divide two
number. They are generally of two type slow algorithm and fast algorithm.
Slow division algorithm are restoring, non-restoring, non-performing restoring,
SRT algorithm and under fast comes Newton–Raphson and Goldschmidt.
In this article, will be performing restoring algorithm for unsigned integer.
Restoring term is due to fact that value of register A is restored after each
iteration.

Here, register Q contain quotient and register A contain remainder. Here, n-bit
dividend is loaded in Q and divisor is loaded in M. Value of Register is initially
kept 0 and this is the register whose value is restored during iteration due to
which it is named Restoring.
Let’s pick the step involved:
•
Step-1: First the registers are initialized with corresponding values (Q =
Dividend, M = Divisor, A = 0, n = number of bits in dividend)
• Step-2: Then the content of register A and Q is shifted left as if they are a
single unit
• Step-3: Then content of register M is subtracted from A and result is
stored in A
• Step-4: Then the most significant bit of the A is checked if it is 0 the least
significant bit of Q is set to 1 otherwise if it is 1 the least significant bit of
Q is set to 0 and value of register A is restored i.e the value of A before
the subtraction with M
• Step-5: The value of counter n is decremented
• Step-6: If the value of n becomes zero, we get of the loop otherwise we
repeat from step 2
• Step-7: Finally, the register Q contain the quotient and A contain
remainder
Examples:
Perform Division Restoring Algorithm
Dividend = 11
Divisor = 3

n M A Q Operation

4 00011 00000 1011 initialize

00011 00001 011_ shift left AQ

00011 11110 011_ A=A-M

00011 00001 0110 Q[0]=0 And restore A

3 00011 00010 110_ shift left AQ

00011 11111 110_ A=A-M

00011 00010 1100 Q[0]=0

2 00011 00101 100_ shift left AQ

00011 00010 100_ A=A-M

 n M A Q Operation

00011 00010 1001 Q[0]=1

1 00011 00101 001_ shift left AQ

00011 00010 001_ A=A-M

00011 00010 0011 Q[0]=1

Remember to restore the value of A most significant bit of A is 1. As that register Q

contain the quotient, i.e. 3 and register A contain remainder 2.
 Float Point Number System
• IEEE754
(Module-2)

Presented By
Dr. Sudipta Basu Pal

1
 Float Point Number System
• All numbers are represented as an integer or
fraction.
• Fractions are frequently used in computer
system.
• Floating point representation of number keeps
track of the position of the radix(binary) point.
• In floating point representation, a number has
two parts, first part is mantissa or fraction and
the second part is exponent.
• EX. 711.2233------- +.7112233 +03
 IEEE 754
• The IEEE Standard for Floating-Point Arithmetic
(IEEE 754) is a technical standard for floating-
point computation.
• IEEE Standard 754 floating point is the most
common representation 16today for real
numbers on computers, including Intel-based
PC’s, Macs, and most Unix platforms
• IEEE 754 has 3 basic components
• i) The Sign of Mantissa
• ii) The Biased exponent
• iii)The Normalised Mantissa
 IEEE 754
• •The IEEE Standard for Floating-Point
Arithmetic (IEEE 754) is a technical standard
for floating-point computation.
• General format of floating point number :

where ,
•M is the mantissa
•r is the base
•E is the exponent
•S is the sign,
• can take values 0 or 1.
 IEEE 754
 The Sign of Mantissa –
• 0 represents a positive number
• 1 represents a negative number.
 The Biased exponent –
The exponent field needs to represent both positive and
negative exponents. A bias is added to the actual exponent
in order to get the stored exponent.
 The Normalised Mantissa –
The mantissa is part of a number in scientific notation or a
floating-point number, consisting of its significant digits.
Here we have only 2 digits, i.e. O and 1. So a normalised
mantissa is one with only one 1 to the left of the decimal.
 IEEE 754 : Two formats
• Single precision:
• There are 32 bits in Standard IEEE 754
representation of floating point numbers in
binary and is divided into three parts namely
as follows

The implied base is 2.

The value stored in exponent field is an unsigned integer
E’ •E’=E+127
 Single precision
Q. Represent the binary positive number
1101011 in IEEE single precision format.
 •Single precision

• Q. Represent following decimal numbers in

IEEE single precision format.

i) -1.75
ii) 21
 IEEE 754 : Two formats
• Double precision:
• There are 64 bits in Standard IEEE 754
representation of floating point numbers in
binary and is divided into three parts namely
as follows
GATE QUESTION
Solution
 Division Algorithms
• A division algorithm provides a quotient and a
remainder when we divide two number. Paper
and pencil (manual method was used).

• Dividend=Quotient x Divisor+ Remainder

 Division Algorithms
• They are generally of two type slow algorithm
and fast algorithm.
• Slow division algorithm is restoring, non-
restoring, non-performing restoring, SRT
algorithm and under fast comes Newton–
Raphson and Goldschmidt.
 Division Algorithm
(Restoring algorithm)
• In this presentation, will be performing restoring
algorithm for unsigned integer. Restoring term is
due to fact that value of register A is restored
after each iteration.

• Here, register Q contain quotient and register A

contain remainder. Here, n-bit dividend is loaded
in Q and divisor is loaded in M. Value of Register
A is initially kept 0 and this is the register whose
value isrestored during iteration due to which it is
named Restoring.
 DIVISION OF UNSIGNED
(Restoring Division Algorithm)
 Dividend, Q = 11 = 1011
Divisor, M = 3 = 0011
• Remember to restore the value of A most significant bit of A is 1.
• Register Q contain the Quotient, i.e. 3;
• Register A contain Remainder, i.e. 2.
 Dividend, Q = 7 = 111
Divisor, M = 3 = 011
• Remember to restore the value of A most significant bit of A is 1.
• Register Q contain the Quotient, i.e. 2;
• Register A contain Remainder, i.e. 1.
 Division Algorithm
(Non Restoring algorithm)
• Now, here perform Non-Restoring division, it
is less complex than the restoring one because
simpler operation are involved i.e. addition
and subtraction, also now restoring step is
performed.

• In the method, rely on the sign bit of the

register which initially contain zero named as
A.
DIVISION OF UNSIGNED NUMBERS (Non Restoring Division
Algorithm)
 Dividend, Q = 11 = 1011
Divisor, M = 3 = 0011
• Remember to restore the value of A most significant bit of A is 1.
• Register Q contain the Quotient, i.e. 3;
• Register A contain Remainder, i.e. 2.
Design of ALU
Inside a computer, there is an Arithmetic Logic Unit (ALU), which is capable of performing
logical operations (e.g. AND, OR, Ex-OR, Invert etc.) in addition to the arithmetic operations
(e.g. Addition, Subtraction etc.). The control unit supplies the data required by the ALU from
memory, or from input devices, and directs the ALU to perform a specific operation based on
the instruction fetched from the memory. ALU is the “calculator” portion of the computer.

An arithmetic logic unit(ALU) is a major component of the central processing unit of the a
computer system. It does all processes related to arithmetic and logic operations that need to
be done on instruction words. In some microprocessor architectures, the ALU is divided into
the arithmetic unit (AU) and the logic unit (LU).
An ALU can be designed by engineers to calculate many different operations. When the
operations become more and more complex, then the ALU will also become more and more
expensive and also takes up more space in the CPU and dissipates more heat. That is why
engineers make the ALU powerful enough to ensure that the CPU is also powerful and fast,
but not so complex as to become prohibitive in terms of cost and other disadvantages.
ALU is also known as an Integer Unit (IU). The arithmetic logic unit is that part of the CPU
that handles all the calculations the CPU may need. Most of these operations are logical in
nature. Depending on how the ALU is designed, it can make the CPU more powerful, but it
also consumes more energy and creates more heat. Therefore, there must be a balance between
how powerful and complex the ALU is and how expensive the whole unit becomes. This is
why faster CPUs are more expensive, consume more power and dissipate more heat.
Different operation as carried out by ALU can be categorized as follows –

• logical operations − These include operations like AND, OR, NOT, XOR, NOR,
NAND, etc.
• Bit-Shifting Operations − This pertains to shifting the positions of the bits by a certain
number of places either towards the right or left, which is considered a multiplication
or division operations.

• Arithmetic operations − This refers to bit addition and subtraction. Although

multiplication and division are sometimes used, these operations are more expensive to
make. Multiplication and subtraction can also be done by repetitive additions and
subtractions respectively.