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M2303adn MPS
M2303adn MPS
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DESCRIPTION FEATURES
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The MP2303A is a monolithic synchronous 3A Output Current
buck regulator. The device integrates a 150mΩ Wide 4.7V to 28V Operating Input Range
high-side MOSFET and a 80mΩ low-side Integrated MOSFET Switches
MOSFET that provide 3A continuous load Output Adjustable from 0.80V to 25V
current over a wide operating input voltage of Up to 95% Efficiency
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4.7V to 28V. Current mode control provides fast Programmable Soft-Start
transient response and cycle-by-cycle current Stable with Low ESR Ceramic Output Capacitors
limit.
Fixed 360kHz Frequency
An adjustable soft-start prevents inrush current Cycle-by-Cycle Over Current Protection
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at turn-on. In shutdown mode, the supply Input Under Voltage Lockout
current drops to lower than 1μA. Available in thermally enhanced 8-Pin SOIC
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N and PDIP-8 packages
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This device, available in an 8-pin SOIC and
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PDIP-8 packages, provides a very compact
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APPLICATIONS
system solution with minimal reliance on
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external components. Distributed Power Systems
Pre-Regulator for Linear Regulators
Notebook Computers
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All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
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“MPS” and “The Future of Analog IC Technology” are registered trademarks of
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TYPICAL APPLICATION
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C5
10nF 100
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VIN=5V
VIN=12V
90
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2 1
7
IN BS
3 80
EN SW VIN=28V VIN=24V
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MP2303A
8
SS FB
5 70
GND COMP
4 6
60
50
VOUT=3.3
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT CURRENT
ORDERING INFORMATION
Part Number Package Top Marking Free Air Temperature (TA)
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MP2303ADN* SOIC8E M2303ADN -40C to +85C
MP2303ADP** PDIP8 MP2303A -40C to +85C
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* For Tape & Reel, add suffix –Z (e.g. MP2303ADN–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP2303ADN–LF–Z)
** For Tape & Reel, add suffix –Z (e.g. MP2303ADP–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP2303ADP–LF–Z)
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PACKAGE REFERENCE
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TOP VIEW
TOP VIEW
8
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BS 1 8 SS
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BS 1 8 SS
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IN 2 7 EN
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IN 2 7 EN
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SW 3 6 COMP
SW 3 6 COMP
GND 4 5 FB
GND 4 5 FB
MP2303A_PD01-PDIP8
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Supply Voltage VIN ........................-0.3V to +30V SOIC8E .................................. 50 ...... 10... C/W
Switch Voltage VSW .................. -1V to VIN + 0.3V PDIP8 .................................... 105 ..... 45... C/W
Boost Voltage VBS .......... VSW - 0.3V to VSW + 6V
All Other Pins ..................................-0.3V to +6V Notes:
1) Exceeding these ratings may damage the device.
Junction Temperature ...............................150°C
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Lead Temperature ....................................260°C regulator will go into thermal shutdown. Internal thermal
Storage Temperature .............. -65°C to +150°C shutdown circuitry protects the device from permanent
damage.
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(3)
Recommended Operating Conditions 3) The device is not guaranteed to function outside of its
operating conditions.
Input Voltage VIN .............................. 4.7V to 28V 4) Measured on JESD51-7, 4-layer PCB..
Output Voltage VOUT ....................... 0.80V to 25V
Maximum Junction Temp. (TJ) ................ +125°C
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Shutdown Supply Current VEN = 0V 0.3 3.0 μA
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Supply Current VEN = 2.7V, VFB = 1.0V 1.45 1.6 mA
4.7V VIN 28V,
0.780 0.800 0.820 V
Feedback Voltage VFB TA = +25°C
-40°C ≤ TA ≤ +85°C 0.765 0.835 V
OVP Threshold Voltage 0.90 0.95 1.00 V
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Error Amplifier Voltage Gain AEA 400 V/V
Error Amplifier Transconductance GEA IC = 10μA 550 820 1100 μA/V
High-Side Switch-On Resistance RDS(ON)1 150 mΩ
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Low-Side Switch-On Resistance RDS(ON)2 80 mΩ
High-Side Switch Leakage Current VEN = 0V, VSW = 0V 0 10 μA
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Upper Switch Current Limit 4.3 6.0 A
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Lower Switch Current Limit From Drain to Source 1.25 A
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COMP to Current Sense
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GCS 7 A/V
Transconductance
TA = +25°C 310 360 410 kHz
Oscillation Frequency Fosc1
-40°C ≤ TA ≤ +85°C 290 430 kHz
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Notes:
5) 100% production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
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PIN FUNCTIONS
Pin # Name Description
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET
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1 BS
switch. Connect a 0.01μF or greater capacitor from SW to BS to power the high side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter switches.
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2 IN Drive IN with a 4.7V to 28V power source. Bypass IN to GND with a suitably large capacitor to
eliminate noise on the input to the IC. See Input Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output. Connect
3 SW the output LC filter from SW to the output load. Note that a capacitor is required from SW to
BS to power the high-side switch.
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4 GND Ground (Connect Exposed Pad to Pin 4)
Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a
5 FB resistive voltage divider from the output voltage. The feedback threshold is 0.80V. See Setting
the Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop. Connect a
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series RC network from COMP to GND to compensate the regulation control loop. In some
6 COMP
cases, an additional capacitor from COMP to GND is required. See Compensation
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Components.
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Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
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7 EN the regulator, drive it low to turn it off. Connect EN with IN through a resistive voltage divider
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for automatic startup. Do not float this pin.
Soft-start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND
8 SS to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the
soft-start feature, leave SS unconnected.
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1.6 120 6
1.4
100 5
1.2
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80 4
1.0
0.8 60 3
0.6
40 2
0.4
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20 1
0.2 VEN=0V
VFB=1V VFB=0.6V
8
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0 0 0
0 5 10 15 20 25 30 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1.0
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G
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0 IOUT=1.5A
0
2.5 VIN=5V -0.5
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0 -3.0 -2.0
0 1 2 3 4 5 6 0 0.5 1 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30
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VOUT
200mV/div VOUT VOUT
2V/div 2V/div
IINDUCTOR VEN
2A/div VEN
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2V/div 2V/div
VSW
VSW 20V/div
10V/div
VSW IINDUCTOR IINDUCTOR
10V/div 2A/div 2A/div
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8
N
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VOUT VOUT
2V/div 2V/div
VOUT
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VEN 2V/div
VEN 2V/div
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2V/div
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VSW VIN
VSW 10V/div 5V/div
VSW
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20V/div 5V/div
IINDUCTOR IINDUCTOR IINDUCTOR
2A/div 2A/div 2A/div
4ms/div
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VOUT
2V/div
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VIN
5V/div
VSW
5V/div
IINDUCTOR
2A/div
4ms/div
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ED
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8
N
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T
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BLOCK DIAGRAM
+
CURRENT
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OVP IN
SENSE
-- AMPLIFIER +
0.95V
RAMP 5V
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OSCILLATOR
FB + --
CLK
360kHz
BS
0.3V --
+ S Q
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-- R Q SW
SS + -- CURRENT
ERROR COMPARATOR
0.8V + AMPLIFIER
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COMP
GND
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EN
1.2V OVP
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IN < 3.95V
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IN
--
INTERNAL
REGULATORS
1.3 V + SHUTDOWN
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COMPARATOR
OPERATION
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output voltage as low as 0.80V, and supplies up greater than the input voltage, a boost capacitor
to 3A of load current. connected between SW and BS is needed to
drive the high side gate. The boost capacitor is
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The MP2303A uses current-mode control to charged from the internal 5V rail when SW is low.
regulate the output voltage. The output voltage
When the MP2303A FB pin exceeds 20% of the
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COMP pin is compared to the switch current COMP pin and the SS pin are discharged to
measured internally to control the output GND, forcing the high-side switch off.
voltage.
APPLICATIONS INFORMATION inductor will result in less ripple current that will
result in lower output ripple voltage. However,
COMPONENT SELECTION the larger value inductor will have a larger
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Setting the Output Voltage physical size, higher series resistance, and/or
The output voltage is set using a resistive lower saturation current. A good rule for
voltage divider from the output voltage to FB pin.
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determining the inductance to use is to allow
The voltage divider divides the output voltage the peak-to-peak ripple current in the inductor
down to the feedback voltage by the ratio: to be approximately 30% of the maximum
R2 switch current limit. Also, make sure that the
VFB VOUT peak inductor current is below the maximum
R1 R2
switch current limit. The inductance value can
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Thus the output voltage is: be calculated by:
R1 R2 VOUT V
VOUT 0.80 L 1 OUT
R2 fS ΔI VIN
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Where VFB is the feedback voltage and VOUT is
Where VIN is the input voltage, fS is the
the output voltage.
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switching frequency, and ΔIL is the peak-to-
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A typical value for R2 can be as high as 100kΩ,
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peak inductor ripple current.
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but a typical value is 10kΩ. Using that value, R1
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Choose an inductor that will not saturate under
is determined by:
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the maximum inductor peak current. The peak
R1 12.5 ( VOUT 0.80)(k) inductor current can be calculated by:
For example, for a 3.3V output voltage, R2 is VOUT V
ILP ILOAD 1 OUT
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resistor (RDOWN from EN pin to GND) to paralleled between the SW pin and GND pin to
determine the automatic start-up voltage: improve overall efficiency. Table 2 lists example
(RUP RDOWN ) Schottky diodes and their Manufacturers.
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supply the AC current to the step-down converter In the case of ceramic capacitors, the impedance
while maintaining the DC input voltage. Use low at the switching frequency is dominated by the
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ESR capacitors for the best performance. capacitance. The output voltage ripple is mainly
Ceramic capacitors are preferred, but tantalum or caused by the capacitance. For simplification, the
low-ESR electrolytic capacitors may also suffice. output voltage ripple can be estimated by:
Choose X5R or X7R dielectrics when using
ceramic capacitors. VOUT V
ΔVOUT 1 OUT
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2 VIN
Since the input capacitor (C1) absorbs the input 8 fS L C2
switching current it requires an adequate ripple In the case of tantalum or electrolytic capacitors,
current rating. The RMS current in the input the ESR dominates the impedance at the
capacitor can be estimated by: switching frequency. For simplification, the output
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VOUT V ripple can be approximated to:
IC1 ILOAD (1 OUT )
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VIN VIN VOUT V
ΔVOUT 1 OUT R ESR
f S L
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VIN
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The worst-case condition occurs at VIN = 2VOUT,
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where: The characteristics of the output capacitor also
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ILOAD affect the stability of the regulation system. The
I C1 MP2303A can be optimized for a wide range of
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capacitance and ESR values.
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The input capacitor can be electrolytic, tantalum The system stability and transient response are
or ceramic. When using electrolytic or tantalum controlled through the COMP pin. COMP pin is
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capacitors, a small, high quality ceramic the output of the internal transconductance
capacitor, i.e. 0.1μF, should be placed as close to error amplifier. A series capacitor-resistor
the IC as possible. When using ceramic combination sets a pole-zero combination to
capacitors, make sure that they have enough control the characteristics of the control system.
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ILOAD V V
VIN OUT 1 OUT Where AVEA is the error amplifier voltage gain,
f S C1 VIN VIN GCS is the current sense transconductance,
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transconductance, and RLOAD is the load resistor
100μF
value. 1.8V 4.7μH 8.2kΩ 3.3nF None
Ceramic
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The system has one zero of importance, due to the 4.7- 47μF
2.5V 5.6kΩ 4.7nF None
compensation capacitor (C3) and the 6.8μH Ceramic
compensation resistor (R3). This zero is located at: 6.8- 22μFx2
3.3V 7.5kΩ 4.7nF None
10μH Ceramic
1
f Z1
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10- 22μFx2
2 C3 R3 5V 10kΩ 3.3nF None
15μH Ceramic
The system may have another zero of 15- 22μFx2
12V 25kΩ 3.3nF None
importance, if the output capacitor has a large 22μH Ceramic
capacitance and/or a high ESR value. The zero, 4.7- 560μF Al.
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due to the ESR and capacitance of the output 2.5V 70kΩ 3.3nF 150pF
6.8μH 30mΩ ESR
capacitor, is located at: 6.8- 560μF Al
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3.3V 90kΩ 3.3nF 100pF
10μH 30mΩ ESR
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1
fESR
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2 C2 R ESR 10- 470μF Al.
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5V 100kΩ 3.3nF 50pF
15μH 30mΩ ESR
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In this case, a third pole set by the 15- 220μF Al.
compensation capacitor (C6) and the 12V 120kΩ 3.3nF 50pF
22μH 30mΩ ESR
compensation resistor (R3) is used to
To optimize the compensation components for
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fP 3
2 C6 R3 1. Choose the compensation resistor (R3) to set
the desired crossover frequency. Determine the
The goal of compensation design is to shape
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crossover frequencies could cause system applications with typical inductor values, setting
unstable. A good rule of thumb is to set the the compensation zero, fZ1, below one forth of
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following equation:
crossover frequency is 36kHz.
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Table 3 lists the typical values of compensation C3
2 R3 f C
components for some standard output voltages
with various output capacitors and inductors. The
values of the compensation components have
been optimized for fast transient responses and
good stability at given conditions.
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less than half of the switching frequency, or the
if the applicable condition is:
following relationship is valid:
VOUT is 5V or 3.3V, and duty cycle is high:
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1 f
S VOUT
2 C2 R ESR 2 D= >65%
VIN
If this is the case, then add the second
In these cases, an external BST diode is
compensation capacitor (C6) to set the pole fP3
recommended from the output of the voltage
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at the location of the ESR zero. Determine the
regulator to BST pin, as shown in Figure.2
C6 value by the equation:
External BST Diode
C2 R ESR IN4148
C6 BST
R3 CBST
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MP2303A
SW 5V or 3.3V
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+
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L
COUT
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Figure 2—Add Optional External Bootstrap
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Diode to Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
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C5
10nF
INPUT
4.7V to 28V
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2 1
7
IN BS
3
OUTPUT
EN SW 2.5V
3A
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MP2303A
8 SS 5
FB
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GND COMP
4 6
D1
C3
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B340
C6 4.7nF (optional)
(optional)
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EVB layout for optimum performance. and direct. Place the feedback resistors and
compensation components as close to the
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If change is necessary, please follow these chip as possible.
guidelines and take Figure 4 for reference.
4) Rout SW away from sensitive analog areas
1) Keep the path of switching current short and such as FB.
minimize the loop area formed by Input cap,
high-side MOSFET and low-side MOSFET. 5) Connect IN, SW, and especially GND
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respectively to a large copper area to cool
the chip to improve thermal performance and
long-term reliability.
C5
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INPUT
4.75V to 23V
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2 1
L1
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IN BS
7 3
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EN SW OUTPUT
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MP2303A R1
8 5
SS FB
C1 GND COMP
4 6
D1 R2 C2
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C3 (optional)
C4
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R3
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R1
SS 8
EN 7
COMP 6
FB 5
C4 R2
R
R1 SGND
PGND
T
4 GND
3 SW
D1
1 BS
2 IN
C2
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C5 C1
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L1
PACKAGE INFORMATION
SOIC8E
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P2 S FO
0.189(4.80) 0.124(3.15)
0.197(5.00) 0.136(3.45)
8 5
ED
0.150(3.80) 0.228(5.80) 0.089(2.26)
PIN 1 ID 0.157(4.00) 0.244(6.20) 0.101(2.56)
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1 4
8
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TOP VIEW BOTTOM VIEW
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SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.000(0.00)
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0.013(0.33) 0.006(0.15)
0.020(0.51) SIDE VIEW
0.050(1.27)
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BSC
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GAUGE PLANE
0.010(0.25) BSC
0.024(0.61) 0.050(1.27)
0.016(0.41)
0o-8o
R
0.050(1.27)
0.063(1.60)
DETAIL "A"
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0.103(2.62) 0.213(5.40)
NOTE:
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PACKAGE INFORMATION
PDIP8
,
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P2 S FO
0.367(9.32)
0.387(9.83)
8 5
ED
0.240(6.10)
PIN 1 ID 0.260(6.60)
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1 4
TOP VIEW
8
N 0.320( 8.13)
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0.400(10.16)
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0.100(2.54) 0.300(7.62)
G
BSC 0.325(8.26)
0.125(3.18)
0.145(3.68)
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0.015(0.38)
0.035(0.89)
E
0.120(3.05)
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0.140(3.56)
0.008(0.20)
EC
0.050(1.27) 0.014(0.36)
0.065(1.65)
0.015(0.38)
0.021(0.53)
NOTE:
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NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.