CMOS Digital VLSI Design - - Unit 9 - Week 8 https://onlinecourses-archive.nptel.ac.in/noc19_...

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Unit 9 - Week 8
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Certification exam Assignment-8
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Course As per our records you have not submitted this Due on 2019-04-24, 23:59 IST.
outline
assignment.

How to access 1) In presence of clock jitter (Tj), under worst case scenario, for proper operation of a 1 point
the portal synchronous sequential logic, the clock period reduces by

Week 1 Tj

2Tj
Week 2
3Tj
Week 3
0.5Tj

Week 4 No, the answer is incorrect.

Score: 0
Week 5
Accepted Answers:
2Tj
Week 6
2) Clock skew between two clocks is influenced by which of the following factor: 1 point
Week 7
Inductance of the interconnect from clock to the sequential block
Week 8
Capacitance of the interconnect from clock to the sequential block
Clocking
On chip local temperature
Strategies for
Sequential None of the above
Design-IV
No, the answer is incorrect.
Sequential
Score: 0
Logic Design
-IX Accepted Answers:
On chip local temperature
Clocking
Strategies for 3) For clock skew and jitter the systematic error is 1 point
Sequential
Design-V
Unpredictable
Concept of
Varies from one chip to other
Memory and its
Designing-I Cannot be modelled during design
Concept of Predictable
Memory and its © 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -
Designing-II No, the answer is incorrect.
A project of In association with
Score: 0
Quiz :
Assignment-8 Accepted Answers:
Predictable
Solution for Funded by
Assignment-8 4) The best way to avoid skew and jitter is 1 point

1 of 3 Thursday 20 June 2019 05:37 PM

CMOS Digital VLSI Design - - Unit 9 - Week 8 https://onlinecourses-archive.nptel.ac.in/noc19_...

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Run clock and by
data in opposite direction
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Run clock and data in the same direction

Text Transcript Have balanced clock loads

Use symmetrical interconnect lengths

Interaction
Session No, the answer is incorrect.
Score: 0
Accepted Answers:
Run clock and data in opposite direction

5) In
a pipeline based sequential circuits, let us assume that we 1 point
are using positive level triggered latches between combinational
block, then which of the following statements is true
The latches should be activated by CLK signal only

The latches should be activated by CLK and CLK(bar) signals

The latches should be activated by CLK(bar) signal only

None of the statement is true

No, the answer is incorrect.

Score: 0
Accepted Answers:
The latches should be activated by CLK and CLK(bar) signals

6) For a C2MOS pipelined circuit to be race free the essential condition is 1 point

All the logic function implanted should be non-inverting

All the logic function implanted should be inverting

The clock should be jitter and skew free

Power fluctuation to be minimized

No, the answer is incorrect.

Score: 0
Accepted Answers:
All the logic function implanted should be non-inverting

7) For a latch based clocking how many phase clock sequence is required 1 point

Single Phase

Three Phase

Two Phase

Four Phase

No, the answer is incorrect.

Score: 0
Accepted Answers:
Two Phase

8) In a latch based clocking scheme if the first D-latch is active low and runs on a clock 1 point
referred to as TCLK1, then the evaluation time for the combinational block next to the latch is

2TCLK1

TCLK1/4

6TCLK1

TCLK1/2

2 of 3 Thursday 20 June 2019 05:37 PM

CMOS Digital VLSI Design - - Unit 9 - Week 8 https://onlinecourses-archive.nptel.ac.in/noc19_...

No, the answer is incorrect.

Score: 0
Accepted Answers:
TCLK1/2

9) Not all clock event occur simultaneously in a system due to 1 point

Clock Skew

Clock Jitter

Both Skew and Jitter

None of these

No, the answer is incorrect.

Score: 0
Accepted Answers:
Both Skew and Jitter

10)Sense Amplifier in a conventional memory design allows 1 point

Full Rail-to-Rail Swing in the output

Reduces the output transition time

Increases the Noise Margin

Reduces the Noise Margin

No, the answer is incorrect.

Score: 0
Accepted Answers:
Full Rail-to-Rail Swing in the output

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3 of 3 Thursday 20 June 2019 05:37 PM