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Electronics
B. Mazhari
Dept. of EE, IIT Kanpur
Obtaining Boolean expressions from truth Table
Elementary Gates
x1
AND: y = x1. x 2 x2
AND y
x1 x1
AND y=0 AND y = x1
0 1
Gate is closed Gate is open
x1
OR y
OR: y = x1 + x 2 x2
x y
NOT: y = x
x1x2
x1
AND x1x2
NAND: y = x1. x 2 x2
x1
NAND y
x2
x1+x2
x1
OR x1+x2
NOR: y = x1 + x 2 x2
x1
NOR y
x2
x1 x2 y
XOR: y = x1 x 2 =x1. x2 x1 . x2
0 0 0
0 1 1
Y is 1 if only one variable is 1 and the other is zero 1 0 1
1 1 0
x1 x1x2
x2
y x1
x1 XOR y
x2
x2 x1x2
y =x1 x 2 =x1 x2
Gates with more than 2 inputs
x1
x2
AND: y = x1. x 2 . x3 ... x3
AND y
x1
x2
OR: y = x1 + x 2 x3 .... x3 y
x S
S x. y.z x. y.z x. y.z x. y.z
y
C
z C x. y x.z y.z
x
x x y z
y y
z
x
y x y z
y
z z
S y
x z C
y
x y z x
z
z
x
y
z x y z
Implementing gates using Switches
x x
VDD = 5V
closed
SP
x y x y
HIGH
LOW
1
0 NOT gate
open
SN
NAND Gate NAND: y = x1. x 2
VDD = 5V
x1 x2
SP SP
x1 x2 y
y
LOW LOW HIGH
LOW HIGH HIGH
x1
SN
HIGH LOW HIGH
HIGH HIGH LOW
x2
SN
NOR Gate NOR: y = x1 + x 2
VDD = 5V
x1
SP
x1 x2 y
LOW LOW HIGH
x2 LOW HIGH LOW
SP
HIGH LOW LOW
y
HIGH HIGH LOW
x1 x2
SN SN
Design Overview
a b c S CY
0 0 0 0 0
a S 0 0 1 1 0
b Full Adder 0 1 0 1 0
c CY
0 1 1 0 1
1 0 0 1 0
VDD = 5V
x
x x1 x2
y y
x y z
x SP SP SP
z
y
x y z y
y
z y
z x1
x
S
z C SN
SN
y
x y z
z x x2
x
z SN
y
z x y z
Representation of Boolean Expressions
x y f1 x y min term
0 0 0 0 0 x.y m0
0 1 1 0 1 x.y m1
1 0 1 1 0 x.y m2
1 1 0 1 1 x.y m3
f1 = x . y x. y f1 = m1 m2 f1 = (1, 2)
f 2 = (0, 2,3) ? f 2 = x . y x. y x . y
x y z min terms
0 0 0 x.y.z m0
0 0 1 x.y.z m1
0 1 0 x.y.z m2
0 1 1 x.y.z m3
1 0 0 x.y.z m4
1 0 1 x.y.z m5
1 1 0 x.y.z m6
1 1 1 x.y.z m7
f 2 = (1, 4, 7) ?
f 2 = x . y. z x. y. z x . y . z
Product of Sum Terms Representation
x y Max term
0 0 x+y M0
0 1 x+y M1
1 0 x+y M2
1 1 x+y M3
f1 = (x y ).( x y ) f1 = M 1. M 2 f1 = (1, 2)
f 2 = (0,3) ?
f 2 = (x y ).( x y )
x y z Max. terms
0 0 0 x + y + z M0
0 0 1 x + y + z M1
0 1 0 x + y + z M2
0 1 1 x + y + z M3
1 0 0 x + y + z M4
1 0 1 x + y + z M5
1 1 0 x + y + z M6
1 1 1 x + y + z M7
f1 = (1,5, 7) ?
f 2 = (x y z ).( x y z ).( x y z )
Simplification
x1 x2 x3 y y= (1,3,5, 7)
0 0 0 0
0 0 1 1 y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3
0 1 0 0
x1
0 1 1 1 x2
1 0 0 0 x3
1 0 1 1 x1
x2
1 1 0 0 x3
y
1 1 1 1 x1
x2
x3
x1
x2
x3
x1
x2
x3
y
x1
x2
x3
x1
x2
x3
Goal of simplification is to reduce the complexity of gate circuit. This requires that we
minimize the number of gates. Since number of gates depends on number of minterms,
one of the goals of simplification is to minimize the number of minterms in SOP
expression
y = x1 . x2 . x3 x1. x2 . x3 x1 . x2 . x3 x1. x2 . x3
y = x1 . x3 x1. x2 . x3 x1. x2 . x3
x1
x2 x1
x3
x3
x1
x2 y
x3 x1
y x2
x1
x2 x3
x3
x1
x1 x2
x2 x3
x3
This circuit is simpler not just because it uses 4 gates instead of 5 but also because
circuit-2 uses one 2-input and three 3-input gates as compared to five 3-input gates
used in circuit-1 V = 5V
VDD = 5V DD
x1 x2 x1 x2
SP SP SP SP x3 SP
y y
x1 x1
2-input NAND SN
SN 3-input NAND
x2 x2
SN SN
x3
SN
Goal of Simplification
Simplification Minimization
Minimization
y = x1 . x3 .( x2 x2 ) x1. x3 .( x2 x2 )
y = x1 . x3 x1. x3
y =( x1 x1 ). x3
y = x3
Principle used: x + x = 1
f = x . y x. y x . y
f = x .( y y ) x . y
f = x x. y
f = x . y x. y x . y x . y x . y x. y x . y
Principle used : x + x = x
f = x . y x. y x . y x . y
x . ( y y ) ( x x). y x y
Simplify f x1. x2 . x3 . x4 x1. x2 . x3 . x4 x1. x2 . x3 . x4 x1. x2 . x3 . x4
x1. x2 . x3 . x4 x1. x2 . x3 . x4
Principle: x + x = 1 and x + x = x
Need a systematic and simpler method for applying these two principles