SUPPLEMENTARY INFORMATION

Stable InSe transistors with high field-effect mobility for reliable

nerve signal sensing

Table of content

Supplementary Figure 1 | Schematic diagram of different InSe FET structures.

Supplementary Figure 2 | Characterization of an InSe film

Supplementary Figure 3 | C-V characterization of high-k dielectric layers

Supplementary Figure 4 | Contact angle of dielectric layers

Supplementary Figure 5 | Raman spectroscopy

Supplementary Figure 6 | Electrical characteristics of various FETs

Supplementary Figure 7 | Hysteresis of various FETs

Supplementary Figure 8 | Electrical stability of various FETs

Supplementary Figure 9 | Electrical characteristics of InSe FETs with different

encapsulation layers
Table S1. Summary of InSe FETs in different encapsulation layers.
Supplementary Figure 10 | Stress mismatch between dielectric layers and InSe

Supplementary Figure 11 | Correspondence between pulse gate voltage VGS and pulse

current △IDS.

Supplementary Figure 12 | Mechanism diagram of sciatic nerve detection.

Supplementary Figure 13 | Video of InSe FETs detecting the sciatic nerve and stimulating

the sciatic nerve

Supplementary Figure 14 | Flexible PMMA/InSe/PMMA-HfO2 FET with a PI substrate

Supplementary Figure 1 | Schematic diagram of different layer InSe FET structures, including

(a) an InSe/SiO2 FET, (b) an InSe/Al2O3 FET, (c) an InSe-HfO2 FET, (d) a PMMA/InSe/PMMA-

SiO2 FET, and (e) a PMMA/InSe/PMMA-Al2O3 FET.

 The Raman spectrum (Supplementary Figure 2a) of the InSe flakes shows peaks at 115, 178 and

228 cm-1, corresponding to the vibration modes of A1’(Γ21), E’(Γ13)-TO, and A1’(Γ31), respectively,

which indicates that the flake has multiple layers. The thickness of InSe was determined by atomic

force microscopy (AFM, CSPM5500). Supplementary Figure 2b shows a typical surface shape

graph and an AFM step scan image of an InSe flake. Energy-dispersive X-ray spectrometry (EDS)

and element mapping images of the InSe layer are shown in Supplementary Figure 2c d e. The

chemical composition of the as-prepared sample consists of indium (In) and selenium (Se) at an

atomic ratio of ∼1:1.

Supplementary Figure 2 | Characterization of an InSe film. (a) Room-temperature Raman

spectrum of the multilayer InSe nanoflakes obtained using a 532 nm laser. (b) Typical AFM

topography graph and height profile of layered InSe. (c)(d)(e) Energy-dispersive X-ray

spectrometry (EDS) results and element mapping images of the InSe layer.
 To perform accurate calculations of the carrier mobility, metal-insulator-semiconductor

capacitors were made to determine the capacitance of the gate dielectric (Cox). Supplementary Fig.

3a, b, c, d, e show the C–V characteristics and a schematic diagram of an Au/HfO2/Al2O3 (10 nm)/n-

Si capacitor, respectively. A very high capacitance of Cox= 1200/680 nF/cm2 (HfO2/Al2O3) was

determined. “refresh” referred to the C-V curve of the original dielectric layer. “PDA” referred to

the C-V curve of the dielectric layer after pre-annealing (700℃, 1min).

Supplementary Figure 3 | C-V characterization of high-k dielectric layers. (a) Schematic

diagram of the MOS structure. (b) SEM image of the MOS. The inset is the corresponding optical

microscope image. (c) Cross-sectional SEM image of the high-k layer. (d) C-V characteristics of

high-k 10 nm HfO2. (e) C-V characteristics of high-k 10 nm Al2O3. Note: “refresh” referred to the

C-V curve of dielectric layer as deposited, and “PDA” referred to the C-V curve of the dielectric

layer after annealing (700 °C, 1 min).

 The contact angles for water on bare SiO2, Al2O3 or HfO2 substrates are 59.3°, 55.8°, and 57.9°

(Supplementary Figure 4a, b, c), respectively, indicating that all the oxidized surfaces are

hydrophilic. When stored in the ambient environment, the oxidized substrate surface has hydroxyl

groups and is hydrated by a network of water molecules. After coating with PMMA, the contact

angles for water are changed to 78.2°for PMMA/HfO2, as shown in Supplementary Fig. 4d. The

substrates become less hydrophilic due to the screening of the hydroxyl groups on the surface.

PMMA is a polar polymer consisting of a polar molecular skeleton and functional groups, resulting

in hydrophobic properties and a large contact angle of water on the PMMA film.

Supplementary Figure 4 | Contact angle of dielectric layers. The contact angles for (a) 100 nm

SiO2, (b) 30 nm Al2O3, (c) 30 nm HfO2, and (d) PMMA/HfO2 (250/30 nm).
 InSe is sensitive to moisture, and oxidation occurs progressively as exposed to the air. Such

spontaneous oxidation can go deep into the inner layers because of the loose structure of the

resulting oxides and leads to a considerable current hysteresis and an uncontrollable p-doping in

transistor operations. [1] PMMA encapsulation can effectively retard water and oxygen molecules

penetrating, which can boost electrical stability of InSe FETs in air. The Raman peak and intensity

did not charge significantly during the 20-day text, indicating that InSe can remain stable for a long

time in the case of PMMA package. Raman data is shown below.

Supplementary Figure 5 | Raman spectroscopy. (a) Optical image of PMMA/InSe/PMMA-HfO2

flakes. (b) Time-dependent Raman spectra of the 30 nm InSe flakes marked in (a). (c) Schematic

image of PMMA/InSe/PMMA-HfO2 in air.

[1] Ho, Po-Hsun, et al. "High-mobility InSe transistors: the role of surface oxides." ACS Nano 11.7

(2017): 7362-7370.
 The transfer and output characteristics of InSe FET structures with different layers are shown in

Supplementary Figure 6a, b, c, d, e, f. The IDS-VDS output characteristics and IDS-VGS transfer

characteristics of InSe FETs were measured with an Agilent B2901A parameter analyzer under

ambient conditions. As shown in Supplementary Figure 6 g, h, the field-effect mobilities derived

from the InSe FETs on thermal SiO2 and on HfO2 with a PMMA sandwiched structure are 246

cm2/V·s and 1206 cm2/V·s, respectively.

Supplementary Figure 6 | Electrical characteristics of various FETs. (a) Transfer characteristics

of a layered InSe FET with 30 nm HfO2. (b) The corresponding output characteristics of a layered
InSe FET with 30 nm HfO2. (c) Transfer characteristics of a layered InSe FET with

PMMA/PMMA/SiO2. (d) The corresponding output characteristics of a layered InSe FET with

PMMA/PMMA/SiO2. (e) Transfer characteristics of a layered InSe FET with PMMA/PMMA/Al2O3.

(f) The derived transconductance and field-effect mobilities of InSe FETs with

PMMA/PMMA/HfO2. (g) The field-effect mobility of multiple devices (35 nm-InSe). (h) The

hysteresis and threshold voltage shifts of multiple devices (35 nm-InSe).

 The VGS sweep takes 16 s, and on the 16 s return sweeps, the layered InSe FETs with different

structures show hysteresis of ~ 4.3/0.8/4.4/1.4/0.6/0.4 V and subthreshold swing (SS) values of

1080/790/540/350/300/260 mV/decade, as shown in Supplementary Figure 7.

Supplementary Figure 7 | Hysteresis of various FETs. Hysteresis of (a) a InSe/SiO2 FET, (b) a

PMMA/InSe/PMMA- SiO2 FET, (c) an InSe/Al2O3 FET, (d) a PMMA/InSe/PMMA- Al2O3 FET, (e)

a InSe/HfO2 FET, and (f) a PMMA/InSe/PMMA- HfO2 FET in the ambient environment. Hysteretic

behavior of IDS-VGS with the same sweeping rates of the gate voltage (0.2 Arrows show the gate

bias sweep direction.

 We investigated the electrical stability of multilayer InSe FETs with different structures by

applying a gate bias stress. The transfer characteristic curves were measured soon after at a constant

VG at regular time intervals of 300 s for each stress, and the transfer characteristics were measured

10 times consecutively. InSe/HfO2 FETs were susceptible to breakdown under high VG (±1 V) due

to the dielectric layers, and other devices (PMMA/InSe/PMMA-SiO2) were subjected to VG=±10

V, which mainly was used to study the electrical trend of a device, as shown in Supplementary

Figure 8.

Supplementary Figure 8 | Electrical stability of various FETs. (a) Transfer characteristics of a

PMMA/InSe/PMMA-SiO2 FET after (a) VGS=+10 V and (b) VGS= -10 V for 300 s. Transfer

characteristics of an InSe/HfO2 FET after (c) VGS=+1 V and (d) VGS= -1 V for 300 s.
 Here in, we added new experiments with different encapsulation layers to compare effects of

different encapsulation layers on electrical properties and stability of the device. As a result, the

PMMA encapsulation layer is superior to the Al2O3/HfO2 encapsulation layer in terms of device

performance improvement. We systematically studied the electrical properties (mobility, current

on/off ratio) and stability (hysteresis, threshold voltage shift) of devices before and after packaging

of different encapsulation layers. The results are shown in Supplementary Figure 9 and Table S1.

Supplementary Figure 9 | Electrical characteristics of InSe FETs with different encapsulation

layers, including (a) PMMA encapsulation, (b) Al2O3 encapsulation, and (c) HfO2 encapsulation.
Table S1. Summary of InSe FETs in different encapsulation layers.
Hysteresis Mobility On/Off Threshold voltage
Device
2
(V) (cm /V·s) Ration shift (V)
6
1-InSe FET 2.7 206 ~10 2.2
7
1-PMMA/InSe FET 1.4 497 ~10 0.9
1-change ratio -48.15% 141.26% - -55.09%
6
2-InSe FET 5.9 231 ~10 3.7
7
2-Al2O3/InSe FET 3.1 289 ~10 1.6
2-change ratio -47.46% 25.11% - -56.76%
3-InSe FET 3.2 249 ~106 1.8
3-HfO2/InSe FET 2.4 321 ~107 1.1
3-change ratio -25.00% 28.91% - -38.89%
 The stress mismatch of different dielectric layer materials and the InSe contact is calculated.

Supplementary Figure 10 a,b,c,d show the stress mismatch (3.25%) between InSe and SiO2, the

stress mismatch (1.17%) between InSe and Al2O3, the stress mismatch (2.02%) between InSe and

HfO2, and the stress mismatch between InSe and PMMA.

Supplementary Figure 10 | Stress mismatch between dielectric layers and InSe. Stress

mismatch between InSe and (a) SiO2, (b) Al2O3, (c) HfO2, and (d) PMMA.
 We fit the relationship between the pulse current I
△ DS and pulse gate voltage VGS.

Supplementary Figure 11 | Correspondence between pulse gate voltage VGS and pulse current

I
△ DS.
If both electrodes are placed on the surface of an axon, the nerve is stimulated, and the nerve impulse

produces a characteristic biphasic potential. As the depolarized state reaches the electrode nearer to

stimulation this electrode becomes negative relation to the other electrode. This is recorded as an

upward deflection. When the impulse passes between the two electrodes, the potential returns to

zero and recorded as isoelectric interval.

As the nerve impulse passes the second electrode, this becomes negative in relation to first electrode

which has already been back to normal and recorded as downward deflection. As the nerve impulse

passes off the second electrode, the potential returns to zero and recorded as isoelectric interval. The

mechanism of detection is shown in the supplementary Figure 12 below.

Supplementary Figure 12 | Mechanism diagram of sciatic nerve detection.

More details are shown in Supplementary Video.

Supplementary Figure 13 Video of sciatic nerve action potential detection using InSe FETs
In order to demonstrate the potential to make flexible InSe FETs, InSe FET was fabricated on

flexible Polyimide (PI) substrate, and its transfer characteristics were measured.

Supplementary Figure 14 | Flexible PMMA/InSe/PMMA-HfO2 FET with a PI substrate