shiftB

ldA Register A[15:0] Register B[15:0] clk

module(pipo) module(pipo3)
clk ldB

compB Comparator compares the

Last bit of B and produces
clk Correspoding response(comp)

ldP
SHIFTER(shift) shift

clrP Register result

(pipo3)[15:0]

clk
ADDER
module