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    Tanmay Talekar
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    This document contains VHDL code to convert between binary and gray code. The first section defines an entity that takes in 4-bit binary inputs and outputs the corresponding 4-bit gray code values. The second section defines another entity that performs the inverse conversion, taking in 4-bit gray code inputs and outputting the 4-bit binary equivalent values. Both entities implement the conversions by applying XOR logic gates to the input bits in a specific order.

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    This document contains VHDL code to convert between binary and gray code. The first section defines an entity that takes in 4-bit binary inputs and outputs the corresponding 4-bit gray code values. The second section defines another entity that performs the inverse conversion, taking in 4-bit gray code inputs and outputting the 4-bit binary equivalent values. Both entities implement the conversions by applying XOR logic gates to the input bits in a specific order.

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    © All Rights Reserved
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    3 views2 pages

    Exp 7

    Uploaded by

    Tanmay Talekar
    This document contains VHDL code to convert between binary and gray code. The first section defines an entity that takes in 4-bit binary inputs and outputs the corresponding 4-bit gray code values. The second section defines another entity that performs the inverse conversion, taking in 4-bit gray code inputs and outputting the 4-bit binary equivalent values. Both entities implement the conversions by applying XOR logic gates to the input bits in a specific order.

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    © All Rights Reserved
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    of 2

    Binary To Grey

    library ieee;
    use ieee.std_logic_1164.all;
    entity tanmay_binary_to_grey is
    port (B3: in std_logic;
    B2: in std_logic;
    B1: in std_logic;
    B0: in std_logic;
    G3: out std_logic;
    G2: out std_logic;
    G1: out std_logic;
    G0: out std_logic);
    end tanmay_binary_to_grey;
    architecture tanmay_binary_to_grey_arch of tanmay_binary_to_grey is
    begin
    G3 <= B3;
    G2 <= B3 XOR B2;
    G1 <= B2 XOR B1;
    G0 <= B1 XOR B0;
    end tanmay_binary_to_grey_arch;
    Grey To Binary
    library ieee;
    use ieee.std_logic_1164.all;
    entity tanmay_grey_to_binary is
    port (G3: in std_logic;
    G2: in std_logic;
    G1: in std_logic;
    G0: in std_logic;
    B3: out std_logic;
    B2: out std_logic;
    B1: out std_logic;
    B0: out std_logic);
    end tanmay_grey_to_binary;
    architecture tanmay_grey_to_binary_arch of tanmay_grey_to_binary is
    begin
    B3 <= G3;
    B2 <= G3 XOR G2;
    B1 <= G3 XOR G2 XOR G1;
    B0 <= G3 XOR G2 XOR G1 XOR G0;
    end tanmay_grey_to_binary_arch;

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