UNIVERSITI KUALA LUMPUR

MALAYSIAN SPANISH INSTITUTE

SAB36603
ADVANCE DIGITAL DESIGN AND FPGA

LAB 2
BASIC LOGIC DESIGN AND I/O INTERFACE

PREPARED BY:

STUDENT’S NAME ID NUMBER

NUR BATRISHA BALQIS BINTI MOHD SURAIS 54215119229
NURUL FARHANA BINTI MOHD FADZLI 54215119170
NURUL FARHANAH BINTI ZAKARIA 54215119177

LECTURER’S NAME: ENCIK MOHD REZAL BIN MOHAMED

OBJECTIVES

• To familiarize ourselves with schematic-based design flow for FPGA implementation using logic
gates and hierarchical modeling
• To design basic logic gates and I/O interface
• To implement the design in the FPGA on the Altera DE2 board

INTRODUCTION

This lab will introduce the Altera Quartus II design environment for implementing FPGA-based designs
using the Altera DE2 board. We will use the schematic entry method to create designs. After creating a
design, it must be compiled before it can be checked for correctness of functionality (through
simulation) and timing. The verification and timing analysis steps may require going back to the earlier
steps of the design cycle to remove bugs or performance bottlenecks. Once the design conforms to the
requirements, it can be implemented in the FPGA on the Altera DE2 board.

Once we have completed this lab, we are able to:

• navigate comfortably through Altera’s schematic design-entry environment,

• compile, debug, test, and simulate our designs,
• download and run our design on a DE2 board.

PROCEDURES

2.0 4-Bit Adder

1. A new project using the New Project Wizard was created; rename the project and top-level
design entity as adder4_de2.

2. In page 3 of the New Project Wizard, at the Family list, Cyclone II is selected.
3. Under Target device, Specific device selected in 'Available devices' list is selected.
4. Under Show in 'Available devices' list, the following options is selected:
 • In the Package list, FBGA is selected.
• In the Pin count list, 672 is selected.
• In the Speed grade list, 6 is selected.
5. In the Available devices list, EP2C35F672C6, as shown in Figure 1 is selected.

6. Finish was clicked to complete the new project creation.

7. A new BDF called adder4_de2.bdf was created. This file is the top-level design entity of the
project.
2.1 Create a Design File with the MegaWizard Plug-In Manager

1. An empty space in the Block Editor window was double-click. The Symbol dialog box appears
automatically.
2. In the Symbol dialog box, MegaWizard Plug-In Manager was clicked. The first page of the
MegaWizard Plug-In Manager appears.

3. Create a new custom megafunction variation is selected and Next is clicked.

4. Under Which megafunction would you like to customize?, the + icon to expand the
Arithmetic folder is clicked. LPM_ADD_SUB as shown in the figure below is selected:

5. The following responses to the remaining wizard prompts is specified below:

 6. To accept the defaults for the remaining questions and generate the symbol, Finish is clicked. A
Summary page lists the files that are generated for the symbol.
7. Finish is clicked. A preview of the new symbol appears in the Symbol dialog box.
8. OK is clicked. An outline of the adder4 symbol is attached to the pointer.

9. To place the symbol, the location you want the symbol to appear in the Block Editor window is
clicked.

2.2 Create HDL Design File and Symbol File

To create the framework of a Verilog Design File for the seven_seg block, follow the procedure below:

1. At the schematic window, the Block Tool and place it anywhere on the workspace is selected.
2. Using the Selection Tool, the block_name was double-clicked and the name to seven_seg was
changed, as shown in the figure below

3. Right-click the block and Block Properties is selected. Under the I/Os tab, define the
input/output as shown in Figure 4. Click OK.
4. Right-click the block and Create Design File from Selected Block from the pop-up menu is
selected. The Create Design File from Selected Block dialog box appears.
5. Under File type, Verilog HDL is selected.

6. Ensure that Add the new design file to the current project is checked.
7. Ensure that the File name is seven_seg.v, as shown in the figure below.

8. OK is clicked.
9. The Quartus II software automatically opens a text editor window that contains the new file,
indicating that the file has been generated successfully. The new file includes a template for
module and port declarations that correspond to the data you entered in the block:
10. The following lines to the seven_seg.v file to implement the design is added. These new lines
just before the endmodule statement are added.

11. The file is saved and closed.

2.3 Connecting the Adder to the 7-Segment Decoder

1. The sum of output of the adder is connected to the 7-segment decoder using Orthogonal Bus
Tool.

2. Right-click the bus wire, Properties menu is selected, and the bus is named as S[3..0].

3. Double-click the mapper symbol and map seg_in[3..0] on the block to S[3..0] bus.
4. The connection is completed as shown in Figure below.

5. Simulation is performed to verify the design.

2.4 Pin Assignment

1. The Start Analysis & Synthesis icon from the toolbar is selected. The Compiler checks the design
files for syntax and semantic errors, synthesizes the logic, and generates a project database. The
OK button is clicked when Analysis & Synthesis is complete.

2. From the main menu, Assignments > Pin Planner is selected to invoke the Pin Planner.
3. You can see a list of node names at the All Pins pane.
4. The Location column is double-clicked and the pin list srolled down to select the desired pin
location, as shown in the figure below.
5. The two 4-bit inputs and 1-bit carry in are assigned to the toggle switches on the DE2 board.
There are 18 toggle switches on the DE2 board. Each switch is connected directly to a pin on the
Cyclone II FPGA. When a switch is in the DOWN position (closest to the edge of the board), it
provides a low logic level to the FPGA; and when the switch is in the UP position, it provides a
high logic level. The schematic of the toggle switches is given in the figure below:

6. A list of the pin locations on the Cyclone II FPGA that are connected to the toggle switches is
given in Appendix A. The switch used for each input of the project and the pin assignment are
listed on the table below.
7. Similarly, the output of the 7-segment decoder is assigned (representing the result of the
addition) to one of the 7-segment displays on the DE2 board. The schematic of the 7-segment
display is given in the figure below. The pin locations on the Cyclone II FPGA that are connected
to the 7-segment displays are given in Appendix A.

8. Finally, the carry out signal is assigned to any of the LEDs on the DE2 board. There are 18 red
LEDs and eight green LEDs on the DE2 board. The schematic of the LEDs is given in the figure
below. Refer to Appendix A for the pin locations.
9. To check the legality of the pin assignment, Processing > Start > Start I/O Assignment Analysis is
selected from the main menu. When a message is received indicating that I/O assignment
analysis has completed successfully, button OK is clicked to close the message box.
10. The design compiled.

11. As a safety precaution, all unused pins should not drive the I/O pins to avoid potential short
circuits with external peripherals. The Assignments > Device… menu is selected to open the
Device setting dialog box.

The Device & Pin Options… button is clicked, the Unused Pins tab is selected, and set Reserve all
unused pins as As input tri-stated as shown in Figure 11.
2.5 Program the Device

1. The USB cable is plugged to the USB-Blaster Port on the DE2 board, and the other end of the
cable to the computer.

2. The Programmer icon is selected from toolbar; a new CDF is opened in the Programmer window
automatically showing the sof file as the current programming file.
3. The Mode list of the Programmer window is selected as JTAG.

4. If the column next to Hardware Setup… button shows No Hardware, click Hardware Setup
button. In the Hardware Setup dialog box, at Currently selected hardware, USB-Blaster is
selected. The dialog box is closed.
5. The Program/Configure checkbox is marked as check, as shown below.

6. In the Programmer window, Start button is clicked. A message will be received indicating that
the configuration is complete, OK button is clicked.
7. To verify the design, for the input values supplied at the toggle switches, the number displayed
on the 7-segment display should show the correct sum and the LED will be lit if there is a carry
out.
CONCLUSION

As a result, we now know that Altera FPGAs need to be loaded with data that configures the part for a
certain design every time power is applied. The user has total control over the board's operation thanks
to the chip's pin connections to all essential parts of the board. We now know enough to navigate the
schematic design-entry environment of Altera with ease. After successfully constructing, integrating,
debugging, testing, and simulating a simple circuit, we also succeeded in downloading and executing the
design using an Altera FPGA DE2 board. For the input values supplied at the toggle switches, the number
displayed on the 7-segment display should show the correct sum and the LED will be lit if there is a carry
out.