®

PG
A20
6
PGA206
PG
PGA207
A2
07

High-Speed Programmable Gain

INSTRUMENTATION AMPLIFIER

FEATURES DESCRIPTION
● DIGITALLY PROGRAMMABLE GAINS: The PGA206 and PGA207 are digitally programmable
PGA206: G=1, 2, 4, 8V/V gain instrumentation amplifiers that are ideally suited
PGA207: G=1, 2, 5, 10V/V for data acquisition systems.
● TRUE INSTRUMENTATION AMP INPUT The PGA206 and PGA207’s fast settling time allows
multiplexed input channels for excellent system effi-
● FAST SETTLING: 3.5µs to 0.01%
ciency. FET inputs eliminate IB errors due to analog
● FET INPUT: IB = 100pA max multiplexer series resistance.
● INPUT PROTECTION: ±40V Gains are selected by two CMOS/TTL-compatible
● LOW OFFSET VOLTAGE: 1.5mV max address lines. Analog inputs are internally protected
● 16-PIN DIP, SOL-16 SOIC PACKAGES for overloads up to ±40V, even with the power sup-
plies off. The PGA206 and PGA207 are laser-trimmed
for low offset voltage and low drift.
APPLICATIONS The PGA206 and PGA207 are available in 16-pin
● MULTIPLE-CHANNEL DATA ACQUISITION plastic DIP and SOL-16 surface-mount packages. Both
are specified for –40°C to +85°C operation.
● MEDICAL, PHYSIOLOGICAL AMPLIFIER
● PC-CONTROLLED ANALOG INPUT
BOARDS

VO1 V+
1 13
PGA206
– 4 Over-Voltage
VIN PGA207
Protection Feedback
A1
12
10kΩ 10kΩ

16
A1 Digitally Selected
15 A3 VO
A0 Feedback Network 11
14
Digital
Ground

A2 Ref
+ 5 Over-Voltage 10
VIN 10kΩ 10kΩ
Protection

6 7 9 8

VOS VO2 V–
Adj

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©
1994 Burr-Brown Corporation PDS-1241B Printed in U.S.A. May, 1995
SPECIFICATIONS
At TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise noted.

PGA206P, U PGA206PA, UA
PGA207P, U PGA207PA, UA
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT
Offset Voltage, RTI All Gains
Initial TA = +25°C ±0.5 ±1.5 ±1 ±2.5 mV
vs Temperature TA = TMIN to TMAX, G = 8, 10 ±2 ✻ µV/°C
vs Power Supply VS = ±4.5V to ±18V ±5 ±20 ±10 ±40 µV/V
Long-Term Stability 4.5 ✻ µV/mo
Impedance, Differential 1013 || 1 ✻ Ω || pF
Common-Mode 1012 || 4 ✻ Ω || pF
Common-Mode Voltage Range(1) VO = 0V ±(|VS|–4) ±(|VS| –2.5) ✻ ✻ V
Safe Input Voltage ±40 ✻ V
Common-Mode Rejection VCM = ±11V, ∆RS = 1kΩ
G=1 80 92 75 86 dB
G=2 85 96 80 90 dB
G = 4 or 5 90 100 84 94 dB
G = 8 or 10 95 100 84 94 dB
INPUT BIAS CURRENT VIN = 0 2 100 ✻ ✻ pA
vs Temperature See Typical Curve ✻
Offset Current 1 100 ✻ ✻ pA
vs Temperature See Typical Curve ✻
NOISE VOLTAGE, RTI G = 8,10; RS = 0Ω
f = 10Hz 30 ✻ nV/√Hz
f = 100Hz 20 ✻ nV/√Hz
f = 1kHz 18 ✻ nV/√Hz
fB = 0.1Hz to 10Hz 1 ✻ µVp-p
Noise Current
f = 1kHz 1.5 ✻ fA/√Hz
GAIN All Gains, VO = ±11V
Gain Error ±0.01 ±0.05 ✻ ±0.1 %
Gain vs Temperature(2) ±1 ±10 ✻ ✻ ppm/°C
Nonlinearity ±0.0003 ±0.002 ✻ ±0.005 % of FSR
OUTPUT
Voltage, Positive (V+) –4 (V+) –2.3 ✻ ✻ V
Negative (V–) +4 (V–) +1.5 ✻ ✻ V
Load Capacitance Stability 1000 ✻ pF
Short-Circuit Current ±17 ✻ mA
FREQUENCY RESPONSE
Bandwidth, –3dB G=1 5 ✻ MHz
G=2 4 ✻ MHz
G = 4, 5 1.3 ✻ MHz
G = 8, 10 600 ✻ kHz
Slew Rate VO = ±10V, G = 1 to 10 25 ✻ V/µs
Settling Time, 0.1% 20V Step, All Gains 2 ✻ µs
0.01% 20V Step, All Gains 3.5 ✻ µs
Output Overload Recovery 50% Overdrive 1.5 ✻ µs
DIGITAL LOGIC INPUTS
Digital Ground Voltage, VDG V– (V+) –4 ✻ ✻ V
Digital Low Voltage V– VDG + 0.8V ✻ ✻ V
Digital Input Current 1 ✻ pA
Digital High Voltage VDG+2 V+ ✻ ✻ V
Gain Switching Time 500 ✻ ns
POWER SUPPLY
Voltage Range ±4.5 ±15 ±18 ✻ ✻ ✻ V
Current VIN = 0V +12.4/–11.2 ±13.5 ✻ mA
TEMPERATURE RANGE
Specification –40 +85 ✻ ✻ °C
Operating –40 +125 ✻ ✻ °C
Thermal Resistance, θJA 80 ✻ °C/W

✻ Specification same as PGA206P or PGA207P.

NOTES: (1) Input common-mode range varies with output voltage—see typical curves. (2) Guaranteed by wafer test.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

PGA206/207 2
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Top View DIP Supply Voltage .................................................................................. ±18V
SOL-16 Analog Input Voltage Range ............................................................. ±40V
Logic Input Voltage Range .................................................................. ±VS
Output Short-Circuit (to ground) .............................................. Continuous
VO1 1 16 A1 Operating Temperature ................................................. –40°C to +125°C
Storage Temperature ..................................................... –40°C to +125°C
NC 2 15 A0 Junction Temperature .................................................................... +150°C
Lead Temperature (soldering –10s) .............................................. +300°C
NC 3 14 Dig. Ground
–
VIN 4 13 V+
+
ORDERING INFORMATION
VIN 5 12 Sense
TEMPERATURE
VOS Adjust 6 11 VO PRODUCT GAINS PACKAGE RANGE
PGA206PA 1, 2, 4, 8V/V 16-Pin Plastic DIP –40°C to +85°C
VOS Adjust 7 10 Ref
PGA206P 1, 2, 4, 8V/V 16-Pin Plastic DIP –40°C to +85°C
V– 8 9 VO2 PGA206UA 1, 2, 4, 8V/V SOL-16 Surface-Mount –40°C to +85°C
PGA206U 1, 2, 4, 8V/V SOL-16 Surface-Mount –40°C to +85°C

NC: No Internal Connection PGA207PA 1, 2, 5, 10V/V 16-Pin Plastic DIP –40°C to +85°C
PGA207P 1, 2, 5, 10V/V 16-Pin Plastic DIP –40°C to +85°C
PGA207UA 1, 2, 5, 10V/V SOL-16 Surface-Mount –40°C to +85°C
PGA207U 1, 2, 5, 10V/V SOL-16 Surface-Mount –40°C to +85°C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1) ELECTROSTATIC
PGA206PA
PGA206P
16-Pin Plastic
16-Pin Plastic
DIP
DIP
180
180
DISCHARGE SENSITIVITY
PGA206UA SOL-16 Surface Mount 211 This integrated circuit can be damaged by ESD. Burr-Brown
PGA206U SOL-16 Surface Mount 211
recommends that all integrated circuits be handled with ap-
PGA207PA 16-Pin Plastic DIP 180
PGA207P 16-Pin Plastic DIP 180
propriate precautions. Failure to observe proper handling and
PGA207UA SOL-16 Surface Mount 211 installation procedures can cause damage.
PGA207U SOL-16 Surface Mount 211
ESD damage can range from subtle performance degradation
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

3 PGA206/207
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.

GAIN vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY

30 120
G = 10 G = 10V/V

Common-Mode Rejection (dB)

G=5
20 100
G=8
Gain (dB)

10 G=4 80

G=2 G = 1V/V
0 60
G=1

–10 40

–20 20
10k 100k 1M 10M 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

INPUT COMMON-MODE VOLTAGE RANGE

POWER SUPPLY REJECTION vs FREQUENCY vs OUTPUT VOLTAGE
120 15
y A1 Limit
ed b + Ou ed by A
G = 10V/V Limit ut Swing tput
tp Swin2
10 + Ou
Power Supply Rejection (dB)

Common-Mode Voltage (V)

100 g
–
VD/2 VO
5 +
80 –
VD/2
+ +

60 0 VCM
(Any Gain)
G = 1V/V A3 + Output
A3 – Output
40 –5 Swing Limit
Swing Limit
Lim
it
20
+PSR –10 – O ed by by A 1 g
–PSR utpu A ited in
t Sw 2
ing Lim put Sw
O ut
–15 –
0
10 100 1k 10k 100k 1M 10M –15 –10 –5 0 5 10 15
Frequency (Hz) Output Voltage (V)

INPUT VOLTAGE NOISE vs FREQUENCY INPUT BIAS CURRENT vs TEMPERATURE

1k 10n
Voltage Noise Density nV/√Hz

1n
Input Bias Current (A)

100p
IB

100 10p
G=1

1p
IOS

100f

G = 10
10 10f
1 10 100 1k 10k 100k –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

PGA206/207 4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

INPUT OVER-VOLTAGE V/I CHARACTERISTIC OFFSET VOLTAGE WARM-UP TIME

6 100
+15V

I
4

Offset Voltage Change (µV)

50
Input Current (mA)

V
2
–15V

0 0

–2 Input current increases when the applied

voltage exceeds the power supply voltage. –50
–4 This V/I characteristic does not vary with
the voltage applied to the other input.

–6 –100
–40 –30 –20 –10 0 10 20 30 40 0 1 2 3 4
Input Voltage (V) Time After Turn-On (minutes)

OFFSET VOLTAGE TEMPERATURE DRIFT QUIESCENT CURRENT

PRODUCTION DISTRIBUTION vs POWER SUPPLY VOLTAGE
35 14
Typical production distribution
30 of packaged units.
13
Quiescent Current (mA)

G = 8, 10V/V
25 +IQ

12 –55°C
Units (%)

20 +25°C
+125°C –IQ
15 11 –55°C
+25°C
10 +125°C
10
5

0 9
–10 –8 –6 –4 –2 0 2 4 6 8 10 0 ±5 ±10 ±15 ±20

Offset Voltage Drift (µV/°C) Power Supply Voltage (V)

TOTAL HARMONIC DISTORTION + NOISE

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY vs FREQUENCY
0.1

VO = 6Vrms
Maximum Output Voltage (Vp-p)

RL = 2kΩ
G = 10V/V
G=1
30
20 RL = 2kΩ
THD + N (%)

G = 2V/V
RL = ∞
10 0.01
G = 1V/V
Maximum output voltage
without slew-rate limiting or G = 10V/V
other large-signal distortion.
Dotted region is beyond
small signal bandwidth.
G = 1V/V
1 0.001
100k 1M 10M 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

5 PGA206/207
 TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE

G = 1, CL = 50pF G = 10, CL = 50pF

100mV/div 100mV/div

1µs/div 1µs/div

LARGE SIGNAL RESPONSE LARGE SIGNAL RESPONSE

G = 1, CL = 50pF G = 10, CL = 50pF

5V/div 5V/div

1µs/div 1µs/div

PGA206/207 6
 +15V
1µF

VO1
1 13
PGA206
– 4 Over-Voltage
VIN PGA207
Protection Sense
A1
12
10kΩ 10kΩ

16
Digitally Selected
15 A3 VO
Feedback Network 11
14
+ –
VO = G (VIN – VIN )

Ref
A2
+ 5 Over-Voltage 10
VIN 10kΩ 10kΩ
Protection

6 7 9 8
Digital Sometimes shown in simplified form:
1µF
Ground VOS VO2
GAIN Adj –
VIN
PGA206 PGA207 A 1 A0
PGA206 VO
1 1 0 0 –15V +
VIN
2 2 0 1
4 5 1 0
8 10 1 1 A1 A0

FIGURE 1. Basic Connections.

APPLICATIONS INFORMATION
Figure 1 shows the circuit diagram for basic operation of the
PGA206 or PGA207. Applications with noisy or high im-
pedance power supplies may require decoupling capacitors
close to the device pins as shown.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 2Ω in series with the Ref pin will cause a typical
device to degrade to approximately 80dB CMR (G = 1).
The output sense connection (pin 12) must be connected to
the output terminal (pin 11) for proper operation. This
connection can be made at the load for best accuracy.
The digital inputs, A0 and A1, are not latched. A change in
logic input immediately selects a new gain. Switching time
of the logic is approximately 500ns. The time to respond to
gain change is equal to switching time, plus the time it takes
the amplifier to settle to a new output voltage in the newly
selected gain (see settling time specifications).
Many applications use an external logic latch to acquire gain
control data from a high speed digital bus. Using an external
latch isolates the high speed digital bus from sensitive
analog circuitry. Locate the digital latch as far as practical
from analog circuitry to avoid coupling digital noise into
analog input circuitry.

OFFSET VOLTAGE ADJUSTMENT

DIGITAL INPUTS
The PGA206 and PGA207 are laser trimmed for very low
The digital inputs A0 and A1 select the gain according to the
offset voltage and drift. Many applications require no exter-
logic table in Figure 1. Logic “1” is defined as a voltage
nal offset adjustment. Multiplexed data acquisition systems
greater than 2V above digital ground potential (pin 14).
generally correct offset by grounding the inputs of one
Digital ground can be connected to any potential ranging
channel to measure offset voltage. Stored offset values for
from the V– power supply to 4V less than V+. Digital
each gain are then subtracted from subsequent readings of
ground is usually equal to analog ground potential and the
other channels.
two grounds are connected at the power supply. The digital
inputs interface directly to CMOS and TTL logic. Figure 2 shows optional offset voltage trim circuits. Offset
voltage changes with the selected gain. To adjust for low
A nearly constant current of approximately 1.2mA flows in
offset voltage in all gains, both input and output offsets must
the digital ground pin. It is good practice to return digital
be trimmed.
ground through a separate connection path so that analog
ground is not affected by the digital ground current.

7 PGA206/207
 Manual output offset trim circuit.
V+
VO1 V+
Resistors can be substituted
1 13 for REF200. Power supply 100µA
PGA206 rejection will be degraded. 1/2 REF200
– 4 Over-Voltage PGA207
VIN
Protection
A1 100Ω
12
10kΩ 10kΩ R2
10kΩ
100Ω
16
A1 Digitally Selected
15 A3 VO
A0 Feedback Network 11
14 100µA
Digital 1/2 REF200
Ground
VREF
A2 V–
5 Over-Voltage 10
V+IN
10kΩ 10kΩ
Protection Offset control with
OPA131 digital/analog converter
6 7 9 8

VO2 V–
Optional Input Offset Adjustment D/A
R1
200kΩ
(100kΩ to 500kΩ)
V+

FIGURE 2. Optional Offset Voltage Trim Circuits.

R1 adjusts the offset of the input amplifiers. Output stage

offset is adjusted with R2. A buffer op amp is required in
the output offset adjustment circuit, as shown, to assure
Microphone,
that the Ref pin is driven by a low source impedance. To Hydrophone PGA
adjust for low offset voltage in all gains, first adjust the etc.
input stage offset in the highest gain. Then adjust the
output stage offset (R2) in G = 1. Iterate the adjustments for 47kΩ 47kΩ
lowest offset in all gains.
Offset can also be adjusted under processor control with a
D/A converter as shown in Figure 2. The D/A’s output
voltage can be reduced with a resistor divider for better
adjustment resolution, but an op amp buffer following the Thermocouple PGA
divider is required to provide a low source impedance to
the ref terminal. A different offset value is required for
each amplifier gain. 10kΩ

INPUT BIAS CURRENT RETURN PATH

The FET inputs of the PGA206 and PGA207 provide ex-
tremely high input impedance. Still, a path must be provided
PGA
for the bias current of each input. Figure 3 shows provisions
for an input bias current path. Without a bias current return
path, the inputs will float to a potential which exceeds the
linear input voltage range and the input amplifiers will VR Center-tap provides
bias current return.
saturate.
If the differential source resistance is low, a bias current
return path can be connected to only one input (see thermo- Bridge
couple example in Figure 3). With higher source impedance,
PGA
using two resistors provides a balanced input with possible
advantages of lower input offset voltage due to bias current
and better common-mode rejection. Bias current return
Many sources or sensors inherently provide a path for input inherrently provided by source.
bias current (e.g. the bridge sensor shown in Figure 3).
These applications do not require additional resistor(s) for FIGURE 3. Providing an Input Bias Current Path.
proper operation.
®

PGA206/207 8
 +15V

14 2
Input Filter
HI-509
See Text
4
1nF
1kΩ
–
VIN 5
8
6
Channel 1 10nF
1kΩ
+
VIN 7
A/D Converter
PGA207
13 ADS7807
1nF
12
9
11

10
15

Channel 4
3 1 16
Software-Zero

–15V

To Address
74HC574 CK
Logic

Data Bus

FIGURE 4. Multiplexed-Input Signal Acquisition System.

INPUT COMMON-MODE RANGE MULTIPLEXED INPUTS

The linear input voltage range of the PGA206 and PGA207
is from approximately 2.3V below the positive supply volt-
age to 1.5V above the negative supply. As a differential
input voltage causes output voltage to increase, however, the
linear input range is limited by the output voltage swing of
amplifiers A1 and A2. So the linear common-mode input
range is related to the output voltage of the complete
amplifier. This behavior also depends on supply voltage—
see performance curves “Input Common-Mode Range vs
Output Voltage”.
Input overload can produce an output voltage that appears
normal. For example, if an input overload condition drives
both input amplifiers to their positive output swing limit, the
difference voltage measured by the output amplifier will be
near zero. The output of the PGA206 or PGA207 will be
near 0V even though both inputs are overloaded. This
condition can be detected by sensing the voltage on the V01
and V02 pins to determine whether they are within their
linear operating range.
The PGA206 and PGA207 are ideally suited for multiple
channel data acquisition. Figure 4 shows a typical applica-
tion with an analog multiplexer used to connect one of four
differential input signals to a single PGA207.
Careful circuit layout will help preserve accuracy of multi-
plexed signals. Run the inverting and non-inverting connec-
tions of each channel parallel to each other over a ground
plane, or directly adjacent on top and bottom of the circuit
board. Grounded guard traces between channels help reduce
stray signal pick-up.
Multiplexed signals from high impedance sources require
special care. As inputs are switched by the multiplexer,
charge can be injected into the source, disturbing the input
signal. Since many such sources involve slow signals, a
simple R/C filter at the input can be used to dramatically
reduce this effect. The arrangement shown filters both the
differential signal and common-mode noise.

INPUT PROTECTION
The inputs of the PGA206 and PGA207 are individually
protected for voltages up to ±40V. For example, a condition
of -40V on one input and +40V on the other input will not
cause damage. Internal circuitry on each input provides low
series impedance under normal signal conditions. If the input
is overloaded, the protection circuitry limits the input current
to a safe value. The typical performance curve “Input Over-
load V/I Characteristic” shows this behavior. The inputs are
protected even if no power supply voltage is applied.

9 PGA206/207
 VO1
–
VIN
+
PGA207 VO
VIN
Ref
VO2

220Ω A1 A0 20kΩ 20kΩ

OPA131
Equal to input
common-mode voltage.

FIGURE 5. Shield Drive Circuit.

GAIN (V/V) A1 A0 A3 A2

G = 1, 2, 5, 10 G = 1, 10, 100 1 0 0 0 0
–
VIN 2 0 1 0 0
7 5 1 0 0 0
PGA207 PGA103 VO 10 1 1 0 0
+ 4
VIN 3 20 0 1 0 1
1 50 1 0 0 1
2
100 1 1 0 1
200 0 1 1 0
A1 A0 A 3 A2 500 1 0 1 0
1000 1 1 1 0

FIGURE 6. Wide Gain Range Programmable IA.

PGA206/207 10