D-00151 FORESEE - LPDDR3 - NCLD3B1256M32 - 178ball - 11x11.5 - 1333Mbps - SPEC

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Lo FORESEE LPDDR3
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NCLD3B1256M32 8Gb
LPDDR3 (x32)
Version: 1.0
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2018.11.09
LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

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SPECIFICATIONS WITHOUT NOTICE.
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C only. All information
Products and specifications discussed herein are for reference purposes
discussed herein is provided on an "AS IS" basis, without warranties of any kind.
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This document and all information discussed herein remain the sole and exclusive property of
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Longsys Electronics. No license of any patent, copyright, mask work, trademark or any other
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intellectual property right is granted by one party to the other party under this document, by
implication, estoppel or other-wise.
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Longsys products are not intended for use in life support, critical care, medical, safety
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equipment, or similar applications where product failure could result in loss of life or personal or
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physical harm, or any military or defense application, or any governmental procurement to
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which special terms or provisions may apply.
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For updates or additional information about Longsys products, contact your nearest Longsys onfi
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gsys office.
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All brand names, trademarks and registered trademarks belong to their respective owners.
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ⓒ 2018 Shenzhen Longsys Electronics Co., Ltd. All rights reserved. Lo
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www.longsys.com f iden Longsys Electronics
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Revision History: C
Rev. Date Changes Remark
1.0 2018/11/09 Basic spec and architecture Preliminary
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CONTENTS
1. Features ..................................................................................................................................... 1
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2. Ordering Information ................................................................................................................. 1
3. Part n
Lo Number Information ........................................................................................................... 2
4. Package Block Diagrams ............................................................................................................ 2
4.1single-Die, Single-Channel Package Block Diagram ..................................................................... 2
5. Package Dimensions .................................................................................................................. 3
5.1 178-Ball FBGA (11mm x 11.5mm) ........................................................................................... 3
6. Ball Assignments ....................................................................................................................... 4
6.1 178-Ball Single-Channel FBGA – 1 x 8Gb Die ............................................................................. 4
7. Ball Descriptions ........................................................................................................................ 5
8. Input/Output Capacitance ......................................................................................................... 6
9. Functional Description ............................................................................................................... 6
9.1Functional Block Diagram ......................................................................................................... 7
10. Simplified State Diagram ......................................................................................................... 8
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11. Mode Register Definitions ........................................................................................................ 9 Lo
11.1 MR0 Device Feature 0 (MA [7:0] = 00h) ............................................................................... 10
11.1.1 MR0 Op-Code BIt Definitions .......................................................................................... 11
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11.2.1 MR1 Op-Code Bit Definitions .......................................................................................... 12
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11.4 MR3 I/O Configuration 1 (MA [7:0] = 03h ............................................................................. 13
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11.5 MR4 Device Temperature (MA [7:0] = 04h)........................................................................... 14
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11.6 MR5 Basic Configuration 1 (MA [7:0] = 05h) ......................................................................... 15
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11.8.1 MR7nOp-Code Bit Definitions .......................................................................................... 15
11.9 MR8
o Configuration 4 (MA [7:0] = 08h) ......................................................................... 15
CBasic t ia
11.9.1 MR8 Op-Code Bit Definitions .......................................................................................... 16 id
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11.10 MR9 Test Mode (MA [7:0] = 09h) .......................................................................................o16
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gsys 11.11 MR10 Calibration (MA [7:0] = 0Ah) .................................................................................... 16
n 11.11.1 MR10 Op-Code Bit Definitions....................................................................................... 16
11.12 MR11 ODT Control (MA [7:0] = 0Bh) .................................................................................. 16
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11.12.1 MR11 Op-Code Bit Definitions....................................................................................... 17
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11.13 MR16 PASR Bank Mask (MA [7:0] = 010h) .......................................................................... 17
11.13.1 MR16 Op-Code Bit Definitions....................................................................................... 17
11.14 MR17 PASR Segment Mask (MA [7:0] = 011h) ..................................................................... 17
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11.14.1 MR17 PASR Segment Mask Definitions........................................................................... 17

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C=o3Fh) – MRW Only ........................................................................ 18
11.15 MR63 RESET (MA [7:0]
11.16 Reserved Mode Registers .................................................................................................. 18
12. Truth Tables ........................................................................................................................... 19
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12.1 Command Truth Table ........................................................................................................ 19
12.2nCKE Truth Table ................................................................................................................. 21
o Current State Bank n to Command to Bank n Truth Table ....................................................... 23
L12.3
12.4 Current State Bank n to Command to Bank m Truth Table ...................................................... 25
12.5 DM Truth Table .................................................................................................................. 26
12.6 ODT States Truth Table....................................................................................................... 26
13. IDD Specifications.................................................................................................................. 27
13.1 IDD Specifications – Single Die ............................................................................................ 27
14. AC and DC Operating Conditions ............................................................................................ 30
14.1 Recommended DC Operating Conditions ............................................................................... 30
14.2 Input Leakage Current ........................................................................................................ 30
15. AC and DC Logic Input Measurement Levels for Single-Ended Signals ................................... 31
15.1 Single-Ended AC and DC Input Levels for CA and CS_n Inputs ................................................. 31
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15.2 Single-Ended AC and DC Input Levels for CKE ....................................................................... 31 Lo
15.3 Single-Ended AC and DC Input Levels for DQ and DM ............................................................. 32
15.4 Differential AC and DC Input Levels ...................................................................................... 33
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15.5 Single-Ended Levels for CK and DQS .................................................................................... 33
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15.6 Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c).............................. 34
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16. Output Characteristics and Operating Conditions ................................................................... 35
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16.1 Single-Ended AC and DC Output Levels ................................................................................. 35
16.2 Differential AC and DC Output Levels .................................................................................... 35
17. AC Overshoot/Undershoot Specification ................................................................................ 36
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18. AC Timing............................................................................................................................... 37
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19. CA and CS_n Setup, Hold, and Derating ................................................................................. 46
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19.1 CA Setup and Hold Base Values ........................................................................................... 46
19.2 CS_n Setup and Hold Base Values ........................................................................................ 47
19.3 Derating Values for AC/DC-Based tIS/tIH (AC150) .................................................................. 47
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19.4 Derating Values for AC/DC-Based tIS/tIH (AC135) .................................................................. 47
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20. Data Setup, Hold,
i denand Slew Rate Derating ............................................................................. 48
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n and Hold Base Values ........................................................................................ 49
20.1 Data Setup
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C Values for AC/DC-Based DS/ DH (AC150) ................................................................ 49 ntia
20.2 Derating t t
20.3 Derating Values for AC/DC-Based DS/ DH (AC135) ................................................................ 49 id

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1. Features C
[LPDDR3]
 Ultra-low-voltage core and I/O power supplies

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Frequency range
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L8noprefetch DDR architecture
-667-10MHz (data rate range: 1333-20Mb/s/pin)

 8 internal banks for concurrent operation
 Multiplexed, double data rate, command/address inputs; command entered on each CK_t/CK_C edge
 Bidirectional/differential data strobe per byte of data(DQS_t/DQS_C)
 Programmable READ and WRITE latencies(RL/WL)
 Burst length:8
 Per-bank refresh for concurrent operation
 Temperature-compensated self refresh (TCSR)
 Partial-array self refresh (PASR)
 Deep power-down mode(DPD)
 Selectable output drive strength(DS)
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 Clock-stop Capability Lo
 On-die termination(ODT)
 ROHS-compliant, ”green” packaging
 Array configuration
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-256M*32(SDP)
 Device configuration
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-1 die in package C
 Operation Temperature
-(-25℃ to +70℃)
 Package
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- 178-ball FBGA - 11.0*11.5mm*1.02mm n g
- Lead & Halogen Free Lo
2. Ordering Information
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Memory Operation
Part Number
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Combination
d Voltage
Density Speed Package
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n LPDDR3 8Gb
NCLD3B1256M32 1.8v/1.2v/1.2v/1.2v 8Gb(x32, DDR3 178Ball FBGA
C o ti a
1CS) 1333 (Lead & Halogen Free)
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3. Part Number Information
NC LD3 B 1 256M32
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n NC：Longsys Density：
Lo 256M32:LPDDR3
256M*32
Memory type：
LD3：LPDDR3
Package： CS：
B: 178ball 1:1CS
4. Package Block Diagrams

4.1single-Die, Single-Channel Package Block Diagram n gs
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5. Package Dimensions
5.1 178-Ball FBGA (11mm x 11.5mm)
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6. Ball Assignments C
6.1 178-Ball Single-Channel FBGA – 1 x 8Gb Die
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7. Ball Descriptions C
SYMBOL TYPE DESCRIPTION
CK_t, CK_c Input Clock: Differential clock inputs. All CA inputs are sampled on both rising and
ng sys falling edges of CK. CS and CKE inputs are sampled at the rising edge of CK.
L o AC timings are referenced to clock.

CA[9:0] Input Command/address inputs: Provide the command and address inputs
according to the command truth table.
CKE[0] Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock signals, input buffers, and output drivers. Power-saving modes are
entered and exited via CKE transitions. CKE is considered part of the
command code. CKE is sampled on the rising edge of CK.
CS[0]_n Input Chip select: Considered part of the command code and is sampled on the
rising edge of CK.
DM[3:0] Input Input data mask: Input mask signal for write data. Although DM balls are
input-only, the DM loading is designed to match that of DQ and DQS balls. DM
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[3:0] is DM for each of the four data bytes, respectively.
Lo
ODT Input On-die termination: Enables and disables termination on the DRAM DQ bus
according to the specified mode register settings. For packages that do not
support ODT, the ODT signal may be grounded internally.
DQS[3:0]_t, Input/Output ti al
Data strobe: Bidirectional (used for read and write data) and complementary
DQS[3:0]_c
i dendata and centered
(DQS_t and DQS_c). It is edge-aligned output with read
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input with write data. DQS [3:0]_t/DQS[3:0]_coisnDQS for each of the four
data bytes, respectively.
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DQ[31:0] Input/Output Data input/output: Bidirectional data bus.
VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity.
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VSSQ Supply g
DQ ground: Isolated on the die for improved noise immunity.
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VDDCA Supply Lo
Command/address power supply: Command/address power supply.
VSSCA Supply Command/address ground: Isolated on the die for improved noise immunity.
VDD1 Supply Core power: Supply 1.
VDD2 Supply
Supply nt
ial Core power: Supply 2.
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VSS Common ground.
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VREFCA, VREFDQ f i
Supply Reference voltage: VREFCA is reference for command/address input buffers,
Co VREFDQ is reference for DQ input buffers.
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ZQ[0] Reference External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
C o
gsys NU - Not usable: Do not connect.
n NC - No connect: Not internally connected.
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8. Input/Output Capacitance
Part Number Density Parameter Symbol Min. Max. Unit Notes
Input capacitance, CK_t and
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Cck 1.0 2.5 pF 1,2
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NCLD3B1256M32 8Gb
Input capacitance, all other
input-only pins
CI 1.0 2.5 pF 1,2
Input/output capacitance, DQ,

CIO 1.5 4.5 pF 1,2
DM, DQS_t, DQS_c
Input/Output Capacitance ZQ CZQ 1.5 3.5 pF 1,2,3
(TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, VDD2 = 1.14-1.3V)
Notes:
1. This parameter applies to both die and package.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured
according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with V DD1,
VDD2,VDDQ, VSS, VSSCA, VSSQ applied and all other pins floating).
3. CI applies to CS_n, CKE, CA0-CA9. n gs
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9. Functional Description
Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device.LPDDR3 uses a
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double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the
t
system. The 10-bit CA bus is used to transmit command, address, and bank information.
i d enEach command uses
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n and falling edges of the
one clock cycle, during which command information is transferred on both the rising
clock. C o
LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data
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rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits
per DQ every clock cycle at the I/O pins. A single n
o read or write access for LPDDR3 effectively consists of a
single 8n-bit-wide, one-clock-cycle data transferLat the internal SDRAM core and eight corresponding nbit-wide,
one-half-clock-cycle data transfers at the I/O pins.
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Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for
a programmed number
f i denof locations in a programmed sequence.
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Accesses begin with the registration of an ACTIVATE command followed by a READ or WRITE command. The
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address and BA bits registered coincident with the ACTIVATE command are used to select the row and bank to fid
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Cothe
be accessed. The address bits registered coincident with the READ or WRITE command are used to select
gsys bank and the starting column location for the burst access.
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9.1Functional Block Diagram
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10. Simplified State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the
commands that control them. For a complete description of device behavior, use the information provided in the
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state diagram with the truth tables and timing specifications. The truth tables describe device behavior and
o n restrictions when considering the actual state of all banks. For command descriptions, see the
applicable
L
Commands and Timing section.
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Notes: onfi
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gsys 1. All banks are precharged in the idle state.
n 2. In the case of using MRW to enter CA training mode or write leveling mode, the state machine will not automatically return
to the idle state. In these cases, an additional MRW command is required to exit either operating mode and return to the
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idle state. See the CA Training Mode or Write Leveling Mode sections.
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Lo
3. Terminated bursts are not allowed. For these state transitions, the burst operation must be completed before a transition
can occur.
4. The state diagram is intended to provide a floorplan of the possible state transitions and commands used to control them,
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but it is not comprehensive. In particular, situations involving more than one bank are not captured in full detail.

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11. Mode Register Definitions
MR MA
Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
# [7:0]
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Device Go to
0 00h R RL3 WL-B RFU RZQI RFU DAI
Lo
info MR0
Device Go to
1 01h W nWR (for AP) RFU BL
Feature 1 MR1
WL
Device WR nWR Go to
2 02h W Selec RFU RL and WL
Feature 2 Lev E MR2
t
I/O Go to
3 03h W RFU DS
config-1 MR3
SDRAM
Go to
4 04h refresh R TUF RFU Refresh rate
MR4
rate
Basic Go to n gs
5 05h
config-1
R Manufacturer ID
MR5 Lo
Basic Go to
6 06h R Revision ID1
config-2 MR6
Basic
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den
7 07h R Revision ID2
config-3 MR7
Basic
o nfi Go to
8 08h
config-4
R I/O width Density
C Type
MR8
Go to
9 09h Test mode W Vendor-specific test mode
MR9
I/O
ngsys Go to
10 0Ah calibratio
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W
Lo Calibration code MR1
0
Go to
PD
11 0Bh ODT W RFU DQ ODT MR1
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ctl
1
en
fid Go to
12–
15
0Ch–
0FhC
onReserved - RFU MR1
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2
d e n
PASR_Ba o nfi
Go to
16 10h W PASR bank mask CMR1
gsys nk
6
n Go to
PASR_Se
17 11h
g
W PASR segment mask
ng sys MR1
Lo
7
Go to
18– 12h–
Reserved - RFU MR1
31 1Fh
8–
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C MR3
1
DQ
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calibratio
32 20h R See Data Calibration Pattern Description
Lo
n
pattern A
Go to
33– 21h– Do not
- MR3
39 27h use
3
DQ
calibratio
40 28h R See Data Calibration Pattern Description
n
pattern B
CA
41 29h W See MRW - CA Training Mode
training 1
CA n gs
42 2Ah
training 2
W See MRW - CA Training Mode
L o
Go to
43– 2Bh– Do not
- MR4
47 2Fh use
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CA
den
48 30h
training 3
W
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See MRW - CA Training Mode
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C Go to
49– 31h–
Reserved - RFU MR4
62 3Eh
9
ng sys Go to
63 3Fh RESET W
Lo X MR6
3
Go to
64– 40h–
Reserved - RFU MR6
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255 FFh
4
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Notes:
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1. RFU bits must be set to 0 during MRW.
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2. RFU bits must be read as 0 during MRR.
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3. For Reads to a write-only or RFU register, DQS is toggled and undefined data is returned.
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4. RFU mode registers must not be written. C
gsys 5. Writes to read-only registers must have no impact on the functionality of the device.
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11.1 MR0 Device Feature 0 (MA [7:0] = 00h)
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OP7 OP6 OP5 OP4 OP3 OP2 ng OP1 OP0
RL3 WL-B RFU RZQI Lo RFU DAI
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11.1.1 MR0 Op-Code BIt Definitions
Register
Tag Type OP Definition
Information
s
Device auto
n gsy 0b: DAI complete
Lo
initialization DAI Read-only OP0
1b: DAI in progress
status
00b: RZQ self-test not supported
Built-in 01b: ZQ pin can connect to VDDCA or float
self-test for 10b: ZQ pin can short to GND
RZQI1 Read-only OP[4:3]
RZQ 11b: ZQ pin self-test completed, no error condition
information detected (ZQ pin must not float; connect to VDD or
short to GND
WL Set B 0b: Device does not support WL Set B
WL-B Read-only OP[6]
support 1b: Device supports WL Set B
0b: Device does not support RL = 3, nWR = 3, WL =
1 n gs
RL3 support RL3 Read-only OP[7] 1b: Device supports RL= 3, nWR = 3, WL = 1 for L o
frequencies
≤166 MHz
Notes:
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1. RZQI will be set upon completion of the MRW ZQ INITIALIZATION CALIBRATION command.
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2. If ZQ is connected to VDDCA to set default calibration, OP [4:3] must be set to 01. If ZQ isnf
not connected to VDDCA, either
OP [4:3] = 01 or OP [4:3] = 10 may indicate a ZQ pin assembly error. C o
3. In the case of a possible assembly error, the device will default to factory trim settings for RON and will ignore ZQ
CALIBRATION commands. In either case, the system may not function as intended.
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4. If the ZQ self-test returns a value of 11b, it indicates that the device has detected a resistor connection to the ZQ pin.
o n value or that the ZQ resistor tolerance meets the specified

However, that result cannot be used to validate the ZQ resistor
limit of 240Ω+/-1%. L
OP7 OP6
t i al OP5 OP4 OP3 OP2 OP1 OP0
WR (for
n
deAP) RFU BL
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11.2.1 MR1 Op-Code Bit Definitions
Feature Type OP Definition Notes
011b: BL8 (default)
BL
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Write-only OP[2:0]
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All others: Reserved
Lo If nWR (MR2 OP[4]) = 0

001b: nWR = 3
100b: nWR = 6
110b: nWR = 8
111b: nWR = 9
If nWR (MR2 OP[4]) = 1
nWR Write-only OP[7:5] 1, 2
000b: nWR = 10 (default)
001b: nWR = 11
010b: nWR = 12
100b: nWR = 14
110b: nWR = 16
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Notes: Lo
1. The programmed value in the nWR register is the number of clock cycles that determine when to start the internal
precharge operation for a WRITE burst with AP enabled. It is determined by RU (tWR/tCK).
2. The range of nWR is extended (MR2 OP [4] = 1) by using an extra bit (nWRE) in MR2.
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OP7 OP6 OP5 OP4 OP3 OP2C OP1 OP0
WR Lev WL Sel RFU nWRE RL and WL
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Feature Type OP Definition
If OP[6] = 0 (default, WL Set A)
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0001b: RL3/WL1 (≤166 MHz)1
Lo
0100b: RL6/WL3 (≤400 MHz)
0110b: RL8/WL4 (≤533 MHz)
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL6 (≤667 MHz, default)
1001b: RL11/WL6 (≤733 MHz)
1010b: RL12/WL6 (≤800 MHz)
1100b: RL14/WL8 (≤933 MHz)
1110b: RL16/WL8 (≤1066 MHz)
RL and WL Write-only OP[3:0]
If OP[6] = 1 (WL Set B)
0001b: RL3/WL1 (≤166 MHz)1
0100b: RL6/WL3 (≤400 MHz)
n gs
0110b: RL8/WL4 (≤533 MHz) Lo
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL8 (≤667 MHz, default)
1001b: RL11/WL9 (≤733 MHz)
ti al
1010b: RL12/WL9 (≤800 MHz)
den
1100b: RL14/WL11 (≤933 MHz)
o nfi
C
1110b: RL16/WL13 (≤1066 MHz)
0b: Enable nWRE programming ≤9
nWRE Write-only OP[4]
g s ys
1b: Enable nWRE programming >9 (default)
0b: Use n
WL Set A (default)
WL select Write-only OP[6] L o
1b: Use WL Set B 2
0b: Disable write leveling (default)

WR Lev Write-only OP[7]
1b: Enable write leveling
Notes:
tial
1. See MR0 OP7.
f i den
2. See MR0 OP6. n
Co n ti a
d e
11.4 MR3 I/O Configuration 1 (MA [7:0] = 03h
n fi
OP7 OP6 OP5 OP4 OP3 OP2 OP1 C
OP0 o
gsys RFU DS
n
s y s
n g
Lo
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C
0001b: 34.3Ω typical
y s
n gs
0010b: 40Ω typical (default)
Lo
0011b: 48Ω typical
0100b: Reserved
DS Write-only OP[3:0] 0110b: Reserved
1001b: 34.3Ω pull-down, 40Ω pull-up
1010b: 40Ω pull-down, 48Ω pull-up
1011b: 34.3Ω pull-down, 48Ω pull-up
11.5 MR4 Device Temperature (MA [7:0] = 04h)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
TUF RFU SDRAM Refresh rate
n gs
11.5.1 MR4 Op-Code Bit Definitions L o
000b: SDRAM low-temperature operating limit exceeded
001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW
ti al
010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW
den
nfi
011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C)
o
SDRAM 100b: 0.5 × REFI, 0.5 × REFIpb, 0.5C
t t × REFW, no AC timing derating
t
Read-only OP[2:0]
Refresh rate 101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, no AC timing
derating
s y s
110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, timing derating
n g
Lo
required
111b: SDRAM high-temperature operating limit exceeded
Temperature
0b: OP[2:0] value has not changed since last read of MR4
update Read-only OP7
flag (TUF) t i al 1b: OP[2:0] value has changed since last read of MR4
en
Notes:
fid
on
1. A mode register read from MR4 will reset OP7 to 0.
C ti a
2. OP7 is reset to 0 at power-up.
d e n
3. If OP2 = 1, the device temperature is greater than 85˚C.
onfi
4. OP7 is set to 1 if OP [2:0] has changed at any time since the last MR4 read. C
gsys 5. The device might not operate properly when OP [2:0] = 000b or 111b.
n 6. For the specified operating temperature range and maximum operating temperature, refer to the Operating
Temperature Range table.
s y s
n g
7. LPDDR3 devices must be derated by adding 1.875ns to the following core timing parameters: RCD, RC, RAS, RP, and RRD.
Lo clock frequency specifications and
t t t t t
The DQSCK parameter must be derated as specified in the AC Timing table. Prevailing
t
related setup and hold timings remain unchanged.

8. The recommended frequency for reading MR4 is provided in the Temperature Sensor section.
t ial
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C 1 (MA [7:0] = 05h)
11.6 MR5 Basic Configuration
Manufacturer ID
g sys
nMR5 Op-Code Bit Definitions
LoFeature
11.6.1
Type OP Definition
0000 0011b: Micron
Manufacturer ID Read-only OP[7:0] 1111 1111b: Micron
11.7 MR6 Basic Configuration 2 (MA [7:0] = 06h)

Revision ID1
Note:
1. MR6 is vendor-specific.
n gs
11.7.1 MR6 Op-Code Bit Definitions Lo
0000 0000b: Revision A
Revision
Read-only OP[7:0] 0000 0001b: Revision B
ti al
den
ID1
0000 0010b: Revision C
o nfi
11.8 MR7 Basic Configuration 3 (MA [7:0] = 07h) C
Revision ID2
s y s
n g
Feature Type OP
Lo Definition
Revision ID2 Read-only OP[7:0] RFU
al
Note:
t i
en
1. MR7 is vendor-specific.
n fid
Co
11.9 MR8 Basic Configuration 4 (MA [7:0] = 08h)
n ti a
d e
I/O width Density Type
onfi
C
gsys
n
s y s
n g
Lo
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n Page 15
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C
11b: LPDDR3
Type
y s Read-only OP[1:0]
n gs
All other states reserved
Lo 0110b: 4Gb
1110b: 6Gb
0111b: 8Gb
Density Read-only OP[5:2] 1101b: 12Gb
1000b: 16Gb
1001b: 32Gb
00b: x32
I/O width Read-only OP[7:6] 01b: x16
11.10 MR9 Test Mode (MA [7:0] = 09h) n gs

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 L o
Vendor-specific test mode
11.11 MR10 Calibration (MA [7:0] = 0Ah)

ti al
OP7 OP6 OP5 OP4 OP3 OP2 en
dOP1 OP0
Calibration code
o nfi
C
Notes 1–4 apply to entire table
Feature Type OP
g s ys Definition
n CALIBRATION command after initialization
Lo0xFF:
0xAB: Long calibration
Calibration code Write-only OP[7:0] 0x56: Short calibration
0xC3: ZQ reset
en tial All others: Reserved

Notes:
fid
on
1. The device ignores calibration commands when a reserved value is written into MR10.
C ti a
2. See AC Timing table for the calibration latency.
d e n
3. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQ CALIBRATION Command) or
onfi
C with
default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates
gsys default calibration and ZQ CALIBRATION commands are ignored. In both cases, the ZQ connection must not change after
n power is supplied to the device.
4. Devices that do not support calibration ignore the ZQ CALIBRATION command.
s y s
n g
11.12 MR11 ODT Control (MA [7:0] = 0Bh) Lo
Reserved PD CTL DQ ODT
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CDefinitions
11.12.1 MR11 Op-Code Bit
00b: Disable (default)
y s
n gs
01b: RZQ/4 (Note1)
DQ ODT Write-only OP[1:0]
Lo
10b: RZQ/2
11b: RZQ/1
00b: ODT disabled by DRAM during power-down (default)
PD control Write-only OP[2]
01b: ODT enabled by DRAM during power-down
Note:
1. RZQ/4 is supported for LPDDR3-1866 and LPDDR3-2133 devices. RZQ/4 support is optional for LPDDR3-1066 and
LPDDR3-1333 devices. Consult Micron specifications for RZQ/4 support for LPDDR3-1066 and LPDDR3-1333.
11.13 MR16 PASR Bank Mask (MA [7:0] = 010h)

PASR bank mask
n gs
11.13.1 MR16 Op-Code Bit Definitions L o
0b: Refresh enable to the bank = unmasked (default)
Bank[7:0] mask Write-only OP[7:0]
1b: Refresh blocked = masked
ti al
den
fi SDRAM
OP Bank Mask
o n8-Bank
0 XXXXXXX1 C Bank 0
1 XXXXXX1X Bank 1
2 XXXXX1XX Bank 2
3 XXXX1XXX
g s ys Bank 3
4 on
XXX1XXXX
L Bank 4
5 XX1XXXXX Bank 5
6 X1XXXXXX Bank 6
7
t i al 1XXXXXXX Bank 7
de n
f i
11.14 MR17 PASR Segment Mask (MA [7:0] = 011h)
n
OP7 Co OP6 OP5 OP4 OP3 OP2 OP1 OP0
n ti a
PASR segment mask d e
onfi
C
gsys 11.14.1 MR17 PASR Segment Mask Definitions
n
s y s
0b: refresh enable to the segment (=unmasked, default)
Segment [7:0] mask Write-only OP[7:0] n g
Lo
1b: refresh blocked (=masked)
6Gb2, 8Gb,
Segment OP Segment Mask 4Gb 32Gb
12Gb2 & 16Gb
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C R[13:11] R[14:12] TBD
0 0 XXXXXXX1 000b
1 1 XXXXXX1X 001b
2
ng sys 2 XXXXX1XX 010b
o
3
L4 3 XXXX1XXX 011b
4 XXX1XXXX 100b
5 5 XX1XXXXX 101b
6 6 X1XXXXXX 110b
7 7 1XXXXXXX 111b
Notes:
1. X = “Don’t Care” for the designated segment.
2. No memory present at addresses with R13 = R14 = HIGH. Segment masks 6 and 7 are ignored.
11.15 MR63 RESET (MA [7:0] = 3Fh) – MRW Only

n gs
X or 0xFCh
Lo
Note:
1. For additional information on MRW RESET, see the Mode Register Write (MRW) section.
11.16 Reserved Mode Registers ti al

Mode
MA Address Restriction OP7 OP6 OP5 OP4 fi den
Register o nOP3 OP2 OP1 OP0
MR[12:15] 0Ch-0Fh Reserved

CReserved
MR[18:31] 12h–1Fh Reserved Reserved
MR[33:39] 21h–27h DNU DNU
s
gsy
MA[7:0]
MR[43:47] 2Bh–2Fh DNU DNU
Reserved o
n
MR[49:62] 31h–3Eh
L Reserved
MR[64:255] 40h–FFh Reserved Reserved
Note:
t i al
1. DNU = Do not use; RVU = Reserved for vendor use.
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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12. Truth Tables C
12.1 Command Truth Table
Notes 1–13 apply to entire table L = LOW; H = HIGH; X = “Don’t Care”
y s Command Pins
n gs
CA Pins
Lo
CKE CK
Command CA CA CA CA CA CA CA CA CA CA
CK CK CS n Edge
0 1 2 3 4 5 6 7 8 9
(n-1) (n)
MA MA MA
L L L L L MA0 MA4 MA5 Rising
1 2 3
MRW H H
OP OP OP
X MA6 MA7 OP0 OP1 OP2 OP6 OP7 Falling
3 4 5
MA MA MA
L L L L H MA0 MA4 MA5 Rising
MRR H H 1 2 3
X MA6 MA7 X Falling
REFRESH L L L H L X Rising
(per bank)
H H
X X Falling n gs
REFRESH L L L H H X Rising L o
H H
(all banks) X X Falling
Enter self H L L L H X Rising

refresh X
L
X X
ti al Falling
BAde
n
ACTIVATE
H H
L L H R8 R9 R10
R1
1
R1
f
2 on 0
i BA1 BA2 Rising
(bank)
X R0 R1 R2 R3 R4 R5
CR6 R7 R13 R14 Falling
BA
WRITE L H L L RFU RFU C1 C2 BA1 BA2 Rising
H H 0
(bank)
X AP C3 C4
g s ysC5 C6 C7 C8 C9 C10 C11 Falling
n
READ L H L Lo H RFU RFU C1 C2
BA
0
BA1 BA2 Rising
H H
(bank)
X AP C3 C4 C5 C6 C7 C8 C9 C10 C11 Falling
PRECHARG
t i alL H H L H AB X X
BA
BA1 BA2 Rising
E
H
deH n 0
(per bank,
n f i
Co
X X Falling
all banks)
ti a
ENTER H L H H L X Rising
d e n
DPD X
L
X X
onfi
Falling
C
gsys NOP H H
L H H H X Rising
n X X Falling
MAINTAIN L H H H X Rising
s
PD,
L L
n gsy
SREF, DPD
(NOP)
X X
Lo Falling
H X Rising
NOP H H
al
X X Falling
nt i
e
www.longsys.com n fid Page 19 Longsys Electronics
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Notes: C
1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
s ys
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur to the bank associated with the
g
READnor WRITE command.
4.
Lo
X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).For PD, SREF and DPD, CS_n, CK
can be floated after tCPDED has been met and until the required exit procedure is initiated as described in their respective
entry/exit procedures.
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during SREF and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS_n and CKE are sampled on the rising edge of the clock.
10. The least significant column address C0 is not transmitted on the CA bus, and is inferred to be zero.
11. AB HIGH during a PRECHARGE command indicates that an all-bank precharge will occur. In this case, bank address is a
"Don't Care."
n gs
12. RFU needs to input H or L (defined logic level). L o
13. When CS_n is HIGH, the CA bus can be floated.
ti al
den
o nfi
C
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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12.2 CKE Truth Table C
L = LOW; H = HIGH; X = “Don’t Care”
s
gsy
Current CKE Comm
CKEn CS_n Operation n Next State Notes
n
Lo
State n-1 -andn
Active Power
Active L L X X Maintain active power-down
Down
power-down
L H H Exit active power-down Active 6,7
Idle
Idle L L X X Maintain idle power-down
power-down
power-down
L H H NOP Exit idle power-down Idle 6,7
Maintain resetting Resetting
L L X X
Resetting idle power-down power-down
power-down Idle or
L H H NOP Exit resetting power-down 6,7,8
resetting
Deep n gs
Deep L L X X Maintain deep power-down
power-down Lo
powerdown
L H H NOP Exit deep power-down Power-on 9
L L X X Maintain self refresh Self refresh
Self refresh
L H H NOP Exit self refresh
ti
Idleal 10, 11
Bank(s)
n
deActive
H L H NOP Enter active power-down i
nfpower-down
active
Co
Idle
H L H NOP Enter idle power-down 12
power-down
ENTER
SELF s s
yEnter
All banks idle H L L
n g self refresh Self refresh 12
REFRE
SH
Lo
Deep
H L L DPD Enter deep power-down 12
power-down
t i al
H en L
Resetting
Resetting H NOP Enter resetting power-down
n fid power-down
Other states o H a
C H Refer to the command truth table
e n ti
Notes:
d
1. Current state is the state of the device immediately prior to clock edge n.
onfi
C
ys
2. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
ngs 3. CKEn is the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the previous clock edge.
4. CS_n is the logic state of CS_n at the clock rising edge n.
s y s
5. Command n is the command registered at clock edge n, and operation n is a result of command n.
g
6.
on
Power-down exit time ( XP) must elapse before any command other than NOP is issued.
t
L
7. The clock must toggle at least twice prior to the XP period.
t
8. Upon exiting the resetting power-down state, the device will return to the idle state if tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power-Down.
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Celapse before any command other than NOP is issued.
10. Self refresh exit time ( XSR) must
t
11. The clock must toggle at least twice prior to the tXSR time.
12. In the case of ODT disabled, all DQ output must be High-Z. In the case of ODT enabled, all DQ must be terminated to
y s
n gs
VDDQ.
Lo
n gs
L o
ti al
den
o nfi
C
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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Cto Command to Bank n Truth Table
12.3 Current State Bank n
Current
ys
Command Operation Next State Notes
State
n g s
Lo
Any NOP Continue previous operation Current state
ACTIVATE Select and activate row Active
REFRESH (per
Begin to refresh Refreshing (per bank) 6
bank)
REFRESH (all
Begin to refresh Refreshing (all banks) 7
Idle banks)
MRW Load value to mode register MR writing 7
MRR Read value from mode register Idle, MR reading
RESET Begin device auto initialization Resetting 7,8
PRECHARGE Deactivate row(s) in bank or banks Precharging 9,10
READ Select column and start read burst Reading
WRITE Select column and start write burst Writing n gs
Row
active MRR Read value from mode register Active MR reading
L o
PRECHARGE Deactivate row(s) in bank or banks Precharging 9
Select column and start new read
Reading
READ
burst
Reading
ti al 11, 12
WRITE Select column and start write burst

i den
Writing
f 11,12, 13
n
Writing
WRITE
Select column and start new write
burst
CoWriting 11, 12
READ Select column and start read burst Reading 11,12,14

Power-on MRW RESET Begin device auto initialization Resetting 7,9
s s
yregister
Resetting MRR
g
Read value from mode
n Resetting MR reading
Notes:
Lo
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or Txp has been met, if the previous state
was power-down.
t i al
2. All states and sequences not shown are illegal or reserved.
en
3. Current state definitions:
State
n fid Definition
Idle o
C The bank or banks have been precharged, and RP has been met.
t
ti a
Active A row in the bank has been activated, and tRCD has been met. No data bursts or accesses, and d e n
no register accesses, are in progress. onfi
C
gsys Reading A READ burst has been initiated with auto precharge disabled, and has not yet terminated.
n Writing A WRITE burst has been initiated with auto precharge disabled, and has not yet terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.NOP commands or supported
g s ys
commands to the other bank should be issued on any clock edge occurring during these states. Supported commands to the
L onthe table: Current State Bank n to

other banks are determined by that bank’s current state, and the definitions given in
Command to Bank m.
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State
C Starts with... Ends
Notes
when...
Precharging Registration of a PRECHARGE command tRP is met After tRP is met, the bank
y s
n gs
is
Lo
in the idle state.
Row activating Registration of an ACTIVATE command tRCD is met After tRCD is met, the bank
is in the active state.
READ with Registration of a READ command with tRP is met After tRP is met, the bank
AP enabled auto precharge enabled is
in the idle state.
WRITE with Registration of a WRITE command with tRP is met After tRP is met, the bank
AP enabled auto precharge enabled is
in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each
positive clock edge during these states.
Ends n gs
State Starts with...
when...
Notes
Lo
Registration of a REFRESH(per tRFCpb is After tRFCpb is met, thebank is
Refreshing(per bank)
bank) command met in the idle state.
Registration of a REFRESH(all tRFCab is i al
After tRFCab is met, the device
t
denbanks idle state.
Refreshing(all banks)
banks) command met is in the all
f i
Aftern MRR is met, the device
Cis oin the all banks idle state.
t
Idle MR reading Registrationof the MRR command tMRR is met
After tMRR is met, the device

Resetting MR reading Registration of the MRR command tMRR is met
is in the all banks idle state.
Active MR reading
ng
Registration of the MRR command sys tMRR is met
After tMRR is met, the bank
Lo is in the active state.

After tMRW is met, the device
MR writing Registration of the MRW command tMRW is met
Registration of a PRECHARGE ALL After tRP is met, the device
Precharging all
t i al
command
tRP is met
n the bank is idle and no bursts are in progress.
dethat
f i
6. Bank-specific; requires
n
Co requires that all banks are idle and no bursts are in progress.
7. Not bank-specific;
n ti a
8. Not bank-specific.
d e
9. This command may or may not be bank-specific. If all banks are being precharged, they must be in a valid state for
onfi
precharging. C
gsys 10. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
n 11. A command other than NOP should not be issued to the same bank while a READ or WRITE with auto precharge is enabled.
12. The new READ or WRITE command could be auto precharge enabled or auto precharge disabled.
s y s
13. A WRITE command can be issued only after the completion of the READ burst. n g
14. A READ command can be issued only after completion of the WRITE burst. Lo
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Cto Command to Bank m Truth Table
12.4 Current State Bank n
Current State Command to Operation Next State Notes

of Bank n y s Bank m for Bank m
n gs
Lo
Idle Any Any command supported to bank m -
Row ACTIVATE Select and activate row in bank m Active 6
activating, READ Select column and start READ burst from Reading 7
active, or bank m
precharging WRITE Select column and start WRITE burst to Writing 7
bank m
PRECHARGE Deactivate row(s) in bank or banks Precharging 8
MRR READ value from mode register Idle MR 9,10,11
reading or
active
MR reading
Reading READ Select column and start READ burst from Reading 7 n gs
(auto bank m Lo
precharge WRITE Select column and start WRITE burst to Writing 7,12
disabled) bank m
ACTIVATE Select and activate row in bank m Active
t i al
PRECHARGE Deactivate row(s) in bank or banks
den
Precharging
f i 8
Writing READ Select column and start READ burst from o n
Reading 7,13
(auto bank m C
precharge WRITE Select column and start WRITE burst to Writing 7
disabled) bank m
ACTIVATE s ys
Select and activate row in bank m
g Active
PRECHARGE
L on in bank or banks
Deactivate row(s) Precharging 8
Reading with READ Select column and start READ burst Reading 7,14
auto from bank m
precharge WRITE Select column and start WRITE burst to Writing 7,12,14
t i al
de n bank m
n f i
ACTIVATE Select and activate row in bank m Active
Co PRECHARGE Deactivate row(s) in bank or banks Precharging 8

n ti a
Writing with READ Select column and start READ burst Reading 7,13,14
d e
auto from bank m
onfi
C
gsys precharge WRITE Select column and start WRITE burst to
bank m
Writing 7,14
n ACTIVATE Select and activate row in bank m Active

PRECHARGE Deactivate row(s) in bank or banks s ys
Precharging
g 8
nResetting
Power-on
Resetting
MRW RESET
MRR
Begin device auto initialization
Read value from mode register
Lo Resetting MR
15,16
reading
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Notes: C
1. This table applies when:
• The previous state was self refresh or power-down;
sys
• After tXSR or tXP has been met; and
g
o
• When nboth CKEn -1 and CKEn are HIGH.
L
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State Starts with... Ends when... Notes

Idle MR reading Registration of the MRR command tMRR is met After tMRR is met, the device is in
the all banks idle state.
Resetting MR Registration of the MRR command tMRR is met After tMRR is met, the device is in
reading the all banks reset state.
Active MR Registration of the MRR command tMRR is met After tMRR is met, the bank is in
reading the active state.
MR writing Registration of the MRW tMRW is met After tMRW is met, the device is in
command the all banks idle state. n gs
6. RRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m.
t Lo
7. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled.
8. This command may or may not be bank-specific. If all banks are being precharged, they must be in a valid state for
precharging.
ti al
9. MRR is supported in the row-activating state.
den
10. MRR is supported in the precharging state.
o nfi
C precharging, or active).
11. The next state for bank m depends on the current state of bank m (idle, row-activating,
12. A WRITE command can be issued only after the completion of the READ burst.
13. A READ command can be issued only after the completion of the WRITE burst.
g s ys
14. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command to
o nPRECHARGE and Auto Precharge Clarification table are met.

other banks, provided that the timing restrictions in the
L
15. Not bank-specific; requires that all banks are idle and no bursts are in progress.
16. RESET command is achieved through the MODE REGISTER WRITE command.
12.5 DM Truth Table t i al

Functional Name
f i den DM DQ Notes
C on
Write enable L Valid 1
ti a
Write inhibit H X 1
d e n
Note:
onfi
1. Used to mask write data; provided simultaneously with the corresponding input data. C
gsys
n 12.6 ODT States Truth Table
CA s
Write
Read/DQ ZQ
g s y Write
Calibration Calibration n
Training Leveling
DQ termination Enabled Disabled Disabled LoDisabled Disabled
DQS termination Enabled Disabled Disabled Disabled Enabled
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i den Rev. 1.0
o nf NCLD3B1256M32
13. IDD SpecificationsC
13.1 IDD Specifications – Single Die
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
s s
ySupply Speed
Symbol
n g Unit Parameter/Condition
Lo
2133 1866 1600 1333
IDD01 VDD1 8 8 8 8 Operating one bank active precharge
IDD02 VDD2 43 41.5 40 40 current tCK = tCK(avg) MIN; tRC = tRC
(MIN); CKE is HIGH;
mA
VDDCA + CS_n is HIGH between valid commands;
IDD0,in 6 6 6 6
VDDQ CA bus inputs are SWITCHING;Data bus
inputs are STABLE;ODT disabled
IDD2P1 VDD1 0.6 0.6 0.6 0.6 Idle power-down standby current
IDD2P2 VDD2 1.3 1.3 1.3 1.3 tCK = tCK(avg) MIN; CKE is LOW; CS_n is
HIGH;
mA
VDDCA + All banks idle; CA bus inputs are
IDD2P,in
VDDQ
0.1 0.1 0.1 0.1
SWITCHING; n gs
Data bus inputs are STABLE;ODT disabled Lo
IDD2PS1 VDD1 0.6 0.6 0.6 0.6 Idle power-down standby current with clock
IDD2PS2 VDD2 1.3 1.3 1.3 1.3 stop
ti al
CK_t = LOW, CK_c = HIGH; CKE is LOW;
mA CS_n is HIGH; All banks
i d enidle;
IDD2PS,in
VDDCA +
0.1 0.1 0.1 0.1 f
n STABLE;
CA bus inputs are
VDDQ o
C are STABLE;
Data bus inputs
ODT disabled
IDD2N1 VDD1 0.6 0.6 0.6 0.6 Idle non power-down standby current
IDD2N2 VDD2 22.5 21.5 20.5 20
ng sys tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
VDDCA +
Lo mA
CA bus inputs are SWITCHING;
IDD2N,in 6 6 6 6
VDDQ Data bus inputs are STABLE;
ODT disabled
IDD2NS1 VDD1
n ial
t0.6 0.6 0.6 0.6 Idle non power-down standby current with
IDD2NS2 VDD2de 18.5 18.5 18.5 18.5 clock stop
n f i
Co
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
ti a
VDDCA +
mA CS_n is HIGH; All banks idle;
d e n
IDD2NS,in
VDDQ
6 6 6 6 CA bus inputs are STABLE;
onfi
Data bus inputs are STABLE; C
gsys ODT disabled
n IDD3P1 VDD1 1 1 1 1 Active power-down standby current
IDD3P2 VDD2 7 7 7 7 tCK
s y s
= tCK(avg) MIN; CKE is LOW;
n g
CS_n is HIGH; One bank active;
IDD3P,in
VDDCA +
0.1 0.1 0.1 0.1
mA
Lo
ODT disabled
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IDD3PS1 VDD1 1 C1 1 1 Active power-down standby current with
IDD3PS2 VDD2 7 7 7 7 clock stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
s s
yVDDCA mA CS_n is HIGH; One bank active;
n g +
Lo
IDD3PS,in 0.1 0.1 0.1 0.1 CA bus inputs are STABLE;
VDDQ
Data bus inputs are STABLE;
ODT disabled
IDD3N1 VDD1 1.3 1.3 1.3 1.3 Active non power-down standby current
tCK
IDD3N2 VDD2 23 22 21 20.5 = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; One bank active;
mA
VDDCA + CA bus inputs are SWITCHING;
IDD3N,in 6 6 6 6
ODT disabled
IDD3NS1 VDD1 1.3 1.3 1.3 1.3 Active non power-down standby current
IDD3NS2 VDD2 19 19 19 19 withclock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
n gs
mA CS_n is HIGH; One bank active; Lo
VDDCA +
IDD3NS,in 6 6 6 6 CA bus inputs are STABLE;
VDDQ
ODT disabled
ti al
IDD4R1 VDD1 2 2 2 2 en
Operating burst read current
i d
330 290 250 220 tCK = tCK(avg) n f
MIN;
IDD4R2 VDD2
(280) (240) (200) (170) CS_n is HIGH
o
C between valid commands;
One bank active; BL = 8; RL = RL (MIN);
mA
IDD4R,in VDDCA 6 6 6 6
s y s 50% data change each burst transfer;
n g ODT disabled;
Lo Values in parenthesis are for x16 bits
IDD4W1 VDD1 2 2 2 2 Operating burst write current
tCK
325 285 245 215 = tCK(avg) MIN;
IDD4W2 VDD2
t i al
(275) (235) (195) (165) CS_n is HIGH between valid commands;
en
fid
One bank active; BL = 8; WL = WL (MIN);
mA
on +
CVDDCA
ti a
IDD4W,in
VDDQ
6 6 6 6 50% data change each burst transfer;
d e n
ODT disabled;
n fi
Values in parenthesis are for x16 bits C o
gsys IDD51 VDD1 30 30 30 30 All bank auto-refresh burst current
n IDD52 VDD2 150 150 150 150 tCK = tCK(avg) MIN;
s y s
CKE is HIGH between valid commands;
mA tRC
n g
= tRFCab (MIN); Burst refresh;
IDD5,in
VDDCA +
VDDQ
6 6 6 6 Lo
ODT disabled
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IDD5AB1 VDD1 3 C3 3 3 All bank auto-refresh average current
tCK
IDD5AB2 VDD2 23 22 21 20.5 = tCK(avg) MIN;
s s
yVDDCA mA tRC = tREFI;
n g +
Lo
IDD5AB,in 6 6 6 6 CA bus inputs are SWITCHING;
VDDQ
ODT disabled
IDD5PB1 VDD1 3 3 3 3 Per bank auto-refresh average current
tCK
IDD5PB2 VDD2 23 22 21 20.5 = tCK(avg) MIN;
mA tRC = tREFIpb;
VDDCA +
IDD5PB,in 6 6 6 6 CA bus inputs are SWITCHING;
VDDQ
ODT disabled
IDD81 VDD1 24 24 24 24 Deep power-down current
IDD82 VDD2 9 9 9 9 CK_t = LOW, CK _c = HIGH; CKE is LOW;
n gs
µA CA bus inputs are STABLE; L o
VDDCA +
IDD8,in 12 12 12 12 Data bus inputs are STABLE;
VDDQ
ODT disabled
Notes:
ti al
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
den
2. IDD current specifications are tested after the device is properly initialized.
o nfi
C
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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C Conditions
14. AC and DC Operating
14.1 Recommended DC Operating Conditions
Note 1 applies to entire table
s
gsy
Symbol Min Typ Max DRAM Unit Notes
o n
VDD1 1.70 1.80 1.95 Core power 1 V 2
LVDD2 1.14 1.20 1.30 Core power 2 V
Input buffer
VDDCA 1.14 1.20 1.30 V
power
I/O buffer
VDDQ 1.14 1.20 1.30 V
power
Notes:
1. The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all noise up
to 1 MHz at the DRAM package ball.
2. VDD1 uses significantly less power than VDD2.
14.2 Input Leakage Current n gs

Parameter/Condition Symbol Min Max Unit Notes L o
Input leakage current: For CA, CKE, CS_n, CK; Any input 0V
II –2 2 µA 1
≤ VIN ≤ VDDCA; (All other pins not under test = 0V)
VREF supply leakage current: VREFDQ = VDDQ/2, or
ti al µA
den
IVREF –1 1 2
VREFCA= VDDCA/2; (All other pins not under test = 0V)
Notes:
o nfi
1. Although DM is for input only, the DM leakage must match the DQ and DQS output C
leakage specification.
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be
minimal.
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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n Page 30
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i den Rev. 1.0
n f NCLD3B1256M32
Co Measurement Levels for Single-Ended Signals
15. AC and DC Logic Input
15.1 Single-Ended AC and DC Input Levels for CA and CS_n Inputs
1333/1600 1866/2133
ys
Parameter Symbol Unit Notes
n g s Min Max Min Max
Lo
AC input logic
HIGH
VIHCA(AC) VREF + 0.150 Note 2 VREF + 0.135 Note 2 V 1,2
AC input logic
VILCA(AC) Note 2 VREF - 0.150 Note 2 VREF - 0.135 V 1,2
LOW
DC input logic
VIHCA(DC) VREF + 0.100 VDDCA VREF + 0.100 VDDCA V 1
HIGH
DC input logic
VILCA(DC) VSSCA VREF - 0.100 VSSCA VREF - 0.100 V 1
LOW
Reference
voltage for CA VREFCA(DC
0.49 × VDDCA 0.51 × VDDCA 0.49 × VDDCA 0.51 × VDDCA V 3,4
and CS_n
gs
)
inputs
o n
Notes: L
1. For CA and CS_n input-only pins. VREF = VREFCA(DC).
2. See figure: Overshoot and Undershoot Definition.
i al
3. The AC peak noise on VREFCA could prevent VREFCA from deviating more than ±1% V DDCA from VREFCA(DC) (for reference,
t
approximately ±12mV).
den
4. For reference, approximately VDDCA/2 ±12mV.
o nfi
C
15.2 Single-Ended AC and DC Input Levels for CKE
Parameter Parameter Min Max Unit Notes
CKE input HIGH
VIHCKE g
0.65 × VDDCA sys Note 1 V 1
level
L on
CKE input LOW level VILCKE Note 1 0.35 × VDDCA V 1
Note:
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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i den Rev. 1.0
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CDC Input Levels for DQ and DM
15.3 Single-Ended AC and
1333/1600 1866/2133
Min Max Min Max
sys
AC input logic
g VIHCA(AC) VREF + 0.150 Note 2 VREF + 0.135 Note 2 V 1,2
HIGHon
L
AC input logic
VILCA(AC) Note 2 VREF - 0.150 Note 2 VREF - 0.135 V 1,2
LOW
DC input logic
VIHCA(DC) VREF + 0.100 VDDQ VREF + 0.100 VDDQ V 1
HIGH
DC input logic
VILCA(DC) VSSQ VREF - 0.100 VSSQ VREF - 0.100 V 1
LOW
Reference
voltage for VREFCA(DC
0.49 × VDDQ 0.51 × VDDQ 0.49 × VDDQ 0.51 × VDDQ V 3,4
DQ and DM )
inputs
Reference n gs
voltage VREFDQ(DC Lo
VODTR/2 - VODTR/2 + VODTR/2 - VODTR/2 +
for DQ and )
0.01 × 0.01 × 0.01 × 0.01 × V 3,5,6
DM DQODT,enab
al
VDDQ VDDQ VDDQ VDDQ
inputs(DQ led
ti
ODT enabled)
den
Notes:
o nfi
1. For DQ input-only pins. VREF = VREFDQ(DC). C
3. The AC peak noise on VREFDQ could prevent VREFDQ from deviating more than ±1% VDDQ from VREFDQ(DC) (for reference,
approximately ±12mV).
s y s
n g
Lo
4. For reference, approximately VDDQ/2 ±12mV.
5. For reference, approximately VODTR/2 ±12mV.
6. The nominal mode register programmed values for RODT and the nominal controller output impedance RON are used for the
calculation of VODTR. For testing purposes, a controller RON value of 50Ω is used.
t i al 2𝑅𝑂𝑁 + 𝑅 𝑇𝑇
en 𝑉𝑂𝐷𝑇𝑅 = × 𝑉𝐷𝐷𝑄
fid
𝑅𝑂𝑁 + 𝑅 𝑇𝑇
n
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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n Page 32
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C Input Levels
15.4 Differential AC and DC
For CK, VREF = VREFCA(DC); For DQS, VREF = VREFDQ(DC)
LPDDR3
ys
n g s Min Max
Lo
Differential input HIGH AC
Differential input LOW AC
VIH,diff(AC)
VIL,diff(AC)
2 × (VIH(AC) - VREF)
Note 1
Note 1
2 × (VIL(AC) - VREF)
V
V
2
2
Differential input HIGH DC VIH,diff(DC) 2 × (VIH(DC) - VREF) Note 1 V 3
Differential input LOW DC VIL,diff(DC) Note 1 2 × (VIL(DC) - VREF) V 3
Notes:
1. These values are not defined; however, the single-ended signals CK and DQS must be within the respective limits (VIH(DC)max,
VIL(DC)min) for single-ended signals, and must comply with the specified limitations for overshoot and undershoot (see figure:
Overshoot and Undershoot Definition).
2. For CK, use VIH/VIL(AC) of CA and VREFCA; for DQS, use VIH/VIL(AC) of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used
for a signal group, the reduced voltage level also applies.
3. Used to define a differential signal slew rate.
n gs
15.5 Single-Ended Levels for CK and DQS L o
Value
Min Max
(VDDQ/2) +
ti aVl
den
Single-ended HIGH level for strobes Note 1 2,3
0.150
VSEH(AC150)
n fi
Single-ended HIGH level for CK
(VDDCA/2) +
o
CNote 1 V 2,3
0.150
(VDDQ/2) -
Single-ended LOW level for strobes Note 1 V 2,3
0.150
VSEL(AC150)
g s ysNote 1 (VDDCA/2) -
Single-ended LOW level for CK
n V 2,3
Lo (VDDQ/2) +
0.150
Single-ended HIGH level for strobes Note 1 V 2,3

0.135
(VDDCA/2) +
Single-ended HIGH level for CK
en tial 0.135
Note 1 V 2,3
f i d (VDDQ/2) +
o n level for strobes
Single-ended LOW Note 1 V 2,3
a
C 0.135
(VDDCA/2) + e n ti
d
Single-ended LOW level for CK Note 1
0.135
V 2,3
onfi
C
ys
Notes:
ngs 1. These values are not defined; however, the single-ended signals CK and DQS[3:0] must be within the respective limits
(VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the specified limitations for overshoot and undershoot
(see figure: Overshoot and Undershoot Definition).
s y s
n g
Lo
2. For CK, use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0]), use VIH/VIL(AC) of DQ.
3. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on VREFCA. If a reduced AC HIGH or AC LOW
is used for a signal group, the reduced level applies.
t ial
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i den Rev. 1.0
nf NCLD3B1256M32
CoDifferential Input Signals (CK, CK_c, DQS_t, DQS_c)
15.6 Crosspoint Voltage for
Parameter Symbol Min Max Unit Notes
Differential input crosspoint voltage relative to
sys
VDDCA/2 for CK
g
VIXCA(AC) –120 120 mV 1, 2
n
Lo
Differential input crosspoint voltage relative to
VDDQ/2 for DQS
VIXDQ(AC) –120 120 mV 1, 2
Notes:
1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations
in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
2. For CK, VREF = VREFCA(DC). For DQS, VREF = VREFDQ(DC).
n gs
L o
ti al
den
o nfi
C
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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C and Operating Conditions
16. Output Characteristics
16.1 Single-Ended AC and DC Output Levels
Parameter Symbol Value Unit Notes
g sys
AC output HIGH measurement level (for output slew rate) VOH(AC) VREF + 0.12 V
L on LOW measurement level (for output slew rate)

AC output VOL(AC) VREF - 0.12 V
DC output HIGH measurement level (for I-V curve linearity) VOH(DC) 0.9 × VDDQ V 1
DC output LOW measurement level (for I-V curve linearity) VOL(DC) 0.1 × VDDQ V 2
VDDQ × {0.1
DC output LOW measurement level (for I-V curve VOL(DC)ODT,enabl + 0.9 ×
V 3
linearity);ODT enabled DQS_t ed [RON / (RTT
+ RON)]}
Output leakage current (DQ, DM, DQS); DQ, DQS are –5 (MIN)
IOZ μA
disabled;0V ≤ VOUT ≤ VDDQ 5 (MAX)
Delta output impedance between pull-up and pull-down for –15 (MIN)
MMPUPD %
DQ/DM 15 (MAX)
n gs
Notes:
1. IOH = –0.1mA. Lo
2. IOL = 0.1mA.
3. The minimum value is derived when using RTT,min and RON,max (±30% uncalibrated, ±15% calibrated).
ti al
16.2 Differential AC and DC Output Levels
fi den
Parameter Symbol o nValue Unit Notes
AC differential output HIGH measurement level (for output SR) VOH,diff(AC)
C 0.2 × V DDQ V 1
AC differential output LOW measurement level (for output SR) VOL,diff(AC) –0.2 × VDDQ V 2
Notes:
1. IOH = –0.1mA. s y s
n g
2. IOL = 0.1mA.
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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n Page 35
Co
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i den Rev. 1.0
o nf NCLD3B1256M32
C
17. AC Overshoot/Undershoot Specification
Parameter 2133 1866 1600 1333 Unit Notes
Maximum peak amplitude provided for overshoot area 0.35 0.35 0.35 0.35 V
g sys
Maximum peak amplitude provided for undershoot area 0.35 0.35 0.35 0.35 V
L on area above V
Maximum DD 0.10 0.10 0.10 0.12 V-ns 1
Maximum area below V SS 0.10 0.10 0.10 0.12 V-ns 2
Notes:
1. VDD = VDDCA for CA [9:0], CK, CS_n, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and ODT.
2. VSS = VSSCA for CA [9:0], CK, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and ODT.
3. Maximum peak amplitude values are referenced from actual VDD and VSS values.
4. Maximum area values are referenced from maximum operating VDD and VSS values.
n gs
Lo
ti al
den
o nfi
C
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
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Co
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o nf NCLD3B1256M32
18. AC Timing C
Notes 1–3 apply to all parameters and conditions
Min/ Data Rate
ys
n g s Max 1333 1600 1866 2133
Lo
Maximum frequency
Clock Timing
- - 667 800 933 1066 MHz
MIN 1.5 1.25 1.071 0.938

Average clock period tCK(avg) ns
MAX 100
Average HIGH pulse MIN 0.45 tCK(avg
tCH(avg)
width MAX 0.55 )
Average LOW pulse MIN 0.45 tCK(avg
tCL(avg)
width MAX 0.55 )
Absolute clock period tCK(abs) MIN tCK(avg) MIN + tJIT(per) MIN ns
Absolute clock HIGH MIN 0.43
tCK(avg
pulse tCH(abs)
MAX 0.57 )
n gs
width
Lo
Absolute clock LOW MIN 0.43
tCK(avg
pulse tCL(abs)
MAX 0.57 )
width
Clock period jitter (with tJIT(per), MIN -80 -70 -60 -50 ti al
den
ps
nfi
supported jitter) allowed MAX 80 70 60 50
Maximum clock jitter
Co
between two tJIT(cc),
MAX 160 140 120 100 ps
consecutive clock cycles allowed
(with allowed jitter)
s y s
g
min((tCH(abs),min-tCH(avg),min),
n
tJIT(duty)
MIN
Lo(min-
tCL(abs),
CL(avg),min))× CK(avg)
t t
Duty cycle jitter (with
, max((tCH(abs),max-tCH(avg),max ps
supported jitter)
allowed
al
),
n t i MAX
(tCL(abs),
e
fid max-tCL(avg),max)) × tCK(avg)
CumulativeC
on errors tERR(2per MIN –118 –103 -88 -74
ti a
), ps
d e n
across 2 cycles
allowed
MAX 118 103 88 74
onfi
C
ys
tERR(3per MIN –140 –122 -105 -87
ngs Cumulative errors

), ps
across 3 cycles MAX 140 122 105 87
allowed
tERR(4per MIN –155 –136 -117 s y
-97 s
Cumulative errors
n g
across 4 cycles
),
allowed
MAX 155 136 117 Lo 97
ps
Cumulative errors tERR(5per MIN –168 –147 -126 -105

ps
across 5 cycles ), MAX 168 147 126 105
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n Page 37
Co
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i den Rev. 1.0
o nf NCLD3B1256M32
C
allowed
tERR(6per MIN –177 –155 -133 -111
Cumulative errors
), ps
across 6 cycles
y s MAX 177 155 133 111
n gs
allowed
Lo
tERR(7per MIN –186 –163 -139 -116
Cumulative errors
), ps
allowed
tERR(8per MIN –193 –169 -145 -121
Cumulative errors
), ps
allowed
tERR(9per MIN –200 –175 -150 -125
Cumulative errors
), ps
allowed
tERR(10p MIN –205 –180 -154 -128
Cumulative errors
er), ps
across 10 cycles
allowed
MAX 205 180 154 128
n gs
Cumulative errors tERR(11p MIN –210 –184 -158 -132 L o
across 11 er), ps
MAX 210 184 158 132
cycles allowed
Cumulative errors tERR(12p MIN –215 –188 -161 -134
ti al
across 12 er),
denps
cycles allowed
MAX 215 188 161
o nfi
134
tERR(nper),allowed C
Cumulative errors MIN MIN=(1+0.68ln(n))×tJIT(per),allo
tERR(npe
across n = wed MIN
13, 14, 15…, 19, 20
r),
allowed s ys
tERR (nper), allowed
g
ps
n
cycles MAX
LoMAX=(1+0.68ln(n))×tJIT(per),
allowed MAX
ZQ Calibration Parameters
Initialization calibration
time t i
t
alZQINIT MIN 1 μs
de n
f i
Long calibration time tZQCL MIN 360 ns
C ontime
Short calibration tZQCS MIN 90 ns
ti a
Calibration RESET time tZQRESET MIN MAX (50ns, 3nCK) ns
d e n
READ Parameters4
onfi
DQS output access time MIN 2500 C
gsys from tDQSCK ps
n CK
MAX 5500
tDQSCKD
s y s
DQSCK delta short MAX 265 220 190
n g165 ps 5
Lo
S
tDQSCKD
DQSCK delta medium MAX 593 511 435 380 ps 6
M
DQSCK delta long tDQSCKD MAX 733 614 525 460 ps 7
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C
L
DQS-DQ skew tDQSQ MAX 165 135 115 110 ps
DQS output HIGH pulse tCK(avg
ys
tQSH MIN tCH(abs) - 0.05
width
g s
n LOW pulse
)
DQS ooutput tCK(avg
L
width
tQSL MIN tCL(abs) - 0.05
)
DQ/DQS output hold
time tQH MIN MIN (tQSH, tQSL) ps
from DQS
tCK(avg
READ preamble tRPRE MIN 0.9 8,9
)
tCK(avg
READ postamble tRPST MIN 0.3 8,10
)
DQS Low-Z from clock tLZ(DQS) MIN tDQSCK (MIN) - 300 ps 8
DQ Low-Z from clock tLZ(DQ) MIN tDQSCK (MIN) - 300 ps 8
DQS High-Z from clock tHZ(DQS) MAX tDQSCK (MAX) - 100 ps 8 n gs
tDQSCK (MAX) + (1.4 × tDQSQ Lo
DQ High-Z from clock tHZ(DQ) MAX ps 8
(MAX))
WRITE Parameters4
DQ and DM input hold
ti al
time tDH MIN 175 150 130 115 denps
(VREF based) o nfi
DQ and DM input setup
C
time tDS MIN 175 150 130 115 ps
(VREF based)
DQ and DM input pulse s y s tCK(avg
tDIPW MIN n g 0.35
width
Write command to first MIN
Lo 0.75
)
tCK(avg
DQS tDQSS
MAX 1.25 )
latching transition
input high-level ti
al
den DQSH
DQS tCK(avg
t MIN 0.4
width
n f i )
input o low-level a
DQS
C ti
tCK(avg
width
t DQSL MIN 0.4
)
d e n
DQS rising edge to CK
onfi
C
gsys falling
edge and DQS falling tCK(avg
n edge
tDSS MIN 0.2
)
to CK rising edge setup
ng sys
time
CK rising edge to DQS
Lo
tCK(avg
falling tDSH MIN 0.2
)
edge and CK falling edge
t ial
n Page 39
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to C
DQS rising edge hold
time
y s
n gs
tCK(avg
Write postamble tWPST MIN 0.4
Lo
)
tCK(avg
Write preamble tWPRE MIN 0.8
)
CKE Input Parameters
CKE minimum pulse
width tCK(avg
tCKE MIN MAX (7.5ns, 3nCK)
(HIGH and LOW pulse )
width)
tCK(avg
CKE input setup time tISCKE MIN 0.25 11
)
tCK(avg
CKE input hold time tIHCKE MIN 0.25
)
12
n gs
Command path disable tCK(avg Lo
tCPDED MIN 2
delay )
Command Address Input Parameters4
Address and control
ti al
input tISCA MIN 175 150 130 115
denps
setup time
o nfi
Address and control C
input t
IHCA MIN 175 150 130 115 ps
hold time
CS_n input setup time tISCS MIN s
290 y s 270 230 205 ps
n g
CS_n input hold time
Lo290
tIHCS MIN 270 230 205 ps
Address and control
tCK(avg
input tIPWCA MIN 0.35
)
pulse width
t i al tCK(avg
den IPWCS
CS_n input pulse width MIN 0.7
t
f i )
on (10–55 MHz)
Boot Parameters
C 14, 15, 16
ti a
Clock cycle time CKb t MAX 100
d e n
CKE input setup time tISCKEb MIN 18
ns
onfi
C
ys CKE input hold time tIHCKEb MIN 2.5 ns
ngs Address and control

input tISb MIN 1150 ps
setup time
ng sys
Address
input
and control
tIHb MIN 1150
Lo ps
hold time
DQS output data access tDQSCKb MIN 2 ns
t ial
e n
Co
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o nf NCLD3B1256M32
time C MAX 10
from CK
Data strobe edge to
output
g sys DQSQb t MAX 1.2 ns
on
data edge
L
Mode Register Parameters
MODE REGISTER WRITE
command period (MRW tCK(avg
tMRW MIN 10
command to MRW )
command interval)
MODE REGISTER SET
command delay (MRW
tMRD MIN MAX (14nx, 10nCK) ns
command to non-MRW
command interval)
MODE REGISTER READ tCK(avg
command period
tMRR MIN 4
) n gs
Additional time after tXP L o
has
expired until MRR tMRRI MIN tRCD (MIN) ns
command
ti al
may be issued
den
Core Parameters17
o nfi
C tCK(avg
READ latency RL MIN 10 12 14 16
)
tCK(avg
WRITE latency (set A) WL MIN 6
g s ys 6 8 8
)
n
Lo 8
tCK(avg
WRITE latency (set B) WL MIN 9 11 13
)
tRAS + tRPab (with all-bank
ACTIVATE-to- ACTIVATE precharge)
tial
tRC MIN ns
command period tRAS + tRPpb (with per-bank
f i den precharge)
n
CKE minimumopulse
a
width
C
e n ti
d
during SELF REFRESH tCKESR MIN MAX (15ns, 3nCK) ns
onfi
(low pulse width during C
gsys SELF REFRESH)
n SELF REFRESH exit to
next tXSR MIN MAX (tRFCab + 10ns, 2nCK)
s y s ns
valid command delay n g
Exit power-down to next Lo
valid tXP MIN MAX (7.5ns, 2nCK) ns
command delay
t ial
n Page 41
Co
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i d en Rev. 1.0
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CAS-to-CAS delay t
C
CCD MIN 4
tCK(avg
)
Internal READ to
PRECHARGE
g sys tRTP MIN MAX (7.5ns, 4nCK) ns
on delay
command
L
RAS-to-CAS delay tRCD MIN MAX (18ns, 3nCK) ns
Row precharge time
tRPpb MIN MAX (18ns, 3nCK) ns
(single bank)
Row precharge time
tRPpab MIN MAX (21ns, 3nCK) ns
(all banks)
MIN MAX (42ns, 3nCK) ns
Row active time tRAS
MAX 70 μs
WRITE recovery time tWR MIN MAX (15ns, 3nCK) ns
Internal WRITE-to-READ
tWTR MIN MAX (7.5ns, 4nCK) ns
command delay
Active bank A to active n gs
bank tRRD MIN MAX (10ns, 2nCK) ns L o
B
Four-bank ACTIVATE
al
tFAW MIN MAX (50ns, 8nCK) ns
window
ti
Minimum deep den
power-down tDPD MIN 500 o nfi μs
time C
ODT Parameters
Asynchronous RTT MIN 1.75
s
turn-on dely
gsy
tODTon ns
MAX n 3.5
from ODT input
Lo
Asynchronous RTT MIN 1.75
turn-off tODToff ns
delay from ODT input
t i al MAX 3.5
f den
Automatic RTT turn-on
i tDQSCK + 1.4 × tDQSQmax +
delay
C on t AODTon MAX
tCK(avg,min)
ps
ti a
after READ data
d e n
Automatic RTT turn-off
onfi
delay tAODToff MIN tDQSCKmin - 300 ps C
gsys after READ data
n RTT disable delay from
power-
tODTd MAX 12 s y s ns
down, self refresh, and n g
deep power-down entry Lo
RTT enable delay from
tODTe MAX 12 ns
power-
t ial
n Page 42
Co
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i den Rev. 1.0
o nf NCLD3B1256M32
down and self refresh C
exit
CA Training Parameters
sys
First CA calibration
g
L on
command
tCAMRD MIN 20
tCK(avg
following CA training )
entry
First CA calibration
tCK(avg
command tCAENT MIN 10
)
following CKE LOW
CA calibration exit
tCK(avg
command tCAEXT MIN 10
)
following CKE HIGH
CKE LOW following CA tCK(avg
tCACKEL MIN 10
calibration mode entry )
CKE HIGH following last n gs
CA tCACKEH MIN 10
tCK(avg
L o
)
calibration results
Data out delay after CA
training calibration
ti al
den
tADR MAX 20 ns
command
entry
o nfi
MRW CA exit command C
to t
MRZ MIN 3 ns
DQ tri-state
s y s
n g
CA calibration command
to
Lo tCK(avg
tCACD MIN RU(tADR/tCK) + 2
CA calibration command )
delay
t
Write Leveling Parameters i al
f i
DQS delay after writeden WLDQSE MIN 25
on
t
leveling
C N -
ns
ti a
mode is programmed
d e n
First DQS edge after MIN 40
onfi
write C
gsys leveling mode is
tWLMRD
-
ns
n programmed
Write leveling output 0
s y s
delay
tWLO
20 n g ns
Write leveling hold time tWLH MIN 205 175 Lo

150 135 ps
Write leveling setup time tWLS MIN 205 175 150 135 ps
Temperature Derating Parameters
t ial
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DQS output access time C ps
from tDQSCK MAX 5620
CK (derated)
g sys
RAS-to-CAS delay
tRCD MIN tRCD + 1.875
ns
on
(derated)
L
ACTIVATE-to- ACTIVATE ns
command period tRC MIN tRC + 1.875
(derated)
Row active time ns
tRAS MIN tRAS + 1.875
(derated)
Row precharge time ns
tRP MIN tRP + 1.875
(derated)
Active bank A to active ns
bank tRRD MIN tRRD + 1.875
B (derated)
Notes: n gs
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities. Lo
2. All AC timings assume an input slew rate of 2 V/ns.
3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX.
4. READ, WRITE, and input setup and hold values are referenced to VREF.
t i al
5. DQSCKDS is the absolute value of the difference between any two DQSCK measurements (in
t t
i d ena byte lane) within a

f
n by design. Temperature
contiguous sequence of bursts in a 160ns rolling window. DQSCKDS is not tested and is guaranteed
t
drift in the system is <10˚C/s. Values do not include clock jitter. C o

6. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs
rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is <10˚C/s. Values do
not include clock jitter
g s ys
n any two DQSCK measurements (in a byte lane) within a 32ms
Lo
7. DQSCKDL is the absolute value of the difference between
t t
rolling window. DQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is <10˚C/s. Values do
t
not include clock jitter.

8. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition
t i al
threshold (VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These
f i den to a specific voltage level but to the time when the device output is no longer driving (for RPST,
parameters are not referenced t
C on or begins driving (for RPRE, LZ(DQS) and LZ(DQ)). The figure below shows a method to calculate
HZ(DQS) and HZ(DQ)),
t t t t
t ia
the point when the device is no longer driving HZ(DQS) and HZ(DQ) or begins driving LZ(DQS) and LZ(DQ) by measuring
t t t t
e n
the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is fid
n
consistent. The parameters LZ(DQS), LZ(DQ), HZ(DQS), and HZ(DQ) are defined as single-ended. The timing parameters
t t t t
Co
gsys t
RPRE and tRPST are determined from the differential signal DQS.
n
s y s
n g
Lo
t ial
n Page 44
Co
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i den Rev. 1.0
o nf NCLD3B1256M32
C
y s
n gs
Lo
9. Measured from the point when DQS begins driving the signal, to the point when DQS begins driving the first rising strobe
edge.
10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driving the signal.
n gs
11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK crossing. L o
12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltage level.
13. Input setup/hold time for signal (CA [9:0], CS_n).
ti al
14. To ensure device operation before the device is configured, a number of AC boot timing parameters are defined in this
den
table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
nfi
15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET (MRW) command, as specified in
o
Mode Register Definition. C
16. The output skew parameters are measured with default output impedance settings using the reference load.
17. The minimum tCK column applies only when tCK is greater than 6ns.
s y s
n g
Lo
t i al
en
n fid
Co n ti a
d e
onfi
C
gsys
n
s y s
n g
Lo
t ial
n Page 45
Co
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i den Rev. 1.0
o nf NCLD3B1256M32
C Hold, and Derating
19. CA and CS_n Setup,
For all input signals (CA and CS_n), the total required setup time ( tIS) and hold time (tIH) is calculated by
adding the data sheet tIS (base) and tIH (base) values to the ΔtIS and ΔtIH derating values, respectively.
y s
Example: tIS (total setup time) = tIS(base) + ΔtIS. (See the series of tables following this section.)
n gs
Lo
The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the last crossing of V REF(DC)
and the first crossing of VIH(AC)min. The typical setup slew rate for a falling signal is defined as the slew rate
between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is consistently earlier
than the typical slew rate line between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for the
derating value (see the Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to
Clock figure).
If the actual signal is later than the typical slew rate line anywhere between the shaded V REF(DC)-to-AC region,
the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value
(see the Tangent Line– tIS for CA and CS_n Relative to Clock figure).The hold ( tIH) typical slew rate for a rising
signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). The hold
n gs
(tIH) typical slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min Lo
and the first crossing of VREF(DC). If the actual signal is consistently later than the typical slew rate line between
the shaded DC-to-VREF(DC) region, use the typical slew rate for the derating value (see the Typical Slew Rate – tIH
ti al
for CA and CS_n Relative to Clock figure). If the actual signal is earlier than the typical slew rate line anywhere
den
between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level
nfi
to VREF(DC) level is used for the derating value (see the Tangent Line – tIH for CA and CS_n Relative to Clock
o
figure). C
For a valid transition, the input signal must remain above or below VIH/VIL (AC) for a specified time, tVAC (see
s y s
the Required Time for Valid Transition – tVAC > VIH(AC) and <VIL(AC) table).
n g
Lo
For slow slew rates, the total setup time could be a negative value (that is, a valid input signal will not have
reached VIH/VIL(AC) at the time of the rising clock transition). A valid input signal is still required to complete the
transition and reach VIH/VIL(AC).
t i al
For slew rates between
i denthe values listed in the Derating Values for AC/DC-Based IS/ IH (AC150) table, the
t t
f
n obtained using linear interpolation. Slew rate values are not typically.
derating values are
C o t ia
de n
19.1 CA Setup and Hold Base Values f i
Parameter
Data Rate
Reference C on
gsys 1333 1600 1866 2133
n tISCA (base) 100 75 - - VIH/VIL(AC) = VREF(DC) ±150mV
tISCA (base) - - 62.5 47.5
s
VIH/VIL(AC) = VREF(DC) ±135mV
s y
tIHCA (base) 125 100 80 65
n gVIH/VIL(DC) = VREF(DC) ±100mV
Note: Lo
1. AC/DC referenced for 2 V/ns CA slew rate and 4 V/ns differential CK slew rate.
t ial
n Page 46
Co
ti al
i den Rev. 1.0
o nf NCLD3B1256M32
CBase Values
19.2 CS_n Setup and Hold
Data Rate
Parameter Reference
1333 1600 1866 2133
tISCS
g sys
(base) 215 195 - - VIH/VIL(AC) = VREF(DC) ±150mV
t
L on(base)
ISCS - - 162.5 137.5 VIH/VIL(AC) = VREF(DC) ±135mV
t IHCS (base) 240 220 180 155 VIH/VIL(DC) = VREF(DC) ±100mV
Note:
1. AC/DC referenced for 2 V/ns CS_n slew rate, and 4 V/ns differential CK slew rate.
19.3 Derating Values for AC/DC-Based tIS/tIH (AC150)

ΔtIS, ΔtIH derating in ps
ΔtIS, ΔtIH Derating in [ps] AC/DC-based

AC150 Threshold -> VIH(ac) = VREF(dc)+150mV, VIL(ac) = VREF(dc) - 150mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
CK_t, CK_c Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns n gs
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH Lo
CA, 4.0 38 25 38 25 38 25 38 25 38 25
CS_n 3.0 25 17 25 17 25 17 25 17 38 29
0 ial
slew 2.0 0 0 0 0 0
e nt 13 13
rate
d
V/ns
1.5 -25 -17
o n-25fi -17 -12 -4
Note: C
1. Shaded cells are not supported.
19.4 Derating Values for AC/DC-Based tIS/tIH (AC135) s y s

n g
ΔtIS, ΔtIH derating in ps
Lo
ΔtIS, ΔtIH Derating in [ps] AC/DC-based
t i al CK_t, CK_c Differential Slew Rate
n
deV/ns
f i
8.0 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns
C onΔ IS Δ IH
t t ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
ti a
CA, 4.0 34 25 34 25 34 25 34 25 34 25
d e n
CS_n 3.0 23 17 23 17 23 17 23 17 34 29
o nfi
slew C13
gsys rate
2.0 0 0 0 0 0 0 11
n V/ns
1.5 -23 -17 -23 -17 -12 -4
Note:
s y s
n g
Lo
1. Shaded cells are not supported
t ial
n Page 47
Co
ti al
i den Rev. 1.0
o nf NCLD3B1256M32
20. Data Setup, Hold, C
and Slew Rate Derating
For all input signals (DQ, DM) calculate the total required setup time (tDS) and hold time (tDH) by adding the
data sheet tDS(base) and tDH(base) values (see the Data Setup and Hold Base Values table) to the ΔtDS and
y s
ΔtDH derating values, respectively (see the Derating Values for AC/DC-Based tDS/tDH (AC150) table). Example:
n gs
Lo
tDS = tDS(base) + ΔtDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIH(AC)min. The typical tDS slew rate for a falling signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIL(AC)max (see the Typical Slew Rate and tVAC – tDS for DQ
Relative to Strobe figure).
If the actual signal is consistently earlier than the typical slew rate line in the Typical Slew Rate and tVAC – tIS
for CA and CS_n Relative to Clock figure in the area shaded gray between the VREF(DC) region and the AC region,
use the typical slew rate for the derating value. If the actual signal is later than the typical slew rate line
anywhere between the shaded VREF(DC) region and the AC region, the slew rate of a tangent line to the actual
signal from the AC level to the DC level is used for the derating value (see the Tangent Line – tIS for CA and
n gs
CS_n Relative to Clock figure). Lo
The typical tDH slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and
ti al
the first crossing of VREF(DC). The typical tDH slew rate for a falling signal is defined as the slew rate between the
den
last crossing of VIH(DC)min and the first crossing of VREF(DC) (see the Typical Slew Rate – tDH for DQ Relative to
nfi
Strobe figure). If the actual signal is consistently later than the typical slew rate line between the shaded
o
DC-level-to-VREF(DC) C actual signal is earlier than the
region, use the typical slew rate for the derating value. If the
typical slew rate line anywhere between shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the
actual signal from the DC level to the VREF(DC) level is used for the derating value (see the Tangent Line – tDH for
DQ with Respect to Strobe figure).
s y s
n g
Lo
For a valid transition, the input signal must remain above or below V IH/VIL(AC) for the specified time, tVAC (see
the Required Time for Valid Transition – tVAC > VIH(AC) or <VIL(AC) table).
i al
The total setup time for slow slew rates could be negative (that is, a valid input signal may not have reached
t
V /V
IH IL(AC)
d n rising clock transition). A valid input signal is still required to complete the transition
at the time ofethe
and reach V /V n . f i
Co
IH IL(AC)
n t ia
For slew rates between the values listed in the following table, the derating values can be obtained using linear id
e
n f
interpolation. Slew rate values are not typically subject to production testing. They are verified by design o and
C
gsys characterization.
n
s y s
n g
Lo
t ial
n Page 48
Co
ti al
i den Rev. 1.0
o nf NCLD3B1256M32
20.1 Data Setup and HoldCBase Values
Data Rate
Parameter Reference
1333 1600 1866 2133
y s
n gs
tDS (base) 100 75 - - VIH/VIL(AC) = VREF(DC) ±150mV
t DS o
(base) - - 62.5 47.5 VIH/VIL(AC) = VREF(DC) ±135mV
t
L
DH (base) 125 100 80 65 VIH/VIL(DC) = VREF(DC) ±100mV
Note:
1. AC/DC referenced for 2 V/ns DQ, DM slew rate, and 4 V/ns differential DQS slew rate and nominal VIX.
20.2 Derating Values for AC/DC-Based tDS/tDH (AC150)

ΔtDS, ΔtDH derating in ps
ΔtDS, ΔtDH Derating in [ps] AC/DC-based

DQS_t, DQS_c Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns n gs
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH Lo
DQ, 4.0 38 25 38 25 38 25 38 25 38 25
DM 3.0 25 17 25 17 25 17 25 17 38 29
0 ial
slew 2.0 0 0 0 0 0
e nt 13 13
rate
d
V/ns
1.5 -25 -17
o nfi
-25 -17 -12 -4
Note: C
20.3 Derating Values for AC/DC-Based tDS/tDH (AC135) s y s

n g
ΔtDS, ΔtDH derating in ps
Lo
ΔtDS, ΔtDH Derating in [ps] AC/DC-based
t i al DQS_t, DQS_c Differential Slew Rate
i en
dV/ns
f
8.0 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns
C oΔnIS Δ IH
t t ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
ti a
DQ, 4.0 34 25 34 25 34 25 34 25 34 25
d e n
DM 3.0 23 17 23 17 23 17 23 17 34 29
o nfi
slew C13
gsys rate
2.0 0 0 0 0 0 0 11
n V/ns
1.5 -23 -17 -23 -17 -12 -4
Note:
s y s
n g
Lo
t ial
n Page 49
Co

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ti al

i den Rev. 1.0

LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

www.longsys.com f iden Longsys Electronics

20.3 Derating Values for AC/DC-Based DS/ DH (AC135) ................................................................ 49 id

4. Package Block Diagrams

L o AC timings are referenced to clock.

n NC - No connect: Not internally connected.

Input/output capacitance, DQ,

www.longsys.com f iden Longsys Electronics

o n value or that the ZQ resistor tolerance meets the specified

Lo If nWR (MR2 OP[4]) = 0

0b: Disable write leveling (default)

11.5 MR4 Device Temperature (MA [7:0] = 04h)

related setup and hold timings remain unchanged.

11.7 MR6 Basic Configuration 2 (MA [7:0] = 06h)

11.10 MR9 Test Mode (MA [7:0] = 09h) n gs

11.11 MR10 Calibration (MA [7:0] = 0Ah)

en tial All others: Reserved

11.13 MR16 PASR Bank Mask (MA [7:0] = 010h)

11.15 MR63 RESET (MA [7:0] = 3Fh) – MRW Only

11.16 Reserved Mode Registers ti al

MR[12:15] 0Ch-0Fh Reserved

X MA6 MA7 X Falling

Enter self H L L L H X Rising

WRITE Select column and start write burst

READ Select column and start read burst Reading 11,12,14

L onthe table: Current State Bank n to

After tMRR is met, the device

Lo is in the active state.

Current State Command to Operation Next State Notes

Co PRECHARGE Deactivate row(s) in bank or banks Precharging 8

n ACTIVATE Select and activate row in bank m Active

State Starts with... Ends when... Notes

o nPRECHARGE and Auto Precharge Clarification table are met.

12.5 DM Truth Table t i al

14.2 Input Leakage Current n gs

n g s Min Max Min Max

Single-ended HIGH level for strobes Note 1 V 2,3

L on LOW measurement level (for output slew rate)

Min/ Data Rate

n g s Max 1333 1600 1866 2133

MIN 1.5 1.25 1.071 0.938

ngs Cumulative errors

Cumulative errors tERR(5per MIN –168 –147 -126 -105

ngs Address and control

Write leveling hold time tWLH MIN 205 175 Lo

i d ena byte lane) within a

drift in the system is <10˚C/s. Values do not include clock jitter. C o

not include clock jitter.

19.3 Derating Values for AC/DC-Based tIS/tIH (AC150)

ΔtIS, ΔtIH Derating in [ps] AC/DC-based

19.4 Derating Values for AC/DC-Based tIS/tIH (AC135) s y s

20.2 Derating Values for AC/DC-Based tDS/tDH (AC150)

ΔtDS, ΔtDH Derating in [ps] AC/DC-based

20.3 Derating Values for AC/DC-Based tDS/tDH (AC135) s y s

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